llvm/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp

//===- ARMTargetStreamer.cpp - ARMTargetStreamer class --*- C++ -*---------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file implements the ARMTargetStreamer class.
//
//===----------------------------------------------------------------------===//

#include "MCTargetDesc/ARMMCTargetDesc.h"
#include "llvm/MC/ConstantPools.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/ARMBuildAttributes.h"

usingnamespacellvm;

//
// ARMTargetStreamer Implemenation
//

ARMTargetStreamer::ARMTargetStreamer(MCStreamer &S)
    : … { … }

ARMTargetStreamer::~ARMTargetStreamer() = default;

// The constant pool handling is shared by all ARMTargetStreamer
// implementations.
const MCExpr *ARMTargetStreamer::addConstantPoolEntry(const MCExpr *Expr, SMLoc Loc) { … }

void ARMTargetStreamer::emitCurrentConstantPool() { … }

// finish() - write out any non-empty assembler constant pools.
void ARMTargetStreamer::emitConstantPools() { … }

// reset() - Reset any state
void ARMTargetStreamer::reset() { … }

void ARMTargetStreamer::emitInst(uint32_t Inst, char Suffix) { … }

// The remaining callbacks should be handled separately by each
// streamer.
void ARMTargetStreamer::emitFnStart() { … }
void ARMTargetStreamer::emitFnEnd() { … }
void ARMTargetStreamer::emitCantUnwind() { … }
void ARMTargetStreamer::emitPersonality(const MCSymbol *Personality) { … }
void ARMTargetStreamer::emitPersonalityIndex(unsigned Index) { … }
void ARMTargetStreamer::emitHandlerData() { … }
void ARMTargetStreamer::emitSetFP(unsigned FpReg, unsigned SpReg,
                                  int64_t Offset) { … }
void ARMTargetStreamer::emitMovSP(unsigned Reg, int64_t Offset) { … }
void ARMTargetStreamer::emitPad(int64_t Offset) { … }
void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<MCRegister> &RegList,
                                    bool isVector) { … }
void ARMTargetStreamer::emitUnwindRaw(int64_t StackOffset,
                                      const SmallVectorImpl<uint8_t> &Opcodes) { … }
void ARMTargetStreamer::switchVendor(StringRef Vendor) { … }
void ARMTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) { … }
void ARMTargetStreamer::emitTextAttribute(unsigned Attribute,
                                          StringRef String) { … }
void ARMTargetStreamer::emitIntTextAttribute(unsigned Attribute,
                                             unsigned IntValue,
                                             StringRef StringValue) { … }
void ARMTargetStreamer::emitArch(ARM::ArchKind Arch) { … }
void ARMTargetStreamer::emitArchExtension(uint64_t ArchExt) { … }
void ARMTargetStreamer::emitObjectArch(ARM::ArchKind Arch) { … }
void ARMTargetStreamer::emitFPU(ARM::FPUKind FPU) { … }
void ARMTargetStreamer::finishAttributeSection() { … }
void ARMTargetStreamer::annotateTLSDescriptorSequence(
    const MCSymbolRefExpr *SRE) { … }
void ARMTargetStreamer::emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) { … }

void ARMTargetStreamer::emitARMWinCFIAllocStack(unsigned Size, bool Wide) { … }
void ARMTargetStreamer::emitARMWinCFISaveRegMask(unsigned Mask, bool Wide) { … }
void ARMTargetStreamer::emitARMWinCFISaveSP(unsigned Reg) { … }
void ARMTargetStreamer::emitARMWinCFISaveFRegs(unsigned First, unsigned Last) { … }
void ARMTargetStreamer::emitARMWinCFISaveLR(unsigned Offset) { … }
void ARMTargetStreamer::emitARMWinCFINop(bool Wide) { … }
void ARMTargetStreamer::emitARMWinCFIPrologEnd(bool Fragment) { … }
void ARMTargetStreamer::emitARMWinCFIEpilogStart(unsigned Condition) { … }
void ARMTargetStreamer::emitARMWinCFIEpilogEnd() { … }
void ARMTargetStreamer::emitARMWinCFICustom(unsigned Opcode) { … }

static ARMBuildAttrs::CPUArch getArchForCPU(const MCSubtargetInfo &STI) { … }

static bool isV8M(const MCSubtargetInfo &STI) { … }

/// Emit the build attributes that only depend on the hardware that we expect
// /to be available, and not on the ABI, or any source-language choices.
void ARMTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) { … }

MCTargetStreamer *
llvm::createARMObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { … }