#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
namespace llvm {
namespace AVR {
enum {
PHI = 0,
INLINEASM = 1,
INLINEASM_BR = 2,
CFI_INSTRUCTION = 3,
EH_LABEL = 4,
GC_LABEL = 5,
ANNOTATION_LABEL = 6,
KILL = 7,
EXTRACT_SUBREG = 8,
INSERT_SUBREG = 9,
IMPLICIT_DEF = 10,
INIT_UNDEF = 11,
SUBREG_TO_REG = 12,
COPY_TO_REGCLASS = 13,
DBG_VALUE = 14,
DBG_VALUE_LIST = 15,
DBG_INSTR_REF = 16,
DBG_PHI = 17,
DBG_LABEL = 18,
REG_SEQUENCE = 19,
COPY = 20,
BUNDLE = 21,
LIFETIME_START = 22,
LIFETIME_END = 23,
PSEUDO_PROBE = 24,
ARITH_FENCE = 25,
STACKMAP = 26,
FENTRY_CALL = 27,
PATCHPOINT = 28,
LOAD_STACK_GUARD = 29,
PREALLOCATED_SETUP = 30,
PREALLOCATED_ARG = 31,
STATEPOINT = 32,
LOCAL_ESCAPE = 33,
FAULTING_OP = 34,
PATCHABLE_OP = 35,
PATCHABLE_FUNCTION_ENTER = 36,
PATCHABLE_RET = 37,
PATCHABLE_FUNCTION_EXIT = 38,
PATCHABLE_TAIL_CALL = 39,
PATCHABLE_EVENT_CALL = 40,
PATCHABLE_TYPED_EVENT_CALL = 41,
ICALL_BRANCH_FUNNEL = 42,
FAKE_USE = 43,
MEMBARRIER = 44,
JUMP_TABLE_DEBUG_INFO = 45,
CONVERGENCECTRL_ENTRY = 46,
CONVERGENCECTRL_ANCHOR = 47,
CONVERGENCECTRL_LOOP = 48,
CONVERGENCECTRL_GLUE = 49,
G_ASSERT_SEXT = 50,
G_ASSERT_ZEXT = 51,
G_ASSERT_ALIGN = 52,
G_ADD = 53,
G_SUB = 54,
G_MUL = 55,
G_SDIV = 56,
G_UDIV = 57,
G_SREM = 58,
G_UREM = 59,
G_SDIVREM = 60,
G_UDIVREM = 61,
G_AND = 62,
G_OR = 63,
G_XOR = 64,
G_IMPLICIT_DEF = 65,
G_PHI = 66,
G_FRAME_INDEX = 67,
G_GLOBAL_VALUE = 68,
G_PTRAUTH_GLOBAL_VALUE = 69,
G_CONSTANT_POOL = 70,
G_EXTRACT = 71,
G_UNMERGE_VALUES = 72,
G_INSERT = 73,
G_MERGE_VALUES = 74,
G_BUILD_VECTOR = 75,
G_BUILD_VECTOR_TRUNC = 76,
G_CONCAT_VECTORS = 77,
G_PTRTOINT = 78,
G_INTTOPTR = 79,
G_BITCAST = 80,
G_FREEZE = 81,
G_CONSTANT_FOLD_BARRIER = 82,
G_INTRINSIC_FPTRUNC_ROUND = 83,
G_INTRINSIC_TRUNC = 84,
G_INTRINSIC_ROUND = 85,
G_INTRINSIC_LRINT = 86,
G_INTRINSIC_LLRINT = 87,
G_INTRINSIC_ROUNDEVEN = 88,
G_READCYCLECOUNTER = 89,
G_READSTEADYCOUNTER = 90,
G_LOAD = 91,
G_SEXTLOAD = 92,
G_ZEXTLOAD = 93,
G_INDEXED_LOAD = 94,
G_INDEXED_SEXTLOAD = 95,
G_INDEXED_ZEXTLOAD = 96,
G_STORE = 97,
G_INDEXED_STORE = 98,
G_ATOMIC_CMPXCHG_WITH_SUCCESS = 99,
G_ATOMIC_CMPXCHG = 100,
G_ATOMICRMW_XCHG = 101,
G_ATOMICRMW_ADD = 102,
G_ATOMICRMW_SUB = 103,
G_ATOMICRMW_AND = 104,
G_ATOMICRMW_NAND = 105,
G_ATOMICRMW_OR = 106,
G_ATOMICRMW_XOR = 107,
G_ATOMICRMW_MAX = 108,
G_ATOMICRMW_MIN = 109,
G_ATOMICRMW_UMAX = 110,
G_ATOMICRMW_UMIN = 111,
G_ATOMICRMW_FADD = 112,
G_ATOMICRMW_FSUB = 113,
G_ATOMICRMW_FMAX = 114,
G_ATOMICRMW_FMIN = 115,
G_ATOMICRMW_UINC_WRAP = 116,
G_ATOMICRMW_UDEC_WRAP = 117,
G_ATOMICRMW_USUB_COND = 118,
G_ATOMICRMW_USUB_SAT = 119,
G_FENCE = 120,
G_PREFETCH = 121,
G_BRCOND = 122,
G_BRINDIRECT = 123,
G_INVOKE_REGION_START = 124,
G_INTRINSIC = 125,
G_INTRINSIC_W_SIDE_EFFECTS = 126,
G_INTRINSIC_CONVERGENT = 127,
G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 128,
G_ANYEXT = 129,
G_TRUNC = 130,
G_CONSTANT = 131,
G_FCONSTANT = 132,
G_VASTART = 133,
G_VAARG = 134,
G_SEXT = 135,
G_SEXT_INREG = 136,
G_ZEXT = 137,
G_SHL = 138,
G_LSHR = 139,
G_ASHR = 140,
G_FSHL = 141,
G_FSHR = 142,
G_ROTR = 143,
G_ROTL = 144,
G_ICMP = 145,
G_FCMP = 146,
G_SCMP = 147,
G_UCMP = 148,
G_SELECT = 149,
G_UADDO = 150,
G_UADDE = 151,
G_USUBO = 152,
G_USUBE = 153,
G_SADDO = 154,
G_SADDE = 155,
G_SSUBO = 156,
G_SSUBE = 157,
G_UMULO = 158,
G_SMULO = 159,
G_UMULH = 160,
G_SMULH = 161,
G_UADDSAT = 162,
G_SADDSAT = 163,
G_USUBSAT = 164,
G_SSUBSAT = 165,
G_USHLSAT = 166,
G_SSHLSAT = 167,
G_SMULFIX = 168,
G_UMULFIX = 169,
G_SMULFIXSAT = 170,
G_UMULFIXSAT = 171,
G_SDIVFIX = 172,
G_UDIVFIX = 173,
G_SDIVFIXSAT = 174,
G_UDIVFIXSAT = 175,
G_FADD = 176,
G_FSUB = 177,
G_FMUL = 178,
G_FMA = 179,
G_FMAD = 180,
G_FDIV = 181,
G_FREM = 182,
G_FPOW = 183,
G_FPOWI = 184,
G_FEXP = 185,
G_FEXP2 = 186,
G_FEXP10 = 187,
G_FLOG = 188,
G_FLOG2 = 189,
G_FLOG10 = 190,
G_FLDEXP = 191,
G_FFREXP = 192,
G_FNEG = 193,
G_FPEXT = 194,
G_FPTRUNC = 195,
G_FPTOSI = 196,
G_FPTOUI = 197,
G_SITOFP = 198,
G_UITOFP = 199,
G_FPTOSI_SAT = 200,
G_FPTOUI_SAT = 201,
G_FABS = 202,
G_FCOPYSIGN = 203,
G_IS_FPCLASS = 204,
G_FCANONICALIZE = 205,
G_FMINNUM = 206,
G_FMAXNUM = 207,
G_FMINNUM_IEEE = 208,
G_FMAXNUM_IEEE = 209,
G_FMINIMUM = 210,
G_FMAXIMUM = 211,
G_GET_FPENV = 212,
G_SET_FPENV = 213,
G_RESET_FPENV = 214,
G_GET_FPMODE = 215,
G_SET_FPMODE = 216,
G_RESET_FPMODE = 217,
G_PTR_ADD = 218,
G_PTRMASK = 219,
G_SMIN = 220,
G_SMAX = 221,
G_UMIN = 222,
G_UMAX = 223,
G_ABS = 224,
G_LROUND = 225,
G_LLROUND = 226,
G_BR = 227,
G_BRJT = 228,
G_VSCALE = 229,
G_INSERT_SUBVECTOR = 230,
G_EXTRACT_SUBVECTOR = 231,
G_INSERT_VECTOR_ELT = 232,
G_EXTRACT_VECTOR_ELT = 233,
G_SHUFFLE_VECTOR = 234,
G_SPLAT_VECTOR = 235,
G_VECTOR_COMPRESS = 236,
G_CTTZ = 237,
G_CTTZ_ZERO_UNDEF = 238,
G_CTLZ = 239,
G_CTLZ_ZERO_UNDEF = 240,
G_CTPOP = 241,
G_BSWAP = 242,
G_BITREVERSE = 243,
G_FCEIL = 244,
G_FCOS = 245,
G_FSIN = 246,
G_FTAN = 247,
G_FACOS = 248,
G_FASIN = 249,
G_FATAN = 250,
G_FCOSH = 251,
G_FSINH = 252,
G_FTANH = 253,
G_FSQRT = 254,
G_FFLOOR = 255,
G_FRINT = 256,
G_FNEARBYINT = 257,
G_ADDRSPACE_CAST = 258,
G_BLOCK_ADDR = 259,
G_JUMP_TABLE = 260,
G_DYN_STACKALLOC = 261,
G_STACKSAVE = 262,
G_STACKRESTORE = 263,
G_STRICT_FADD = 264,
G_STRICT_FSUB = 265,
G_STRICT_FMUL = 266,
G_STRICT_FDIV = 267,
G_STRICT_FREM = 268,
G_STRICT_FMA = 269,
G_STRICT_FSQRT = 270,
G_STRICT_FLDEXP = 271,
G_READ_REGISTER = 272,
G_WRITE_REGISTER = 273,
G_MEMCPY = 274,
G_MEMCPY_INLINE = 275,
G_MEMMOVE = 276,
G_MEMSET = 277,
G_BZERO = 278,
G_TRAP = 279,
G_DEBUGTRAP = 280,
G_UBSANTRAP = 281,
G_VECREDUCE_SEQ_FADD = 282,
G_VECREDUCE_SEQ_FMUL = 283,
G_VECREDUCE_FADD = 284,
G_VECREDUCE_FMUL = 285,
G_VECREDUCE_FMAX = 286,
G_VECREDUCE_FMIN = 287,
G_VECREDUCE_FMAXIMUM = 288,
G_VECREDUCE_FMINIMUM = 289,
G_VECREDUCE_ADD = 290,
G_VECREDUCE_MUL = 291,
G_VECREDUCE_AND = 292,
G_VECREDUCE_OR = 293,
G_VECREDUCE_XOR = 294,
G_VECREDUCE_SMAX = 295,
G_VECREDUCE_SMIN = 296,
G_VECREDUCE_UMAX = 297,
G_VECREDUCE_UMIN = 298,
G_SBFX = 299,
G_UBFX = 300,
ADCWRdRr = 301,
ADDWRdRr = 302,
ADJCALLSTACKDOWN = 303,
ADJCALLSTACKUP = 304,
ANDIWRdK = 305,
ANDWRdRr = 306,
ASRBNRd = 307,
ASRWLoRd = 308,
ASRWNRd = 309,
ASRWRd = 310,
Asr16 = 311,
Asr32 = 312,
Asr8 = 313,
AtomicFence = 314,
AtomicLoad16 = 315,
AtomicLoad8 = 316,
AtomicLoadAdd16 = 317,
AtomicLoadAdd8 = 318,
AtomicLoadAnd16 = 319,
AtomicLoadAnd8 = 320,
AtomicLoadOr16 = 321,
AtomicLoadOr8 = 322,
AtomicLoadSub16 = 323,
AtomicLoadSub8 = 324,
AtomicLoadXor16 = 325,
AtomicLoadXor8 = 326,
AtomicStore16 = 327,
AtomicStore8 = 328,
COMWRd = 329,
CPCWRdRr = 330,
CPWRdRr = 331,
CopyZero = 332,
ELPMBRdZ = 333,
ELPMBRdZPi = 334,
ELPMWRdZ = 335,
ELPMWRdZPi = 336,
EORWRdRr = 337,
FRMIDX = 338,
INWRdA = 339,
LDDWRdPtrQ = 340,
LDDWRdYQ = 341,
LDIWRdK = 342,
LDSWRdK = 343,
LDWRdPtr = 344,
LDWRdPtrPd = 345,
LDWRdPtrPi = 346,
LPMBRdZ = 347,
LPMWRdZ = 348,
LPMWRdZPi = 349,
LSLBNRd = 350,
LSLWHiRd = 351,
LSLWNRd = 352,
LSLWRd = 353,
LSRBNRd = 354,
LSRWLoRd = 355,
LSRWNRd = 356,
LSRWRd = 357,
Lsl16 = 358,
Lsl32 = 359,
Lsl8 = 360,
Lsr16 = 361,
Lsr32 = 362,
Lsr8 = 363,
NEGWRd = 364,
ORIWRdK = 365,
ORWRdRr = 366,
OUTWARr = 367,
POPWRd = 368,
PUSHWRr = 369,
ROLBRdR1 = 370,
ROLBRdR17 = 371,
ROLWRd = 372,
RORBRd = 373,
RORWRd = 374,
Rol16 = 375,
Rol8 = 376,
Ror16 = 377,
Ror8 = 378,
SBCIWRdK = 379,
SBCWRdRr = 380,
SEXT = 381,
SPREAD = 382,
SPWRITE = 383,
STDSPQRr = 384,
STDWPtrQRr = 385,
STDWSPQRr = 386,
STSWKRr = 387,
STWPtrPdRr = 388,
STWPtrPiRr = 389,
STWPtrRr = 390,
SUBIWRdK = 391,
SUBWRdRr = 392,
Select16 = 393,
Select8 = 394,
ZEXT = 395,
ADCRdRr = 396,
ADDRdRr = 397,
ADIWRdK = 398,
ANDIRdK = 399,
ANDRdRr = 400,
ASRRd = 401,
BCLRs = 402,
BLD = 403,
BRBCsk = 404,
BRBSsk = 405,
BREAK = 406,
BREQk = 407,
BRGEk = 408,
BRLOk = 409,
BRLTk = 410,
BRMIk = 411,
BRNEk = 412,
BRPLk = 413,
BRSHk = 414,
BSETs = 415,
BST = 416,
CALLk = 417,
CBIAb = 418,
COMRd = 419,
CPCRdRr = 420,
CPIRdK = 421,
CPRdRr = 422,
CPSE = 423,
DECRd = 424,
DESK = 425,
EICALL = 426,
EIJMP = 427,
ELPM = 428,
ELPMRdZ = 429,
ELPMRdZPi = 430,
EORRdRr = 431,
FMUL = 432,
FMULS = 433,
FMULSU = 434,
ICALL = 435,
IJMP = 436,
INCRd = 437,
INRdA = 438,
JMPk = 439,
LACZRd = 440,
LASZRd = 441,
LATZRd = 442,
LDDRdPtrQ = 443,
LDIRdK = 444,
LDRdPtr = 445,
LDRdPtrPd = 446,
LDRdPtrPi = 447,
LDSRdK = 448,
LDSRdKTiny = 449,
LPM = 450,
LPMRdZ = 451,
LPMRdZPi = 452,
LSRRd = 453,
MOVRdRr = 454,
MOVWRdRr = 455,
MULRdRr = 456,
MULSRdRr = 457,
MULSURdRr = 458,
NEGRd = 459,
NOP = 460,
ORIRdK = 461,
ORRdRr = 462,
OUTARr = 463,
POPRd = 464,
PUSHRr = 465,
RCALLk = 466,
RET = 467,
RETI = 468,
RJMPk = 469,
RORRd = 470,
SBCIRdK = 471,
SBCRdRr = 472,
SBIAb = 473,
SBICAb = 474,
SBISAb = 475,
SBIWRdK = 476,
SBRCRrB = 477,
SBRSRrB = 478,
SLEEP = 479,
SPM = 480,
SPMZPi = 481,
STDPtrQRr = 482,
STPtrPdRr = 483,
STPtrPiRr = 484,
STPtrRr = 485,
STSKRr = 486,
STSKRrTiny = 487,
SUBIRdK = 488,
SUBRdRr = 489,
SWAPRd = 490,
WDR = 491,
XCHZRd = 492,
INSTRUCTION_LIST_END = 493
};
}
}
#endif
#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM
namespace llvm {
namespace AVR {
namespace Sched {
enum {
NoInstrModel = 0,
SCHED_LIST_END = 1
};
}
}
}
#endif
#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
namespace llvm {
struct AVRInstrTable {
MCInstrDesc Insts[493];
static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
MCOperandInfo OperandInfo[319];
static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
MCPhysReg ImplicitOps[44];
};
}
#endif
#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC
namespace llvm {
static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
static constexpr unsigned AVRImpOpBase = sizeof AVRInstrTable::OperandInfo / (sizeof(MCPhysReg));
extern const AVRInstrTable AVRDescs = {
{
{ 492, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 223, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 491, 0, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 490, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 238, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 489, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 269, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 488, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 275, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 487, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 317, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 486, 2, 0, 4, 0, 0, 0, AVRImpOpBase + 0, 305, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 485, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 315, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 484, 4, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 311, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 483, 4, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 311, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 482, 3, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 308, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 481, 1, 0, 2, 0, 2, 1, AVRImpOpBase + 41, 307, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 480, 0, 0, 2, 0, 3, 0, AVRImpOpBase + 38, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 479, 0, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 478, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 283, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 477, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 283, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 476, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 272, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 475, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 285, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 474, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 285, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 473, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 285, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 472, 3, 1, 2, 0, 1, 1, AVRImpOpBase + 0, 269, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 471, 3, 1, 2, 0, 1, 1, AVRImpOpBase + 0, 275, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 470, 2, 1, 2, 0, 1, 1, AVRImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 469, 1, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 468, 0, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 467, 0, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 466, 1, 0, 2, 0, 1, 0, AVRImpOpBase + 16, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 465, 1, 0, 2, 0, 1, 1, AVRImpOpBase + 10, 193, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 464, 1, 1, 2, 0, 1, 1, AVRImpOpBase + 10, 193, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 463, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 305, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 462, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 269, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 461, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 275, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 460, 0, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 459, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 238, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 458, 2, 0, 2, 0, 0, 3, AVRImpOpBase + 35, 291, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 457, 2, 0, 2, 0, 0, 3, AVRImpOpBase + 35, 303, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 456, 2, 0, 2, 0, 0, 3, AVRImpOpBase + 35, 287, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 455, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 191, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 454, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 287, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 453, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 238, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 452, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 9, 223, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 451, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 223, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 450, 0, 0, 2, 0, 1, 1, AVRImpOpBase + 33, 1, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 449, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 289, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 448, 2, 1, 4, 0, 0, 0, AVRImpOpBase + 0, 293, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 447, 3, 2, 2, 0, 0, 0, AVRImpOpBase + 0, 300, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 446, 3, 2, 2, 0, 0, 0, AVRImpOpBase + 0, 300, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 445, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 298, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 444, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 289, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 443, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 295, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 442, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 223, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 441, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 223, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 440, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 223, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 439, 1, 0, 4, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 438, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 293, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 437, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 238, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 436, 0, 0, 2, 0, 1, 0, AVRImpOpBase + 9, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 435, 0, 0, 2, 0, 2, 0, AVRImpOpBase + 6, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 434, 2, 0, 2, 0, 0, 3, AVRImpOpBase + 35, 291, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 433, 2, 0, 2, 0, 0, 3, AVRImpOpBase + 35, 291, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 432, 2, 0, 2, 0, 0, 3, AVRImpOpBase + 35, 291, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 431, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 269, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 430, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 9, 223, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 429, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 223, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 428, 0, 0, 2, 0, 1, 1, AVRImpOpBase + 33, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 427, 0, 0, 2, 0, 1, 0, AVRImpOpBase + 9, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 426, 0, 0, 2, 0, 2, 0, AVRImpOpBase + 6, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 425, 1, 0, 2, 0, 0, 16, AVRImpOpBase + 17, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 424, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 238, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 423, 2, 0, 2, 0, 0, 1, AVRImpOpBase + 2, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 422, 2, 0, 2, 0, 0, 1, AVRImpOpBase + 2, 287, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 421, 2, 0, 2, 0, 0, 1, AVRImpOpBase + 2, 289, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 420, 2, 0, 2, 0, 1, 1, AVRImpOpBase + 0, 287, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 419, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 238, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 418, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 285, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 417, 1, 0, 4, 0, 1, 0, AVRImpOpBase + 16, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 416, 2, 0, 2, 0, 0, 1, AVRImpOpBase + 2, 283, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 415, 1, 0, 2, 0, 0, 1, AVRImpOpBase + 2, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 414, 1, 0, 2, 0, 1, 0, AVRImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 413, 1, 0, 2, 0, 1, 0, AVRImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 412, 1, 0, 2, 0, 1, 0, AVRImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 411, 1, 0, 2, 0, 1, 0, AVRImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 410, 1, 0, 2, 0, 1, 0, AVRImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 409, 1, 0, 2, 0, 1, 0, AVRImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 408, 1, 0, 2, 0, 1, 0, AVRImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 407, 1, 0, 2, 0, 1, 0, AVRImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 406, 0, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 405, 2, 0, 2, 0, 1, 0, AVRImpOpBase + 2, 281, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 404, 2, 0, 2, 0, 1, 0, AVRImpOpBase + 2, 281, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 403, 3, 1, 2, 0, 1, 0, AVRImpOpBase + 2, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 402, 1, 0, 2, 0, 0, 1, AVRImpOpBase + 2, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 401, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 238, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 400, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 269, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 399, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 275, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 398, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 272, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 397, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 269, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 396, 3, 1, 2, 0, 1, 1, AVRImpOpBase + 0, 269, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 395, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 240, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 394, 4, 1, 2, 0, 1, 0, AVRImpOpBase + 2, 265, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 393, 4, 1, 2, 0, 1, 0, AVRImpOpBase + 2, 261, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 392, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 391, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 155, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 390, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 389, 4, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 257, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 388, 4, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 257, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 387, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 255, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 386, 3, 0, 2, 0, 0, 1, AVRImpOpBase + 16, 252, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 385, 3, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 249, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 384, 3, 0, 2, 0, 0, 1, AVRImpOpBase + 16, 246, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 383, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 16, 244, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 382, 2, 1, 2, 0, 1, 0, AVRImpOpBase + 16, 242, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 381, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 240, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 380, 3, 1, 2, 0, 1, 1, AVRImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 379, 3, 1, 2, 0, 1, 1, AVRImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 378, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 174, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 377, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 376, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 174, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 375, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 374, 2, 1, 2, 0, 1, 1, AVRImpOpBase + 0, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 373, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 372, 2, 1, 2, 0, 1, 1, AVRImpOpBase + 0, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 371, 2, 1, 2, 0, 1, 1, AVRImpOpBase + 14, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 370, 2, 1, 2, 0, 1, 1, AVRImpOpBase + 12, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 369, 1, 0, 2, 0, 1, 1, AVRImpOpBase + 10, 237, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 368, 1, 1, 2, 0, 1, 1, AVRImpOpBase + 10, 237, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 367, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 235, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 366, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 365, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 155, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 364, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 363, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 174, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 362, 5, 2, 2, 0, 0, 1, AVRImpOpBase + 2, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 361, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 360, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 174, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 359, 5, 2, 2, 0, 0, 1, AVRImpOpBase + 2, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 358, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 357, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 356, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 355, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 354, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 158, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 353, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 352, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 351, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 350, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 158, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 349, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 9, 227, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 348, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 8, 225, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 347, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 8, 223, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 346, 3, 2, 2, 0, 0, 0, AVRImpOpBase + 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 345, 3, 2, 2, 0, 0, 0, AVRImpOpBase + 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 344, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 218, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 343, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 216, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 342, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 214, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 341, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 211, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 340, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 339, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 206, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 338, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 203, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 337, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 336, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 9, 200, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 335, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 8, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 334, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 9, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 333, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 8, 194, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 332, 1, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 193, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 331, 2, 0, 2, 0, 0, 1, AVRImpOpBase + 2, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 330, 2, 0, 2, 0, 1, 1, AVRImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 329, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 328, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 189, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 327, 2, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 187, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 326, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 184, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 325, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 324, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 184, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 323, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 322, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 184, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 321, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 320, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 184, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 319, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 318, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 184, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 317, 3, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 316, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 315, 2, 1, 2, 0, 0, 0, AVRImpOpBase + 0, 177, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 314, 0, 0, 2, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 313, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 174, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 312, 5, 2, 2, 0, 0, 1, AVRImpOpBase + 2, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 311, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 310, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 309, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 163, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 308, 2, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 307, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 158, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 306, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 305, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 155, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 304, 2, 0, 2, 0, 1, 1, AVRImpOpBase + 6, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 303, 2, 0, 2, 0, 1, 2, AVRImpOpBase + 3, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 302, 3, 1, 2, 0, 0, 1, AVRImpOpBase + 2, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 301, 3, 1, 2, 0, 1, 1, AVRImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 300, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 299, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 298, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 297, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 296, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 295, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 294, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 293, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 292, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 291, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 290, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 289, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 288, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 287, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 286, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 285, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 284, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 283, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 282, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 281, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 280, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 279, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 278, 3, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 277, 4, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 276, 4, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 275, 3, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 274, 4, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 273, 2, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 272, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 271, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 270, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 269, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 268, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 267, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 266, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 265, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 264, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 263, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 262, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 261, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 260, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 259, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 258, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 257, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 256, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 255, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 254, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 253, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 252, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 251, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 250, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 249, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 248, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 247, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 246, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 245, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 244, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 243, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 242, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 241, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 240, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 239, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 238, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 237, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 236, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 235, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 234, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 233, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 232, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 231, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 230, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 229, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 228, 3, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 227, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 226, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 225, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 224, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 223, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 222, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 221, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 220, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 219, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 218, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 217, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 216, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 215, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 214, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 213, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 212, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 211, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 210, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 209, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 208, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 207, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 206, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 205, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 204, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 203, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 202, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 201, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 200, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 199, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 198, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 197, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 196, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 195, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 194, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 193, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 192, 3, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 191, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 190, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 189, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 188, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 187, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 186, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 185, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 184, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 183, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 182, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 181, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 180, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 179, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 178, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 177, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 176, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 175, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 174, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 173, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 172, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 171, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 170, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 169, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 168, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 167, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 166, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 165, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 164, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 163, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 162, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 161, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 160, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 159, 4, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 158, 4, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 157, 5, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 156, 4, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 155, 5, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 154, 4, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 153, 5, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 152, 4, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 151, 5, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 150, 4, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 149, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 148, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 147, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 146, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 145, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 144, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 143, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 142, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 141, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 140, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 139, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 138, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 137, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 136, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 135, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 134, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 133, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 132, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 131, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 130, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 129, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 128, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 127, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 126, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 125, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 124, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 123, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 122, 2, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 121, 4, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 94, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 120, 2, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 119, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 118, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 117, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 116, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 115, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 114, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 113, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 112, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 111, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 110, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 109, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 108, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 107, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 106, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 105, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 104, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 103, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 102, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 101, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 100, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 99, 5, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 98, 5, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 97, 2, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 96, 5, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 95, 5, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 94, 5, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 93, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 92, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 91, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 90, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 89, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 88, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 87, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 86, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 85, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 84, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 83, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 82, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 81, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 80, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 79, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 78, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 77, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 76, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 75, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 74, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 73, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 72, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 71, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 70, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 69, 5, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 68, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 67, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 66, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 65, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 64, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 63, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 62, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 61, 4, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 60, 4, 2, 0, 0, 0, 0, AVRImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 59, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 58, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 57, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 56, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 55, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 54, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 53, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 52, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 51, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 50, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 49, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 48, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 47, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 46, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 45, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 44, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 43, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 42, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 41, 3, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 40, 2, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 39, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 38, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 37, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 36, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 35, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 34, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 33, 2, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 32, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 31, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 30, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 29, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 28, 6, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 27, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 26, 2, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 25, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 24, 4, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 23, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 22, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 21, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 20, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 19, 2, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 18, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 17, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 16, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 15, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 14, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 13, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 12, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 11, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 10, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 9, 4, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 8, 3, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 7, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 6, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 5, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 4, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 3, 1, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 2, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 1, 0, 0, 0, 0, 0, 0, AVRImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 0, 1, 1, 0, 0, 0, 0, AVRImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
}, {
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
{ -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) },
{ AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::GPRSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::GPRSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::GPRSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::IWREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::IWREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ AVR::LD8loRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8loRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
{ AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
}, {
AVR::SREG, AVR::SREG,
AVR::SREG,
AVR::SP, AVR::SP, AVR::SREG,
AVR::SP, AVR::R31R30,
AVR::R0,
AVR::R31R30,
AVR::SP, AVR::SP,
AVR::R1, AVR::SREG,
AVR::R17, AVR::SREG,
AVR::SP,
AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R1, AVR::R0,
AVR::R31R30, AVR::R0,
AVR::R1, AVR::R0, AVR::SREG,
AVR::R31R30, AVR::R1, AVR::R0,
AVR::R1, AVR::R0, AVR::R31R30,
}
};
#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char AVRInstrNameData[] = {
"G_FLOG10\0"
"G_FEXP10\0"
"ROLBRdR1\0"
"Lsl32\0"
"Asr32\0"
"Lsr32\0"
"G_FLOG2\0"
"G_FEXP2\0"
"AtomicLoadSub16\0"
"AtomicLoad16\0"
"AtomicLoadAdd16\0"
"AtomicLoadAnd16\0"
"AtomicStore16\0"
"Rol16\0"
"Lsl16\0"
"AtomicLoadOr16\0"
"Ror16\0"
"AtomicLoadXor16\0"
"Asr16\0"
"Lsr16\0"
"Select16\0"
"ROLBRdR17\0"
"AtomicLoadSub8\0"
"AtomicLoad8\0"
"AtomicLoadAdd8\0"
"AtomicLoadAnd8\0"
"AtomicStore8\0"
"Rol8\0"
"Lsl8\0"
"AtomicLoadOr8\0"
"Ror8\0"
"AtomicLoadXor8\0"
"Asr8\0"
"Lsr8\0"
"Select8\0"
"G_FMA\0"
"G_STRICT_FMA\0"
"INRdA\0"
"INWRdA\0"
"G_FSUB\0"
"G_STRICT_FSUB\0"
"G_ATOMICRMW_FSUB\0"
"G_SUB\0"
"G_ATOMICRMW_SUB\0"
"SBRCRrB\0"
"SBRSRrB\0"
"G_INTRINSIC\0"
"G_FPTRUNC\0"
"G_INTRINSIC_TRUNC\0"
"G_TRUNC\0"
"G_BUILD_VECTOR_TRUNC\0"
"G_DYN_STACKALLOC\0"
"SPREAD\0"
"G_FMAD\0"
"G_INDEXED_SEXTLOAD\0"
"G_SEXTLOAD\0"
"G_INDEXED_ZEXTLOAD\0"
"G_ZEXTLOAD\0"
"G_INDEXED_LOAD\0"
"G_LOAD\0"
"G_VECREDUCE_FADD\0"
"G_FADD\0"
"G_VECREDUCE_SEQ_FADD\0"
"G_STRICT_FADD\0"
"G_ATOMICRMW_FADD\0"
"G_VECREDUCE_ADD\0"
"G_ADD\0"
"G_PTR_ADD\0"
"G_ATOMICRMW_ADD\0"
"BLD\0"
"G_ATOMICRMW_NAND\0"
"G_VECREDUCE_AND\0"
"G_AND\0"
"G_ATOMICRMW_AND\0"
"LIFETIME_END\0"
"G_BRCOND\0"
"G_ATOMICRMW_USUB_COND\0"
"G_LLROUND\0"
"G_LROUND\0"
"G_INTRINSIC_ROUND\0"
"G_INTRINSIC_FPTRUNC_ROUND\0"
"LOAD_STACK_GUARD\0"
"PSEUDO_PROBE\0"
"G_SSUBE\0"
"G_USUBE\0"
"G_FENCE\0"
"ARITH_FENCE\0"
"REG_SEQUENCE\0"
"G_SADDE\0"
"G_UADDE\0"
"G_GET_FPMODE\0"
"G_RESET_FPMODE\0"
"G_SET_FPMODE\0"
"G_FMINNUM_IEEE\0"
"G_FMAXNUM_IEEE\0"
"G_VSCALE\0"
"G_JUMP_TABLE\0"
"BUNDLE\0"
"G_MEMCPY_INLINE\0"
"LOCAL_ESCAPE\0"
"G_STACKRESTORE\0"
"G_INDEXED_STORE\0"
"G_STORE\0"
"CPSE\0"
"G_BITREVERSE\0"
"FAKE_USE\0"
"SPWRITE\0"
"DBG_VALUE\0"
"G_GLOBAL_VALUE\0"
"G_PTRAUTH_GLOBAL_VALUE\0"
"CONVERGENCECTRL_GLUE\0"
"G_STACKSAVE\0"
"G_MEMMOVE\0"
"G_FREEZE\0"
"G_FCANONICALIZE\0"
"G_CTLZ_ZERO_UNDEF\0"
"G_CTTZ_ZERO_UNDEF\0"
"INIT_UNDEF\0"
"G_IMPLICIT_DEF\0"
"DBG_INSTR_REF\0"
"G_FNEG\0"
"EXTRACT_SUBREG\0"
"INSERT_SUBREG\0"
"G_SEXT_INREG\0"
"SUBREG_TO_REG\0"
"G_ATOMIC_CMPXCHG\0"
"G_ATOMICRMW_XCHG\0"
"G_FLOG\0"
"G_VAARG\0"
"PREALLOCATED_ARG\0"
"G_PREFETCH\0"
"G_SMULH\0"
"G_UMULH\0"
"G_FTANH\0"
"G_FSINH\0"
"G_FCOSH\0"
"DBG_PHI\0"
"G_FPTOSI\0"
"RETI\0"
"G_FPTOUI\0"
"G_FPOWI\0"
"BREAK\0"
"G_PTRMASK\0"
"DESK\0"
"SUBIRdK\0"
"SBCIRdK\0"
"LDIRdK\0"
"ANDIRdK\0"
"CPIRdK\0"
"ORIRdK\0"
"LDSRdK\0"
"SBIWRdK\0"
"SUBIWRdK\0"
"SBCIWRdK\0"
"ADIWRdK\0"
"LDIWRdK\0"
"ANDIWRdK\0"
"ORIWRdK\0"
"LDSWRdK\0"
"GC_LABEL\0"
"DBG_LABEL\0"
"EH_LABEL\0"
"ANNOTATION_LABEL\0"
"ICALL_BRANCH_FUNNEL\0"
"G_FSHL\0"
"G_SHL\0"
"G_FCEIL\0"
"EICALL\0"
"PATCHABLE_TAIL_CALL\0"
"PATCHABLE_TYPED_EVENT_CALL\0"
"PATCHABLE_EVENT_CALL\0"
"FENTRY_CALL\0"
"KILL\0"
"G_CONSTANT_POOL\0"
"G_ROTL\0"
"G_VECREDUCE_FMUL\0"
"G_FMUL\0"
"G_VECREDUCE_SEQ_FMUL\0"
"G_STRICT_FMUL\0"
"G_VECREDUCE_MUL\0"
"G_MUL\0"
"G_FREM\0"
"G_STRICT_FREM\0"
"G_SREM\0"
"G_UREM\0"
"G_SDIVREM\0"
"G_UDIVREM\0"
"ELPM\0"
"SPM\0"
"INLINEASM\0"
"G_VECREDUCE_FMINIMUM\0"
"G_FMINIMUM\0"
"G_VECREDUCE_FMAXIMUM\0"
"G_FMAXIMUM\0"
"G_FMINNUM\0"
"G_FMAXNUM\0"
"G_FATAN\0"
"G_FTAN\0"
"G_INTRINSIC_ROUNDEVEN\0"
"G_ASSERT_ALIGN\0"
"G_FCOPYSIGN\0"
"G_VECREDUCE_FMIN\0"
"G_ATOMICRMW_FMIN\0"
"G_VECREDUCE_SMIN\0"
"G_SMIN\0"
"G_VECREDUCE_UMIN\0"
"G_UMIN\0"
"G_ATOMICRMW_UMIN\0"
"G_ATOMICRMW_MIN\0"
"G_FASIN\0"
"G_FSIN\0"
"CFI_INSTRUCTION\0"
"ADJCALLSTACKDOWN\0"
"G_SSUBO\0"
"G_USUBO\0"
"G_SADDO\0"
"G_UADDO\0"
"JUMP_TABLE_DEBUG_INFO\0"
"G_SMULO\0"
"G_UMULO\0"
"G_BZERO\0"
"STACKMAP\0"
"G_DEBUGTRAP\0"
"G_UBSANTRAP\0"
"G_TRAP\0"
"G_ATOMICRMW_UDEC_WRAP\0"
"G_ATOMICRMW_UINC_WRAP\0"
"G_BSWAP\0"
"SLEEP\0"
"G_SITOFP\0"
"G_UITOFP\0"
"G_FCMP\0"
"G_ICMP\0"
"G_SCMP\0"
"G_UCMP\0"
"EIJMP\0"
"NOP\0"
"CONVERGENCECTRL_LOOP\0"
"G_CTPOP\0"
"PATCHABLE_OP\0"
"FAULTING_OP\0"
"ADJCALLSTACKUP\0"
"PREALLOCATED_SETUP\0"
"G_FLDEXP\0"
"G_STRICT_FLDEXP\0"
"G_FEXP\0"
"G_FFREXP\0"
"LDDWRdYQ\0"
"LDDRdPtrQ\0"
"LDDWRdPtrQ\0"
"G_BR\0"
"INLINEASM_BR\0"
"G_BLOCK_ADDR\0"
"WDR\0"
"MEMBARRIER\0"
"G_CONSTANT_FOLD_BARRIER\0"
"PATCHABLE_FUNCTION_ENTER\0"
"G_READCYCLECOUNTER\0"
"G_READSTEADYCOUNTER\0"
"G_READ_REGISTER\0"
"G_WRITE_REGISTER\0"
"G_ASHR\0"
"G_FSHR\0"
"G_LSHR\0"
"CONVERGENCECTRL_ANCHOR\0"
"G_FFLOOR\0"
"G_EXTRACT_SUBVECTOR\0"
"G_INSERT_SUBVECTOR\0"
"G_BUILD_VECTOR\0"
"G_SHUFFLE_VECTOR\0"
"G_SPLAT_VECTOR\0"
"G_VECREDUCE_XOR\0"
"G_XOR\0"
"G_ATOMICRMW_XOR\0"
"G_VECREDUCE_OR\0"
"G_OR\0"
"G_ATOMICRMW_OR\0"
"G_ROTR\0"
"G_INTTOPTR\0"
"G_FABS\0"
"G_ABS\0"
"G_UNMERGE_VALUES\0"
"G_MERGE_VALUES\0"
"FMULS\0"
"G_FACOS\0"
"G_FCOS\0"
"G_CONCAT_VECTORS\0"
"COPY_TO_REGCLASS\0"
"G_IS_FPCLASS\0"
"G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
"G_VECTOR_COMPRESS\0"
"G_INTRINSIC_W_SIDE_EFFECTS\0"
"G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
"G_SSUBSAT\0"
"G_USUBSAT\0"
"G_SADDSAT\0"
"G_UADDSAT\0"
"G_SSHLSAT\0"
"G_USHLSAT\0"
"G_SMULFIXSAT\0"
"G_UMULFIXSAT\0"
"G_SDIVFIXSAT\0"
"G_UDIVFIXSAT\0"
"G_ATOMICRMW_USUB_SAT\0"
"G_FPTOSI_SAT\0"
"G_FPTOUI_SAT\0"
"G_EXTRACT\0"
"G_SELECT\0"
"G_BRINDIRECT\0"
"PATCHABLE_RET\0"
"G_MEMSET\0"
"PATCHABLE_FUNCTION_EXIT\0"
"G_BRJT\0"
"G_EXTRACT_VECTOR_ELT\0"
"G_INSERT_VECTOR_ELT\0"
"G_FCONSTANT\0"
"G_CONSTANT\0"
"G_INTRINSIC_CONVERGENT\0"
"STATEPOINT\0"
"PATCHPOINT\0"
"G_PTRTOINT\0"
"G_FRINT\0"
"G_INTRINSIC_LLRINT\0"
"G_INTRINSIC_LRINT\0"
"G_FNEARBYINT\0"
"G_VASTART\0"
"LIFETIME_START\0"
"G_INVOKE_REGION_START\0"
"G_INSERT\0"
"G_FSQRT\0"
"G_STRICT_FSQRT\0"
"G_BITCAST\0"
"G_ADDRSPACE_CAST\0"
"BST\0"
"DBG_VALUE_LIST\0"
"G_FPEXT\0"
"G_SEXT\0"
"G_ASSERT_SEXT\0"
"G_ANYEXT\0"
"G_ZEXT\0"
"G_ASSERT_ZEXT\0"
"FMULSU\0"
"G_FDIV\0"
"G_STRICT_FDIV\0"
"G_SDIV\0"
"G_UDIV\0"
"G_GET_FPENV\0"
"G_RESET_FPENV\0"
"G_SET_FPENV\0"
"G_FPOW\0"
"G_VECREDUCE_FMAX\0"
"G_ATOMICRMW_FMAX\0"
"G_VECREDUCE_SMAX\0"
"G_SMAX\0"
"G_VECREDUCE_UMAX\0"
"G_UMAX\0"
"G_ATOMICRMW_UMAX\0"
"G_ATOMICRMW_MAX\0"
"FRMIDX\0"
"G_FRAME_INDEX\0"
"G_SBFX\0"
"G_UBFX\0"
"G_SMULFIX\0"
"G_UMULFIX\0"
"G_SDIVFIX\0"
"G_UDIVFIX\0"
"G_MEMCPY\0"
"COPY\0"
"CONVERGENCECTRL_ENTRY\0"
"G_CTLZ\0"
"G_CTTZ\0"
"ELPMBRdZ\0"
"ELPMRdZ\0"
"ELPMWRdZ\0"
"SBICAb\0"
"CBIAb\0"
"SBIAb\0"
"SBISAb\0"
"LDRdPtrPd\0"
"LDWRdPtrPd\0"
"RORBRd\0"
"DECRd\0"
"INCRd\0"
"NEGRd\0"
"COMRd\0"
"LSLBNRd\0"
"ASRBNRd\0"
"LSRBNRd\0"
"LSLWNRd\0"
"ASRWNRd\0"
"LSRWNRd\0"
"SWAPRd\0"
"POPRd\0"
"RORRd\0"
"ASRRd\0"
"LSRRd\0"
"NEGWRd\0"
"ROLWRd\0"
"LSLWRd\0"
"COMWRd\0"
"POPWRd\0"
"RORWRd\0"
"ASRWRd\0"
"LSRWRd\0"
"LACZRd\0"
"XCHZRd\0"
"LASZRd\0"
"LATZRd\0"
"LSLWHiRd\0"
"ASRWLoRd\0"
"LSRWLoRd\0"
"AtomicFence\0"
"SPMZPi\0"
"ELPMBRdZPi\0"
"ELPMRdZPi\0"
"ELPMWRdZPi\0"
"LDRdPtrPi\0"
"LDWRdPtrPi\0"
"BRGEk\0"
"BRNEk\0"
"BRSHk\0"
"BRMIk\0"
"RCALLk\0"
"BRPLk\0"
"BRLOk\0"
"RJMPk\0"
"BREQk\0"
"BRLTk\0"
"BRBCsk\0"
"BRBSsk\0"
"CopyZero\0"
"OUTARr\0"
"OUTWARr\0"
"PUSHRr\0"
"STSKRr\0"
"STSWKRr\0"
"STDSPQRr\0"
"STDWSPQRr\0"
"STDPtrQRr\0"
"STDWPtrQRr\0"
"PUSHWRr\0"
"STPtrPdRr\0"
"STWPtrPdRr\0"
"SUBRdRr\0"
"SBCRdRr\0"
"ADCRdRr\0"
"CPCRdRr\0"
"ADDRdRr\0"
"ANDRdRr\0"
"MULRdRr\0"
"CPRdRr\0"
"EORRdRr\0"
"MULSRdRr\0"
"MULSURdRr\0"
"MOVRdRr\0"
"SUBWRdRr\0"
"SBCWRdRr\0"
"ADCWRdRr\0"
"CPCWRdRr\0"
"ADDWRdRr\0"
"ANDWRdRr\0"
"CPWRdRr\0"
"EORWRdRr\0"
"MOVWRdRr\0"
"STPtrPiRr\0"
"STWPtrPiRr\0"
"STPtrRr\0"
"STWPtrRr\0"
"LDRdPtr\0"
"LDWRdPtr\0"
"BCLRs\0"
"BSETs\0"
"LDSRdKTiny\0"
"STSKRrTiny\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif
extern const unsigned AVRInstrNameIndices[] = {
1602U, 2123U, 2840U, 2411U, 1796U, 1777U, 1805U, 1950U,
1425U, 1440U, 1391U, 1378U, 1467U, 3315U, 1226U, 3991U,
1404U, 1598U, 1786U, 994U, 4351U, 1116U, 3891U, 821U,
945U, 982U, 2522U, 1938U, 3801U, 928U, 2745U, 1530U,
3790U, 1139U, 2718U, 2705U, 2905U, 3649U, 3672U, 1870U,
1917U, 1890U, 1822U, 1209U, 2870U, 2476U, 4356U, 3023U,
2676U, 1274U, 4021U, 4051U, 2254U, 730U, 418U, 2053U,
4093U, 4100U, 2080U, 2087U, 2094U, 2104U, 799U, 3194U,
3157U, 1389U, 1600U, 4274U, 1236U, 1251U, 1955U, 3617U,
3245U, 3928U, 3262U, 3094U, 504U, 3298U, 3812U, 3221U,
3960U, 1317U, 2881U, 902U, 478U, 884U, 3850U, 3831U,
2232U, 2930U, 2949U, 631U, 575U, 605U, 616U, 556U,
586U, 1183U, 1167U, 3345U, 1481U, 1498U, 746U, 424U,
805U, 766U, 3199U, 3163U, 4251U, 2380U, 4234U, 2363U,
697U, 401U, 4169U, 2298U, 2584U, 2562U, 843U, 3570U,
974U, 1547U, 834U, 3636U, 3906U, 456U, 3393U, 3767U,
3420U, 4035U, 496U, 3756U, 3744U, 3881U, 1522U, 4014U,
1454U, 4044U, 1849U, 3016U, 3002U, 1842U, 3009U, 3214U,
1971U, 2645U, 2638U, 2652U, 2659U, 3627U, 2468U, 1015U,
2452U, 966U, 2460U, 1007U, 2444U, 958U, 2506U, 2498U,
1566U, 1558U, 3488U, 3478U, 3468U, 3458U, 3508U, 3498U,
4302U, 4312U, 3518U, 3531U, 4322U, 4332U, 3544U, 3557U,
655U, 380U, 1995U, 348U, 549U, 4072U, 2059U, 4145U,
1629U, 2789U, 53U, 9U, 1515U, 45U, 0U, 2764U,
2796U, 1418U, 4006U, 468U, 1606U, 1620U, 2620U, 2629U,
3591U, 3604U, 3232U, 2269U, 3332U, 1326U, 2197U, 2207U,
1064U, 1079U, 2154U, 2186U, 4107U, 4133U, 4119U, 1023U,
1051U, 1036U, 736U, 1643U, 2332U, 4203U, 2356U, 4227U,
3239U, 875U, 865U, 2835U, 3696U, 1094U, 3075U, 3055U,
3724U, 3703U, 3109U, 3126U, 3375U, 4385U, 1360U, 4378U,
1342U, 2697U, 2606U, 1196U, 1855U, 3291U, 2404U, 2225U,
3283U, 2396U, 2217U, 1590U, 1582U, 1574U, 3937U, 3046U,
3823U, 3868U, 3970U, 2853U, 1103U, 525U, 1295U, 1152U,
683U, 387U, 2023U, 4079U, 2066U, 354U, 3945U, 2773U,
2969U, 2985U, 4342U, 1123U, 1307U, 3663U, 2514U, 2555U,
2531U, 2543U, 662U, 2002U, 638U, 1978U, 4152U, 2281U,
2165U, 2133U, 714U, 2037U, 783U, 3179U, 3141U, 4186U,
2315U, 4210U, 2339U, 4288U, 4295U, 5064U, 5082U, 2427U,
2730U, 1752U, 5091U, 4504U, 4668U, 4528U, 4617U, 185U,
33U, 330U, 4686U, 77U, 231U, 90U, 243U, 106U,
258U, 148U, 296U, 61U, 216U, 169U, 315U, 122U,
273U, 4596U, 5073U, 5100U, 4833U, 4392U, 4705U, 4409U,
4726U, 5108U, 4267U, 373U, 2824U, 2805U, 1744U, 1769U,
5172U, 4454U, 4747U, 4393U, 4410U, 4727U, 4496U, 4659U,
4520U, 4589U, 4512U, 4677U, 4536U, 4624U, 142U, 27U,
291U, 191U, 39U, 335U, 4575U, 1761U, 5109U, 4849U,
4603U, 4919U, 18U, 206U, 4582U, 4465U, 4610U, 136U,
286U, 163U, 310U, 1727U, 5055U, 4016U, 542U, 1218U,
4879U, 4908U, 4888U, 4871U, 4937U, 5136U, 5155U, 1718U,
5046U, 197U, 340U, 4046U, 4964U, 4980U, 1736U, 1681U,
4988U, 4563U, 5181U, 762U, 4819U, 4826U, 1637U, 4807U,
4758U, 4795U, 4813U, 4776U, 4764U, 4789U, 4770U, 5187U,
3987U, 4783U, 4425U, 4490U, 4972U, 1689U, 5004U, 1191U,
4472U, 1653U, 1863U, 2666U, 2114U, 4401U, 4716U, 5011U,
1990U, 3277U, 4065U, 1864U, 2667U, 4478U, 367U, 4802U,
4631U, 4645U, 4652U, 2814U, 1674U, 5164U, 4444U, 4737U,
1703U, 5193U, 2115U, 4402U, 4717U, 4569U, 5038U, 5117U,
4996U, 5019U, 5028U, 4484U, 2672U, 1696U, 5012U, 4842U,
4551U, 4857U, 4782U, 3659U, 1615U, 4801U, 4557U, 1666U,
4956U, 4431U, 4418U, 4437U, 1710U, 440U, 448U, 2614U,
2119U, 4698U, 4898U, 4927U, 5126U, 5147U, 4864U, 5204U,
1658U, 4948U, 4544U, 2866U, 4638U,
};
static inline void InitAVRMCInstrInfo(MCInstrInfo *II) {
II->InitMCInstrInfo(AVRDescs.Insts, AVRInstrNameIndices, AVRInstrNameData, nullptr, nullptr, 493);
}
}
#endif
#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER
namespace llvm {
struct AVRGenInstrInfo : public TargetInstrInfo { … };
}
#endif
#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS
#endif
#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS
#endif
#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR
namespace llvm {
extern const AVRInstrTable AVRDescs;
extern const unsigned AVRInstrNameIndices[];
extern const char AVRInstrNameData[];
AVRGenInstrInfo::AVRGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
: TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
InitMCInstrInfo(AVRDescs.Insts, AVRInstrNameIndices, AVRInstrNameData, nullptr, nullptr, 493);
}
}
#endif
#ifdef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_OPERAND_ENUM
namespace llvm {
namespace AVR {
namespace OpName {
enum {
OPERAND_LAST
};
}
}
}
#endif
#ifdef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_NAMED_OPS
namespace llvm {
namespace AVR {
LLVM_READONLY
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
return -1;
}
}
}
#endif
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
namespace llvm {
namespace AVR {
namespace OpTypes {
enum OperandType {
LDDSTDPtrReg = 0,
LDSTPtrReg = 1,
brtarget_13 = 2,
call_target = 3,
f32imm = 4,
f64imm = 5,
i1imm = 6,
i8imm = 7,
i16imm = 8,
i32imm = 9,
i64imm = 10,
imm7tiny = 11,
imm16 = 12,
imm_arith6 = 13,
imm_com8 = 14,
imm_ldi8 = 15,
imm_port5 = 16,
imm_port6 = 17,
memri = 18,
memspi = 19,
ptype0 = 20,
ptype1 = 21,
ptype2 = 22,
ptype3 = 23,
ptype4 = 24,
ptype5 = 25,
rcalltarget_13 = 26,
relbrtarget_7 = 27,
type0 = 28,
type1 = 29,
type2 = 30,
type3 = 31,
type4 = 32,
type5 = 33,
untyped_imm_0 = 34,
CCR = 35,
DLDREGS = 36,
DREGS = 37,
DREGSLD8lo = 38,
DREGSMOVW = 39,
DREGSlo = 40,
GPR8 = 41,
GPR8lo = 42,
GPRSP = 43,
IWREGS = 44,
LD8 = 45,
LD8lo = 46,
PTRDISPREGS = 47,
PTRREGS = 48,
ZREG = 49,
OPERAND_TYPE_LIST_END
};
}
}
}
#endif
#ifdef GET_INSTRINFO_OPERAND_TYPE
#undef GET_INSTRINFO_OPERAND_TYPE
namespace llvm {
namespace AVR {
LLVM_READONLY
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
static const uint16_t Offsets[] = {
0,
1,
1,
1,
2,
3,
4,
5,
5,
8,
12,
13,
14,
18,
21,
21,
21,
21,
21,
22,
24,
26,
26,
27,
28,
32,
34,
36,
36,
42,
43,
44,
47,
47,
49,
50,
50,
50,
50,
50,
50,
52,
55,
55,
55,
55,
56,
57,
58,
60,
61,
64,
67,
70,
73,
76,
79,
82,
85,
88,
91,
95,
99,
102,
105,
108,
109,
110,
112,
114,
119,
121,
124,
126,
130,
132,
134,
136,
138,
140,
142,
144,
146,
148,
151,
153,
155,
157,
159,
161,
162,
163,
165,
167,
169,
174,
179,
184,
186,
191,
196,
200,
203,
206,
209,
212,
215,
218,
221,
224,
227,
230,
233,
236,
239,
242,
245,
248,
251,
254,
257,
259,
263,
265,
266,
266,
267,
268,
269,
270,
272,
274,
276,
278,
279,
282,
284,
287,
289,
292,
295,
298,
302,
306,
309,
312,
316,
320,
323,
326,
330,
334,
339,
343,
348,
352,
357,
361,
366,
370,
374,
377,
380,
383,
386,
389,
392,
395,
398,
402,
406,
410,
414,
418,
422,
426,
430,
433,
436,
439,
443,
447,
450,
453,
456,
459,
461,
463,
465,
467,
469,
471,
474,
477,
479,
481,
483,
485,
487,
489,
491,
493,
495,
497,
500,
503,
505,
508,
511,
514,
517,
520,
523,
524,
525,
525,
526,
527,
527,
530,
533,
536,
539,
542,
545,
547,
549,
551,
552,
555,
557,
561,
564,
568,
571,
575,
577,
581,
583,
585,
587,
589,
591,
593,
595,
597,
599,
601,
603,
605,
607,
609,
611,
613,
615,
617,
619,
621,
623,
625,
627,
629,
632,
633,
634,
637,
640,
643,
646,
649,
653,
655,
658,
660,
662,
666,
669,
673,
677,
680,
680,
680,
681,
684,
687,
689,
691,
693,
695,
697,
699,
701,
703,
705,
707,
709,
711,
713,
715,
717,
721,
725,
728,
731,
733,
735,
738,
741,
744,
746,
749,
751,
754,
759,
762,
762,
764,
766,
769,
772,
775,
778,
781,
784,
787,
790,
793,
796,
798,
800,
802,
804,
806,
807,
810,
813,
816,
819,
822,
825,
827,
830,
833,
835,
837,
839,
842,
845,
847,
849,
851,
854,
856,
859,
861,
864,
866,
869,
871,
874,
879,
882,
885,
890,
893,
896,
899,
902,
904,
905,
906,
908,
910,
912,
914,
916,
919,
922,
925,
928,
931,
934,
936,
938,
940,
943,
946,
949,
951,
955,
959,
961,
964,
967,
971,
975,
977,
980,
983,
986,
989,
992,
994,
995,
998,
1000,
1002,
1002,
1003,
1004,
1005,
1006,
1007,
1008,
1009,
1010,
1011,
1013,
1014,
1016,
1018,
1020,
1022,
1024,
1026,
1028,
1029,
1029,
1029,
1029,
1031,
1033,
1036,
1038,
1040,
1042,
1042,
1042,
1044,
1046,
1047,
1049,
1051,
1053,
1056,
1058,
1060,
1063,
1066,
1068,
1070,
1070,
1072,
1074,
1076,
1078,
1080,
1082,
1084,
1086,
1088,
1088,
1091,
1094,
1096,
1097,
1098,
1099,
1099,
1099,
1100,
1102,
1105,
1108,
1110,
1112,
1114,
1117,
1119,
1121,
1121,
1121,
1122,
1125,
1129,
1133,
1135,
1137,
1139,
1142,
1145,
1147,
1147,
};
using namespace OpTypes;
static const int8_t OpcodeOperandTypes[] = {
-1,
i32imm,
i32imm,
i32imm,
i32imm,
-1, -1, i32imm,
-1, -1, -1, i32imm,
-1,
-1,
-1, -1, -1, i32imm,
-1, -1, i32imm,
-1,
-1, -1,
-1, -1,
i32imm,
i32imm,
i64imm, i64imm, i8imm, i32imm,
-1, -1,
i64imm, i32imm,
-1, i64imm, i32imm, -1, i32imm, i32imm,
-1,
i32imm,
-1, i32imm, i32imm,
-1, i32imm,
-1,
-1, -1,
-1, -1, -1,
i64imm,
-1,
-1,
-1, -1,
-1,
type0, type0, untyped_imm_0,
type0, type0, untyped_imm_0,
type0, type0, untyped_imm_0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0, type0,
type0, type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0,
type0,
type0, -1,
type0, -1,
type0, -1, i32imm, type1, i64imm,
type0, -1,
type0, type1, untyped_imm_0,
type0, type1,
type0, type0, type1, untyped_imm_0,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type0,
type0, type0,
type0, type1, i32imm,
type0, type0,
type0, type0,
type0, type1,
type0, type1,
type0, type0,
type0,
type0,
type0, ptype1,
type0, ptype1,
type0, ptype1,
type0, ptype1, ptype1, type2, -1,
type0, ptype1, ptype1, type2, -1,
type0, ptype1, ptype1, type2, -1,
type0, ptype1,
ptype0, type1, ptype0, ptype2, -1,
type0, type1, type2, type0, type0,
type0, ptype1, type0, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
i32imm, i32imm,
ptype0, i32imm, i32imm, i32imm,
type0, -1,
type0,
-1,
-1,
-1,
-1,
type0, type1,
type0, type1,
type0, -1,
type0, -1,
type0,
type0, type1, -1,
type0, type1,
type0, type0, untyped_imm_0,
type0, type1,
type0, type0, type1,
type0, type0, type1,
type0, type0, type1,
type0, type0, type0, type1,
type0, type0, type0, type1,
type0, type0, type1,
type0, type0, type1,
type0, -1, type1, type1,
type0, -1, type1, type1,
type0, type1, type1,
type0, type1, type1,
type0, type1, type0, type0,
type0, type1, type0, type0,
type0, type1, type0, type0, type1,
type0, type1, type0, type0,
type0, type1, type0, type0, type1,
type0, type1, type0, type0,
type0, type1, type0, type0, type1,
type0, type1, type0, type0,
type0, type1, type0, type0, type1,
type0, type1, type0, type0,
type0, type1, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type1,
type0, type0, type1,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0, type0,
type0, type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type1,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0, type1,
type0, type1, type0,
type0, type0,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type0,
type0, type0, type1,
type0, type1, -1,
type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0,
type0,
type0,
type0,
ptype0, ptype0, type1,
ptype0, ptype0, type1,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0,
type0, type1,
type0, type1,
-1,
ptype0, -1, type1,
type0, -1,
type0, type0, type1, untyped_imm_0,
type0, type0, untyped_imm_0,
type0, type0, type1, type2,
type0, type1, type2,
type0, type1, type1, -1,
type0, type1,
type0, type0, type1, type0,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type1,
type0, -1,
type0, -1,
ptype0, type1, i32imm,
ptype0,
ptype0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0, type0,
type0, type0,
type0, type0, type1,
type0, -1,
-1, type0,
ptype0, ptype1, type2, untyped_imm_0,
ptype0, ptype1, type2,
ptype0, ptype1, type2, untyped_imm_0,
ptype0, type1, type2, untyped_imm_0,
ptype0, type1, untyped_imm_0,
i8imm,
type0, type1, type2,
type0, type1, type2,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type0, type1, type1,
type0, type0, type1, type1,
DREGS, DREGS, DREGS,
DREGS, DREGS, DREGS,
i16imm, i16imm,
i16imm, i16imm,
DLDREGS, DLDREGS, i16imm,
DREGS, DREGS, DREGS,
LD8, GPR8, imm_ldi8,
DREGS, DREGS,
DREGS, DREGS, imm16,
DREGS, DREGS,
DREGS, DREGS, GPR8,
DREGS, DREGS, DREGS, DREGS, i8imm,
GPR8, GPR8, GPR8,
DREGS, PTRDISPREGS,
GPR8, PTRREGS,
DREGS, PTRDISPREGS, DREGS,
GPR8, PTRREGS, GPR8,
DREGS, PTRDISPREGS, DREGS,
GPR8, PTRREGS, GPR8,
DREGS, PTRDISPREGS, DREGS,
GPR8, PTRREGS, GPR8,
DREGS, PTRDISPREGS, DREGS,
GPR8, PTRREGS, GPR8,
DREGS, PTRDISPREGS, DREGS,
GPR8, PTRREGS, GPR8,
PTRDISPREGS, DREGS,
PTRREGS, GPR8,
DREGS, DREGS,
DREGS, DREGS,
DREGS, DREGS,
GPR8,
GPR8, ZREG, LD8,
GPR8, ZREG, LD8,
DREGS, ZREG, LD8,
DREGS, ZREG, LD8,
DREGS, DREGS, DREGS,
DLDREGS, DLDREGS, i16imm,
DREGS, imm_port6,
DREGS, PTRDISPREGS, i16imm,
DREGS, PTRDISPREGS, i16imm,
DLDREGS, i16imm,
DREGS, i16imm,
DREGS, PTRDISPREGS,
DREGS, PTRREGS, PTRREGS,
DREGS, PTRREGS, PTRREGS,
GPR8, ZREG,
DREGS, ZREG,
DREGS, ZREG,
LD8, GPR8, imm_ldi8,
DREGS, DREGS,
DLDREGS, DREGS, imm16,
DREGS, DREGS,
LD8, GPR8, imm_ldi8,
DREGS, DREGS,
DLDREGS, DREGS, imm16,
DREGS, DREGS,
DREGS, DREGS, GPR8,
DREGS, DREGS, DREGS, DREGS, i8imm,
GPR8, GPR8, GPR8,
DREGS, DREGS, GPR8,
DREGS, DREGS, DREGS, DREGS, i8imm,
GPR8, GPR8, GPR8,
DREGS, DREGS, GPR8,
DLDREGS, DLDREGS, i16imm,
DREGS, DREGS, DREGS,
imm_port6, DREGS,
DREGS,
DREGS,
GPR8, GPR8,
GPR8, GPR8,
DREGS, DREGS,
GPR8, GPR8,
DREGS, DREGS,
DREGS, DREGS, GPR8,
GPR8, GPR8, GPR8,
DREGS, DREGS, GPR8,
GPR8, GPR8, GPR8,
DLDREGS, DLDREGS, i16imm,
DREGS, DREGS, DREGS,
DREGS, GPR8,
DREGS, GPRSP,
GPRSP, DREGS,
GPRSP, i16imm, GPR8,
PTRDISPREGS, i16imm, DREGS,
GPRSP, i16imm, DREGS,
i16imm, DREGS,
PTRREGS, PTRREGS, DREGS, i8imm,
PTRREGS, PTRREGS, DREGS, i8imm,
PTRDISPREGS, DREGS,
DLDREGS, DLDREGS, i16imm,
DREGS, DREGS, DREGS,
DREGS, DREGS, DREGS, i8imm,
GPR8, GPR8, GPR8, i8imm,
DREGS, GPR8,
GPR8, GPR8, GPR8,
GPR8, GPR8, GPR8,
IWREGS, IWREGS, imm_arith6,
LD8, LD8, imm_ldi8,
GPR8, GPR8, GPR8,
GPR8, GPR8,
i8imm,
GPR8, GPR8, i8imm,
i8imm, relbrtarget_7,
i8imm, relbrtarget_7,
relbrtarget_7,
relbrtarget_7,
relbrtarget_7,
relbrtarget_7,
relbrtarget_7,
relbrtarget_7,
relbrtarget_7,
relbrtarget_7,
i8imm,
GPR8, i8imm,
call_target,
imm_port5, i8imm,
GPR8, GPR8,
GPR8, GPR8,
LD8, imm_ldi8,
GPR8, GPR8,
GPR8, GPR8,
GPR8, GPR8,
i8imm,
GPR8, ZREG,
GPR8, ZREG,
GPR8, GPR8, GPR8,
LD8lo, LD8lo,
LD8lo, LD8lo,
LD8lo, LD8lo,
GPR8, GPR8,
GPR8, imm_port6,
call_target,
GPR8, ZREG,
GPR8, ZREG,
GPR8, ZREG,
GPR8, PTRDISPREGS, i16imm,
LD8, imm_ldi8,
GPR8, PTRREGS,
GPR8, PTRREGS, PTRREGS,
GPR8, PTRREGS, PTRREGS,
GPR8, imm16,
LD8, imm7tiny,
GPR8, ZREG,
GPR8, ZREG,
GPR8, GPR8,
GPR8, GPR8,
DREGS, DREGS,
GPR8, GPR8,
LD8, LD8,
LD8lo, LD8lo,
GPR8, GPR8,
LD8, LD8, imm_ldi8,
GPR8, GPR8, GPR8,
imm_port6, GPR8,
GPR8,
GPR8,
rcalltarget_13,
brtarget_13,
GPR8, GPR8,
LD8, LD8, imm_ldi8,
GPR8, GPR8, GPR8,
imm_port5, i8imm,
imm_port5, i8imm,
imm_port5, i8imm,
IWREGS, IWREGS, imm_arith6,
GPR8, i8imm,
GPR8, i8imm,
ZREG,
PTRDISPREGS, i16imm, GPR8,
PTRREGS, PTRREGS, GPR8, i8imm,
PTRREGS, PTRREGS, GPR8, i8imm,
PTRREGS, GPR8,
imm16, GPR8,
imm7tiny, LD8,
LD8, LD8, imm_ldi8,
GPR8, GPR8, GPR8,
GPR8, GPR8,
GPR8, ZREG,
};
return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
}
}
}
#endif
#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
namespace llvm {
namespace AVR {
LLVM_READONLY
static int getMemOperandSize(int OpType) {
switch (OpType) {
default: return 0;
}
}
}
}
#endif
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
namespace llvm {
namespace AVR {
LLVM_READONLY static unsigned
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
return LogicalOpIdx;
}
LLVM_READONLY static inline unsigned
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
auto S = 0U;
for (auto i = 0U; i < LogicalOpIdx; ++i)
S += getLogicalOperandSize(Opcode, i);
return S;
}
}
}
#endif
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
namespace llvm {
namespace AVR {
LLVM_READONLY static int
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
return -1;
}
}
}
#endif
#ifdef GET_INSTRINFO_MC_HELPER_DECLS
#undef GET_INSTRINFO_MC_HELPER_DECLS
namespace llvm {
class MCInst;
class FeatureBitset;
namespace AVR_MC {
void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
}
}
#endif
#ifdef GET_INSTRINFO_MC_HELPERS
#undef GET_INSTRINFO_MC_HELPERS
namespace llvm {
namespace AVR_MC {
}
}
#endif
#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
defined(GET_AVAILABLE_OPCODE_CHECKER)
#define GET_COMPUTE_FEATURES
#endif
#ifdef GET_COMPUTE_FEATURES
#undef GET_COMPUTE_FEATURES
namespace llvm {
namespace AVR_MC {
enum SubtargetFeatureBits : uint8_t {
Feature_HasSRAMBit = 14,
Feature_HasJMPCALLBit = 7,
Feature_HasIJMPCALLBit = 6,
Feature_HasEIJMPCALLBit = 3,
Feature_HasADDSUBIWBit = 0,
Feature_HasSmallStackBit = 15,
Feature_HasMOVWBit = 10,
Feature_HasLPMBit = 8,
Feature_HasLPMXBit = 9,
Feature_HasELPMBit = 4,
Feature_HasELPMXBit = 5,
Feature_HasSPMBit = 12,
Feature_HasSPMXBit = 13,
Feature_HasDESBit = 2,
Feature_SupportsRMWBit = 18,
Feature_SupportsMultiplicationBit = 17,
Feature_HasBREAKBit = 1,
Feature_HasTinyEncodingBit = 16,
Feature_HasNonTinyEncodingBit = 11,
};
inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
FeatureBitset Features;
if (FB[AVR::FeatureSRAM])
Features.set(Feature_HasSRAMBit);
if (FB[AVR::FeatureJMPCALL])
Features.set(Feature_HasJMPCALLBit);
if (FB[AVR::FeatureIJMPCALL])
Features.set(Feature_HasIJMPCALLBit);
if (FB[AVR::FeatureEIJMPCALL])
Features.set(Feature_HasEIJMPCALLBit);
if (FB[AVR::FeatureADDSUBIW])
Features.set(Feature_HasADDSUBIWBit);
if (FB[AVR::FeatureSmallStack])
Features.set(Feature_HasSmallStackBit);
if (FB[AVR::FeatureMOVW])
Features.set(Feature_HasMOVWBit);
if (FB[AVR::FeatureLPM])
Features.set(Feature_HasLPMBit);
if (FB[AVR::FeatureLPMX])
Features.set(Feature_HasLPMXBit);
if (FB[AVR::FeatureELPM])
Features.set(Feature_HasELPMBit);
if (FB[AVR::FeatureELPMX])
Features.set(Feature_HasELPMXBit);
if (FB[AVR::FeatureSPM])
Features.set(Feature_HasSPMBit);
if (FB[AVR::FeatureSPMX])
Features.set(Feature_HasSPMXBit);
if (FB[AVR::FeatureDES])
Features.set(Feature_HasDESBit);
if (FB[AVR::FeatureRMW])
Features.set(Feature_SupportsRMWBit);
if (FB[AVR::FeatureMultiplication])
Features.set(Feature_SupportsMultiplicationBit);
if (FB[AVR::FeatureBREAK])
Features.set(Feature_HasBREAKBit);
if (FB[AVR::FeatureTinyEncoding])
Features.set(Feature_HasTinyEncodingBit);
if (!FB[AVR::FeatureTinyEncoding])
Features.set(Feature_HasNonTinyEncodingBit);
return Features;
}
inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
enum : uint8_t {
CEFBS_None,
CEFBS_HasADDSUBIW,
CEFBS_HasBREAK,
CEFBS_HasDES,
CEFBS_HasEIJMPCALL,
CEFBS_HasELPM,
CEFBS_HasELPMX,
CEFBS_HasIJMPCALL,
CEFBS_HasJMPCALL,
CEFBS_HasLPM,
CEFBS_HasLPMX,
CEFBS_HasMOVW,
CEFBS_HasNonTinyEncoding,
CEFBS_HasSPM,
CEFBS_HasSPMX,
CEFBS_HasSRAM,
CEFBS_HasTinyEncoding,
CEFBS_SupportsMultiplication,
CEFBS_SupportsRMW,
CEFBS_HasSRAM_HasNonTinyEncoding,
CEFBS_HasSRAM_HasTinyEncoding,
};
static constexpr FeatureBitset FeatureBitsets[] = {
{},
{Feature_HasADDSUBIWBit, },
{Feature_HasBREAKBit, },
{Feature_HasDESBit, },
{Feature_HasEIJMPCALLBit, },
{Feature_HasELPMBit, },
{Feature_HasELPMXBit, },
{Feature_HasIJMPCALLBit, },
{Feature_HasJMPCALLBit, },
{Feature_HasLPMBit, },
{Feature_HasLPMXBit, },
{Feature_HasMOVWBit, },
{Feature_HasNonTinyEncodingBit, },
{Feature_HasSPMBit, },
{Feature_HasSPMXBit, },
{Feature_HasSRAMBit, },
{Feature_HasTinyEncodingBit, },
{Feature_SupportsMultiplicationBit, },
{Feature_SupportsRMWBit, },
{Feature_HasSRAMBit, Feature_HasNonTinyEncodingBit, },
{Feature_HasSRAMBit, Feature_HasTinyEncodingBit, },
};
static constexpr uint8_t RequiredFeaturesRefs[] = {
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasELPM,
CEFBS_HasELPMX,
CEFBS_HasELPM,
CEFBS_HasELPMX,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasSRAM,
CEFBS_HasSRAM,
CEFBS_None,
CEFBS_HasSRAM_HasNonTinyEncoding,
CEFBS_HasSRAM,
CEFBS_HasSRAM,
CEFBS_HasSRAM,
CEFBS_HasLPM,
CEFBS_HasLPM,
CEFBS_HasLPMX,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasSRAM,
CEFBS_HasSRAM,
CEFBS_HasNonTinyEncoding,
CEFBS_HasTinyEncoding,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasSRAM,
CEFBS_None,
CEFBS_HasSRAM_HasNonTinyEncoding,
CEFBS_HasSRAM,
CEFBS_HasSRAM,
CEFBS_HasSRAM,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasADDSUBIW,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasBREAK,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasJMPCALL,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasDES,
CEFBS_HasEIJMPCALL,
CEFBS_HasEIJMPCALL,
CEFBS_HasELPM,
CEFBS_HasELPMX,
CEFBS_HasELPMX,
CEFBS_None,
CEFBS_SupportsMultiplication,
CEFBS_SupportsMultiplication,
CEFBS_SupportsMultiplication,
CEFBS_HasIJMPCALL,
CEFBS_HasIJMPCALL,
CEFBS_None,
CEFBS_None,
CEFBS_HasJMPCALL,
CEFBS_SupportsRMW,
CEFBS_SupportsRMW,
CEFBS_SupportsRMW,
CEFBS_HasSRAM_HasNonTinyEncoding,
CEFBS_None,
CEFBS_HasSRAM,
CEFBS_HasSRAM,
CEFBS_HasSRAM,
CEFBS_HasSRAM_HasNonTinyEncoding,
CEFBS_HasSRAM_HasTinyEncoding,
CEFBS_HasLPM,
CEFBS_HasLPMX,
CEFBS_HasLPMX,
CEFBS_None,
CEFBS_None,
CEFBS_HasMOVW,
CEFBS_SupportsMultiplication,
CEFBS_SupportsMultiplication,
CEFBS_SupportsMultiplication,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasSRAM,
CEFBS_HasSRAM,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasADDSUBIW,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasSPM,
CEFBS_HasSPMX,
CEFBS_HasSRAM_HasNonTinyEncoding,
CEFBS_HasSRAM,
CEFBS_HasSRAM,
CEFBS_HasSRAM,
CEFBS_HasSRAM_HasNonTinyEncoding,
CEFBS_HasSRAM_HasTinyEncoding,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_SupportsRMW,
};
assert(Opcode < 493);
return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
}
}
}
#endif
#ifdef GET_AVAILABLE_OPCODE_CHECKER
#undef GET_AVAILABLE_OPCODE_CHECKER
namespace llvm {
namespace AVR_MC {
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
FeatureBitset MissingFeatures =
(AvailableFeatures & RequiredFeatures) ^
RequiredFeatures;
return !MissingFeatures.any();
}
}
}
#endif
#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
#undef ENABLE_INSTR_PREDICATE_VERIFIER
#include <sstream>
namespace llvm {
namespace AVR_MC {
#ifndef NDEBUG
static const char *SubtargetFeatureNames[] = {
"Feature_HasADDSUBIW",
"Feature_HasBREAK",
"Feature_HasDES",
"Feature_HasEIJMPCALL",
"Feature_HasELPM",
"Feature_HasELPMX",
"Feature_HasIJMPCALL",
"Feature_HasJMPCALL",
"Feature_HasLPM",
"Feature_HasLPMX",
"Feature_HasMOVW",
"Feature_HasNonTinyEncoding",
"Feature_HasSPM",
"Feature_HasSPMX",
"Feature_HasSRAM",
"Feature_HasSmallStack",
"Feature_HasTinyEncoding",
"Feature_SupportsMultiplication",
"Feature_SupportsRMW",
nullptr
};
#endif
void verifyInstructionPredicates(
unsigned Opcode, const FeatureBitset &Features) {
#ifndef NDEBUG
FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
FeatureBitset MissingFeatures =
(AvailableFeatures & RequiredFeatures) ^
RequiredFeatures;
if (MissingFeatures.any()) {
std::ostringstream Msg;
Msg << "Attempting to emit " << &AVRInstrNameData[AVRInstrNameIndices[Opcode]]
<< " instruction but the ";
for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
if (MissingFeatures.test(i))
Msg << SubtargetFeatureNames[i] << " ";
Msg << "predicate(s) are not met";
report_fatal_error(Msg.str().c_str());
}
#endif
}
}
}
#endif