llvm/lib/Target/AVR/AVRGenInstrInfo.inc

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Instruction Enum Values and Descriptors                             *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
namespace llvm {

namespace AVR {
  enum {
    PHI	= 0,
    INLINEASM	= 1,
    INLINEASM_BR	= 2,
    CFI_INSTRUCTION	= 3,
    EH_LABEL	= 4,
    GC_LABEL	= 5,
    ANNOTATION_LABEL	= 6,
    KILL	= 7,
    EXTRACT_SUBREG	= 8,
    INSERT_SUBREG	= 9,
    IMPLICIT_DEF	= 10,
    INIT_UNDEF	= 11,
    SUBREG_TO_REG	= 12,
    COPY_TO_REGCLASS	= 13,
    DBG_VALUE	= 14,
    DBG_VALUE_LIST	= 15,
    DBG_INSTR_REF	= 16,
    DBG_PHI	= 17,
    DBG_LABEL	= 18,
    REG_SEQUENCE	= 19,
    COPY	= 20,
    BUNDLE	= 21,
    LIFETIME_START	= 22,
    LIFETIME_END	= 23,
    PSEUDO_PROBE	= 24,
    ARITH_FENCE	= 25,
    STACKMAP	= 26,
    FENTRY_CALL	= 27,
    PATCHPOINT	= 28,
    LOAD_STACK_GUARD	= 29,
    PREALLOCATED_SETUP	= 30,
    PREALLOCATED_ARG	= 31,
    STATEPOINT	= 32,
    LOCAL_ESCAPE	= 33,
    FAULTING_OP	= 34,
    PATCHABLE_OP	= 35,
    PATCHABLE_FUNCTION_ENTER	= 36,
    PATCHABLE_RET	= 37,
    PATCHABLE_FUNCTION_EXIT	= 38,
    PATCHABLE_TAIL_CALL	= 39,
    PATCHABLE_EVENT_CALL	= 40,
    PATCHABLE_TYPED_EVENT_CALL	= 41,
    ICALL_BRANCH_FUNNEL	= 42,
    FAKE_USE	= 43,
    MEMBARRIER	= 44,
    JUMP_TABLE_DEBUG_INFO	= 45,
    CONVERGENCECTRL_ENTRY	= 46,
    CONVERGENCECTRL_ANCHOR	= 47,
    CONVERGENCECTRL_LOOP	= 48,
    CONVERGENCECTRL_GLUE	= 49,
    G_ASSERT_SEXT	= 50,
    G_ASSERT_ZEXT	= 51,
    G_ASSERT_ALIGN	= 52,
    G_ADD	= 53,
    G_SUB	= 54,
    G_MUL	= 55,
    G_SDIV	= 56,
    G_UDIV	= 57,
    G_SREM	= 58,
    G_UREM	= 59,
    G_SDIVREM	= 60,
    G_UDIVREM	= 61,
    G_AND	= 62,
    G_OR	= 63,
    G_XOR	= 64,
    G_IMPLICIT_DEF	= 65,
    G_PHI	= 66,
    G_FRAME_INDEX	= 67,
    G_GLOBAL_VALUE	= 68,
    G_PTRAUTH_GLOBAL_VALUE	= 69,
    G_CONSTANT_POOL	= 70,
    G_EXTRACT	= 71,
    G_UNMERGE_VALUES	= 72,
    G_INSERT	= 73,
    G_MERGE_VALUES	= 74,
    G_BUILD_VECTOR	= 75,
    G_BUILD_VECTOR_TRUNC	= 76,
    G_CONCAT_VECTORS	= 77,
    G_PTRTOINT	= 78,
    G_INTTOPTR	= 79,
    G_BITCAST	= 80,
    G_FREEZE	= 81,
    G_CONSTANT_FOLD_BARRIER	= 82,
    G_INTRINSIC_FPTRUNC_ROUND	= 83,
    G_INTRINSIC_TRUNC	= 84,
    G_INTRINSIC_ROUND	= 85,
    G_INTRINSIC_LRINT	= 86,
    G_INTRINSIC_LLRINT	= 87,
    G_INTRINSIC_ROUNDEVEN	= 88,
    G_READCYCLECOUNTER	= 89,
    G_READSTEADYCOUNTER	= 90,
    G_LOAD	= 91,
    G_SEXTLOAD	= 92,
    G_ZEXTLOAD	= 93,
    G_INDEXED_LOAD	= 94,
    G_INDEXED_SEXTLOAD	= 95,
    G_INDEXED_ZEXTLOAD	= 96,
    G_STORE	= 97,
    G_INDEXED_STORE	= 98,
    G_ATOMIC_CMPXCHG_WITH_SUCCESS	= 99,
    G_ATOMIC_CMPXCHG	= 100,
    G_ATOMICRMW_XCHG	= 101,
    G_ATOMICRMW_ADD	= 102,
    G_ATOMICRMW_SUB	= 103,
    G_ATOMICRMW_AND	= 104,
    G_ATOMICRMW_NAND	= 105,
    G_ATOMICRMW_OR	= 106,
    G_ATOMICRMW_XOR	= 107,
    G_ATOMICRMW_MAX	= 108,
    G_ATOMICRMW_MIN	= 109,
    G_ATOMICRMW_UMAX	= 110,
    G_ATOMICRMW_UMIN	= 111,
    G_ATOMICRMW_FADD	= 112,
    G_ATOMICRMW_FSUB	= 113,
    G_ATOMICRMW_FMAX	= 114,
    G_ATOMICRMW_FMIN	= 115,
    G_ATOMICRMW_UINC_WRAP	= 116,
    G_ATOMICRMW_UDEC_WRAP	= 117,
    G_ATOMICRMW_USUB_COND	= 118,
    G_ATOMICRMW_USUB_SAT	= 119,
    G_FENCE	= 120,
    G_PREFETCH	= 121,
    G_BRCOND	= 122,
    G_BRINDIRECT	= 123,
    G_INVOKE_REGION_START	= 124,
    G_INTRINSIC	= 125,
    G_INTRINSIC_W_SIDE_EFFECTS	= 126,
    G_INTRINSIC_CONVERGENT	= 127,
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS	= 128,
    G_ANYEXT	= 129,
    G_TRUNC	= 130,
    G_CONSTANT	= 131,
    G_FCONSTANT	= 132,
    G_VASTART	= 133,
    G_VAARG	= 134,
    G_SEXT	= 135,
    G_SEXT_INREG	= 136,
    G_ZEXT	= 137,
    G_SHL	= 138,
    G_LSHR	= 139,
    G_ASHR	= 140,
    G_FSHL	= 141,
    G_FSHR	= 142,
    G_ROTR	= 143,
    G_ROTL	= 144,
    G_ICMP	= 145,
    G_FCMP	= 146,
    G_SCMP	= 147,
    G_UCMP	= 148,
    G_SELECT	= 149,
    G_UADDO	= 150,
    G_UADDE	= 151,
    G_USUBO	= 152,
    G_USUBE	= 153,
    G_SADDO	= 154,
    G_SADDE	= 155,
    G_SSUBO	= 156,
    G_SSUBE	= 157,
    G_UMULO	= 158,
    G_SMULO	= 159,
    G_UMULH	= 160,
    G_SMULH	= 161,
    G_UADDSAT	= 162,
    G_SADDSAT	= 163,
    G_USUBSAT	= 164,
    G_SSUBSAT	= 165,
    G_USHLSAT	= 166,
    G_SSHLSAT	= 167,
    G_SMULFIX	= 168,
    G_UMULFIX	= 169,
    G_SMULFIXSAT	= 170,
    G_UMULFIXSAT	= 171,
    G_SDIVFIX	= 172,
    G_UDIVFIX	= 173,
    G_SDIVFIXSAT	= 174,
    G_UDIVFIXSAT	= 175,
    G_FADD	= 176,
    G_FSUB	= 177,
    G_FMUL	= 178,
    G_FMA	= 179,
    G_FMAD	= 180,
    G_FDIV	= 181,
    G_FREM	= 182,
    G_FPOW	= 183,
    G_FPOWI	= 184,
    G_FEXP	= 185,
    G_FEXP2	= 186,
    G_FEXP10	= 187,
    G_FLOG	= 188,
    G_FLOG2	= 189,
    G_FLOG10	= 190,
    G_FLDEXP	= 191,
    G_FFREXP	= 192,
    G_FNEG	= 193,
    G_FPEXT	= 194,
    G_FPTRUNC	= 195,
    G_FPTOSI	= 196,
    G_FPTOUI	= 197,
    G_SITOFP	= 198,
    G_UITOFP	= 199,
    G_FPTOSI_SAT	= 200,
    G_FPTOUI_SAT	= 201,
    G_FABS	= 202,
    G_FCOPYSIGN	= 203,
    G_IS_FPCLASS	= 204,
    G_FCANONICALIZE	= 205,
    G_FMINNUM	= 206,
    G_FMAXNUM	= 207,
    G_FMINNUM_IEEE	= 208,
    G_FMAXNUM_IEEE	= 209,
    G_FMINIMUM	= 210,
    G_FMAXIMUM	= 211,
    G_GET_FPENV	= 212,
    G_SET_FPENV	= 213,
    G_RESET_FPENV	= 214,
    G_GET_FPMODE	= 215,
    G_SET_FPMODE	= 216,
    G_RESET_FPMODE	= 217,
    G_PTR_ADD	= 218,
    G_PTRMASK	= 219,
    G_SMIN	= 220,
    G_SMAX	= 221,
    G_UMIN	= 222,
    G_UMAX	= 223,
    G_ABS	= 224,
    G_LROUND	= 225,
    G_LLROUND	= 226,
    G_BR	= 227,
    G_BRJT	= 228,
    G_VSCALE	= 229,
    G_INSERT_SUBVECTOR	= 230,
    G_EXTRACT_SUBVECTOR	= 231,
    G_INSERT_VECTOR_ELT	= 232,
    G_EXTRACT_VECTOR_ELT	= 233,
    G_SHUFFLE_VECTOR	= 234,
    G_SPLAT_VECTOR	= 235,
    G_VECTOR_COMPRESS	= 236,
    G_CTTZ	= 237,
    G_CTTZ_ZERO_UNDEF	= 238,
    G_CTLZ	= 239,
    G_CTLZ_ZERO_UNDEF	= 240,
    G_CTPOP	= 241,
    G_BSWAP	= 242,
    G_BITREVERSE	= 243,
    G_FCEIL	= 244,
    G_FCOS	= 245,
    G_FSIN	= 246,
    G_FTAN	= 247,
    G_FACOS	= 248,
    G_FASIN	= 249,
    G_FATAN	= 250,
    G_FCOSH	= 251,
    G_FSINH	= 252,
    G_FTANH	= 253,
    G_FSQRT	= 254,
    G_FFLOOR	= 255,
    G_FRINT	= 256,
    G_FNEARBYINT	= 257,
    G_ADDRSPACE_CAST	= 258,
    G_BLOCK_ADDR	= 259,
    G_JUMP_TABLE	= 260,
    G_DYN_STACKALLOC	= 261,
    G_STACKSAVE	= 262,
    G_STACKRESTORE	= 263,
    G_STRICT_FADD	= 264,
    G_STRICT_FSUB	= 265,
    G_STRICT_FMUL	= 266,
    G_STRICT_FDIV	= 267,
    G_STRICT_FREM	= 268,
    G_STRICT_FMA	= 269,
    G_STRICT_FSQRT	= 270,
    G_STRICT_FLDEXP	= 271,
    G_READ_REGISTER	= 272,
    G_WRITE_REGISTER	= 273,
    G_MEMCPY	= 274,
    G_MEMCPY_INLINE	= 275,
    G_MEMMOVE	= 276,
    G_MEMSET	= 277,
    G_BZERO	= 278,
    G_TRAP	= 279,
    G_DEBUGTRAP	= 280,
    G_UBSANTRAP	= 281,
    G_VECREDUCE_SEQ_FADD	= 282,
    G_VECREDUCE_SEQ_FMUL	= 283,
    G_VECREDUCE_FADD	= 284,
    G_VECREDUCE_FMUL	= 285,
    G_VECREDUCE_FMAX	= 286,
    G_VECREDUCE_FMIN	= 287,
    G_VECREDUCE_FMAXIMUM	= 288,
    G_VECREDUCE_FMINIMUM	= 289,
    G_VECREDUCE_ADD	= 290,
    G_VECREDUCE_MUL	= 291,
    G_VECREDUCE_AND	= 292,
    G_VECREDUCE_OR	= 293,
    G_VECREDUCE_XOR	= 294,
    G_VECREDUCE_SMAX	= 295,
    G_VECREDUCE_SMIN	= 296,
    G_VECREDUCE_UMAX	= 297,
    G_VECREDUCE_UMIN	= 298,
    G_SBFX	= 299,
    G_UBFX	= 300,
    ADCWRdRr	= 301,
    ADDWRdRr	= 302,
    ADJCALLSTACKDOWN	= 303,
    ADJCALLSTACKUP	= 304,
    ANDIWRdK	= 305,
    ANDWRdRr	= 306,
    ASRBNRd	= 307,
    ASRWLoRd	= 308,
    ASRWNRd	= 309,
    ASRWRd	= 310,
    Asr16	= 311,
    Asr32	= 312,
    Asr8	= 313,
    AtomicFence	= 314,
    AtomicLoad16	= 315,
    AtomicLoad8	= 316,
    AtomicLoadAdd16	= 317,
    AtomicLoadAdd8	= 318,
    AtomicLoadAnd16	= 319,
    AtomicLoadAnd8	= 320,
    AtomicLoadOr16	= 321,
    AtomicLoadOr8	= 322,
    AtomicLoadSub16	= 323,
    AtomicLoadSub8	= 324,
    AtomicLoadXor16	= 325,
    AtomicLoadXor8	= 326,
    AtomicStore16	= 327,
    AtomicStore8	= 328,
    COMWRd	= 329,
    CPCWRdRr	= 330,
    CPWRdRr	= 331,
    CopyZero	= 332,
    ELPMBRdZ	= 333,
    ELPMBRdZPi	= 334,
    ELPMWRdZ	= 335,
    ELPMWRdZPi	= 336,
    EORWRdRr	= 337,
    FRMIDX	= 338,
    INWRdA	= 339,
    LDDWRdPtrQ	= 340,
    LDDWRdYQ	= 341,
    LDIWRdK	= 342,
    LDSWRdK	= 343,
    LDWRdPtr	= 344,
    LDWRdPtrPd	= 345,
    LDWRdPtrPi	= 346,
    LPMBRdZ	= 347,
    LPMWRdZ	= 348,
    LPMWRdZPi	= 349,
    LSLBNRd	= 350,
    LSLWHiRd	= 351,
    LSLWNRd	= 352,
    LSLWRd	= 353,
    LSRBNRd	= 354,
    LSRWLoRd	= 355,
    LSRWNRd	= 356,
    LSRWRd	= 357,
    Lsl16	= 358,
    Lsl32	= 359,
    Lsl8	= 360,
    Lsr16	= 361,
    Lsr32	= 362,
    Lsr8	= 363,
    NEGWRd	= 364,
    ORIWRdK	= 365,
    ORWRdRr	= 366,
    OUTWARr	= 367,
    POPWRd	= 368,
    PUSHWRr	= 369,
    ROLBRdR1	= 370,
    ROLBRdR17	= 371,
    ROLWRd	= 372,
    RORBRd	= 373,
    RORWRd	= 374,
    Rol16	= 375,
    Rol8	= 376,
    Ror16	= 377,
    Ror8	= 378,
    SBCIWRdK	= 379,
    SBCWRdRr	= 380,
    SEXT	= 381,
    SPREAD	= 382,
    SPWRITE	= 383,
    STDSPQRr	= 384,
    STDWPtrQRr	= 385,
    STDWSPQRr	= 386,
    STSWKRr	= 387,
    STWPtrPdRr	= 388,
    STWPtrPiRr	= 389,
    STWPtrRr	= 390,
    SUBIWRdK	= 391,
    SUBWRdRr	= 392,
    Select16	= 393,
    Select8	= 394,
    ZEXT	= 395,
    ADCRdRr	= 396,
    ADDRdRr	= 397,
    ADIWRdK	= 398,
    ANDIRdK	= 399,
    ANDRdRr	= 400,
    ASRRd	= 401,
    BCLRs	= 402,
    BLD	= 403,
    BRBCsk	= 404,
    BRBSsk	= 405,
    BREAK	= 406,
    BREQk	= 407,
    BRGEk	= 408,
    BRLOk	= 409,
    BRLTk	= 410,
    BRMIk	= 411,
    BRNEk	= 412,
    BRPLk	= 413,
    BRSHk	= 414,
    BSETs	= 415,
    BST	= 416,
    CALLk	= 417,
    CBIAb	= 418,
    COMRd	= 419,
    CPCRdRr	= 420,
    CPIRdK	= 421,
    CPRdRr	= 422,
    CPSE	= 423,
    DECRd	= 424,
    DESK	= 425,
    EICALL	= 426,
    EIJMP	= 427,
    ELPM	= 428,
    ELPMRdZ	= 429,
    ELPMRdZPi	= 430,
    EORRdRr	= 431,
    FMUL	= 432,
    FMULS	= 433,
    FMULSU	= 434,
    ICALL	= 435,
    IJMP	= 436,
    INCRd	= 437,
    INRdA	= 438,
    JMPk	= 439,
    LACZRd	= 440,
    LASZRd	= 441,
    LATZRd	= 442,
    LDDRdPtrQ	= 443,
    LDIRdK	= 444,
    LDRdPtr	= 445,
    LDRdPtrPd	= 446,
    LDRdPtrPi	= 447,
    LDSRdK	= 448,
    LDSRdKTiny	= 449,
    LPM	= 450,
    LPMRdZ	= 451,
    LPMRdZPi	= 452,
    LSRRd	= 453,
    MOVRdRr	= 454,
    MOVWRdRr	= 455,
    MULRdRr	= 456,
    MULSRdRr	= 457,
    MULSURdRr	= 458,
    NEGRd	= 459,
    NOP	= 460,
    ORIRdK	= 461,
    ORRdRr	= 462,
    OUTARr	= 463,
    POPRd	= 464,
    PUSHRr	= 465,
    RCALLk	= 466,
    RET	= 467,
    RETI	= 468,
    RJMPk	= 469,
    RORRd	= 470,
    SBCIRdK	= 471,
    SBCRdRr	= 472,
    SBIAb	= 473,
    SBICAb	= 474,
    SBISAb	= 475,
    SBIWRdK	= 476,
    SBRCRrB	= 477,
    SBRSRrB	= 478,
    SLEEP	= 479,
    SPM	= 480,
    SPMZPi	= 481,
    STDPtrQRr	= 482,
    STPtrPdRr	= 483,
    STPtrPiRr	= 484,
    STPtrRr	= 485,
    STSKRr	= 486,
    STSKRrTiny	= 487,
    SUBIRdK	= 488,
    SUBRdRr	= 489,
    SWAPRd	= 490,
    WDR	= 491,
    XCHZRd	= 492,
    INSTRUCTION_LIST_END = 493
  };

} // end namespace AVR
} // end namespace llvm
#endif // GET_INSTRINFO_ENUM

#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM
namespace llvm {

namespace AVR {
namespace Sched {
  enum {
    NoInstrModel	= 0,
    SCHED_LIST_END = 1
  };
} // end namespace Sched
} // end namespace AVR
} // end namespace llvm
#endif // GET_INSTRINFO_SCHED_ENUM

#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
namespace llvm {

struct AVRInstrTable {
  MCInstrDesc Insts[493];
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
  MCOperandInfo OperandInfo[319];
  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
  MCPhysReg ImplicitOps[44];
};

} // end namespace llvm
#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)

#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC
namespace llvm {

static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
static constexpr unsigned AVRImpOpBase = sizeof AVRInstrTable::OperandInfo / (sizeof(MCPhysReg));

extern const AVRInstrTable AVRDescs = {
  {
    { 492,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	223,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #492 = XCHZRd
    { 491,	0,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #491 = WDR
    { 490,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	238,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #490 = SWAPRd
    { 489,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	269,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #489 = SUBRdRr
    { 488,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	275,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #488 = SUBIRdK
    { 487,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	317,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #487 = STSKRrTiny
    { 486,	2,	0,	4,	0,	0,	0,	AVRImpOpBase + 0,	305,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #486 = STSKRr
    { 485,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	315,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #485 = STPtrRr
    { 484,	4,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	311,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #484 = STPtrPiRr
    { 483,	4,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	311,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #483 = STPtrPdRr
    { 482,	3,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	308,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #482 = STDPtrQRr
    { 481,	1,	0,	2,	0,	2,	1,	AVRImpOpBase + 41,	307,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #481 = SPMZPi
    { 480,	0,	0,	2,	0,	3,	0,	AVRImpOpBase + 38,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #480 = SPM
    { 479,	0,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #479 = SLEEP
    { 478,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	283,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #478 = SBRSRrB
    { 477,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	283,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #477 = SBRCRrB
    { 476,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	272,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #476 = SBIWRdK
    { 475,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	285,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #475 = SBISAb
    { 474,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	285,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #474 = SBICAb
    { 473,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	285,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #473 = SBIAb
    { 472,	3,	1,	2,	0,	1,	1,	AVRImpOpBase + 0,	269,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #472 = SBCRdRr
    { 471,	3,	1,	2,	0,	1,	1,	AVRImpOpBase + 0,	275,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #471 = SBCIRdK
    { 470,	2,	1,	2,	0,	1,	1,	AVRImpOpBase + 0,	238,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #470 = RORRd
    { 469,	1,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #469 = RJMPk
    { 468,	0,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #468 = RETI
    { 467,	0,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #467 = RET
    { 466,	1,	0,	2,	0,	1,	0,	AVRImpOpBase + 16,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #466 = RCALLk
    { 465,	1,	0,	2,	0,	1,	1,	AVRImpOpBase + 10,	193,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #465 = PUSHRr
    { 464,	1,	1,	2,	0,	1,	1,	AVRImpOpBase + 10,	193,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #464 = POPRd
    { 463,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	305,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #463 = OUTARr
    { 462,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	269,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #462 = ORRdRr
    { 461,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	275,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #461 = ORIRdK
    { 460,	0,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #460 = NOP
    { 459,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	238,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #459 = NEGRd
    { 458,	2,	0,	2,	0,	0,	3,	AVRImpOpBase + 35,	291,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #458 = MULSURdRr
    { 457,	2,	0,	2,	0,	0,	3,	AVRImpOpBase + 35,	303,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #457 = MULSRdRr
    { 456,	2,	0,	2,	0,	0,	3,	AVRImpOpBase + 35,	287,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #456 = MULRdRr
    { 455,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #455 = MOVWRdRr
    { 454,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	287,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #454 = MOVRdRr
    { 453,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	238,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #453 = LSRRd
    { 452,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 9,	223,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #452 = LPMRdZPi
    { 451,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	223,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #451 = LPMRdZ
    { 450,	0,	0,	2,	0,	1,	1,	AVRImpOpBase + 33,	1,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #450 = LPM
    { 449,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	289,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #449 = LDSRdKTiny
    { 448,	2,	1,	4,	0,	0,	0,	AVRImpOpBase + 0,	293,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #448 = LDSRdK
    { 447,	3,	2,	2,	0,	0,	0,	AVRImpOpBase + 0,	300,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #447 = LDRdPtrPi
    { 446,	3,	2,	2,	0,	0,	0,	AVRImpOpBase + 0,	300,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #446 = LDRdPtrPd
    { 445,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	298,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #445 = LDRdPtr
    { 444,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	289,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #444 = LDIRdK
    { 443,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	295,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #443 = LDDRdPtrQ
    { 442,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	223,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #442 = LATZRd
    { 441,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	223,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #441 = LASZRd
    { 440,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	223,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #440 = LACZRd
    { 439,	1,	0,	4,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #439 = JMPk
    { 438,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	293,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #438 = INRdA
    { 437,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	238,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #437 = INCRd
    { 436,	0,	0,	2,	0,	1,	0,	AVRImpOpBase + 9,	1,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #436 = IJMP
    { 435,	0,	0,	2,	0,	2,	0,	AVRImpOpBase + 6,	1,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #435 = ICALL
    { 434,	2,	0,	2,	0,	0,	3,	AVRImpOpBase + 35,	291,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #434 = FMULSU
    { 433,	2,	0,	2,	0,	0,	3,	AVRImpOpBase + 35,	291,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #433 = FMULS
    { 432,	2,	0,	2,	0,	0,	3,	AVRImpOpBase + 35,	291,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #432 = FMUL
    { 431,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	269,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #431 = EORRdRr
    { 430,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 9,	223,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #430 = ELPMRdZPi
    { 429,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	223,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #429 = ELPMRdZ
    { 428,	0,	0,	2,	0,	1,	1,	AVRImpOpBase + 33,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #428 = ELPM
    { 427,	0,	0,	2,	0,	1,	0,	AVRImpOpBase + 9,	1,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #427 = EIJMP
    { 426,	0,	0,	2,	0,	2,	0,	AVRImpOpBase + 6,	1,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #426 = EICALL
    { 425,	1,	0,	2,	0,	0,	16,	AVRImpOpBase + 17,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #425 = DESK
    { 424,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	238,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #424 = DECRd
    { 423,	2,	0,	2,	0,	0,	1,	AVRImpOpBase + 2,	287,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #423 = CPSE
    { 422,	2,	0,	2,	0,	0,	1,	AVRImpOpBase + 2,	287,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #422 = CPRdRr
    { 421,	2,	0,	2,	0,	0,	1,	AVRImpOpBase + 2,	289,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #421 = CPIRdK
    { 420,	2,	0,	2,	0,	1,	1,	AVRImpOpBase + 0,	287,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #420 = CPCRdRr
    { 419,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	238,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #419 = COMRd
    { 418,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	285,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #418 = CBIAb
    { 417,	1,	0,	4,	0,	1,	0,	AVRImpOpBase + 16,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #417 = CALLk
    { 416,	2,	0,	2,	0,	0,	1,	AVRImpOpBase + 2,	283,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #416 = BST
    { 415,	1,	0,	2,	0,	0,	1,	AVRImpOpBase + 2,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #415 = BSETs
    { 414,	1,	0,	2,	0,	1,	0,	AVRImpOpBase + 2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #414 = BRSHk
    { 413,	1,	0,	2,	0,	1,	0,	AVRImpOpBase + 2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #413 = BRPLk
    { 412,	1,	0,	2,	0,	1,	0,	AVRImpOpBase + 2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #412 = BRNEk
    { 411,	1,	0,	2,	0,	1,	0,	AVRImpOpBase + 2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #411 = BRMIk
    { 410,	1,	0,	2,	0,	1,	0,	AVRImpOpBase + 2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #410 = BRLTk
    { 409,	1,	0,	2,	0,	1,	0,	AVRImpOpBase + 2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #409 = BRLOk
    { 408,	1,	0,	2,	0,	1,	0,	AVRImpOpBase + 2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #408 = BRGEk
    { 407,	1,	0,	2,	0,	1,	0,	AVRImpOpBase + 2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #407 = BREQk
    { 406,	0,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #406 = BREAK
    { 405,	2,	0,	2,	0,	1,	0,	AVRImpOpBase + 2,	281,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #405 = BRBSsk
    { 404,	2,	0,	2,	0,	1,	0,	AVRImpOpBase + 2,	281,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #404 = BRBCsk
    { 403,	3,	1,	2,	0,	1,	0,	AVRImpOpBase + 2,	278,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #403 = BLD
    { 402,	1,	0,	2,	0,	0,	1,	AVRImpOpBase + 2,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #402 = BCLRs
    { 401,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	238,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #401 = ASRRd
    { 400,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	269,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #400 = ANDRdRr
    { 399,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	275,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #399 = ANDIRdK
    { 398,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	272,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #398 = ADIWRdK
    { 397,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	269,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #397 = ADDRdRr
    { 396,	3,	1,	2,	0,	1,	1,	AVRImpOpBase + 0,	269,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #396 = ADCRdRr
    { 395,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	240,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #395 = ZEXT
    { 394,	4,	1,	2,	0,	1,	0,	AVRImpOpBase + 2,	265,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #394 = Select8
    { 393,	4,	1,	2,	0,	1,	0,	AVRImpOpBase + 2,	261,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #393 = Select16
    { 392,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #392 = SUBWRdRr
    { 391,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	155,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #391 = SUBIWRdK
    { 390,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	187,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #390 = STWPtrRr
    { 389,	4,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	257,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #389 = STWPtrPiRr
    { 388,	4,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	257,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #388 = STWPtrPdRr
    { 387,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	255,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #387 = STSWKRr
    { 386,	3,	0,	2,	0,	0,	1,	AVRImpOpBase + 16,	252,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #386 = STDWSPQRr
    { 385,	3,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	249,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #385 = STDWPtrQRr
    { 384,	3,	0,	2,	0,	0,	1,	AVRImpOpBase + 16,	246,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #384 = STDSPQRr
    { 383,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 16,	244,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #383 = SPWRITE
    { 382,	2,	1,	2,	0,	1,	0,	AVRImpOpBase + 16,	242,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #382 = SPREAD
    { 381,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	240,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #381 = SEXT
    { 380,	3,	1,	2,	0,	1,	1,	AVRImpOpBase + 0,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #380 = SBCWRdRr
    { 379,	3,	1,	2,	0,	1,	1,	AVRImpOpBase + 0,	155,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #379 = SBCIWRdK
    { 378,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	174,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #378 = Ror8
    { 377,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	166,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #377 = Ror16
    { 376,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	174,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #376 = Rol8
    { 375,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	166,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #375 = Rol16
    { 374,	2,	1,	2,	0,	1,	1,	AVRImpOpBase + 0,	161,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #374 = RORWRd
    { 373,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	238,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #373 = RORBRd
    { 372,	2,	1,	2,	0,	1,	1,	AVRImpOpBase + 0,	161,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #372 = ROLWRd
    { 371,	2,	1,	2,	0,	1,	1,	AVRImpOpBase + 14,	238,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #371 = ROLBRdR17
    { 370,	2,	1,	2,	0,	1,	1,	AVRImpOpBase + 12,	238,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #370 = ROLBRdR1
    { 369,	1,	0,	2,	0,	1,	1,	AVRImpOpBase + 10,	237,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #369 = PUSHWRr
    { 368,	1,	1,	2,	0,	1,	1,	AVRImpOpBase + 10,	237,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #368 = POPWRd
    { 367,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	235,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #367 = OUTWARr
    { 366,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #366 = ORWRdRr
    { 365,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	155,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #365 = ORIWRdK
    { 364,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	232,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #364 = NEGWRd
    { 363,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	174,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #363 = Lsr8
    { 362,	5,	2,	2,	0,	0,	1,	AVRImpOpBase + 2,	169,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #362 = Lsr32
    { 361,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	166,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #361 = Lsr16
    { 360,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	174,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #360 = Lsl8
    { 359,	5,	2,	2,	0,	0,	1,	AVRImpOpBase + 2,	169,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #359 = Lsl32
    { 358,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	166,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #358 = Lsl16
    { 357,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	161,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #357 = LSRWRd
    { 356,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	229,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #356 = LSRWNRd
    { 355,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	161,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #355 = LSRWLoRd
    { 354,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	158,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #354 = LSRBNRd
    { 353,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	161,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #353 = LSLWRd
    { 352,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	229,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #352 = LSLWNRd
    { 351,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	161,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #351 = LSLWHiRd
    { 350,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	158,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #350 = LSLBNRd
    { 349,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 9,	227,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #349 = LPMWRdZPi
    { 348,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 8,	225,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #348 = LPMWRdZ
    { 347,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 8,	223,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #347 = LPMBRdZ
    { 346,	3,	2,	2,	0,	0,	0,	AVRImpOpBase + 0,	220,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #346 = LDWRdPtrPi
    { 345,	3,	2,	2,	0,	0,	0,	AVRImpOpBase + 0,	220,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #345 = LDWRdPtrPd
    { 344,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	218,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #344 = LDWRdPtr
    { 343,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	216,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #343 = LDSWRdK
    { 342,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	214,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #342 = LDIWRdK
    { 341,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	211,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #341 = LDDWRdYQ
    { 340,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	208,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #340 = LDDWRdPtrQ
    { 339,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	206,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #339 = INWRdA
    { 338,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	203,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #338 = FRMIDX
    { 337,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #337 = EORWRdRr
    { 336,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 9,	200,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #336 = ELPMWRdZPi
    { 335,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 8,	197,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #335 = ELPMWRdZ
    { 334,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 9,	194,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #334 = ELPMBRdZPi
    { 333,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 8,	194,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #333 = ELPMBRdZ
    { 332,	1,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	193,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #332 = CopyZero
    { 331,	2,	0,	2,	0,	0,	1,	AVRImpOpBase + 2,	191,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #331 = CPWRdRr
    { 330,	2,	0,	2,	0,	1,	1,	AVRImpOpBase + 0,	191,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #330 = CPCWRdRr
    { 329,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	161,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #329 = COMWRd
    { 328,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	189,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #328 = AtomicStore8
    { 327,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	187,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #327 = AtomicStore16
    { 326,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	184,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #326 = AtomicLoadXor8
    { 325,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	181,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #325 = AtomicLoadXor16
    { 324,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	184,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #324 = AtomicLoadSub8
    { 323,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	181,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #323 = AtomicLoadSub16
    { 322,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	184,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #322 = AtomicLoadOr8
    { 321,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	181,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #321 = AtomicLoadOr16
    { 320,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	184,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #320 = AtomicLoadAnd8
    { 319,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	181,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #319 = AtomicLoadAnd16
    { 318,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	184,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #318 = AtomicLoadAdd8
    { 317,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	181,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #317 = AtomicLoadAdd16
    { 316,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	179,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #316 = AtomicLoad8
    { 315,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	177,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #315 = AtomicLoad16
    { 314,	0,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #314 = AtomicFence
    { 313,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	174,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #313 = Asr8
    { 312,	5,	2,	2,	0,	0,	1,	AVRImpOpBase + 2,	169,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #312 = Asr32
    { 311,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	166,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #311 = Asr16
    { 310,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	161,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #310 = ASRWRd
    { 309,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	163,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #309 = ASRWNRd
    { 308,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	161,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #308 = ASRWLoRd
    { 307,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	158,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #307 = ASRBNRd
    { 306,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #306 = ANDWRdRr
    { 305,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	155,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #305 = ANDIWRdK
    { 304,	2,	0,	2,	0,	1,	1,	AVRImpOpBase + 6,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #304 = ADJCALLSTACKUP
    { 303,	2,	0,	2,	0,	1,	2,	AVRImpOpBase + 3,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #303 = ADJCALLSTACKDOWN
    { 302,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #302 = ADDWRdRr
    { 301,	3,	1,	2,	0,	1,	1,	AVRImpOpBase + 0,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #301 = ADCWRdRr
    { 300,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #300 = G_UBFX
    { 299,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #299 = G_SBFX
    { 298,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #298 = G_VECREDUCE_UMIN
    { 297,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #297 = G_VECREDUCE_UMAX
    { 296,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #296 = G_VECREDUCE_SMIN
    { 295,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #295 = G_VECREDUCE_SMAX
    { 294,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #294 = G_VECREDUCE_XOR
    { 293,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #293 = G_VECREDUCE_OR
    { 292,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #292 = G_VECREDUCE_AND
    { 291,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #291 = G_VECREDUCE_MUL
    { 290,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #290 = G_VECREDUCE_ADD
    { 289,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #289 = G_VECREDUCE_FMINIMUM
    { 288,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #288 = G_VECREDUCE_FMAXIMUM
    { 287,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #287 = G_VECREDUCE_FMIN
    { 286,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #286 = G_VECREDUCE_FMAX
    { 285,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #285 = G_VECREDUCE_FMUL
    { 284,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #284 = G_VECREDUCE_FADD
    { 283,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #283 = G_VECREDUCE_SEQ_FMUL
    { 282,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #282 = G_VECREDUCE_SEQ_FADD
    { 281,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #281 = G_UBSANTRAP
    { 280,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #280 = G_DEBUGTRAP
    { 279,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #279 = G_TRAP
    { 278,	3,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #278 = G_BZERO
    { 277,	4,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #277 = G_MEMSET
    { 276,	4,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #276 = G_MEMMOVE
    { 275,	3,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #275 = G_MEMCPY_INLINE
    { 274,	4,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #274 = G_MEMCPY
    { 273,	2,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	142,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #273 = G_WRITE_REGISTER
    { 272,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #272 = G_READ_REGISTER
    { 271,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #271 = G_STRICT_FLDEXP
    { 270,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #270 = G_STRICT_FSQRT
    { 269,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #269 = G_STRICT_FMA
    { 268,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #268 = G_STRICT_FREM
    { 267,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #267 = G_STRICT_FDIV
    { 266,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #266 = G_STRICT_FMUL
    { 265,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #265 = G_STRICT_FSUB
    { 264,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #264 = G_STRICT_FADD
    { 263,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #263 = G_STACKRESTORE
    { 262,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #262 = G_STACKSAVE
    { 261,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #261 = G_DYN_STACKALLOC
    { 260,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #260 = G_JUMP_TABLE
    { 259,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #259 = G_BLOCK_ADDR
    { 258,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #258 = G_ADDRSPACE_CAST
    { 257,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #257 = G_FNEARBYINT
    { 256,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #256 = G_FRINT
    { 255,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #255 = G_FFLOOR
    { 254,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #254 = G_FSQRT
    { 253,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #253 = G_FTANH
    { 252,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #252 = G_FSINH
    { 251,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #251 = G_FCOSH
    { 250,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #250 = G_FATAN
    { 249,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #249 = G_FASIN
    { 248,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #248 = G_FACOS
    { 247,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #247 = G_FTAN
    { 246,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #246 = G_FSIN
    { 245,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #245 = G_FCOS
    { 244,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #244 = G_FCEIL
    { 243,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #243 = G_BITREVERSE
    { 242,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #242 = G_BSWAP
    { 241,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #241 = G_CTPOP
    { 240,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #240 = G_CTLZ_ZERO_UNDEF
    { 239,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #239 = G_CTLZ
    { 238,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #238 = G_CTTZ_ZERO_UNDEF
    { 237,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #237 = G_CTTZ
    { 236,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	138,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #236 = G_VECTOR_COMPRESS
    { 235,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #235 = G_SPLAT_VECTOR
    { 234,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	134,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #234 = G_SHUFFLE_VECTOR
    { 233,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #233 = G_EXTRACT_VECTOR_ELT
    { 232,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	127,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #232 = G_INSERT_VECTOR_ELT
    { 231,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #231 = G_EXTRACT_SUBVECTOR
    { 230,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #230 = G_INSERT_SUBVECTOR
    { 229,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #229 = G_VSCALE
    { 228,	3,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	124,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #228 = G_BRJT
    { 227,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #227 = G_BR
    { 226,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #226 = G_LLROUND
    { 225,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #225 = G_LROUND
    { 224,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #224 = G_ABS
    { 223,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #223 = G_UMAX
    { 222,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #222 = G_UMIN
    { 221,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #221 = G_SMAX
    { 220,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #220 = G_SMIN
    { 219,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #219 = G_PTRMASK
    { 218,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #218 = G_PTR_ADD
    { 217,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #217 = G_RESET_FPMODE
    { 216,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #216 = G_SET_FPMODE
    { 215,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #215 = G_GET_FPMODE
    { 214,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #214 = G_RESET_FPENV
    { 213,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #213 = G_SET_FPENV
    { 212,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #212 = G_GET_FPENV
    { 211,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #211 = G_FMAXIMUM
    { 210,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #210 = G_FMINIMUM
    { 209,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #209 = G_FMAXNUM_IEEE
    { 208,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #208 = G_FMINNUM_IEEE
    { 207,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #207 = G_FMAXNUM
    { 206,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #206 = G_FMINNUM
    { 205,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #205 = G_FCANONICALIZE
    { 204,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #204 = G_IS_FPCLASS
    { 203,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #203 = G_FCOPYSIGN
    { 202,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #202 = G_FABS
    { 201,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #201 = G_FPTOUI_SAT
    { 200,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #200 = G_FPTOSI_SAT
    { 199,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #199 = G_UITOFP
    { 198,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #198 = G_SITOFP
    { 197,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #197 = G_FPTOUI
    { 196,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #196 = G_FPTOSI
    { 195,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #195 = G_FPTRUNC
    { 194,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #194 = G_FPEXT
    { 193,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #193 = G_FNEG
    { 192,	3,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #192 = G_FFREXP
    { 191,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #191 = G_FLDEXP
    { 190,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #190 = G_FLOG10
    { 189,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #189 = G_FLOG2
    { 188,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #188 = G_FLOG
    { 187,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #187 = G_FEXP10
    { 186,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #186 = G_FEXP2
    { 185,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #185 = G_FEXP
    { 184,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #184 = G_FPOWI
    { 183,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #183 = G_FPOW
    { 182,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #182 = G_FREM
    { 181,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #181 = G_FDIV
    { 180,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #180 = G_FMAD
    { 179,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #179 = G_FMA
    { 178,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #178 = G_FMUL
    { 177,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #177 = G_FSUB
    { 176,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #176 = G_FADD
    { 175,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #175 = G_UDIVFIXSAT
    { 174,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #174 = G_SDIVFIXSAT
    { 173,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #173 = G_UDIVFIX
    { 172,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #172 = G_SDIVFIX
    { 171,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #171 = G_UMULFIXSAT
    { 170,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #170 = G_SMULFIXSAT
    { 169,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #169 = G_UMULFIX
    { 168,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #168 = G_SMULFIX
    { 167,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #167 = G_SSHLSAT
    { 166,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #166 = G_USHLSAT
    { 165,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #165 = G_SSUBSAT
    { 164,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #164 = G_USUBSAT
    { 163,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #163 = G_SADDSAT
    { 162,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #162 = G_UADDSAT
    { 161,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #161 = G_SMULH
    { 160,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #160 = G_UMULH
    { 159,	4,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #159 = G_SMULO
    { 158,	4,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #158 = G_UMULO
    { 157,	5,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #157 = G_SSUBE
    { 156,	4,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #156 = G_SSUBO
    { 155,	5,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #155 = G_SADDE
    { 154,	4,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #154 = G_SADDO
    { 153,	5,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #153 = G_USUBE
    { 152,	4,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #152 = G_USUBO
    { 151,	5,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #151 = G_UADDE
    { 150,	4,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #150 = G_UADDO
    { 149,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #149 = G_SELECT
    { 148,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #148 = G_UCMP
    { 147,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #147 = G_SCMP
    { 146,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #146 = G_FCMP
    { 145,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #145 = G_ICMP
    { 144,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #144 = G_ROTL
    { 143,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #143 = G_ROTR
    { 142,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #142 = G_FSHR
    { 141,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #141 = G_FSHL
    { 140,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #140 = G_ASHR
    { 139,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #139 = G_LSHR
    { 138,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #138 = G_SHL
    { 137,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #137 = G_ZEXT
    { 136,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #136 = G_SEXT_INREG
    { 135,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #135 = G_SEXT
    { 134,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #134 = G_VAARG
    { 133,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #133 = G_VASTART
    { 132,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #132 = G_FCONSTANT
    { 131,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #131 = G_CONSTANT
    { 130,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #130 = G_TRUNC
    { 129,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #129 = G_ANYEXT
    { 128,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #128 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
    { 127,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #127 = G_INTRINSIC_CONVERGENT
    { 126,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #126 = G_INTRINSIC_W_SIDE_EFFECTS
    { 125,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #125 = G_INTRINSIC
    { 124,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #124 = G_INVOKE_REGION_START
    { 123,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #123 = G_BRINDIRECT
    { 122,	2,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #122 = G_BRCOND
    { 121,	4,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	94,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #121 = G_PREFETCH
    { 120,	2,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	21,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #120 = G_FENCE
    { 119,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #119 = G_ATOMICRMW_USUB_SAT
    { 118,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #118 = G_ATOMICRMW_USUB_COND
    { 117,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #117 = G_ATOMICRMW_UDEC_WRAP
    { 116,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #116 = G_ATOMICRMW_UINC_WRAP
    { 115,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #115 = G_ATOMICRMW_FMIN
    { 114,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #114 = G_ATOMICRMW_FMAX
    { 113,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #113 = G_ATOMICRMW_FSUB
    { 112,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #112 = G_ATOMICRMW_FADD
    { 111,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #111 = G_ATOMICRMW_UMIN
    { 110,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #110 = G_ATOMICRMW_UMAX
    { 109,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #109 = G_ATOMICRMW_MIN
    { 108,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #108 = G_ATOMICRMW_MAX
    { 107,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #107 = G_ATOMICRMW_XOR
    { 106,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #106 = G_ATOMICRMW_OR
    { 105,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #105 = G_ATOMICRMW_NAND
    { 104,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #104 = G_ATOMICRMW_AND
    { 103,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #103 = G_ATOMICRMW_SUB
    { 102,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #102 = G_ATOMICRMW_ADD
    { 101,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #101 = G_ATOMICRMW_XCHG
    { 100,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #100 = G_ATOMIC_CMPXCHG
    { 99,	5,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	82,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #99 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
    { 98,	5,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	77,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #98 = G_INDEXED_STORE
    { 97,	2,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #97 = G_STORE
    { 96,	5,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #96 = G_INDEXED_ZEXTLOAD
    { 95,	5,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #95 = G_INDEXED_SEXTLOAD
    { 94,	5,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #94 = G_INDEXED_LOAD
    { 93,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #93 = G_ZEXTLOAD
    { 92,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #92 = G_SEXTLOAD
    { 91,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #91 = G_LOAD
    { 90,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #90 = G_READSTEADYCOUNTER
    { 89,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #89 = G_READCYCLECOUNTER
    { 88,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #88 = G_INTRINSIC_ROUNDEVEN
    { 87,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #87 = G_INTRINSIC_LLRINT
    { 86,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #86 = G_INTRINSIC_LRINT
    { 85,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #85 = G_INTRINSIC_ROUND
    { 84,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #84 = G_INTRINSIC_TRUNC
    { 83,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #83 = G_INTRINSIC_FPTRUNC_ROUND
    { 82,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #82 = G_CONSTANT_FOLD_BARRIER
    { 81,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #81 = G_FREEZE
    { 80,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #80 = G_BITCAST
    { 79,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #79 = G_INTTOPTR
    { 78,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #78 = G_PTRTOINT
    { 77,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #77 = G_CONCAT_VECTORS
    { 76,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #76 = G_BUILD_VECTOR_TRUNC
    { 75,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #75 = G_BUILD_VECTOR
    { 74,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #74 = G_MERGE_VALUES
    { 73,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #73 = G_INSERT
    { 72,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #72 = G_UNMERGE_VALUES
    { 71,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #71 = G_EXTRACT
    { 70,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #70 = G_CONSTANT_POOL
    { 69,	5,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	53,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #69 = G_PTRAUTH_GLOBAL_VALUE
    { 68,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #68 = G_GLOBAL_VALUE
    { 67,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #67 = G_FRAME_INDEX
    { 66,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #66 = G_PHI
    { 65,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #65 = G_IMPLICIT_DEF
    { 64,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #64 = G_XOR
    { 63,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #63 = G_OR
    { 62,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #62 = G_AND
    { 61,	4,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #61 = G_UDIVREM
    { 60,	4,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #60 = G_SDIVREM
    { 59,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #59 = G_UREM
    { 58,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #58 = G_SREM
    { 57,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #57 = G_UDIV
    { 56,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #56 = G_SDIV
    { 55,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #55 = G_MUL
    { 54,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #54 = G_SUB
    { 53,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #53 = G_ADD
    { 52,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #52 = G_ASSERT_ALIGN
    { 51,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #51 = G_ASSERT_ZEXT
    { 50,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #50 = G_ASSERT_SEXT
    { 49,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #49 = CONVERGENCECTRL_GLUE
    { 48,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #48 = CONVERGENCECTRL_LOOP
    { 47,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #47 = CONVERGENCECTRL_ANCHOR
    { 46,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #46 = CONVERGENCECTRL_ENTRY
    { 45,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #45 = JUMP_TABLE_DEBUG_INFO
    { 44,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #44 = MEMBARRIER
    { 43,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #43 = FAKE_USE
    { 42,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #42 = ICALL_BRANCH_FUNNEL
    { 41,	3,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	37,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #41 = PATCHABLE_TYPED_EVENT_CALL
    { 40,	2,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	35,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #40 = PATCHABLE_EVENT_CALL
    { 39,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #39 = PATCHABLE_TAIL_CALL
    { 38,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #38 = PATCHABLE_FUNCTION_EXIT
    { 37,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #37 = PATCHABLE_RET
    { 36,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #36 = PATCHABLE_FUNCTION_ENTER
    { 35,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #35 = PATCHABLE_OP
    { 34,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #34 = FAULTING_OP
    { 33,	2,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	33,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #33 = LOCAL_ESCAPE
    { 32,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #32 = STATEPOINT
    { 31,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	30,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #31 = PREALLOCATED_ARG
    { 30,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #30 = PREALLOCATED_SETUP
    { 29,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	29,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #29 = LOAD_STACK_GUARD
    { 28,	6,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	23,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #28 = PATCHPOINT
    { 27,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #27 = FENTRY_CALL
    { 26,	2,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #26 = STACKMAP
    { 25,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	19,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #25 = ARITH_FENCE
    { 24,	4,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	15,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #24 = PSEUDO_PROBE
    { 23,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #23 = LIFETIME_END
    { 22,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #22 = LIFETIME_START
    { 21,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #21 = BUNDLE
    { 20,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #20 = COPY
    { 19,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #19 = REG_SEQUENCE
    { 18,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #18 = DBG_LABEL
    { 17,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #17 = DBG_PHI
    { 16,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #16 = DBG_INSTR_REF
    { 15,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #15 = DBG_VALUE_LIST
    { 14,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #14 = DBG_VALUE
    { 13,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #13 = COPY_TO_REGCLASS
    { 12,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #12 = SUBREG_TO_REG
    { 11,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #11 = INIT_UNDEF
    { 10,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #10 = IMPLICIT_DEF
    { 9,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	5,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #9 = INSERT_SUBREG
    { 8,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #8 = EXTRACT_SUBREG
    { 7,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #7 = KILL
    { 6,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #6 = ANNOTATION_LABEL
    { 5,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #5 = GC_LABEL
    { 4,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #4 = EH_LABEL
    { 3,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #3 = CFI_INSTRUCTION
    { 2,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #2 = INLINEASM_BR
    { 1,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1 = INLINEASM
    { 0,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #0 = PHI
  }, {
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 1 */
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
    /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
    /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 152 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 155 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 158 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 161 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
    /* 163 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 166 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 169 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 174 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 177 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 179 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 181 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 184 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 187 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 189 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 191 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 193 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 194 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 197 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 200 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 203 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 206 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 208 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 211 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 214 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 216 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 218 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 220 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) },
    /* 223 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 225 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 227 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 229 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 232 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 235 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 237 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 238 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
    /* 240 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 242 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 244 */ { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 246 */ { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 249 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 252 */ { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 255 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 257 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 261 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 265 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 269 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 272 */ { AVR::IWREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::IWREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 275 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 278 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 281 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 283 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 285 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 287 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 289 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 291 */ { AVR::LD8loRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8loRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 293 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 295 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 298 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 300 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
    /* 303 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 305 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 307 */ { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 308 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 311 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 315 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 317 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
  }, {
    /* 0 */
    /* 0 */ AVR::SREG, AVR::SREG,
    /* 2 */ AVR::SREG,
    /* 3 */ AVR::SP, AVR::SP, AVR::SREG,
    /* 6 */ AVR::SP, AVR::R31R30,
    /* 8 */ AVR::R0,
    /* 9 */ AVR::R31R30,
    /* 10 */ AVR::SP, AVR::SP,
    /* 12 */ AVR::R1, AVR::SREG,
    /* 14 */ AVR::R17, AVR::SREG,
    /* 16 */ AVR::SP,
    /* 17 */ AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R1, AVR::R0,
    /* 33 */ AVR::R31R30, AVR::R0,
    /* 35 */ AVR::R1, AVR::R0, AVR::SREG,
    /* 38 */ AVR::R31R30, AVR::R1, AVR::R0,
    /* 41 */ AVR::R1, AVR::R0, AVR::R31R30,
  }
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char AVRInstrNameData[] = {
  /* 0 */ "G_FLOG10\0"
  /* 9 */ "G_FEXP10\0"
  /* 18 */ "ROLBRdR1\0"
  /* 27 */ "Lsl32\0"
  /* 33 */ "Asr32\0"
  /* 39 */ "Lsr32\0"
  /* 45 */ "G_FLOG2\0"
  /* 53 */ "G_FEXP2\0"
  /* 61 */ "AtomicLoadSub16\0"
  /* 77 */ "AtomicLoad16\0"
  /* 90 */ "AtomicLoadAdd16\0"
  /* 106 */ "AtomicLoadAnd16\0"
  /* 122 */ "AtomicStore16\0"
  /* 136 */ "Rol16\0"
  /* 142 */ "Lsl16\0"
  /* 148 */ "AtomicLoadOr16\0"
  /* 163 */ "Ror16\0"
  /* 169 */ "AtomicLoadXor16\0"
  /* 185 */ "Asr16\0"
  /* 191 */ "Lsr16\0"
  /* 197 */ "Select16\0"
  /* 206 */ "ROLBRdR17\0"
  /* 216 */ "AtomicLoadSub8\0"
  /* 231 */ "AtomicLoad8\0"
  /* 243 */ "AtomicLoadAdd8\0"
  /* 258 */ "AtomicLoadAnd8\0"
  /* 273 */ "AtomicStore8\0"
  /* 286 */ "Rol8\0"
  /* 291 */ "Lsl8\0"
  /* 296 */ "AtomicLoadOr8\0"
  /* 310 */ "Ror8\0"
  /* 315 */ "AtomicLoadXor8\0"
  /* 330 */ "Asr8\0"
  /* 335 */ "Lsr8\0"
  /* 340 */ "Select8\0"
  /* 348 */ "G_FMA\0"
  /* 354 */ "G_STRICT_FMA\0"
  /* 367 */ "INRdA\0"
  /* 373 */ "INWRdA\0"
  /* 380 */ "G_FSUB\0"
  /* 387 */ "G_STRICT_FSUB\0"
  /* 401 */ "G_ATOMICRMW_FSUB\0"
  /* 418 */ "G_SUB\0"
  /* 424 */ "G_ATOMICRMW_SUB\0"
  /* 440 */ "SBRCRrB\0"
  /* 448 */ "SBRSRrB\0"
  /* 456 */ "G_INTRINSIC\0"
  /* 468 */ "G_FPTRUNC\0"
  /* 478 */ "G_INTRINSIC_TRUNC\0"
  /* 496 */ "G_TRUNC\0"
  /* 504 */ "G_BUILD_VECTOR_TRUNC\0"
  /* 525 */ "G_DYN_STACKALLOC\0"
  /* 542 */ "SPREAD\0"
  /* 549 */ "G_FMAD\0"
  /* 556 */ "G_INDEXED_SEXTLOAD\0"
  /* 575 */ "G_SEXTLOAD\0"
  /* 586 */ "G_INDEXED_ZEXTLOAD\0"
  /* 605 */ "G_ZEXTLOAD\0"
  /* 616 */ "G_INDEXED_LOAD\0"
  /* 631 */ "G_LOAD\0"
  /* 638 */ "G_VECREDUCE_FADD\0"
  /* 655 */ "G_FADD\0"
  /* 662 */ "G_VECREDUCE_SEQ_FADD\0"
  /* 683 */ "G_STRICT_FADD\0"
  /* 697 */ "G_ATOMICRMW_FADD\0"
  /* 714 */ "G_VECREDUCE_ADD\0"
  /* 730 */ "G_ADD\0"
  /* 736 */ "G_PTR_ADD\0"
  /* 746 */ "G_ATOMICRMW_ADD\0"
  /* 762 */ "BLD\0"
  /* 766 */ "G_ATOMICRMW_NAND\0"
  /* 783 */ "G_VECREDUCE_AND\0"
  /* 799 */ "G_AND\0"
  /* 805 */ "G_ATOMICRMW_AND\0"
  /* 821 */ "LIFETIME_END\0"
  /* 834 */ "G_BRCOND\0"
  /* 843 */ "G_ATOMICRMW_USUB_COND\0"
  /* 865 */ "G_LLROUND\0"
  /* 875 */ "G_LROUND\0"
  /* 884 */ "G_INTRINSIC_ROUND\0"
  /* 902 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
  /* 928 */ "LOAD_STACK_GUARD\0"
  /* 945 */ "PSEUDO_PROBE\0"
  /* 958 */ "G_SSUBE\0"
  /* 966 */ "G_USUBE\0"
  /* 974 */ "G_FENCE\0"
  /* 982 */ "ARITH_FENCE\0"
  /* 994 */ "REG_SEQUENCE\0"
  /* 1007 */ "G_SADDE\0"
  /* 1015 */ "G_UADDE\0"
  /* 1023 */ "G_GET_FPMODE\0"
  /* 1036 */ "G_RESET_FPMODE\0"
  /* 1051 */ "G_SET_FPMODE\0"
  /* 1064 */ "G_FMINNUM_IEEE\0"
  /* 1079 */ "G_FMAXNUM_IEEE\0"
  /* 1094 */ "G_VSCALE\0"
  /* 1103 */ "G_JUMP_TABLE\0"
  /* 1116 */ "BUNDLE\0"
  /* 1123 */ "G_MEMCPY_INLINE\0"
  /* 1139 */ "LOCAL_ESCAPE\0"
  /* 1152 */ "G_STACKRESTORE\0"
  /* 1167 */ "G_INDEXED_STORE\0"
  /* 1183 */ "G_STORE\0"
  /* 1191 */ "CPSE\0"
  /* 1196 */ "G_BITREVERSE\0"
  /* 1209 */ "FAKE_USE\0"
  /* 1218 */ "SPWRITE\0"
  /* 1226 */ "DBG_VALUE\0"
  /* 1236 */ "G_GLOBAL_VALUE\0"
  /* 1251 */ "G_PTRAUTH_GLOBAL_VALUE\0"
  /* 1274 */ "CONVERGENCECTRL_GLUE\0"
  /* 1295 */ "G_STACKSAVE\0"
  /* 1307 */ "G_MEMMOVE\0"
  /* 1317 */ "G_FREEZE\0"
  /* 1326 */ "G_FCANONICALIZE\0"
  /* 1342 */ "G_CTLZ_ZERO_UNDEF\0"
  /* 1360 */ "G_CTTZ_ZERO_UNDEF\0"
  /* 1378 */ "INIT_UNDEF\0"
  /* 1389 */ "G_IMPLICIT_DEF\0"
  /* 1404 */ "DBG_INSTR_REF\0"
  /* 1418 */ "G_FNEG\0"
  /* 1425 */ "EXTRACT_SUBREG\0"
  /* 1440 */ "INSERT_SUBREG\0"
  /* 1454 */ "G_SEXT_INREG\0"
  /* 1467 */ "SUBREG_TO_REG\0"
  /* 1481 */ "G_ATOMIC_CMPXCHG\0"
  /* 1498 */ "G_ATOMICRMW_XCHG\0"
  /* 1515 */ "G_FLOG\0"
  /* 1522 */ "G_VAARG\0"
  /* 1530 */ "PREALLOCATED_ARG\0"
  /* 1547 */ "G_PREFETCH\0"
  /* 1558 */ "G_SMULH\0"
  /* 1566 */ "G_UMULH\0"
  /* 1574 */ "G_FTANH\0"
  /* 1582 */ "G_FSINH\0"
  /* 1590 */ "G_FCOSH\0"
  /* 1598 */ "DBG_PHI\0"
  /* 1606 */ "G_FPTOSI\0"
  /* 1615 */ "RETI\0"
  /* 1620 */ "G_FPTOUI\0"
  /* 1629 */ "G_FPOWI\0"
  /* 1637 */ "BREAK\0"
  /* 1643 */ "G_PTRMASK\0"
  /* 1653 */ "DESK\0"
  /* 1658 */ "SUBIRdK\0"
  /* 1666 */ "SBCIRdK\0"
  /* 1674 */ "LDIRdK\0"
  /* 1681 */ "ANDIRdK\0"
  /* 1689 */ "CPIRdK\0"
  /* 1696 */ "ORIRdK\0"
  /* 1703 */ "LDSRdK\0"
  /* 1710 */ "SBIWRdK\0"
  /* 1718 */ "SUBIWRdK\0"
  /* 1727 */ "SBCIWRdK\0"
  /* 1736 */ "ADIWRdK\0"
  /* 1744 */ "LDIWRdK\0"
  /* 1752 */ "ANDIWRdK\0"
  /* 1761 */ "ORIWRdK\0"
  /* 1769 */ "LDSWRdK\0"
  /* 1777 */ "GC_LABEL\0"
  /* 1786 */ "DBG_LABEL\0"
  /* 1796 */ "EH_LABEL\0"
  /* 1805 */ "ANNOTATION_LABEL\0"
  /* 1822 */ "ICALL_BRANCH_FUNNEL\0"
  /* 1842 */ "G_FSHL\0"
  /* 1849 */ "G_SHL\0"
  /* 1855 */ "G_FCEIL\0"
  /* 1863 */ "EICALL\0"
  /* 1870 */ "PATCHABLE_TAIL_CALL\0"
  /* 1890 */ "PATCHABLE_TYPED_EVENT_CALL\0"
  /* 1917 */ "PATCHABLE_EVENT_CALL\0"
  /* 1938 */ "FENTRY_CALL\0"
  /* 1950 */ "KILL\0"
  /* 1955 */ "G_CONSTANT_POOL\0"
  /* 1971 */ "G_ROTL\0"
  /* 1978 */ "G_VECREDUCE_FMUL\0"
  /* 1995 */ "G_FMUL\0"
  /* 2002 */ "G_VECREDUCE_SEQ_FMUL\0"
  /* 2023 */ "G_STRICT_FMUL\0"
  /* 2037 */ "G_VECREDUCE_MUL\0"
  /* 2053 */ "G_MUL\0"
  /* 2059 */ "G_FREM\0"
  /* 2066 */ "G_STRICT_FREM\0"
  /* 2080 */ "G_SREM\0"
  /* 2087 */ "G_UREM\0"
  /* 2094 */ "G_SDIVREM\0"
  /* 2104 */ "G_UDIVREM\0"
  /* 2114 */ "ELPM\0"
  /* 2119 */ "SPM\0"
  /* 2123 */ "INLINEASM\0"
  /* 2133 */ "G_VECREDUCE_FMINIMUM\0"
  /* 2154 */ "G_FMINIMUM\0"
  /* 2165 */ "G_VECREDUCE_FMAXIMUM\0"
  /* 2186 */ "G_FMAXIMUM\0"
  /* 2197 */ "G_FMINNUM\0"
  /* 2207 */ "G_FMAXNUM\0"
  /* 2217 */ "G_FATAN\0"
  /* 2225 */ "G_FTAN\0"
  /* 2232 */ "G_INTRINSIC_ROUNDEVEN\0"
  /* 2254 */ "G_ASSERT_ALIGN\0"
  /* 2269 */ "G_FCOPYSIGN\0"
  /* 2281 */ "G_VECREDUCE_FMIN\0"
  /* 2298 */ "G_ATOMICRMW_FMIN\0"
  /* 2315 */ "G_VECREDUCE_SMIN\0"
  /* 2332 */ "G_SMIN\0"
  /* 2339 */ "G_VECREDUCE_UMIN\0"
  /* 2356 */ "G_UMIN\0"
  /* 2363 */ "G_ATOMICRMW_UMIN\0"
  /* 2380 */ "G_ATOMICRMW_MIN\0"
  /* 2396 */ "G_FASIN\0"
  /* 2404 */ "G_FSIN\0"
  /* 2411 */ "CFI_INSTRUCTION\0"
  /* 2427 */ "ADJCALLSTACKDOWN\0"
  /* 2444 */ "G_SSUBO\0"
  /* 2452 */ "G_USUBO\0"
  /* 2460 */ "G_SADDO\0"
  /* 2468 */ "G_UADDO\0"
  /* 2476 */ "JUMP_TABLE_DEBUG_INFO\0"
  /* 2498 */ "G_SMULO\0"
  /* 2506 */ "G_UMULO\0"
  /* 2514 */ "G_BZERO\0"
  /* 2522 */ "STACKMAP\0"
  /* 2531 */ "G_DEBUGTRAP\0"
  /* 2543 */ "G_UBSANTRAP\0"
  /* 2555 */ "G_TRAP\0"
  /* 2562 */ "G_ATOMICRMW_UDEC_WRAP\0"
  /* 2584 */ "G_ATOMICRMW_UINC_WRAP\0"
  /* 2606 */ "G_BSWAP\0"
  /* 2614 */ "SLEEP\0"
  /* 2620 */ "G_SITOFP\0"
  /* 2629 */ "G_UITOFP\0"
  /* 2638 */ "G_FCMP\0"
  /* 2645 */ "G_ICMP\0"
  /* 2652 */ "G_SCMP\0"
  /* 2659 */ "G_UCMP\0"
  /* 2666 */ "EIJMP\0"
  /* 2672 */ "NOP\0"
  /* 2676 */ "CONVERGENCECTRL_LOOP\0"
  /* 2697 */ "G_CTPOP\0"
  /* 2705 */ "PATCHABLE_OP\0"
  /* 2718 */ "FAULTING_OP\0"
  /* 2730 */ "ADJCALLSTACKUP\0"
  /* 2745 */ "PREALLOCATED_SETUP\0"
  /* 2764 */ "G_FLDEXP\0"
  /* 2773 */ "G_STRICT_FLDEXP\0"
  /* 2789 */ "G_FEXP\0"
  /* 2796 */ "G_FFREXP\0"
  /* 2805 */ "LDDWRdYQ\0"
  /* 2814 */ "LDDRdPtrQ\0"
  /* 2824 */ "LDDWRdPtrQ\0"
  /* 2835 */ "G_BR\0"
  /* 2840 */ "INLINEASM_BR\0"
  /* 2853 */ "G_BLOCK_ADDR\0"
  /* 2866 */ "WDR\0"
  /* 2870 */ "MEMBARRIER\0"
  /* 2881 */ "G_CONSTANT_FOLD_BARRIER\0"
  /* 2905 */ "PATCHABLE_FUNCTION_ENTER\0"
  /* 2930 */ "G_READCYCLECOUNTER\0"
  /* 2949 */ "G_READSTEADYCOUNTER\0"
  /* 2969 */ "G_READ_REGISTER\0"
  /* 2985 */ "G_WRITE_REGISTER\0"
  /* 3002 */ "G_ASHR\0"
  /* 3009 */ "G_FSHR\0"
  /* 3016 */ "G_LSHR\0"
  /* 3023 */ "CONVERGENCECTRL_ANCHOR\0"
  /* 3046 */ "G_FFLOOR\0"
  /* 3055 */ "G_EXTRACT_SUBVECTOR\0"
  /* 3075 */ "G_INSERT_SUBVECTOR\0"
  /* 3094 */ "G_BUILD_VECTOR\0"
  /* 3109 */ "G_SHUFFLE_VECTOR\0"
  /* 3126 */ "G_SPLAT_VECTOR\0"
  /* 3141 */ "G_VECREDUCE_XOR\0"
  /* 3157 */ "G_XOR\0"
  /* 3163 */ "G_ATOMICRMW_XOR\0"
  /* 3179 */ "G_VECREDUCE_OR\0"
  /* 3194 */ "G_OR\0"
  /* 3199 */ "G_ATOMICRMW_OR\0"
  /* 3214 */ "G_ROTR\0"
  /* 3221 */ "G_INTTOPTR\0"
  /* 3232 */ "G_FABS\0"
  /* 3239 */ "G_ABS\0"
  /* 3245 */ "G_UNMERGE_VALUES\0"
  /* 3262 */ "G_MERGE_VALUES\0"
  /* 3277 */ "FMULS\0"
  /* 3283 */ "G_FACOS\0"
  /* 3291 */ "G_FCOS\0"
  /* 3298 */ "G_CONCAT_VECTORS\0"
  /* 3315 */ "COPY_TO_REGCLASS\0"
  /* 3332 */ "G_IS_FPCLASS\0"
  /* 3345 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
  /* 3375 */ "G_VECTOR_COMPRESS\0"
  /* 3393 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
  /* 3420 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
  /* 3458 */ "G_SSUBSAT\0"
  /* 3468 */ "G_USUBSAT\0"
  /* 3478 */ "G_SADDSAT\0"
  /* 3488 */ "G_UADDSAT\0"
  /* 3498 */ "G_SSHLSAT\0"
  /* 3508 */ "G_USHLSAT\0"
  /* 3518 */ "G_SMULFIXSAT\0"
  /* 3531 */ "G_UMULFIXSAT\0"
  /* 3544 */ "G_SDIVFIXSAT\0"
  /* 3557 */ "G_UDIVFIXSAT\0"
  /* 3570 */ "G_ATOMICRMW_USUB_SAT\0"
  /* 3591 */ "G_FPTOSI_SAT\0"
  /* 3604 */ "G_FPTOUI_SAT\0"
  /* 3617 */ "G_EXTRACT\0"
  /* 3627 */ "G_SELECT\0"
  /* 3636 */ "G_BRINDIRECT\0"
  /* 3649 */ "PATCHABLE_RET\0"
  /* 3663 */ "G_MEMSET\0"
  /* 3672 */ "PATCHABLE_FUNCTION_EXIT\0"
  /* 3696 */ "G_BRJT\0"
  /* 3703 */ "G_EXTRACT_VECTOR_ELT\0"
  /* 3724 */ "G_INSERT_VECTOR_ELT\0"
  /* 3744 */ "G_FCONSTANT\0"
  /* 3756 */ "G_CONSTANT\0"
  /* 3767 */ "G_INTRINSIC_CONVERGENT\0"
  /* 3790 */ "STATEPOINT\0"
  /* 3801 */ "PATCHPOINT\0"
  /* 3812 */ "G_PTRTOINT\0"
  /* 3823 */ "G_FRINT\0"
  /* 3831 */ "G_INTRINSIC_LLRINT\0"
  /* 3850 */ "G_INTRINSIC_LRINT\0"
  /* 3868 */ "G_FNEARBYINT\0"
  /* 3881 */ "G_VASTART\0"
  /* 3891 */ "LIFETIME_START\0"
  /* 3906 */ "G_INVOKE_REGION_START\0"
  /* 3928 */ "G_INSERT\0"
  /* 3937 */ "G_FSQRT\0"
  /* 3945 */ "G_STRICT_FSQRT\0"
  /* 3960 */ "G_BITCAST\0"
  /* 3970 */ "G_ADDRSPACE_CAST\0"
  /* 3987 */ "BST\0"
  /* 3991 */ "DBG_VALUE_LIST\0"
  /* 4006 */ "G_FPEXT\0"
  /* 4014 */ "G_SEXT\0"
  /* 4021 */ "G_ASSERT_SEXT\0"
  /* 4035 */ "G_ANYEXT\0"
  /* 4044 */ "G_ZEXT\0"
  /* 4051 */ "G_ASSERT_ZEXT\0"
  /* 4065 */ "FMULSU\0"
  /* 4072 */ "G_FDIV\0"
  /* 4079 */ "G_STRICT_FDIV\0"
  /* 4093 */ "G_SDIV\0"
  /* 4100 */ "G_UDIV\0"
  /* 4107 */ "G_GET_FPENV\0"
  /* 4119 */ "G_RESET_FPENV\0"
  /* 4133 */ "G_SET_FPENV\0"
  /* 4145 */ "G_FPOW\0"
  /* 4152 */ "G_VECREDUCE_FMAX\0"
  /* 4169 */ "G_ATOMICRMW_FMAX\0"
  /* 4186 */ "G_VECREDUCE_SMAX\0"
  /* 4203 */ "G_SMAX\0"
  /* 4210 */ "G_VECREDUCE_UMAX\0"
  /* 4227 */ "G_UMAX\0"
  /* 4234 */ "G_ATOMICRMW_UMAX\0"
  /* 4251 */ "G_ATOMICRMW_MAX\0"
  /* 4267 */ "FRMIDX\0"
  /* 4274 */ "G_FRAME_INDEX\0"
  /* 4288 */ "G_SBFX\0"
  /* 4295 */ "G_UBFX\0"
  /* 4302 */ "G_SMULFIX\0"
  /* 4312 */ "G_UMULFIX\0"
  /* 4322 */ "G_SDIVFIX\0"
  /* 4332 */ "G_UDIVFIX\0"
  /* 4342 */ "G_MEMCPY\0"
  /* 4351 */ "COPY\0"
  /* 4356 */ "CONVERGENCECTRL_ENTRY\0"
  /* 4378 */ "G_CTLZ\0"
  /* 4385 */ "G_CTTZ\0"
  /* 4392 */ "ELPMBRdZ\0"
  /* 4401 */ "ELPMRdZ\0"
  /* 4409 */ "ELPMWRdZ\0"
  /* 4418 */ "SBICAb\0"
  /* 4425 */ "CBIAb\0"
  /* 4431 */ "SBIAb\0"
  /* 4437 */ "SBISAb\0"
  /* 4444 */ "LDRdPtrPd\0"
  /* 4454 */ "LDWRdPtrPd\0"
  /* 4465 */ "RORBRd\0"
  /* 4472 */ "DECRd\0"
  /* 4478 */ "INCRd\0"
  /* 4484 */ "NEGRd\0"
  /* 4490 */ "COMRd\0"
  /* 4496 */ "LSLBNRd\0"
  /* 4504 */ "ASRBNRd\0"
  /* 4512 */ "LSRBNRd\0"
  /* 4520 */ "LSLWNRd\0"
  /* 4528 */ "ASRWNRd\0"
  /* 4536 */ "LSRWNRd\0"
  /* 4544 */ "SWAPRd\0"
  /* 4551 */ "POPRd\0"
  /* 4557 */ "RORRd\0"
  /* 4563 */ "ASRRd\0"
  /* 4569 */ "LSRRd\0"
  /* 4575 */ "NEGWRd\0"
  /* 4582 */ "ROLWRd\0"
  /* 4589 */ "LSLWRd\0"
  /* 4596 */ "COMWRd\0"
  /* 4603 */ "POPWRd\0"
  /* 4610 */ "RORWRd\0"
  /* 4617 */ "ASRWRd\0"
  /* 4624 */ "LSRWRd\0"
  /* 4631 */ "LACZRd\0"
  /* 4638 */ "XCHZRd\0"
  /* 4645 */ "LASZRd\0"
  /* 4652 */ "LATZRd\0"
  /* 4659 */ "LSLWHiRd\0"
  /* 4668 */ "ASRWLoRd\0"
  /* 4677 */ "LSRWLoRd\0"
  /* 4686 */ "AtomicFence\0"
  /* 4698 */ "SPMZPi\0"
  /* 4705 */ "ELPMBRdZPi\0"
  /* 4716 */ "ELPMRdZPi\0"
  /* 4726 */ "ELPMWRdZPi\0"
  /* 4737 */ "LDRdPtrPi\0"
  /* 4747 */ "LDWRdPtrPi\0"
  /* 4758 */ "BRGEk\0"
  /* 4764 */ "BRNEk\0"
  /* 4770 */ "BRSHk\0"
  /* 4776 */ "BRMIk\0"
  /* 4782 */ "RCALLk\0"
  /* 4789 */ "BRPLk\0"
  /* 4795 */ "BRLOk\0"
  /* 4801 */ "RJMPk\0"
  /* 4807 */ "BREQk\0"
  /* 4813 */ "BRLTk\0"
  /* 4819 */ "BRBCsk\0"
  /* 4826 */ "BRBSsk\0"
  /* 4833 */ "CopyZero\0"
  /* 4842 */ "OUTARr\0"
  /* 4849 */ "OUTWARr\0"
  /* 4857 */ "PUSHRr\0"
  /* 4864 */ "STSKRr\0"
  /* 4871 */ "STSWKRr\0"
  /* 4879 */ "STDSPQRr\0"
  /* 4888 */ "STDWSPQRr\0"
  /* 4898 */ "STDPtrQRr\0"
  /* 4908 */ "STDWPtrQRr\0"
  /* 4919 */ "PUSHWRr\0"
  /* 4927 */ "STPtrPdRr\0"
  /* 4937 */ "STWPtrPdRr\0"
  /* 4948 */ "SUBRdRr\0"
  /* 4956 */ "SBCRdRr\0"
  /* 4964 */ "ADCRdRr\0"
  /* 4972 */ "CPCRdRr\0"
  /* 4980 */ "ADDRdRr\0"
  /* 4988 */ "ANDRdRr\0"
  /* 4996 */ "MULRdRr\0"
  /* 5004 */ "CPRdRr\0"
  /* 5011 */ "EORRdRr\0"
  /* 5019 */ "MULSRdRr\0"
  /* 5028 */ "MULSURdRr\0"
  /* 5038 */ "MOVRdRr\0"
  /* 5046 */ "SUBWRdRr\0"
  /* 5055 */ "SBCWRdRr\0"
  /* 5064 */ "ADCWRdRr\0"
  /* 5073 */ "CPCWRdRr\0"
  /* 5082 */ "ADDWRdRr\0"
  /* 5091 */ "ANDWRdRr\0"
  /* 5100 */ "CPWRdRr\0"
  /* 5108 */ "EORWRdRr\0"
  /* 5117 */ "MOVWRdRr\0"
  /* 5126 */ "STPtrPiRr\0"
  /* 5136 */ "STWPtrPiRr\0"
  /* 5147 */ "STPtrRr\0"
  /* 5155 */ "STWPtrRr\0"
  /* 5164 */ "LDRdPtr\0"
  /* 5172 */ "LDWRdPtr\0"
  /* 5181 */ "BCLRs\0"
  /* 5187 */ "BSETs\0"
  /* 5193 */ "LDSRdKTiny\0"
  /* 5204 */ "STSKRrTiny\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const unsigned AVRInstrNameIndices[] = {
    1602U, 2123U, 2840U, 2411U, 1796U, 1777U, 1805U, 1950U, 
    1425U, 1440U, 1391U, 1378U, 1467U, 3315U, 1226U, 3991U, 
    1404U, 1598U, 1786U, 994U, 4351U, 1116U, 3891U, 821U, 
    945U, 982U, 2522U, 1938U, 3801U, 928U, 2745U, 1530U, 
    3790U, 1139U, 2718U, 2705U, 2905U, 3649U, 3672U, 1870U, 
    1917U, 1890U, 1822U, 1209U, 2870U, 2476U, 4356U, 3023U, 
    2676U, 1274U, 4021U, 4051U, 2254U, 730U, 418U, 2053U, 
    4093U, 4100U, 2080U, 2087U, 2094U, 2104U, 799U, 3194U, 
    3157U, 1389U, 1600U, 4274U, 1236U, 1251U, 1955U, 3617U, 
    3245U, 3928U, 3262U, 3094U, 504U, 3298U, 3812U, 3221U, 
    3960U, 1317U, 2881U, 902U, 478U, 884U, 3850U, 3831U, 
    2232U, 2930U, 2949U, 631U, 575U, 605U, 616U, 556U, 
    586U, 1183U, 1167U, 3345U, 1481U, 1498U, 746U, 424U, 
    805U, 766U, 3199U, 3163U, 4251U, 2380U, 4234U, 2363U, 
    697U, 401U, 4169U, 2298U, 2584U, 2562U, 843U, 3570U, 
    974U, 1547U, 834U, 3636U, 3906U, 456U, 3393U, 3767U, 
    3420U, 4035U, 496U, 3756U, 3744U, 3881U, 1522U, 4014U, 
    1454U, 4044U, 1849U, 3016U, 3002U, 1842U, 3009U, 3214U, 
    1971U, 2645U, 2638U, 2652U, 2659U, 3627U, 2468U, 1015U, 
    2452U, 966U, 2460U, 1007U, 2444U, 958U, 2506U, 2498U, 
    1566U, 1558U, 3488U, 3478U, 3468U, 3458U, 3508U, 3498U, 
    4302U, 4312U, 3518U, 3531U, 4322U, 4332U, 3544U, 3557U, 
    655U, 380U, 1995U, 348U, 549U, 4072U, 2059U, 4145U, 
    1629U, 2789U, 53U, 9U, 1515U, 45U, 0U, 2764U, 
    2796U, 1418U, 4006U, 468U, 1606U, 1620U, 2620U, 2629U, 
    3591U, 3604U, 3232U, 2269U, 3332U, 1326U, 2197U, 2207U, 
    1064U, 1079U, 2154U, 2186U, 4107U, 4133U, 4119U, 1023U, 
    1051U, 1036U, 736U, 1643U, 2332U, 4203U, 2356U, 4227U, 
    3239U, 875U, 865U, 2835U, 3696U, 1094U, 3075U, 3055U, 
    3724U, 3703U, 3109U, 3126U, 3375U, 4385U, 1360U, 4378U, 
    1342U, 2697U, 2606U, 1196U, 1855U, 3291U, 2404U, 2225U, 
    3283U, 2396U, 2217U, 1590U, 1582U, 1574U, 3937U, 3046U, 
    3823U, 3868U, 3970U, 2853U, 1103U, 525U, 1295U, 1152U, 
    683U, 387U, 2023U, 4079U, 2066U, 354U, 3945U, 2773U, 
    2969U, 2985U, 4342U, 1123U, 1307U, 3663U, 2514U, 2555U, 
    2531U, 2543U, 662U, 2002U, 638U, 1978U, 4152U, 2281U, 
    2165U, 2133U, 714U, 2037U, 783U, 3179U, 3141U, 4186U, 
    2315U, 4210U, 2339U, 4288U, 4295U, 5064U, 5082U, 2427U, 
    2730U, 1752U, 5091U, 4504U, 4668U, 4528U, 4617U, 185U, 
    33U, 330U, 4686U, 77U, 231U, 90U, 243U, 106U, 
    258U, 148U, 296U, 61U, 216U, 169U, 315U, 122U, 
    273U, 4596U, 5073U, 5100U, 4833U, 4392U, 4705U, 4409U, 
    4726U, 5108U, 4267U, 373U, 2824U, 2805U, 1744U, 1769U, 
    5172U, 4454U, 4747U, 4393U, 4410U, 4727U, 4496U, 4659U, 
    4520U, 4589U, 4512U, 4677U, 4536U, 4624U, 142U, 27U, 
    291U, 191U, 39U, 335U, 4575U, 1761U, 5109U, 4849U, 
    4603U, 4919U, 18U, 206U, 4582U, 4465U, 4610U, 136U, 
    286U, 163U, 310U, 1727U, 5055U, 4016U, 542U, 1218U, 
    4879U, 4908U, 4888U, 4871U, 4937U, 5136U, 5155U, 1718U, 
    5046U, 197U, 340U, 4046U, 4964U, 4980U, 1736U, 1681U, 
    4988U, 4563U, 5181U, 762U, 4819U, 4826U, 1637U, 4807U, 
    4758U, 4795U, 4813U, 4776U, 4764U, 4789U, 4770U, 5187U, 
    3987U, 4783U, 4425U, 4490U, 4972U, 1689U, 5004U, 1191U, 
    4472U, 1653U, 1863U, 2666U, 2114U, 4401U, 4716U, 5011U, 
    1990U, 3277U, 4065U, 1864U, 2667U, 4478U, 367U, 4802U, 
    4631U, 4645U, 4652U, 2814U, 1674U, 5164U, 4444U, 4737U, 
    1703U, 5193U, 2115U, 4402U, 4717U, 4569U, 5038U, 5117U, 
    4996U, 5019U, 5028U, 4484U, 2672U, 1696U, 5012U, 4842U, 
    4551U, 4857U, 4782U, 3659U, 1615U, 4801U, 4557U, 1666U, 
    4956U, 4431U, 4418U, 4437U, 1710U, 440U, 448U, 2614U, 
    2119U, 4698U, 4898U, 4927U, 5126U, 5147U, 4864U, 5204U, 
    1658U, 4948U, 4544U, 2866U, 4638U, 
};

static inline void InitAVRMCInstrInfo(MCInstrInfo *II) {
  II->InitMCInstrInfo(AVRDescs.Insts, AVRInstrNameIndices, AVRInstrNameData, nullptr, nullptr, 493);
}

} // end namespace llvm
#endif // GET_INSTRINFO_MC_DESC

#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER
namespace llvm {
struct AVRGenInstrInfo : public TargetInstrInfo { … };
} // end namespace llvm
#endif // GET_INSTRINFO_HEADER

#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS


#endif // GET_INSTRINFO_HELPER_DECLS

#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS

#endif // GET_INSTRINFO_HELPERS

#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR
namespace llvm {
extern const AVRInstrTable AVRDescs;
extern const unsigned AVRInstrNameIndices[];
extern const char AVRInstrNameData[];
AVRGenInstrInfo::AVRGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
  InitMCInstrInfo(AVRDescs.Insts, AVRInstrNameIndices, AVRInstrNameData, nullptr, nullptr, 493);
}
} // end namespace llvm
#endif // GET_INSTRINFO_CTOR_DTOR

#ifdef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_OPERAND_ENUM
namespace llvm {
namespace AVR {
namespace OpName {
enum {
  OPERAND_LAST
};
} // end namespace OpName
} // end namespace AVR
} // end namespace llvm
#endif //GET_INSTRINFO_OPERAND_ENUM

#ifdef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_NAMED_OPS
namespace llvm {
namespace AVR {
LLVM_READONLY
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
  return -1;
}
} // end namespace AVR
} // end namespace llvm
#endif //GET_INSTRINFO_NAMED_OPS

#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
namespace llvm {
namespace AVR {
namespace OpTypes {
enum OperandType {
  LDDSTDPtrReg = 0,
  LDSTPtrReg = 1,
  brtarget_13 = 2,
  call_target = 3,
  f32imm = 4,
  f64imm = 5,
  i1imm = 6,
  i8imm = 7,
  i16imm = 8,
  i32imm = 9,
  i64imm = 10,
  imm7tiny = 11,
  imm16 = 12,
  imm_arith6 = 13,
  imm_com8 = 14,
  imm_ldi8 = 15,
  imm_port5 = 16,
  imm_port6 = 17,
  memri = 18,
  memspi = 19,
  ptype0 = 20,
  ptype1 = 21,
  ptype2 = 22,
  ptype3 = 23,
  ptype4 = 24,
  ptype5 = 25,
  rcalltarget_13 = 26,
  relbrtarget_7 = 27,
  type0 = 28,
  type1 = 29,
  type2 = 30,
  type3 = 31,
  type4 = 32,
  type5 = 33,
  untyped_imm_0 = 34,
  CCR = 35,
  DLDREGS = 36,
  DREGS = 37,
  DREGSLD8lo = 38,
  DREGSMOVW = 39,
  DREGSlo = 40,
  GPR8 = 41,
  GPR8lo = 42,
  GPRSP = 43,
  IWREGS = 44,
  LD8 = 45,
  LD8lo = 46,
  PTRDISPREGS = 47,
  PTRREGS = 48,
  ZREG = 49,
  OPERAND_TYPE_LIST_END
};
} // end namespace OpTypes
} // end namespace AVR
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM

#ifdef GET_INSTRINFO_OPERAND_TYPE
#undef GET_INSTRINFO_OPERAND_TYPE
namespace llvm {
namespace AVR {
LLVM_READONLY
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
  static const uint16_t Offsets[] = {
    /* PHI */
    0,
    /* INLINEASM */
    1,
    /* INLINEASM_BR */
    1,
    /* CFI_INSTRUCTION */
    1,
    /* EH_LABEL */
    2,
    /* GC_LABEL */
    3,
    /* ANNOTATION_LABEL */
    4,
    /* KILL */
    5,
    /* EXTRACT_SUBREG */
    5,
    /* INSERT_SUBREG */
    8,
    /* IMPLICIT_DEF */
    12,
    /* INIT_UNDEF */
    13,
    /* SUBREG_TO_REG */
    14,
    /* COPY_TO_REGCLASS */
    18,
    /* DBG_VALUE */
    21,
    /* DBG_VALUE_LIST */
    21,
    /* DBG_INSTR_REF */
    21,
    /* DBG_PHI */
    21,
    /* DBG_LABEL */
    21,
    /* REG_SEQUENCE */
    22,
    /* COPY */
    24,
    /* BUNDLE */
    26,
    /* LIFETIME_START */
    26,
    /* LIFETIME_END */
    27,
    /* PSEUDO_PROBE */
    28,
    /* ARITH_FENCE */
    32,
    /* STACKMAP */
    34,
    /* FENTRY_CALL */
    36,
    /* PATCHPOINT */
    36,
    /* LOAD_STACK_GUARD */
    42,
    /* PREALLOCATED_SETUP */
    43,
    /* PREALLOCATED_ARG */
    44,
    /* STATEPOINT */
    47,
    /* LOCAL_ESCAPE */
    47,
    /* FAULTING_OP */
    49,
    /* PATCHABLE_OP */
    50,
    /* PATCHABLE_FUNCTION_ENTER */
    50,
    /* PATCHABLE_RET */
    50,
    /* PATCHABLE_FUNCTION_EXIT */
    50,
    /* PATCHABLE_TAIL_CALL */
    50,
    /* PATCHABLE_EVENT_CALL */
    50,
    /* PATCHABLE_TYPED_EVENT_CALL */
    52,
    /* ICALL_BRANCH_FUNNEL */
    55,
    /* FAKE_USE */
    55,
    /* MEMBARRIER */
    55,
    /* JUMP_TABLE_DEBUG_INFO */
    55,
    /* CONVERGENCECTRL_ENTRY */
    56,
    /* CONVERGENCECTRL_ANCHOR */
    57,
    /* CONVERGENCECTRL_LOOP */
    58,
    /* CONVERGENCECTRL_GLUE */
    60,
    /* G_ASSERT_SEXT */
    61,
    /* G_ASSERT_ZEXT */
    64,
    /* G_ASSERT_ALIGN */
    67,
    /* G_ADD */
    70,
    /* G_SUB */
    73,
    /* G_MUL */
    76,
    /* G_SDIV */
    79,
    /* G_UDIV */
    82,
    /* G_SREM */
    85,
    /* G_UREM */
    88,
    /* G_SDIVREM */
    91,
    /* G_UDIVREM */
    95,
    /* G_AND */
    99,
    /* G_OR */
    102,
    /* G_XOR */
    105,
    /* G_IMPLICIT_DEF */
    108,
    /* G_PHI */
    109,
    /* G_FRAME_INDEX */
    110,
    /* G_GLOBAL_VALUE */
    112,
    /* G_PTRAUTH_GLOBAL_VALUE */
    114,
    /* G_CONSTANT_POOL */
    119,
    /* G_EXTRACT */
    121,
    /* G_UNMERGE_VALUES */
    124,
    /* G_INSERT */
    126,
    /* G_MERGE_VALUES */
    130,
    /* G_BUILD_VECTOR */
    132,
    /* G_BUILD_VECTOR_TRUNC */
    134,
    /* G_CONCAT_VECTORS */
    136,
    /* G_PTRTOINT */
    138,
    /* G_INTTOPTR */
    140,
    /* G_BITCAST */
    142,
    /* G_FREEZE */
    144,
    /* G_CONSTANT_FOLD_BARRIER */
    146,
    /* G_INTRINSIC_FPTRUNC_ROUND */
    148,
    /* G_INTRINSIC_TRUNC */
    151,
    /* G_INTRINSIC_ROUND */
    153,
    /* G_INTRINSIC_LRINT */
    155,
    /* G_INTRINSIC_LLRINT */
    157,
    /* G_INTRINSIC_ROUNDEVEN */
    159,
    /* G_READCYCLECOUNTER */
    161,
    /* G_READSTEADYCOUNTER */
    162,
    /* G_LOAD */
    163,
    /* G_SEXTLOAD */
    165,
    /* G_ZEXTLOAD */
    167,
    /* G_INDEXED_LOAD */
    169,
    /* G_INDEXED_SEXTLOAD */
    174,
    /* G_INDEXED_ZEXTLOAD */
    179,
    /* G_STORE */
    184,
    /* G_INDEXED_STORE */
    186,
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    191,
    /* G_ATOMIC_CMPXCHG */
    196,
    /* G_ATOMICRMW_XCHG */
    200,
    /* G_ATOMICRMW_ADD */
    203,
    /* G_ATOMICRMW_SUB */
    206,
    /* G_ATOMICRMW_AND */
    209,
    /* G_ATOMICRMW_NAND */
    212,
    /* G_ATOMICRMW_OR */
    215,
    /* G_ATOMICRMW_XOR */
    218,
    /* G_ATOMICRMW_MAX */
    221,
    /* G_ATOMICRMW_MIN */
    224,
    /* G_ATOMICRMW_UMAX */
    227,
    /* G_ATOMICRMW_UMIN */
    230,
    /* G_ATOMICRMW_FADD */
    233,
    /* G_ATOMICRMW_FSUB */
    236,
    /* G_ATOMICRMW_FMAX */
    239,
    /* G_ATOMICRMW_FMIN */
    242,
    /* G_ATOMICRMW_UINC_WRAP */
    245,
    /* G_ATOMICRMW_UDEC_WRAP */
    248,
    /* G_ATOMICRMW_USUB_COND */
    251,
    /* G_ATOMICRMW_USUB_SAT */
    254,
    /* G_FENCE */
    257,
    /* G_PREFETCH */
    259,
    /* G_BRCOND */
    263,
    /* G_BRINDIRECT */
    265,
    /* G_INVOKE_REGION_START */
    266,
    /* G_INTRINSIC */
    266,
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    267,
    /* G_INTRINSIC_CONVERGENT */
    268,
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    269,
    /* G_ANYEXT */
    270,
    /* G_TRUNC */
    272,
    /* G_CONSTANT */
    274,
    /* G_FCONSTANT */
    276,
    /* G_VASTART */
    278,
    /* G_VAARG */
    279,
    /* G_SEXT */
    282,
    /* G_SEXT_INREG */
    284,
    /* G_ZEXT */
    287,
    /* G_SHL */
    289,
    /* G_LSHR */
    292,
    /* G_ASHR */
    295,
    /* G_FSHL */
    298,
    /* G_FSHR */
    302,
    /* G_ROTR */
    306,
    /* G_ROTL */
    309,
    /* G_ICMP */
    312,
    /* G_FCMP */
    316,
    /* G_SCMP */
    320,
    /* G_UCMP */
    323,
    /* G_SELECT */
    326,
    /* G_UADDO */
    330,
    /* G_UADDE */
    334,
    /* G_USUBO */
    339,
    /* G_USUBE */
    343,
    /* G_SADDO */
    348,
    /* G_SADDE */
    352,
    /* G_SSUBO */
    357,
    /* G_SSUBE */
    361,
    /* G_UMULO */
    366,
    /* G_SMULO */
    370,
    /* G_UMULH */
    374,
    /* G_SMULH */
    377,
    /* G_UADDSAT */
    380,
    /* G_SADDSAT */
    383,
    /* G_USUBSAT */
    386,
    /* G_SSUBSAT */
    389,
    /* G_USHLSAT */
    392,
    /* G_SSHLSAT */
    395,
    /* G_SMULFIX */
    398,
    /* G_UMULFIX */
    402,
    /* G_SMULFIXSAT */
    406,
    /* G_UMULFIXSAT */
    410,
    /* G_SDIVFIX */
    414,
    /* G_UDIVFIX */
    418,
    /* G_SDIVFIXSAT */
    422,
    /* G_UDIVFIXSAT */
    426,
    /* G_FADD */
    430,
    /* G_FSUB */
    433,
    /* G_FMUL */
    436,
    /* G_FMA */
    439,
    /* G_FMAD */
    443,
    /* G_FDIV */
    447,
    /* G_FREM */
    450,
    /* G_FPOW */
    453,
    /* G_FPOWI */
    456,
    /* G_FEXP */
    459,
    /* G_FEXP2 */
    461,
    /* G_FEXP10 */
    463,
    /* G_FLOG */
    465,
    /* G_FLOG2 */
    467,
    /* G_FLOG10 */
    469,
    /* G_FLDEXP */
    471,
    /* G_FFREXP */
    474,
    /* G_FNEG */
    477,
    /* G_FPEXT */
    479,
    /* G_FPTRUNC */
    481,
    /* G_FPTOSI */
    483,
    /* G_FPTOUI */
    485,
    /* G_SITOFP */
    487,
    /* G_UITOFP */
    489,
    /* G_FPTOSI_SAT */
    491,
    /* G_FPTOUI_SAT */
    493,
    /* G_FABS */
    495,
    /* G_FCOPYSIGN */
    497,
    /* G_IS_FPCLASS */
    500,
    /* G_FCANONICALIZE */
    503,
    /* G_FMINNUM */
    505,
    /* G_FMAXNUM */
    508,
    /* G_FMINNUM_IEEE */
    511,
    /* G_FMAXNUM_IEEE */
    514,
    /* G_FMINIMUM */
    517,
    /* G_FMAXIMUM */
    520,
    /* G_GET_FPENV */
    523,
    /* G_SET_FPENV */
    524,
    /* G_RESET_FPENV */
    525,
    /* G_GET_FPMODE */
    525,
    /* G_SET_FPMODE */
    526,
    /* G_RESET_FPMODE */
    527,
    /* G_PTR_ADD */
    527,
    /* G_PTRMASK */
    530,
    /* G_SMIN */
    533,
    /* G_SMAX */
    536,
    /* G_UMIN */
    539,
    /* G_UMAX */
    542,
    /* G_ABS */
    545,
    /* G_LROUND */
    547,
    /* G_LLROUND */
    549,
    /* G_BR */
    551,
    /* G_BRJT */
    552,
    /* G_VSCALE */
    555,
    /* G_INSERT_SUBVECTOR */
    557,
    /* G_EXTRACT_SUBVECTOR */
    561,
    /* G_INSERT_VECTOR_ELT */
    564,
    /* G_EXTRACT_VECTOR_ELT */
    568,
    /* G_SHUFFLE_VECTOR */
    571,
    /* G_SPLAT_VECTOR */
    575,
    /* G_VECTOR_COMPRESS */
    577,
    /* G_CTTZ */
    581,
    /* G_CTTZ_ZERO_UNDEF */
    583,
    /* G_CTLZ */
    585,
    /* G_CTLZ_ZERO_UNDEF */
    587,
    /* G_CTPOP */
    589,
    /* G_BSWAP */
    591,
    /* G_BITREVERSE */
    593,
    /* G_FCEIL */
    595,
    /* G_FCOS */
    597,
    /* G_FSIN */
    599,
    /* G_FTAN */
    601,
    /* G_FACOS */
    603,
    /* G_FASIN */
    605,
    /* G_FATAN */
    607,
    /* G_FCOSH */
    609,
    /* G_FSINH */
    611,
    /* G_FTANH */
    613,
    /* G_FSQRT */
    615,
    /* G_FFLOOR */
    617,
    /* G_FRINT */
    619,
    /* G_FNEARBYINT */
    621,
    /* G_ADDRSPACE_CAST */
    623,
    /* G_BLOCK_ADDR */
    625,
    /* G_JUMP_TABLE */
    627,
    /* G_DYN_STACKALLOC */
    629,
    /* G_STACKSAVE */
    632,
    /* G_STACKRESTORE */
    633,
    /* G_STRICT_FADD */
    634,
    /* G_STRICT_FSUB */
    637,
    /* G_STRICT_FMUL */
    640,
    /* G_STRICT_FDIV */
    643,
    /* G_STRICT_FREM */
    646,
    /* G_STRICT_FMA */
    649,
    /* G_STRICT_FSQRT */
    653,
    /* G_STRICT_FLDEXP */
    655,
    /* G_READ_REGISTER */
    658,
    /* G_WRITE_REGISTER */
    660,
    /* G_MEMCPY */
    662,
    /* G_MEMCPY_INLINE */
    666,
    /* G_MEMMOVE */
    669,
    /* G_MEMSET */
    673,
    /* G_BZERO */
    677,
    /* G_TRAP */
    680,
    /* G_DEBUGTRAP */
    680,
    /* G_UBSANTRAP */
    680,
    /* G_VECREDUCE_SEQ_FADD */
    681,
    /* G_VECREDUCE_SEQ_FMUL */
    684,
    /* G_VECREDUCE_FADD */
    687,
    /* G_VECREDUCE_FMUL */
    689,
    /* G_VECREDUCE_FMAX */
    691,
    /* G_VECREDUCE_FMIN */
    693,
    /* G_VECREDUCE_FMAXIMUM */
    695,
    /* G_VECREDUCE_FMINIMUM */
    697,
    /* G_VECREDUCE_ADD */
    699,
    /* G_VECREDUCE_MUL */
    701,
    /* G_VECREDUCE_AND */
    703,
    /* G_VECREDUCE_OR */
    705,
    /* G_VECREDUCE_XOR */
    707,
    /* G_VECREDUCE_SMAX */
    709,
    /* G_VECREDUCE_SMIN */
    711,
    /* G_VECREDUCE_UMAX */
    713,
    /* G_VECREDUCE_UMIN */
    715,
    /* G_SBFX */
    717,
    /* G_UBFX */
    721,
    /* ADCWRdRr */
    725,
    /* ADDWRdRr */
    728,
    /* ADJCALLSTACKDOWN */
    731,
    /* ADJCALLSTACKUP */
    733,
    /* ANDIWRdK */
    735,
    /* ANDWRdRr */
    738,
    /* ASRBNRd */
    741,
    /* ASRWLoRd */
    744,
    /* ASRWNRd */
    746,
    /* ASRWRd */
    749,
    /* Asr16 */
    751,
    /* Asr32 */
    754,
    /* Asr8 */
    759,
    /* AtomicFence */
    762,
    /* AtomicLoad16 */
    762,
    /* AtomicLoad8 */
    764,
    /* AtomicLoadAdd16 */
    766,
    /* AtomicLoadAdd8 */
    769,
    /* AtomicLoadAnd16 */
    772,
    /* AtomicLoadAnd8 */
    775,
    /* AtomicLoadOr16 */
    778,
    /* AtomicLoadOr8 */
    781,
    /* AtomicLoadSub16 */
    784,
    /* AtomicLoadSub8 */
    787,
    /* AtomicLoadXor16 */
    790,
    /* AtomicLoadXor8 */
    793,
    /* AtomicStore16 */
    796,
    /* AtomicStore8 */
    798,
    /* COMWRd */
    800,
    /* CPCWRdRr */
    802,
    /* CPWRdRr */
    804,
    /* CopyZero */
    806,
    /* ELPMBRdZ */
    807,
    /* ELPMBRdZPi */
    810,
    /* ELPMWRdZ */
    813,
    /* ELPMWRdZPi */
    816,
    /* EORWRdRr */
    819,
    /* FRMIDX */
    822,
    /* INWRdA */
    825,
    /* LDDWRdPtrQ */
    827,
    /* LDDWRdYQ */
    830,
    /* LDIWRdK */
    833,
    /* LDSWRdK */
    835,
    /* LDWRdPtr */
    837,
    /* LDWRdPtrPd */
    839,
    /* LDWRdPtrPi */
    842,
    /* LPMBRdZ */
    845,
    /* LPMWRdZ */
    847,
    /* LPMWRdZPi */
    849,
    /* LSLBNRd */
    851,
    /* LSLWHiRd */
    854,
    /* LSLWNRd */
    856,
    /* LSLWRd */
    859,
    /* LSRBNRd */
    861,
    /* LSRWLoRd */
    864,
    /* LSRWNRd */
    866,
    /* LSRWRd */
    869,
    /* Lsl16 */
    871,
    /* Lsl32 */
    874,
    /* Lsl8 */
    879,
    /* Lsr16 */
    882,
    /* Lsr32 */
    885,
    /* Lsr8 */
    890,
    /* NEGWRd */
    893,
    /* ORIWRdK */
    896,
    /* ORWRdRr */
    899,
    /* OUTWARr */
    902,
    /* POPWRd */
    904,
    /* PUSHWRr */
    905,
    /* ROLBRdR1 */
    906,
    /* ROLBRdR17 */
    908,
    /* ROLWRd */
    910,
    /* RORBRd */
    912,
    /* RORWRd */
    914,
    /* Rol16 */
    916,
    /* Rol8 */
    919,
    /* Ror16 */
    922,
    /* Ror8 */
    925,
    /* SBCIWRdK */
    928,
    /* SBCWRdRr */
    931,
    /* SEXT */
    934,
    /* SPREAD */
    936,
    /* SPWRITE */
    938,
    /* STDSPQRr */
    940,
    /* STDWPtrQRr */
    943,
    /* STDWSPQRr */
    946,
    /* STSWKRr */
    949,
    /* STWPtrPdRr */
    951,
    /* STWPtrPiRr */
    955,
    /* STWPtrRr */
    959,
    /* SUBIWRdK */
    961,
    /* SUBWRdRr */
    964,
    /* Select16 */
    967,
    /* Select8 */
    971,
    /* ZEXT */
    975,
    /* ADCRdRr */
    977,
    /* ADDRdRr */
    980,
    /* ADIWRdK */
    983,
    /* ANDIRdK */
    986,
    /* ANDRdRr */
    989,
    /* ASRRd */
    992,
    /* BCLRs */
    994,
    /* BLD */
    995,
    /* BRBCsk */
    998,
    /* BRBSsk */
    1000,
    /* BREAK */
    1002,
    /* BREQk */
    1002,
    /* BRGEk */
    1003,
    /* BRLOk */
    1004,
    /* BRLTk */
    1005,
    /* BRMIk */
    1006,
    /* BRNEk */
    1007,
    /* BRPLk */
    1008,
    /* BRSHk */
    1009,
    /* BSETs */
    1010,
    /* BST */
    1011,
    /* CALLk */
    1013,
    /* CBIAb */
    1014,
    /* COMRd */
    1016,
    /* CPCRdRr */
    1018,
    /* CPIRdK */
    1020,
    /* CPRdRr */
    1022,
    /* CPSE */
    1024,
    /* DECRd */
    1026,
    /* DESK */
    1028,
    /* EICALL */
    1029,
    /* EIJMP */
    1029,
    /* ELPM */
    1029,
    /* ELPMRdZ */
    1029,
    /* ELPMRdZPi */
    1031,
    /* EORRdRr */
    1033,
    /* FMUL */
    1036,
    /* FMULS */
    1038,
    /* FMULSU */
    1040,
    /* ICALL */
    1042,
    /* IJMP */
    1042,
    /* INCRd */
    1042,
    /* INRdA */
    1044,
    /* JMPk */
    1046,
    /* LACZRd */
    1047,
    /* LASZRd */
    1049,
    /* LATZRd */
    1051,
    /* LDDRdPtrQ */
    1053,
    /* LDIRdK */
    1056,
    /* LDRdPtr */
    1058,
    /* LDRdPtrPd */
    1060,
    /* LDRdPtrPi */
    1063,
    /* LDSRdK */
    1066,
    /* LDSRdKTiny */
    1068,
    /* LPM */
    1070,
    /* LPMRdZ */
    1070,
    /* LPMRdZPi */
    1072,
    /* LSRRd */
    1074,
    /* MOVRdRr */
    1076,
    /* MOVWRdRr */
    1078,
    /* MULRdRr */
    1080,
    /* MULSRdRr */
    1082,
    /* MULSURdRr */
    1084,
    /* NEGRd */
    1086,
    /* NOP */
    1088,
    /* ORIRdK */
    1088,
    /* ORRdRr */
    1091,
    /* OUTARr */
    1094,
    /* POPRd */
    1096,
    /* PUSHRr */
    1097,
    /* RCALLk */
    1098,
    /* RET */
    1099,
    /* RETI */
    1099,
    /* RJMPk */
    1099,
    /* RORRd */
    1100,
    /* SBCIRdK */
    1102,
    /* SBCRdRr */
    1105,
    /* SBIAb */
    1108,
    /* SBICAb */
    1110,
    /* SBISAb */
    1112,
    /* SBIWRdK */
    1114,
    /* SBRCRrB */
    1117,
    /* SBRSRrB */
    1119,
    /* SLEEP */
    1121,
    /* SPM */
    1121,
    /* SPMZPi */
    1121,
    /* STDPtrQRr */
    1122,
    /* STPtrPdRr */
    1125,
    /* STPtrPiRr */
    1129,
    /* STPtrRr */
    1133,
    /* STSKRr */
    1135,
    /* STSKRrTiny */
    1137,
    /* SUBIRdK */
    1139,
    /* SUBRdRr */
    1142,
    /* SWAPRd */
    1145,
    /* WDR */
    1147,
    /* XCHZRd */
    1147,
  };

  using namespace OpTypes;
  static const int8_t OpcodeOperandTypes[] = {
    
    /* PHI */
    -1, 
    /* INLINEASM */
    /* INLINEASM_BR */
    /* CFI_INSTRUCTION */
    i32imm, 
    /* EH_LABEL */
    i32imm, 
    /* GC_LABEL */
    i32imm, 
    /* ANNOTATION_LABEL */
    i32imm, 
    /* KILL */
    /* EXTRACT_SUBREG */
    -1, -1, i32imm, 
    /* INSERT_SUBREG */
    -1, -1, -1, i32imm, 
    /* IMPLICIT_DEF */
    -1, 
    /* INIT_UNDEF */
    -1, 
    /* SUBREG_TO_REG */
    -1, -1, -1, i32imm, 
    /* COPY_TO_REGCLASS */
    -1, -1, i32imm, 
    /* DBG_VALUE */
    /* DBG_VALUE_LIST */
    /* DBG_INSTR_REF */
    /* DBG_PHI */
    /* DBG_LABEL */
    -1, 
    /* REG_SEQUENCE */
    -1, -1, 
    /* COPY */
    -1, -1, 
    /* BUNDLE */
    /* LIFETIME_START */
    i32imm, 
    /* LIFETIME_END */
    i32imm, 
    /* PSEUDO_PROBE */
    i64imm, i64imm, i8imm, i32imm, 
    /* ARITH_FENCE */
    -1, -1, 
    /* STACKMAP */
    i64imm, i32imm, 
    /* FENTRY_CALL */
    /* PATCHPOINT */
    -1, i64imm, i32imm, -1, i32imm, i32imm, 
    /* LOAD_STACK_GUARD */
    -1, 
    /* PREALLOCATED_SETUP */
    i32imm, 
    /* PREALLOCATED_ARG */
    -1, i32imm, i32imm, 
    /* STATEPOINT */
    /* LOCAL_ESCAPE */
    -1, i32imm, 
    /* FAULTING_OP */
    -1, 
    /* PATCHABLE_OP */
    /* PATCHABLE_FUNCTION_ENTER */
    /* PATCHABLE_RET */
    /* PATCHABLE_FUNCTION_EXIT */
    /* PATCHABLE_TAIL_CALL */
    /* PATCHABLE_EVENT_CALL */
    -1, -1, 
    /* PATCHABLE_TYPED_EVENT_CALL */
    -1, -1, -1, 
    /* ICALL_BRANCH_FUNNEL */
    /* FAKE_USE */
    /* MEMBARRIER */
    /* JUMP_TABLE_DEBUG_INFO */
    i64imm, 
    /* CONVERGENCECTRL_ENTRY */
    -1, 
    /* CONVERGENCECTRL_ANCHOR */
    -1, 
    /* CONVERGENCECTRL_LOOP */
    -1, -1, 
    /* CONVERGENCECTRL_GLUE */
    -1, 
    /* G_ASSERT_SEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ZEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ALIGN */
    type0, type0, untyped_imm_0, 
    /* G_ADD */
    type0, type0, type0, 
    /* G_SUB */
    type0, type0, type0, 
    /* G_MUL */
    type0, type0, type0, 
    /* G_SDIV */
    type0, type0, type0, 
    /* G_UDIV */
    type0, type0, type0, 
    /* G_SREM */
    type0, type0, type0, 
    /* G_UREM */
    type0, type0, type0, 
    /* G_SDIVREM */
    type0, type0, type0, type0, 
    /* G_UDIVREM */
    type0, type0, type0, type0, 
    /* G_AND */
    type0, type0, type0, 
    /* G_OR */
    type0, type0, type0, 
    /* G_XOR */
    type0, type0, type0, 
    /* G_IMPLICIT_DEF */
    type0, 
    /* G_PHI */
    type0, 
    /* G_FRAME_INDEX */
    type0, -1, 
    /* G_GLOBAL_VALUE */
    type0, -1, 
    /* G_PTRAUTH_GLOBAL_VALUE */
    type0, -1, i32imm, type1, i64imm, 
    /* G_CONSTANT_POOL */
    type0, -1, 
    /* G_EXTRACT */
    type0, type1, untyped_imm_0, 
    /* G_UNMERGE_VALUES */
    type0, type1, 
    /* G_INSERT */
    type0, type0, type1, untyped_imm_0, 
    /* G_MERGE_VALUES */
    type0, type1, 
    /* G_BUILD_VECTOR */
    type0, type1, 
    /* G_BUILD_VECTOR_TRUNC */
    type0, type1, 
    /* G_CONCAT_VECTORS */
    type0, type1, 
    /* G_PTRTOINT */
    type0, type1, 
    /* G_INTTOPTR */
    type0, type1, 
    /* G_BITCAST */
    type0, type1, 
    /* G_FREEZE */
    type0, type0, 
    /* G_CONSTANT_FOLD_BARRIER */
    type0, type0, 
    /* G_INTRINSIC_FPTRUNC_ROUND */
    type0, type1, i32imm, 
    /* G_INTRINSIC_TRUNC */
    type0, type0, 
    /* G_INTRINSIC_ROUND */
    type0, type0, 
    /* G_INTRINSIC_LRINT */
    type0, type1, 
    /* G_INTRINSIC_LLRINT */
    type0, type1, 
    /* G_INTRINSIC_ROUNDEVEN */
    type0, type0, 
    /* G_READCYCLECOUNTER */
    type0, 
    /* G_READSTEADYCOUNTER */
    type0, 
    /* G_LOAD */
    type0, ptype1, 
    /* G_SEXTLOAD */
    type0, ptype1, 
    /* G_ZEXTLOAD */
    type0, ptype1, 
    /* G_INDEXED_LOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_SEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_ZEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_STORE */
    type0, ptype1, 
    /* G_INDEXED_STORE */
    ptype0, type1, ptype0, ptype2, -1, 
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    type0, type1, type2, type0, type0, 
    /* G_ATOMIC_CMPXCHG */
    type0, ptype1, type0, type0, 
    /* G_ATOMICRMW_XCHG */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_ADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_SUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_AND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_NAND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_OR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_XOR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FSUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UINC_WRAP */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UDEC_WRAP */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_USUB_COND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_USUB_SAT */
    type0, ptype1, type0, 
    /* G_FENCE */
    i32imm, i32imm, 
    /* G_PREFETCH */
    ptype0, i32imm, i32imm, i32imm, 
    /* G_BRCOND */
    type0, -1, 
    /* G_BRINDIRECT */
    type0, 
    /* G_INVOKE_REGION_START */
    /* G_INTRINSIC */
    -1, 
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    -1, 
    /* G_INTRINSIC_CONVERGENT */
    -1, 
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    -1, 
    /* G_ANYEXT */
    type0, type1, 
    /* G_TRUNC */
    type0, type1, 
    /* G_CONSTANT */
    type0, -1, 
    /* G_FCONSTANT */
    type0, -1, 
    /* G_VASTART */
    type0, 
    /* G_VAARG */
    type0, type1, -1, 
    /* G_SEXT */
    type0, type1, 
    /* G_SEXT_INREG */
    type0, type0, untyped_imm_0, 
    /* G_ZEXT */
    type0, type1, 
    /* G_SHL */
    type0, type0, type1, 
    /* G_LSHR */
    type0, type0, type1, 
    /* G_ASHR */
    type0, type0, type1, 
    /* G_FSHL */
    type0, type0, type0, type1, 
    /* G_FSHR */
    type0, type0, type0, type1, 
    /* G_ROTR */
    type0, type0, type1, 
    /* G_ROTL */
    type0, type0, type1, 
    /* G_ICMP */
    type0, -1, type1, type1, 
    /* G_FCMP */
    type0, -1, type1, type1, 
    /* G_SCMP */
    type0, type1, type1, 
    /* G_UCMP */
    type0, type1, type1, 
    /* G_SELECT */
    type0, type1, type0, type0, 
    /* G_UADDO */
    type0, type1, type0, type0, 
    /* G_UADDE */
    type0, type1, type0, type0, type1, 
    /* G_USUBO */
    type0, type1, type0, type0, 
    /* G_USUBE */
    type0, type1, type0, type0, type1, 
    /* G_SADDO */
    type0, type1, type0, type0, 
    /* G_SADDE */
    type0, type1, type0, type0, type1, 
    /* G_SSUBO */
    type0, type1, type0, type0, 
    /* G_SSUBE */
    type0, type1, type0, type0, type1, 
    /* G_UMULO */
    type0, type1, type0, type0, 
    /* G_SMULO */
    type0, type1, type0, type0, 
    /* G_UMULH */
    type0, type0, type0, 
    /* G_SMULH */
    type0, type0, type0, 
    /* G_UADDSAT */
    type0, type0, type0, 
    /* G_SADDSAT */
    type0, type0, type0, 
    /* G_USUBSAT */
    type0, type0, type0, 
    /* G_SSUBSAT */
    type0, type0, type0, 
    /* G_USHLSAT */
    type0, type0, type1, 
    /* G_SSHLSAT */
    type0, type0, type1, 
    /* G_SMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_FADD */
    type0, type0, type0, 
    /* G_FSUB */
    type0, type0, type0, 
    /* G_FMUL */
    type0, type0, type0, 
    /* G_FMA */
    type0, type0, type0, type0, 
    /* G_FMAD */
    type0, type0, type0, type0, 
    /* G_FDIV */
    type0, type0, type0, 
    /* G_FREM */
    type0, type0, type0, 
    /* G_FPOW */
    type0, type0, type0, 
    /* G_FPOWI */
    type0, type0, type1, 
    /* G_FEXP */
    type0, type0, 
    /* G_FEXP2 */
    type0, type0, 
    /* G_FEXP10 */
    type0, type0, 
    /* G_FLOG */
    type0, type0, 
    /* G_FLOG2 */
    type0, type0, 
    /* G_FLOG10 */
    type0, type0, 
    /* G_FLDEXP */
    type0, type0, type1, 
    /* G_FFREXP */
    type0, type1, type0, 
    /* G_FNEG */
    type0, type0, 
    /* G_FPEXT */
    type0, type1, 
    /* G_FPTRUNC */
    type0, type1, 
    /* G_FPTOSI */
    type0, type1, 
    /* G_FPTOUI */
    type0, type1, 
    /* G_SITOFP */
    type0, type1, 
    /* G_UITOFP */
    type0, type1, 
    /* G_FPTOSI_SAT */
    type0, type1, 
    /* G_FPTOUI_SAT */
    type0, type1, 
    /* G_FABS */
    type0, type0, 
    /* G_FCOPYSIGN */
    type0, type0, type1, 
    /* G_IS_FPCLASS */
    type0, type1, -1, 
    /* G_FCANONICALIZE */
    type0, type0, 
    /* G_FMINNUM */
    type0, type0, type0, 
    /* G_FMAXNUM */
    type0, type0, type0, 
    /* G_FMINNUM_IEEE */
    type0, type0, type0, 
    /* G_FMAXNUM_IEEE */
    type0, type0, type0, 
    /* G_FMINIMUM */
    type0, type0, type0, 
    /* G_FMAXIMUM */
    type0, type0, type0, 
    /* G_GET_FPENV */
    type0, 
    /* G_SET_FPENV */
    type0, 
    /* G_RESET_FPENV */
    /* G_GET_FPMODE */
    type0, 
    /* G_SET_FPMODE */
    type0, 
    /* G_RESET_FPMODE */
    /* G_PTR_ADD */
    ptype0, ptype0, type1, 
    /* G_PTRMASK */
    ptype0, ptype0, type1, 
    /* G_SMIN */
    type0, type0, type0, 
    /* G_SMAX */
    type0, type0, type0, 
    /* G_UMIN */
    type0, type0, type0, 
    /* G_UMAX */
    type0, type0, type0, 
    /* G_ABS */
    type0, type0, 
    /* G_LROUND */
    type0, type1, 
    /* G_LLROUND */
    type0, type1, 
    /* G_BR */
    -1, 
    /* G_BRJT */
    ptype0, -1, type1, 
    /* G_VSCALE */
    type0, -1, 
    /* G_INSERT_SUBVECTOR */
    type0, type0, type1, untyped_imm_0, 
    /* G_EXTRACT_SUBVECTOR */
    type0, type0, untyped_imm_0, 
    /* G_INSERT_VECTOR_ELT */
    type0, type0, type1, type2, 
    /* G_EXTRACT_VECTOR_ELT */
    type0, type1, type2, 
    /* G_SHUFFLE_VECTOR */
    type0, type1, type1, -1, 
    /* G_SPLAT_VECTOR */
    type0, type1, 
    /* G_VECTOR_COMPRESS */
    type0, type0, type1, type0, 
    /* G_CTTZ */
    type0, type1, 
    /* G_CTTZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTLZ */
    type0, type1, 
    /* G_CTLZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTPOP */
    type0, type1, 
    /* G_BSWAP */
    type0, type0, 
    /* G_BITREVERSE */
    type0, type0, 
    /* G_FCEIL */
    type0, type0, 
    /* G_FCOS */
    type0, type0, 
    /* G_FSIN */
    type0, type0, 
    /* G_FTAN */
    type0, type0, 
    /* G_FACOS */
    type0, type0, 
    /* G_FASIN */
    type0, type0, 
    /* G_FATAN */
    type0, type0, 
    /* G_FCOSH */
    type0, type0, 
    /* G_FSINH */
    type0, type0, 
    /* G_FTANH */
    type0, type0, 
    /* G_FSQRT */
    type0, type0, 
    /* G_FFLOOR */
    type0, type0, 
    /* G_FRINT */
    type0, type0, 
    /* G_FNEARBYINT */
    type0, type0, 
    /* G_ADDRSPACE_CAST */
    type0, type1, 
    /* G_BLOCK_ADDR */
    type0, -1, 
    /* G_JUMP_TABLE */
    type0, -1, 
    /* G_DYN_STACKALLOC */
    ptype0, type1, i32imm, 
    /* G_STACKSAVE */
    ptype0, 
    /* G_STACKRESTORE */
    ptype0, 
    /* G_STRICT_FADD */
    type0, type0, type0, 
    /* G_STRICT_FSUB */
    type0, type0, type0, 
    /* G_STRICT_FMUL */
    type0, type0, type0, 
    /* G_STRICT_FDIV */
    type0, type0, type0, 
    /* G_STRICT_FREM */
    type0, type0, type0, 
    /* G_STRICT_FMA */
    type0, type0, type0, type0, 
    /* G_STRICT_FSQRT */
    type0, type0, 
    /* G_STRICT_FLDEXP */
    type0, type0, type1, 
    /* G_READ_REGISTER */
    type0, -1, 
    /* G_WRITE_REGISTER */
    -1, type0, 
    /* G_MEMCPY */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMCPY_INLINE */
    ptype0, ptype1, type2, 
    /* G_MEMMOVE */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMSET */
    ptype0, type1, type2, untyped_imm_0, 
    /* G_BZERO */
    ptype0, type1, untyped_imm_0, 
    /* G_TRAP */
    /* G_DEBUGTRAP */
    /* G_UBSANTRAP */
    i8imm, 
    /* G_VECREDUCE_SEQ_FADD */
    type0, type1, type2, 
    /* G_VECREDUCE_SEQ_FMUL */
    type0, type1, type2, 
    /* G_VECREDUCE_FADD */
    type0, type1, 
    /* G_VECREDUCE_FMUL */
    type0, type1, 
    /* G_VECREDUCE_FMAX */
    type0, type1, 
    /* G_VECREDUCE_FMIN */
    type0, type1, 
    /* G_VECREDUCE_FMAXIMUM */
    type0, type1, 
    /* G_VECREDUCE_FMINIMUM */
    type0, type1, 
    /* G_VECREDUCE_ADD */
    type0, type1, 
    /* G_VECREDUCE_MUL */
    type0, type1, 
    /* G_VECREDUCE_AND */
    type0, type1, 
    /* G_VECREDUCE_OR */
    type0, type1, 
    /* G_VECREDUCE_XOR */
    type0, type1, 
    /* G_VECREDUCE_SMAX */
    type0, type1, 
    /* G_VECREDUCE_SMIN */
    type0, type1, 
    /* G_VECREDUCE_UMAX */
    type0, type1, 
    /* G_VECREDUCE_UMIN */
    type0, type1, 
    /* G_SBFX */
    type0, type0, type1, type1, 
    /* G_UBFX */
    type0, type0, type1, type1, 
    /* ADCWRdRr */
    DREGS, DREGS, DREGS, 
    /* ADDWRdRr */
    DREGS, DREGS, DREGS, 
    /* ADJCALLSTACKDOWN */
    i16imm, i16imm, 
    /* ADJCALLSTACKUP */
    i16imm, i16imm, 
    /* ANDIWRdK */
    DLDREGS, DLDREGS, i16imm, 
    /* ANDWRdRr */
    DREGS, DREGS, DREGS, 
    /* ASRBNRd */
    LD8, GPR8, imm_ldi8, 
    /* ASRWLoRd */
    DREGS, DREGS, 
    /* ASRWNRd */
    DREGS, DREGS, imm16, 
    /* ASRWRd */
    DREGS, DREGS, 
    /* Asr16 */
    DREGS, DREGS, GPR8, 
    /* Asr32 */
    DREGS, DREGS, DREGS, DREGS, i8imm, 
    /* Asr8 */
    GPR8, GPR8, GPR8, 
    /* AtomicFence */
    /* AtomicLoad16 */
    DREGS, PTRDISPREGS, 
    /* AtomicLoad8 */
    GPR8, PTRREGS, 
    /* AtomicLoadAdd16 */
    DREGS, PTRDISPREGS, DREGS, 
    /* AtomicLoadAdd8 */
    GPR8, PTRREGS, GPR8, 
    /* AtomicLoadAnd16 */
    DREGS, PTRDISPREGS, DREGS, 
    /* AtomicLoadAnd8 */
    GPR8, PTRREGS, GPR8, 
    /* AtomicLoadOr16 */
    DREGS, PTRDISPREGS, DREGS, 
    /* AtomicLoadOr8 */
    GPR8, PTRREGS, GPR8, 
    /* AtomicLoadSub16 */
    DREGS, PTRDISPREGS, DREGS, 
    /* AtomicLoadSub8 */
    GPR8, PTRREGS, GPR8, 
    /* AtomicLoadXor16 */
    DREGS, PTRDISPREGS, DREGS, 
    /* AtomicLoadXor8 */
    GPR8, PTRREGS, GPR8, 
    /* AtomicStore16 */
    PTRDISPREGS, DREGS, 
    /* AtomicStore8 */
    PTRREGS, GPR8, 
    /* COMWRd */
    DREGS, DREGS, 
    /* CPCWRdRr */
    DREGS, DREGS, 
    /* CPWRdRr */
    DREGS, DREGS, 
    /* CopyZero */
    GPR8, 
    /* ELPMBRdZ */
    GPR8, ZREG, LD8, 
    /* ELPMBRdZPi */
    GPR8, ZREG, LD8, 
    /* ELPMWRdZ */
    DREGS, ZREG, LD8, 
    /* ELPMWRdZPi */
    DREGS, ZREG, LD8, 
    /* EORWRdRr */
    DREGS, DREGS, DREGS, 
    /* FRMIDX */
    DLDREGS, DLDREGS, i16imm, 
    /* INWRdA */
    DREGS, imm_port6, 
    /* LDDWRdPtrQ */
    DREGS, PTRDISPREGS, i16imm, 
    /* LDDWRdYQ */
    DREGS, PTRDISPREGS, i16imm, 
    /* LDIWRdK */
    DLDREGS, i16imm, 
    /* LDSWRdK */
    DREGS, i16imm, 
    /* LDWRdPtr */
    DREGS, PTRDISPREGS, 
    /* LDWRdPtrPd */
    DREGS, PTRREGS, PTRREGS, 
    /* LDWRdPtrPi */
    DREGS, PTRREGS, PTRREGS, 
    /* LPMBRdZ */
    GPR8, ZREG, 
    /* LPMWRdZ */
    DREGS, ZREG, 
    /* LPMWRdZPi */
    DREGS, ZREG, 
    /* LSLBNRd */
    LD8, GPR8, imm_ldi8, 
    /* LSLWHiRd */
    DREGS, DREGS, 
    /* LSLWNRd */
    DLDREGS, DREGS, imm16, 
    /* LSLWRd */
    DREGS, DREGS, 
    /* LSRBNRd */
    LD8, GPR8, imm_ldi8, 
    /* LSRWLoRd */
    DREGS, DREGS, 
    /* LSRWNRd */
    DLDREGS, DREGS, imm16, 
    /* LSRWRd */
    DREGS, DREGS, 
    /* Lsl16 */
    DREGS, DREGS, GPR8, 
    /* Lsl32 */
    DREGS, DREGS, DREGS, DREGS, i8imm, 
    /* Lsl8 */
    GPR8, GPR8, GPR8, 
    /* Lsr16 */
    DREGS, DREGS, GPR8, 
    /* Lsr32 */
    DREGS, DREGS, DREGS, DREGS, i8imm, 
    /* Lsr8 */
    GPR8, GPR8, GPR8, 
    /* NEGWRd */
    DREGS, DREGS, GPR8, 
    /* ORIWRdK */
    DLDREGS, DLDREGS, i16imm, 
    /* ORWRdRr */
    DREGS, DREGS, DREGS, 
    /* OUTWARr */
    imm_port6, DREGS, 
    /* POPWRd */
    DREGS, 
    /* PUSHWRr */
    DREGS, 
    /* ROLBRdR1 */
    GPR8, GPR8, 
    /* ROLBRdR17 */
    GPR8, GPR8, 
    /* ROLWRd */
    DREGS, DREGS, 
    /* RORBRd */
    GPR8, GPR8, 
    /* RORWRd */
    DREGS, DREGS, 
    /* Rol16 */
    DREGS, DREGS, GPR8, 
    /* Rol8 */
    GPR8, GPR8, GPR8, 
    /* Ror16 */
    DREGS, DREGS, GPR8, 
    /* Ror8 */
    GPR8, GPR8, GPR8, 
    /* SBCIWRdK */
    DLDREGS, DLDREGS, i16imm, 
    /* SBCWRdRr */
    DREGS, DREGS, DREGS, 
    /* SEXT */
    DREGS, GPR8, 
    /* SPREAD */
    DREGS, GPRSP, 
    /* SPWRITE */
    GPRSP, DREGS, 
    /* STDSPQRr */
    GPRSP, i16imm, GPR8, 
    /* STDWPtrQRr */
    PTRDISPREGS, i16imm, DREGS, 
    /* STDWSPQRr */
    GPRSP, i16imm, DREGS, 
    /* STSWKRr */
    i16imm, DREGS, 
    /* STWPtrPdRr */
    PTRREGS, PTRREGS, DREGS, i8imm, 
    /* STWPtrPiRr */
    PTRREGS, PTRREGS, DREGS, i8imm, 
    /* STWPtrRr */
    PTRDISPREGS, DREGS, 
    /* SUBIWRdK */
    DLDREGS, DLDREGS, i16imm, 
    /* SUBWRdRr */
    DREGS, DREGS, DREGS, 
    /* Select16 */
    DREGS, DREGS, DREGS, i8imm, 
    /* Select8 */
    GPR8, GPR8, GPR8, i8imm, 
    /* ZEXT */
    DREGS, GPR8, 
    /* ADCRdRr */
    GPR8, GPR8, GPR8, 
    /* ADDRdRr */
    GPR8, GPR8, GPR8, 
    /* ADIWRdK */
    IWREGS, IWREGS, imm_arith6, 
    /* ANDIRdK */
    LD8, LD8, imm_ldi8, 
    /* ANDRdRr */
    GPR8, GPR8, GPR8, 
    /* ASRRd */
    GPR8, GPR8, 
    /* BCLRs */
    i8imm, 
    /* BLD */
    GPR8, GPR8, i8imm, 
    /* BRBCsk */
    i8imm, relbrtarget_7, 
    /* BRBSsk */
    i8imm, relbrtarget_7, 
    /* BREAK */
    /* BREQk */
    relbrtarget_7, 
    /* BRGEk */
    relbrtarget_7, 
    /* BRLOk */
    relbrtarget_7, 
    /* BRLTk */
    relbrtarget_7, 
    /* BRMIk */
    relbrtarget_7, 
    /* BRNEk */
    relbrtarget_7, 
    /* BRPLk */
    relbrtarget_7, 
    /* BRSHk */
    relbrtarget_7, 
    /* BSETs */
    i8imm, 
    /* BST */
    GPR8, i8imm, 
    /* CALLk */
    call_target, 
    /* CBIAb */
    imm_port5, i8imm, 
    /* COMRd */
    GPR8, GPR8, 
    /* CPCRdRr */
    GPR8, GPR8, 
    /* CPIRdK */
    LD8, imm_ldi8, 
    /* CPRdRr */
    GPR8, GPR8, 
    /* CPSE */
    GPR8, GPR8, 
    /* DECRd */
    GPR8, GPR8, 
    /* DESK */
    i8imm, 
    /* EICALL */
    /* EIJMP */
    /* ELPM */
    /* ELPMRdZ */
    GPR8, ZREG, 
    /* ELPMRdZPi */
    GPR8, ZREG, 
    /* EORRdRr */
    GPR8, GPR8, GPR8, 
    /* FMUL */
    LD8lo, LD8lo, 
    /* FMULS */
    LD8lo, LD8lo, 
    /* FMULSU */
    LD8lo, LD8lo, 
    /* ICALL */
    /* IJMP */
    /* INCRd */
    GPR8, GPR8, 
    /* INRdA */
    GPR8, imm_port6, 
    /* JMPk */
    call_target, 
    /* LACZRd */
    GPR8, ZREG, 
    /* LASZRd */
    GPR8, ZREG, 
    /* LATZRd */
    GPR8, ZREG, 
    /* LDDRdPtrQ */
    GPR8, PTRDISPREGS, i16imm, 
    /* LDIRdK */
    LD8, imm_ldi8, 
    /* LDRdPtr */
    GPR8, PTRREGS, 
    /* LDRdPtrPd */
    GPR8, PTRREGS, PTRREGS, 
    /* LDRdPtrPi */
    GPR8, PTRREGS, PTRREGS, 
    /* LDSRdK */
    GPR8, imm16, 
    /* LDSRdKTiny */
    LD8, imm7tiny, 
    /* LPM */
    /* LPMRdZ */
    GPR8, ZREG, 
    /* LPMRdZPi */
    GPR8, ZREG, 
    /* LSRRd */
    GPR8, GPR8, 
    /* MOVRdRr */
    GPR8, GPR8, 
    /* MOVWRdRr */
    DREGS, DREGS, 
    /* MULRdRr */
    GPR8, GPR8, 
    /* MULSRdRr */
    LD8, LD8, 
    /* MULSURdRr */
    LD8lo, LD8lo, 
    /* NEGRd */
    GPR8, GPR8, 
    /* NOP */
    /* ORIRdK */
    LD8, LD8, imm_ldi8, 
    /* ORRdRr */
    GPR8, GPR8, GPR8, 
    /* OUTARr */
    imm_port6, GPR8, 
    /* POPRd */
    GPR8, 
    /* PUSHRr */
    GPR8, 
    /* RCALLk */
    rcalltarget_13, 
    /* RET */
    /* RETI */
    /* RJMPk */
    brtarget_13, 
    /* RORRd */
    GPR8, GPR8, 
    /* SBCIRdK */
    LD8, LD8, imm_ldi8, 
    /* SBCRdRr */
    GPR8, GPR8, GPR8, 
    /* SBIAb */
    imm_port5, i8imm, 
    /* SBICAb */
    imm_port5, i8imm, 
    /* SBISAb */
    imm_port5, i8imm, 
    /* SBIWRdK */
    IWREGS, IWREGS, imm_arith6, 
    /* SBRCRrB */
    GPR8, i8imm, 
    /* SBRSRrB */
    GPR8, i8imm, 
    /* SLEEP */
    /* SPM */
    /* SPMZPi */
    ZREG, 
    /* STDPtrQRr */
    PTRDISPREGS, i16imm, GPR8, 
    /* STPtrPdRr */
    PTRREGS, PTRREGS, GPR8, i8imm, 
    /* STPtrPiRr */
    PTRREGS, PTRREGS, GPR8, i8imm, 
    /* STPtrRr */
    PTRREGS, GPR8, 
    /* STSKRr */
    imm16, GPR8, 
    /* STSKRrTiny */
    imm7tiny, LD8, 
    /* SUBIRdK */
    LD8, LD8, imm_ldi8, 
    /* SUBRdRr */
    GPR8, GPR8, GPR8, 
    /* SWAPRd */
    GPR8, GPR8, 
    /* WDR */
    /* XCHZRd */
    GPR8, ZREG, 
  };
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
}
} // end namespace AVR
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPE

#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
namespace llvm {
namespace AVR {
LLVM_READONLY
static int getMemOperandSize(int OpType) {
  switch (OpType) {
  default: return 0;
  }
}
} // end namespace AVR
} // end namespace llvm
#endif // GET_INSTRINFO_MEM_OPERAND_SIZE

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
namespace llvm {
namespace AVR {
LLVM_READONLY static unsigned
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return LogicalOpIdx;
}
LLVM_READONLY static inline unsigned
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
  auto S = 0U;
  for (auto i = 0U; i < LogicalOpIdx; ++i)
    S += getLogicalOperandSize(Opcode, i);
  return S;
}
} // end namespace AVR
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
namespace llvm {
namespace AVR {
LLVM_READONLY static int
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return -1;
}
} // end namespace AVR
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP

#ifdef GET_INSTRINFO_MC_HELPER_DECLS
#undef GET_INSTRINFO_MC_HELPER_DECLS

namespace llvm {
class MCInst;
class FeatureBitset;

namespace AVR_MC {

void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);

} // end namespace AVR_MC
} // end namespace llvm

#endif // GET_INSTRINFO_MC_HELPER_DECLS

#ifdef GET_INSTRINFO_MC_HELPERS
#undef GET_INSTRINFO_MC_HELPERS

namespace llvm {
namespace AVR_MC {

} // end namespace AVR_MC
} // end namespace llvm

#endif // GET_GENISTRINFO_MC_HELPERS

#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
    defined(GET_AVAILABLE_OPCODE_CHECKER)
#define GET_COMPUTE_FEATURES
#endif
#ifdef GET_COMPUTE_FEATURES
#undef GET_COMPUTE_FEATURES
namespace llvm {
namespace AVR_MC {

// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
  Feature_HasSRAMBit = 14,
  Feature_HasJMPCALLBit = 7,
  Feature_HasIJMPCALLBit = 6,
  Feature_HasEIJMPCALLBit = 3,
  Feature_HasADDSUBIWBit = 0,
  Feature_HasSmallStackBit = 15,
  Feature_HasMOVWBit = 10,
  Feature_HasLPMBit = 8,
  Feature_HasLPMXBit = 9,
  Feature_HasELPMBit = 4,
  Feature_HasELPMXBit = 5,
  Feature_HasSPMBit = 12,
  Feature_HasSPMXBit = 13,
  Feature_HasDESBit = 2,
  Feature_SupportsRMWBit = 18,
  Feature_SupportsMultiplicationBit = 17,
  Feature_HasBREAKBit = 1,
  Feature_HasTinyEncodingBit = 16,
  Feature_HasNonTinyEncodingBit = 11,
};

inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
  FeatureBitset Features;
  if (FB[AVR::FeatureSRAM])
    Features.set(Feature_HasSRAMBit);
  if (FB[AVR::FeatureJMPCALL])
    Features.set(Feature_HasJMPCALLBit);
  if (FB[AVR::FeatureIJMPCALL])
    Features.set(Feature_HasIJMPCALLBit);
  if (FB[AVR::FeatureEIJMPCALL])
    Features.set(Feature_HasEIJMPCALLBit);
  if (FB[AVR::FeatureADDSUBIW])
    Features.set(Feature_HasADDSUBIWBit);
  if (FB[AVR::FeatureSmallStack])
    Features.set(Feature_HasSmallStackBit);
  if (FB[AVR::FeatureMOVW])
    Features.set(Feature_HasMOVWBit);
  if (FB[AVR::FeatureLPM])
    Features.set(Feature_HasLPMBit);
  if (FB[AVR::FeatureLPMX])
    Features.set(Feature_HasLPMXBit);
  if (FB[AVR::FeatureELPM])
    Features.set(Feature_HasELPMBit);
  if (FB[AVR::FeatureELPMX])
    Features.set(Feature_HasELPMXBit);
  if (FB[AVR::FeatureSPM])
    Features.set(Feature_HasSPMBit);
  if (FB[AVR::FeatureSPMX])
    Features.set(Feature_HasSPMXBit);
  if (FB[AVR::FeatureDES])
    Features.set(Feature_HasDESBit);
  if (FB[AVR::FeatureRMW])
    Features.set(Feature_SupportsRMWBit);
  if (FB[AVR::FeatureMultiplication])
    Features.set(Feature_SupportsMultiplicationBit);
  if (FB[AVR::FeatureBREAK])
    Features.set(Feature_HasBREAKBit);
  if (FB[AVR::FeatureTinyEncoding])
    Features.set(Feature_HasTinyEncodingBit);
  if (!FB[AVR::FeatureTinyEncoding])
    Features.set(Feature_HasNonTinyEncodingBit);
  return Features;
}

inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
  enum : uint8_t {
    CEFBS_None,
    CEFBS_HasADDSUBIW,
    CEFBS_HasBREAK,
    CEFBS_HasDES,
    CEFBS_HasEIJMPCALL,
    CEFBS_HasELPM,
    CEFBS_HasELPMX,
    CEFBS_HasIJMPCALL,
    CEFBS_HasJMPCALL,
    CEFBS_HasLPM,
    CEFBS_HasLPMX,
    CEFBS_HasMOVW,
    CEFBS_HasNonTinyEncoding,
    CEFBS_HasSPM,
    CEFBS_HasSPMX,
    CEFBS_HasSRAM,
    CEFBS_HasTinyEncoding,
    CEFBS_SupportsMultiplication,
    CEFBS_SupportsRMW,
    CEFBS_HasSRAM_HasNonTinyEncoding,
    CEFBS_HasSRAM_HasTinyEncoding,
  };

  static constexpr FeatureBitset FeatureBitsets[] = {
    {}, // CEFBS_None
    {Feature_HasADDSUBIWBit, },
    {Feature_HasBREAKBit, },
    {Feature_HasDESBit, },
    {Feature_HasEIJMPCALLBit, },
    {Feature_HasELPMBit, },
    {Feature_HasELPMXBit, },
    {Feature_HasIJMPCALLBit, },
    {Feature_HasJMPCALLBit, },
    {Feature_HasLPMBit, },
    {Feature_HasLPMXBit, },
    {Feature_HasMOVWBit, },
    {Feature_HasNonTinyEncodingBit, },
    {Feature_HasSPMBit, },
    {Feature_HasSPMXBit, },
    {Feature_HasSRAMBit, },
    {Feature_HasTinyEncodingBit, },
    {Feature_SupportsMultiplicationBit, },
    {Feature_SupportsRMWBit, },
    {Feature_HasSRAMBit, Feature_HasNonTinyEncodingBit, },
    {Feature_HasSRAMBit, Feature_HasTinyEncodingBit, },
  };
  static constexpr uint8_t RequiredFeaturesRefs[] = {
    CEFBS_None, // PHI = 0
    CEFBS_None, // INLINEASM = 1
    CEFBS_None, // INLINEASM_BR = 2
    CEFBS_None, // CFI_INSTRUCTION = 3
    CEFBS_None, // EH_LABEL = 4
    CEFBS_None, // GC_LABEL = 5
    CEFBS_None, // ANNOTATION_LABEL = 6
    CEFBS_None, // KILL = 7
    CEFBS_None, // EXTRACT_SUBREG = 8
    CEFBS_None, // INSERT_SUBREG = 9
    CEFBS_None, // IMPLICIT_DEF = 10
    CEFBS_None, // INIT_UNDEF = 11
    CEFBS_None, // SUBREG_TO_REG = 12
    CEFBS_None, // COPY_TO_REGCLASS = 13
    CEFBS_None, // DBG_VALUE = 14
    CEFBS_None, // DBG_VALUE_LIST = 15
    CEFBS_None, // DBG_INSTR_REF = 16
    CEFBS_None, // DBG_PHI = 17
    CEFBS_None, // DBG_LABEL = 18
    CEFBS_None, // REG_SEQUENCE = 19
    CEFBS_None, // COPY = 20
    CEFBS_None, // BUNDLE = 21
    CEFBS_None, // LIFETIME_START = 22
    CEFBS_None, // LIFETIME_END = 23
    CEFBS_None, // PSEUDO_PROBE = 24
    CEFBS_None, // ARITH_FENCE = 25
    CEFBS_None, // STACKMAP = 26
    CEFBS_None, // FENTRY_CALL = 27
    CEFBS_None, // PATCHPOINT = 28
    CEFBS_None, // LOAD_STACK_GUARD = 29
    CEFBS_None, // PREALLOCATED_SETUP = 30
    CEFBS_None, // PREALLOCATED_ARG = 31
    CEFBS_None, // STATEPOINT = 32
    CEFBS_None, // LOCAL_ESCAPE = 33
    CEFBS_None, // FAULTING_OP = 34
    CEFBS_None, // PATCHABLE_OP = 35
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 36
    CEFBS_None, // PATCHABLE_RET = 37
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 38
    CEFBS_None, // PATCHABLE_TAIL_CALL = 39
    CEFBS_None, // PATCHABLE_EVENT_CALL = 40
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 41
    CEFBS_None, // ICALL_BRANCH_FUNNEL = 42
    CEFBS_None, // FAKE_USE = 43
    CEFBS_None, // MEMBARRIER = 44
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 45
    CEFBS_None, // CONVERGENCECTRL_ENTRY = 46
    CEFBS_None, // CONVERGENCECTRL_ANCHOR = 47
    CEFBS_None, // CONVERGENCECTRL_LOOP = 48
    CEFBS_None, // CONVERGENCECTRL_GLUE = 49
    CEFBS_None, // G_ASSERT_SEXT = 50
    CEFBS_None, // G_ASSERT_ZEXT = 51
    CEFBS_None, // G_ASSERT_ALIGN = 52
    CEFBS_None, // G_ADD = 53
    CEFBS_None, // G_SUB = 54
    CEFBS_None, // G_MUL = 55
    CEFBS_None, // G_SDIV = 56
    CEFBS_None, // G_UDIV = 57
    CEFBS_None, // G_SREM = 58
    CEFBS_None, // G_UREM = 59
    CEFBS_None, // G_SDIVREM = 60
    CEFBS_None, // G_UDIVREM = 61
    CEFBS_None, // G_AND = 62
    CEFBS_None, // G_OR = 63
    CEFBS_None, // G_XOR = 64
    CEFBS_None, // G_IMPLICIT_DEF = 65
    CEFBS_None, // G_PHI = 66
    CEFBS_None, // G_FRAME_INDEX = 67
    CEFBS_None, // G_GLOBAL_VALUE = 68
    CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 69
    CEFBS_None, // G_CONSTANT_POOL = 70
    CEFBS_None, // G_EXTRACT = 71
    CEFBS_None, // G_UNMERGE_VALUES = 72
    CEFBS_None, // G_INSERT = 73
    CEFBS_None, // G_MERGE_VALUES = 74
    CEFBS_None, // G_BUILD_VECTOR = 75
    CEFBS_None, // G_BUILD_VECTOR_TRUNC = 76
    CEFBS_None, // G_CONCAT_VECTORS = 77
    CEFBS_None, // G_PTRTOINT = 78
    CEFBS_None, // G_INTTOPTR = 79
    CEFBS_None, // G_BITCAST = 80
    CEFBS_None, // G_FREEZE = 81
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 82
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 83
    CEFBS_None, // G_INTRINSIC_TRUNC = 84
    CEFBS_None, // G_INTRINSIC_ROUND = 85
    CEFBS_None, // G_INTRINSIC_LRINT = 86
    CEFBS_None, // G_INTRINSIC_LLRINT = 87
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 88
    CEFBS_None, // G_READCYCLECOUNTER = 89
    CEFBS_None, // G_READSTEADYCOUNTER = 90
    CEFBS_None, // G_LOAD = 91
    CEFBS_None, // G_SEXTLOAD = 92
    CEFBS_None, // G_ZEXTLOAD = 93
    CEFBS_None, // G_INDEXED_LOAD = 94
    CEFBS_None, // G_INDEXED_SEXTLOAD = 95
    CEFBS_None, // G_INDEXED_ZEXTLOAD = 96
    CEFBS_None, // G_STORE = 97
    CEFBS_None, // G_INDEXED_STORE = 98
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 99
    CEFBS_None, // G_ATOMIC_CMPXCHG = 100
    CEFBS_None, // G_ATOMICRMW_XCHG = 101
    CEFBS_None, // G_ATOMICRMW_ADD = 102
    CEFBS_None, // G_ATOMICRMW_SUB = 103
    CEFBS_None, // G_ATOMICRMW_AND = 104
    CEFBS_None, // G_ATOMICRMW_NAND = 105
    CEFBS_None, // G_ATOMICRMW_OR = 106
    CEFBS_None, // G_ATOMICRMW_XOR = 107
    CEFBS_None, // G_ATOMICRMW_MAX = 108
    CEFBS_None, // G_ATOMICRMW_MIN = 109
    CEFBS_None, // G_ATOMICRMW_UMAX = 110
    CEFBS_None, // G_ATOMICRMW_UMIN = 111
    CEFBS_None, // G_ATOMICRMW_FADD = 112
    CEFBS_None, // G_ATOMICRMW_FSUB = 113
    CEFBS_None, // G_ATOMICRMW_FMAX = 114
    CEFBS_None, // G_ATOMICRMW_FMIN = 115
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 116
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 117
    CEFBS_None, // G_ATOMICRMW_USUB_COND = 118
    CEFBS_None, // G_ATOMICRMW_USUB_SAT = 119
    CEFBS_None, // G_FENCE = 120
    CEFBS_None, // G_PREFETCH = 121
    CEFBS_None, // G_BRCOND = 122
    CEFBS_None, // G_BRINDIRECT = 123
    CEFBS_None, // G_INVOKE_REGION_START = 124
    CEFBS_None, // G_INTRINSIC = 125
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 126
    CEFBS_None, // G_INTRINSIC_CONVERGENT = 127
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 128
    CEFBS_None, // G_ANYEXT = 129
    CEFBS_None, // G_TRUNC = 130
    CEFBS_None, // G_CONSTANT = 131
    CEFBS_None, // G_FCONSTANT = 132
    CEFBS_None, // G_VASTART = 133
    CEFBS_None, // G_VAARG = 134
    CEFBS_None, // G_SEXT = 135
    CEFBS_None, // G_SEXT_INREG = 136
    CEFBS_None, // G_ZEXT = 137
    CEFBS_None, // G_SHL = 138
    CEFBS_None, // G_LSHR = 139
    CEFBS_None, // G_ASHR = 140
    CEFBS_None, // G_FSHL = 141
    CEFBS_None, // G_FSHR = 142
    CEFBS_None, // G_ROTR = 143
    CEFBS_None, // G_ROTL = 144
    CEFBS_None, // G_ICMP = 145
    CEFBS_None, // G_FCMP = 146
    CEFBS_None, // G_SCMP = 147
    CEFBS_None, // G_UCMP = 148
    CEFBS_None, // G_SELECT = 149
    CEFBS_None, // G_UADDO = 150
    CEFBS_None, // G_UADDE = 151
    CEFBS_None, // G_USUBO = 152
    CEFBS_None, // G_USUBE = 153
    CEFBS_None, // G_SADDO = 154
    CEFBS_None, // G_SADDE = 155
    CEFBS_None, // G_SSUBO = 156
    CEFBS_None, // G_SSUBE = 157
    CEFBS_None, // G_UMULO = 158
    CEFBS_None, // G_SMULO = 159
    CEFBS_None, // G_UMULH = 160
    CEFBS_None, // G_SMULH = 161
    CEFBS_None, // G_UADDSAT = 162
    CEFBS_None, // G_SADDSAT = 163
    CEFBS_None, // G_USUBSAT = 164
    CEFBS_None, // G_SSUBSAT = 165
    CEFBS_None, // G_USHLSAT = 166
    CEFBS_None, // G_SSHLSAT = 167
    CEFBS_None, // G_SMULFIX = 168
    CEFBS_None, // G_UMULFIX = 169
    CEFBS_None, // G_SMULFIXSAT = 170
    CEFBS_None, // G_UMULFIXSAT = 171
    CEFBS_None, // G_SDIVFIX = 172
    CEFBS_None, // G_UDIVFIX = 173
    CEFBS_None, // G_SDIVFIXSAT = 174
    CEFBS_None, // G_UDIVFIXSAT = 175
    CEFBS_None, // G_FADD = 176
    CEFBS_None, // G_FSUB = 177
    CEFBS_None, // G_FMUL = 178
    CEFBS_None, // G_FMA = 179
    CEFBS_None, // G_FMAD = 180
    CEFBS_None, // G_FDIV = 181
    CEFBS_None, // G_FREM = 182
    CEFBS_None, // G_FPOW = 183
    CEFBS_None, // G_FPOWI = 184
    CEFBS_None, // G_FEXP = 185
    CEFBS_None, // G_FEXP2 = 186
    CEFBS_None, // G_FEXP10 = 187
    CEFBS_None, // G_FLOG = 188
    CEFBS_None, // G_FLOG2 = 189
    CEFBS_None, // G_FLOG10 = 190
    CEFBS_None, // G_FLDEXP = 191
    CEFBS_None, // G_FFREXP = 192
    CEFBS_None, // G_FNEG = 193
    CEFBS_None, // G_FPEXT = 194
    CEFBS_None, // G_FPTRUNC = 195
    CEFBS_None, // G_FPTOSI = 196
    CEFBS_None, // G_FPTOUI = 197
    CEFBS_None, // G_SITOFP = 198
    CEFBS_None, // G_UITOFP = 199
    CEFBS_None, // G_FPTOSI_SAT = 200
    CEFBS_None, // G_FPTOUI_SAT = 201
    CEFBS_None, // G_FABS = 202
    CEFBS_None, // G_FCOPYSIGN = 203
    CEFBS_None, // G_IS_FPCLASS = 204
    CEFBS_None, // G_FCANONICALIZE = 205
    CEFBS_None, // G_FMINNUM = 206
    CEFBS_None, // G_FMAXNUM = 207
    CEFBS_None, // G_FMINNUM_IEEE = 208
    CEFBS_None, // G_FMAXNUM_IEEE = 209
    CEFBS_None, // G_FMINIMUM = 210
    CEFBS_None, // G_FMAXIMUM = 211
    CEFBS_None, // G_GET_FPENV = 212
    CEFBS_None, // G_SET_FPENV = 213
    CEFBS_None, // G_RESET_FPENV = 214
    CEFBS_None, // G_GET_FPMODE = 215
    CEFBS_None, // G_SET_FPMODE = 216
    CEFBS_None, // G_RESET_FPMODE = 217
    CEFBS_None, // G_PTR_ADD = 218
    CEFBS_None, // G_PTRMASK = 219
    CEFBS_None, // G_SMIN = 220
    CEFBS_None, // G_SMAX = 221
    CEFBS_None, // G_UMIN = 222
    CEFBS_None, // G_UMAX = 223
    CEFBS_None, // G_ABS = 224
    CEFBS_None, // G_LROUND = 225
    CEFBS_None, // G_LLROUND = 226
    CEFBS_None, // G_BR = 227
    CEFBS_None, // G_BRJT = 228
    CEFBS_None, // G_VSCALE = 229
    CEFBS_None, // G_INSERT_SUBVECTOR = 230
    CEFBS_None, // G_EXTRACT_SUBVECTOR = 231
    CEFBS_None, // G_INSERT_VECTOR_ELT = 232
    CEFBS_None, // G_EXTRACT_VECTOR_ELT = 233
    CEFBS_None, // G_SHUFFLE_VECTOR = 234
    CEFBS_None, // G_SPLAT_VECTOR = 235
    CEFBS_None, // G_VECTOR_COMPRESS = 236
    CEFBS_None, // G_CTTZ = 237
    CEFBS_None, // G_CTTZ_ZERO_UNDEF = 238
    CEFBS_None, // G_CTLZ = 239
    CEFBS_None, // G_CTLZ_ZERO_UNDEF = 240
    CEFBS_None, // G_CTPOP = 241
    CEFBS_None, // G_BSWAP = 242
    CEFBS_None, // G_BITREVERSE = 243
    CEFBS_None, // G_FCEIL = 244
    CEFBS_None, // G_FCOS = 245
    CEFBS_None, // G_FSIN = 246
    CEFBS_None, // G_FTAN = 247
    CEFBS_None, // G_FACOS = 248
    CEFBS_None, // G_FASIN = 249
    CEFBS_None, // G_FATAN = 250
    CEFBS_None, // G_FCOSH = 251
    CEFBS_None, // G_FSINH = 252
    CEFBS_None, // G_FTANH = 253
    CEFBS_None, // G_FSQRT = 254
    CEFBS_None, // G_FFLOOR = 255
    CEFBS_None, // G_FRINT = 256
    CEFBS_None, // G_FNEARBYINT = 257
    CEFBS_None, // G_ADDRSPACE_CAST = 258
    CEFBS_None, // G_BLOCK_ADDR = 259
    CEFBS_None, // G_JUMP_TABLE = 260
    CEFBS_None, // G_DYN_STACKALLOC = 261
    CEFBS_None, // G_STACKSAVE = 262
    CEFBS_None, // G_STACKRESTORE = 263
    CEFBS_None, // G_STRICT_FADD = 264
    CEFBS_None, // G_STRICT_FSUB = 265
    CEFBS_None, // G_STRICT_FMUL = 266
    CEFBS_None, // G_STRICT_FDIV = 267
    CEFBS_None, // G_STRICT_FREM = 268
    CEFBS_None, // G_STRICT_FMA = 269
    CEFBS_None, // G_STRICT_FSQRT = 270
    CEFBS_None, // G_STRICT_FLDEXP = 271
    CEFBS_None, // G_READ_REGISTER = 272
    CEFBS_None, // G_WRITE_REGISTER = 273
    CEFBS_None, // G_MEMCPY = 274
    CEFBS_None, // G_MEMCPY_INLINE = 275
    CEFBS_None, // G_MEMMOVE = 276
    CEFBS_None, // G_MEMSET = 277
    CEFBS_None, // G_BZERO = 278
    CEFBS_None, // G_TRAP = 279
    CEFBS_None, // G_DEBUGTRAP = 280
    CEFBS_None, // G_UBSANTRAP = 281
    CEFBS_None, // G_VECREDUCE_SEQ_FADD = 282
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 283
    CEFBS_None, // G_VECREDUCE_FADD = 284
    CEFBS_None, // G_VECREDUCE_FMUL = 285
    CEFBS_None, // G_VECREDUCE_FMAX = 286
    CEFBS_None, // G_VECREDUCE_FMIN = 287
    CEFBS_None, // G_VECREDUCE_FMAXIMUM = 288
    CEFBS_None, // G_VECREDUCE_FMINIMUM = 289
    CEFBS_None, // G_VECREDUCE_ADD = 290
    CEFBS_None, // G_VECREDUCE_MUL = 291
    CEFBS_None, // G_VECREDUCE_AND = 292
    CEFBS_None, // G_VECREDUCE_OR = 293
    CEFBS_None, // G_VECREDUCE_XOR = 294
    CEFBS_None, // G_VECREDUCE_SMAX = 295
    CEFBS_None, // G_VECREDUCE_SMIN = 296
    CEFBS_None, // G_VECREDUCE_UMAX = 297
    CEFBS_None, // G_VECREDUCE_UMIN = 298
    CEFBS_None, // G_SBFX = 299
    CEFBS_None, // G_UBFX = 300
    CEFBS_None, // ADCWRdRr = 301
    CEFBS_None, // ADDWRdRr = 302
    CEFBS_None, // ADJCALLSTACKDOWN = 303
    CEFBS_None, // ADJCALLSTACKUP = 304
    CEFBS_None, // ANDIWRdK = 305
    CEFBS_None, // ANDWRdRr = 306
    CEFBS_None, // ASRBNRd = 307
    CEFBS_None, // ASRWLoRd = 308
    CEFBS_None, // ASRWNRd = 309
    CEFBS_None, // ASRWRd = 310
    CEFBS_None, // Asr16 = 311
    CEFBS_None, // Asr32 = 312
    CEFBS_None, // Asr8 = 313
    CEFBS_None, // AtomicFence = 314
    CEFBS_None, // AtomicLoad16 = 315
    CEFBS_None, // AtomicLoad8 = 316
    CEFBS_None, // AtomicLoadAdd16 = 317
    CEFBS_None, // AtomicLoadAdd8 = 318
    CEFBS_None, // AtomicLoadAnd16 = 319
    CEFBS_None, // AtomicLoadAnd8 = 320
    CEFBS_None, // AtomicLoadOr16 = 321
    CEFBS_None, // AtomicLoadOr8 = 322
    CEFBS_None, // AtomicLoadSub16 = 323
    CEFBS_None, // AtomicLoadSub8 = 324
    CEFBS_None, // AtomicLoadXor16 = 325
    CEFBS_None, // AtomicLoadXor8 = 326
    CEFBS_None, // AtomicStore16 = 327
    CEFBS_None, // AtomicStore8 = 328
    CEFBS_None, // COMWRd = 329
    CEFBS_None, // CPCWRdRr = 330
    CEFBS_None, // CPWRdRr = 331
    CEFBS_None, // CopyZero = 332
    CEFBS_HasELPM, // ELPMBRdZ = 333
    CEFBS_HasELPMX, // ELPMBRdZPi = 334
    CEFBS_HasELPM, // ELPMWRdZ = 335
    CEFBS_HasELPMX, // ELPMWRdZPi = 336
    CEFBS_None, // EORWRdRr = 337
    CEFBS_None, // FRMIDX = 338
    CEFBS_None, // INWRdA = 339
    CEFBS_HasSRAM, // LDDWRdPtrQ = 340
    CEFBS_HasSRAM, // LDDWRdYQ = 341
    CEFBS_None, // LDIWRdK = 342
    CEFBS_HasSRAM_HasNonTinyEncoding, // LDSWRdK = 343
    CEFBS_HasSRAM, // LDWRdPtr = 344
    CEFBS_HasSRAM, // LDWRdPtrPd = 345
    CEFBS_HasSRAM, // LDWRdPtrPi = 346
    CEFBS_HasLPM, // LPMBRdZ = 347
    CEFBS_HasLPM, // LPMWRdZ = 348
    CEFBS_HasLPMX, // LPMWRdZPi = 349
    CEFBS_None, // LSLBNRd = 350
    CEFBS_None, // LSLWHiRd = 351
    CEFBS_None, // LSLWNRd = 352
    CEFBS_None, // LSLWRd = 353
    CEFBS_None, // LSRBNRd = 354
    CEFBS_None, // LSRWLoRd = 355
    CEFBS_None, // LSRWNRd = 356
    CEFBS_None, // LSRWRd = 357
    CEFBS_None, // Lsl16 = 358
    CEFBS_None, // Lsl32 = 359
    CEFBS_None, // Lsl8 = 360
    CEFBS_None, // Lsr16 = 361
    CEFBS_None, // Lsr32 = 362
    CEFBS_None, // Lsr8 = 363
    CEFBS_None, // NEGWRd = 364
    CEFBS_None, // ORIWRdK = 365
    CEFBS_None, // ORWRdRr = 366
    CEFBS_None, // OUTWARr = 367
    CEFBS_HasSRAM, // POPWRd = 368
    CEFBS_HasSRAM, // PUSHWRr = 369
    CEFBS_HasNonTinyEncoding, // ROLBRdR1 = 370
    CEFBS_HasTinyEncoding, // ROLBRdR17 = 371
    CEFBS_None, // ROLWRd = 372
    CEFBS_None, // RORBRd = 373
    CEFBS_None, // RORWRd = 374
    CEFBS_None, // Rol16 = 375
    CEFBS_None, // Rol8 = 376
    CEFBS_None, // Ror16 = 377
    CEFBS_None, // Ror8 = 378
    CEFBS_None, // SBCIWRdK = 379
    CEFBS_None, // SBCWRdRr = 380
    CEFBS_None, // SEXT = 381
    CEFBS_None, // SPREAD = 382
    CEFBS_None, // SPWRITE = 383
    CEFBS_None, // STDSPQRr = 384
    CEFBS_HasSRAM, // STDWPtrQRr = 385
    CEFBS_None, // STDWSPQRr = 386
    CEFBS_HasSRAM_HasNonTinyEncoding, // STSWKRr = 387
    CEFBS_HasSRAM, // STWPtrPdRr = 388
    CEFBS_HasSRAM, // STWPtrPiRr = 389
    CEFBS_HasSRAM, // STWPtrRr = 390
    CEFBS_None, // SUBIWRdK = 391
    CEFBS_None, // SUBWRdRr = 392
    CEFBS_None, // Select16 = 393
    CEFBS_None, // Select8 = 394
    CEFBS_None, // ZEXT = 395
    CEFBS_None, // ADCRdRr = 396
    CEFBS_None, // ADDRdRr = 397
    CEFBS_HasADDSUBIW, // ADIWRdK = 398
    CEFBS_None, // ANDIRdK = 399
    CEFBS_None, // ANDRdRr = 400
    CEFBS_None, // ASRRd = 401
    CEFBS_None, // BCLRs = 402
    CEFBS_None, // BLD = 403
    CEFBS_None, // BRBCsk = 404
    CEFBS_None, // BRBSsk = 405
    CEFBS_HasBREAK, // BREAK = 406
    CEFBS_None, // BREQk = 407
    CEFBS_None, // BRGEk = 408
    CEFBS_None, // BRLOk = 409
    CEFBS_None, // BRLTk = 410
    CEFBS_None, // BRMIk = 411
    CEFBS_None, // BRNEk = 412
    CEFBS_None, // BRPLk = 413
    CEFBS_None, // BRSHk = 414
    CEFBS_None, // BSETs = 415
    CEFBS_None, // BST = 416
    CEFBS_HasJMPCALL, // CALLk = 417
    CEFBS_None, // CBIAb = 418
    CEFBS_None, // COMRd = 419
    CEFBS_None, // CPCRdRr = 420
    CEFBS_None, // CPIRdK = 421
    CEFBS_None, // CPRdRr = 422
    CEFBS_None, // CPSE = 423
    CEFBS_None, // DECRd = 424
    CEFBS_HasDES, // DESK = 425
    CEFBS_HasEIJMPCALL, // EICALL = 426
    CEFBS_HasEIJMPCALL, // EIJMP = 427
    CEFBS_HasELPM, // ELPM = 428
    CEFBS_HasELPMX, // ELPMRdZ = 429
    CEFBS_HasELPMX, // ELPMRdZPi = 430
    CEFBS_None, // EORRdRr = 431
    CEFBS_SupportsMultiplication, // FMUL = 432
    CEFBS_SupportsMultiplication, // FMULS = 433
    CEFBS_SupportsMultiplication, // FMULSU = 434
    CEFBS_HasIJMPCALL, // ICALL = 435
    CEFBS_HasIJMPCALL, // IJMP = 436
    CEFBS_None, // INCRd = 437
    CEFBS_None, // INRdA = 438
    CEFBS_HasJMPCALL, // JMPk = 439
    CEFBS_SupportsRMW, // LACZRd = 440
    CEFBS_SupportsRMW, // LASZRd = 441
    CEFBS_SupportsRMW, // LATZRd = 442
    CEFBS_HasSRAM_HasNonTinyEncoding, // LDDRdPtrQ = 443
    CEFBS_None, // LDIRdK = 444
    CEFBS_HasSRAM, // LDRdPtr = 445
    CEFBS_HasSRAM, // LDRdPtrPd = 446
    CEFBS_HasSRAM, // LDRdPtrPi = 447
    CEFBS_HasSRAM_HasNonTinyEncoding, // LDSRdK = 448
    CEFBS_HasSRAM_HasTinyEncoding, // LDSRdKTiny = 449
    CEFBS_HasLPM, // LPM = 450
    CEFBS_HasLPMX, // LPMRdZ = 451
    CEFBS_HasLPMX, // LPMRdZPi = 452
    CEFBS_None, // LSRRd = 453
    CEFBS_None, // MOVRdRr = 454
    CEFBS_HasMOVW, // MOVWRdRr = 455
    CEFBS_SupportsMultiplication, // MULRdRr = 456
    CEFBS_SupportsMultiplication, // MULSRdRr = 457
    CEFBS_SupportsMultiplication, // MULSURdRr = 458
    CEFBS_None, // NEGRd = 459
    CEFBS_None, // NOP = 460
    CEFBS_None, // ORIRdK = 461
    CEFBS_None, // ORRdRr = 462
    CEFBS_None, // OUTARr = 463
    CEFBS_HasSRAM, // POPRd = 464
    CEFBS_HasSRAM, // PUSHRr = 465
    CEFBS_None, // RCALLk = 466
    CEFBS_None, // RET = 467
    CEFBS_None, // RETI = 468
    CEFBS_None, // RJMPk = 469
    CEFBS_None, // RORRd = 470
    CEFBS_None, // SBCIRdK = 471
    CEFBS_None, // SBCRdRr = 472
    CEFBS_None, // SBIAb = 473
    CEFBS_None, // SBICAb = 474
    CEFBS_None, // SBISAb = 475
    CEFBS_HasADDSUBIW, // SBIWRdK = 476
    CEFBS_None, // SBRCRrB = 477
    CEFBS_None, // SBRSRrB = 478
    CEFBS_None, // SLEEP = 479
    CEFBS_HasSPM, // SPM = 480
    CEFBS_HasSPMX, // SPMZPi = 481
    CEFBS_HasSRAM_HasNonTinyEncoding, // STDPtrQRr = 482
    CEFBS_HasSRAM, // STPtrPdRr = 483
    CEFBS_HasSRAM, // STPtrPiRr = 484
    CEFBS_HasSRAM, // STPtrRr = 485
    CEFBS_HasSRAM_HasNonTinyEncoding, // STSKRr = 486
    CEFBS_HasSRAM_HasTinyEncoding, // STSKRrTiny = 487
    CEFBS_None, // SUBIRdK = 488
    CEFBS_None, // SUBRdRr = 489
    CEFBS_None, // SWAPRd = 490
    CEFBS_None, // WDR = 491
    CEFBS_SupportsRMW, // XCHZRd = 492
  };

  assert(Opcode < 493);
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
}

} // end namespace AVR_MC
} // end namespace llvm
#endif // GET_COMPUTE_FEATURES

#ifdef GET_AVAILABLE_OPCODE_CHECKER
#undef GET_AVAILABLE_OPCODE_CHECKER
namespace llvm {
namespace AVR_MC {
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  return !MissingFeatures.any();
}
} // end namespace AVR_MC
} // end namespace llvm
#endif // GET_AVAILABLE_OPCODE_CHECKER

#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
#undef ENABLE_INSTR_PREDICATE_VERIFIER
#include <sstream>

namespace llvm {
namespace AVR_MC {

#ifndef NDEBUG
static const char *SubtargetFeatureNames[] = {
  "Feature_HasADDSUBIW",
  "Feature_HasBREAK",
  "Feature_HasDES",
  "Feature_HasEIJMPCALL",
  "Feature_HasELPM",
  "Feature_HasELPMX",
  "Feature_HasIJMPCALL",
  "Feature_HasJMPCALL",
  "Feature_HasLPM",
  "Feature_HasLPMX",
  "Feature_HasMOVW",
  "Feature_HasNonTinyEncoding",
  "Feature_HasSPM",
  "Feature_HasSPMX",
  "Feature_HasSRAM",
  "Feature_HasSmallStack",
  "Feature_HasTinyEncoding",
  "Feature_SupportsMultiplication",
  "Feature_SupportsRMW",
  nullptr
};

#endif // NDEBUG

void verifyInstructionPredicates(
    unsigned Opcode, const FeatureBitset &Features) {
#ifndef NDEBUG
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  if (MissingFeatures.any()) {
    std::ostringstream Msg;
    Msg << "Attempting to emit " << &AVRInstrNameData[AVRInstrNameIndices[Opcode]]
        << " instruction but the ";
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
      if (MissingFeatures.test(i))
        Msg << SubtargetFeatureNames[i] << " ";
    Msg << "predicate(s) are not met";
    report_fatal_error(Msg.str().c_str());
  }
#endif // NDEBUG
}
} // end namespace AVR_MC
} // end namespace llvm
#endif // ENABLE_INSTR_PREDICATE_VERIFIER