#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
namespace llvm {
namespace BPF {
enum { … };
}
}
#endif
#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM
namespace llvm {
namespace BPF {
namespace Sched {
enum {
NoInstrModel = 0,
SCHED_LIST_END = 1
};
}
}
}
#endif
#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
namespace llvm {
struct BPFInstrTable {
MCInstrDesc Insts[492];
static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
MCOperandInfo OperandInfo[284];
static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
MCPhysReg ImplicitOps[14];
};
}
#endif
#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC
namespace llvm {
static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
static constexpr unsigned BPFImpOpBase = sizeof BPFInstrTable::OperandInfo / (sizeof(MCPhysReg));
extern const BPFInstrTable BPFDescs = {
{
{ 491, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 280, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 490, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 276, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 489, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 488, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 487, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 486, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 485, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 280, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 484, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 276, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 483, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 280, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 482, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 276, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 481, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 280, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 480, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 276, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 479, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 280, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 478, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 276, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 477, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 280, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 476, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 276, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 475, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 280, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 474, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 276, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 473, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 280, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 472, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 276, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 471, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 280, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 470, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 276, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 469, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 276, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 468, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 467, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 466, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 465, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 464, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 273, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 463, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 256, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 462, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 461, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 273, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 460, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 256, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 459, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 458, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 273, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 457, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 456, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 273, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 455, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 256, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 454, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 453, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 452, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 451, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 450, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 449, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 448, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 447, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 446, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 445, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 444, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 443, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 442, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 441, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 440, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 439, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 438, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 437, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 436, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 435, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 434, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 433, 0, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 432, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 431, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 430, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 429, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 428, 1, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 427, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 219, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 426, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 271, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 425, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 424, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 423, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 422, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 421, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 265, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 420, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 261, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 419, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 269, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 418, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 259, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 417, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 267, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 416, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 261, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 415, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 265, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 414, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 265, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 413, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 261, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 412, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 261, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 411, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 410, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 409, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 408, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 407, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 219, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 406, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 219, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 405, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 219, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 404, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 403, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 263, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 402, 2, 0, 8, 0, 1, 6, BPFImpOpBase + 7, 261, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 401, 2, 0, 8, 0, 1, 6, BPFImpOpBase + 7, 261, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 400, 2, 0, 8, 0, 1, 6, BPFImpOpBase + 7, 261, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 399, 2, 0, 8, 0, 1, 6, BPFImpOpBase + 7, 259, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 398, 2, 0, 8, 0, 1, 6, BPFImpOpBase + 7, 259, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 397, 2, 0, 8, 0, 1, 6, BPFImpOpBase + 7, 259, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 396, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 395, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 256, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 394, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 393, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 392, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 256, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 391, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 390, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 389, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 388, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 256, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 387, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 386, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 385, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 384, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 383, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 382, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 381, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 380, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 379, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 378, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 377, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 376, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 375, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 374, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 373, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 372, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 371, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 370, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 369, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 368, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 367, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 366, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 365, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 364, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 363, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 362, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 361, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 360, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 359, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 358, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 357, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 356, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 355, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 354, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 353, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 352, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 351, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 350, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 349, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 348, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 347, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 346, 1, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 345, 1, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 344, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 253, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 343, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 250, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 342, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 247, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 341, 3, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 244, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 340, 1, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 339, 1, 0, 8, 0, 1, 0, BPFImpOpBase + 6, 243, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 338, 1, 0, 8, 0, 1, 0, BPFImpOpBase + 6, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 337, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 336, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 335, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 334, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 333, 4, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 239, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 332, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 235, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 331, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 231, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 330, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 227, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 329, 3, 0, 8, 0, 1, 1, BPFImpOpBase + 4, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 328, 3, 0, 8, 0, 1, 1, BPFImpOpBase + 2, 221, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 327, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 219, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 326, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 219, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 325, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 219, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 324, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 219, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 323, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 219, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 322, 2, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 219, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 321, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 320, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 319, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 318, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 317, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 216, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 316, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 213, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 315, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 210, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 314, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 207, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 313, 4, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 312, 6, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 201, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 311, 6, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 195, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 310, 6, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 189, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 309, 6, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 183, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 308, 6, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 177, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 307, 6, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 171, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 306, 6, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 165, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 305, 6, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 304, 4, 0, 8, 0, 0, 0, BPFImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 303, 3, 1, 8, 0, 0, 0, BPFImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 302, 2, 0, 8, 0, 1, 1, BPFImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 301, 2, 0, 8, 0, 1, 1, BPFImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 300, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 299, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 298, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 297, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 296, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 295, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 294, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 293, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 292, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 291, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 290, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 289, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 288, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 287, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 286, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 285, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 284, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 283, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 282, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 281, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 280, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 279, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 278, 3, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 277, 4, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 276, 4, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 275, 3, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 274, 4, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 273, 2, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 272, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 271, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 270, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 269, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 268, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 267, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 266, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 265, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 264, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 263, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 262, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 261, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 260, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 259, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 258, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 257, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 256, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 255, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 254, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 253, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 252, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 251, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 250, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 249, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 248, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 247, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 246, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 245, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 244, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 243, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 242, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 241, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 240, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 239, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 238, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 237, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 236, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 235, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 234, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 233, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 232, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 231, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 230, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 229, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 228, 3, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 227, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 226, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 225, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 224, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 223, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 222, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 221, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 220, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 219, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 218, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 217, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 216, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 215, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 214, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 213, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 212, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 211, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 210, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 209, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 208, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 207, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 206, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 205, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 204, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 203, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 202, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 201, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 200, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 199, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 198, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 197, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 196, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 195, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 194, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 193, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 192, 3, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 191, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 190, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 189, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 188, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 187, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 186, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 185, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 184, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 183, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 182, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 181, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 180, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 179, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 178, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 177, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 176, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 175, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 174, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 173, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 172, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 171, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 170, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 169, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 168, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 167, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 166, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 165, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 164, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 163, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 162, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 161, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 160, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 159, 4, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 158, 4, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 157, 5, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 156, 4, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 155, 5, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 154, 4, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 153, 5, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 152, 4, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 151, 5, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 150, 4, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 149, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 148, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 147, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 146, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 145, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 144, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 143, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 142, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 141, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 140, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 139, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 138, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 137, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 136, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 135, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 134, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 133, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 132, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 131, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 130, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 129, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 128, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 127, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 126, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 125, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 124, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 123, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 122, 2, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 121, 4, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 94, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 120, 2, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 119, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 118, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 117, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 116, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 115, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 114, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 113, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 112, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 111, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 110, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 109, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 108, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 107, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 106, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 105, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 104, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 103, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 102, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 101, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 100, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 99, 5, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 98, 5, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 97, 2, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 96, 5, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 95, 5, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 94, 5, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 93, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 92, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 91, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 90, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 89, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 88, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 87, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 86, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 85, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 84, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 83, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 82, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 81, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 80, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 79, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 78, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 77, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 76, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 75, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 74, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 73, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 72, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 71, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 70, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 69, 5, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 68, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 67, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 66, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 65, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 64, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 63, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 62, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 61, 4, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 60, 4, 2, 0, 0, 0, 0, BPFImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 59, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 58, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 57, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 56, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 55, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 54, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 53, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 52, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 51, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 50, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 49, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 48, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 47, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 46, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 45, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 44, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 43, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 42, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 41, 3, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 40, 2, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 39, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 38, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 37, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 36, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 35, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 34, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 33, 2, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 32, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 31, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 30, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 29, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 28, 6, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 27, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 26, 2, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 25, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 24, 4, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 23, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 22, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 21, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 20, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 19, 2, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 18, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 17, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 16, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 15, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 14, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 13, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 12, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 11, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 10, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 9, 4, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 8, 3, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 7, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 6, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 5, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 4, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 3, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 2, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 1, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 0, 1, 1, 0, 0, 0, 0, BPFImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
}, {
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
{ -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
{ BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
{ -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
{ BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
}, {
BPF::R11, BPF::R11,
BPF::R0, BPF::R0,
BPF::W0, BPF::W0,
BPF::R11,
BPF::R6, BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5,
}
};
#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char BPFInstrNameData[] = {
"G_FLOG10\0"
"G_FEXP10\0"
"LDB32\0"
"STB32\0"
"CORE_LD32\0"
"BE32\0"
"LE32\0"
"LDH32\0"
"STH32\0"
"BSWAP32\0"
"XFADDW32\0"
"XADDW32\0"
"LDW32\0"
"XFANDW32\0"
"XANDW32\0"
"CMPXCHGW32\0"
"XFORW32\0"
"XFXORW32\0"
"XXORW32\0"
"STW32\0"
"Select_Ri_64_32\0"
"Select_64_32\0"
"NEG_32\0"
"Select_Ri_32\0"
"SRA_ri_32\0"
"SUB_ri_32\0"
"ADD_ri_32\0"
"AND_ri_32\0"
"SMOD_ri_32\0"
"JSGE_ri_32\0"
"JUGE_ri_32\0"
"JSLE_ri_32\0"
"JULE_ri_32\0"
"JNE_ri_32\0"
"SLL_ri_32\0"
"SRL_ri_32\0"
"MUL_ri_32\0"
"JEQ_ri_32\0"
"XOR_ri_32\0"
"JSET_ri_32\0"
"JSGT_ri_32\0"
"JUGT_ri_32\0"
"JSLT_ri_32\0"
"JULT_ri_32\0"
"SDIV_ri_32\0"
"MOV_ri_32\0"
"SRA_rr_32\0"
"SUB_rr_32\0"
"ADD_rr_32\0"
"AND_rr_32\0"
"SMOD_rr_32\0"
"JSGE_rr_32\0"
"JUGE_rr_32\0"
"JSLE_rr_32\0"
"JULE_rr_32\0"
"JNE_rr_32\0"
"SLL_rr_32\0"
"SRL_rr_32\0"
"MUL_rr_32\0"
"JEQ_rr_32\0"
"XOR_rr_32\0"
"JSET_rr_32\0"
"JSGT_rr_32\0"
"JUGT_rr_32\0"
"JSLT_rr_32\0"
"JULT_rr_32\0"
"SDIV_rr_32\0"
"MOV_rr_32\0"
"MOVSX_rr_32\0"
"Select_32\0"
"G_FLOG2\0"
"G_FEXP2\0"
"CORE_LD64\0"
"BE64\0"
"LE64\0"
"BSWAP64\0"
"MOV_32_64\0"
"Select_Ri_32_64\0"
"Select_32_64\0"
"NEG_64\0"
"LD_imm64\0"
"BE16\0"
"LE16\0"
"BSWAP16\0"
"MOVSX_rr_32_16\0"
"MOVSX_rr_16\0"
"MOVSX_rr_32_8\0"
"MOVSX_rr_8\0"
"G_FMA\0"
"G_STRICT_FMA\0"
"LDB\0"
"STB\0"
"G_FSUB\0"
"G_STRICT_FSUB\0"
"G_ATOMICRMW_FSUB\0"
"G_SUB\0"
"G_ATOMICRMW_SUB\0"
"LD_IND_B\0"
"LD_ABS_B\0"
"G_INTRINSIC\0"
"G_FPTRUNC\0"
"G_INTRINSIC_TRUNC\0"
"G_TRUNC\0"
"G_BUILD_VECTOR_TRUNC\0"
"G_DYN_STACKALLOC\0"
"G_FMAD\0"
"G_INDEXED_SEXTLOAD\0"
"G_SEXTLOAD\0"
"G_INDEXED_ZEXTLOAD\0"
"G_ZEXTLOAD\0"
"G_INDEXED_LOAD\0"
"G_LOAD\0"
"G_VECREDUCE_FADD\0"
"G_FADD\0"
"G_VECREDUCE_SEQ_FADD\0"
"G_STRICT_FADD\0"
"G_ATOMICRMW_FADD\0"
"G_VECREDUCE_ADD\0"
"G_ADD\0"
"G_PTR_ADD\0"
"G_ATOMICRMW_ADD\0"
"XFADDD\0"
"XADDD\0"
"LDD\0"
"XFANDD\0"
"XANDD\0"
"CMPXCHGD\0"
"G_ATOMICRMW_NAND\0"
"G_VECREDUCE_AND\0"
"G_AND\0"
"G_ATOMICRMW_AND\0"
"LIFETIME_END\0"
"JCOND\0"
"G_BRCOND\0"
"G_ATOMICRMW_USUB_COND\0"
"G_LLROUND\0"
"G_LROUND\0"
"G_INTRINSIC_ROUND\0"
"G_INTRINSIC_FPTRUNC_ROUND\0"
"LOAD_STACK_GUARD\0"
"XFORD\0"
"XFXORD\0"
"XXORD\0"
"STD\0"
"PSEUDO_PROBE\0"
"G_SSUBE\0"
"G_USUBE\0"
"G_FENCE\0"
"ARITH_FENCE\0"
"REG_SEQUENCE\0"
"G_SADDE\0"
"G_UADDE\0"
"G_GET_FPMODE\0"
"G_RESET_FPMODE\0"
"G_SET_FPMODE\0"
"G_FMINNUM_IEEE\0"
"G_FMAXNUM_IEEE\0"
"G_VSCALE\0"
"G_JUMP_TABLE\0"
"BUNDLE\0"
"G_MEMCPY_INLINE\0"
"LOCAL_ESCAPE\0"
"G_STACKRESTORE\0"
"G_INDEXED_STORE\0"
"G_STORE\0"
"G_BITREVERSE\0"
"FAKE_USE\0"
"DBG_VALUE\0"
"G_GLOBAL_VALUE\0"
"G_PTRAUTH_GLOBAL_VALUE\0"
"CONVERGENCECTRL_GLUE\0"
"G_STACKSAVE\0"
"G_MEMMOVE\0"
"G_FREEZE\0"
"G_FCANONICALIZE\0"
"G_CTLZ_ZERO_UNDEF\0"
"G_CTTZ_ZERO_UNDEF\0"
"INIT_UNDEF\0"
"G_IMPLICIT_DEF\0"
"DBG_INSTR_REF\0"
"G_FNEG\0"
"EXTRACT_SUBREG\0"
"INSERT_SUBREG\0"
"G_SEXT_INREG\0"
"SUBREG_TO_REG\0"
"G_ATOMIC_CMPXCHG\0"
"G_ATOMICRMW_XCHG\0"
"G_FLOG\0"
"G_VAARG\0"
"PREALLOCATED_ARG\0"
"G_PREFETCH\0"
"LDH\0"
"G_SMULH\0"
"G_UMULH\0"
"G_FTANH\0"
"G_FSINH\0"
"G_FCOSH\0"
"STH\0"
"LD_IND_H\0"
"LD_ABS_H\0"
"DBG_PHI\0"
"G_FPTOSI\0"
"G_FPTOUI\0"
"G_FPOWI\0"
"G_PTRMASK\0"
"JAL\0"
"GC_LABEL\0"
"DBG_LABEL\0"
"EH_LABEL\0"
"ANNOTATION_LABEL\0"
"ICALL_BRANCH_FUNNEL\0"
"G_FSHL\0"
"G_SHL\0"
"G_FCEIL\0"
"PATCHABLE_TAIL_CALL\0"
"PATCHABLE_TYPED_EVENT_CALL\0"
"PATCHABLE_EVENT_CALL\0"
"FENTRY_CALL\0"
"KILL\0"
"G_CONSTANT_POOL\0"
"JMPL\0"
"G_ROTL\0"
"G_VECREDUCE_FMUL\0"
"G_FMUL\0"
"G_VECREDUCE_SEQ_FMUL\0"
"G_STRICT_FMUL\0"
"G_VECREDUCE_MUL\0"
"G_MUL\0"
"G_FREM\0"
"G_STRICT_FREM\0"
"G_SREM\0"
"G_UREM\0"
"G_SDIVREM\0"
"G_UDIVREM\0"
"INLINEASM\0"
"G_VECREDUCE_FMINIMUM\0"
"G_FMINIMUM\0"
"G_VECREDUCE_FMAXIMUM\0"
"G_FMAXIMUM\0"
"G_FMINNUM\0"
"G_FMAXNUM\0"
"G_FATAN\0"
"G_FTAN\0"
"G_INTRINSIC_ROUNDEVEN\0"
"G_ASSERT_ALIGN\0"
"G_FCOPYSIGN\0"
"G_VECREDUCE_FMIN\0"
"G_ATOMICRMW_FMIN\0"
"G_VECREDUCE_SMIN\0"
"G_SMIN\0"
"G_VECREDUCE_UMIN\0"
"G_UMIN\0"
"G_ATOMICRMW_UMIN\0"
"G_ATOMICRMW_MIN\0"
"G_FASIN\0"
"G_FSIN\0"
"CFI_INSTRUCTION\0"
"ADJCALLSTACKDOWN\0"
"G_SSUBO\0"
"G_USUBO\0"
"G_SADDO\0"
"G_UADDO\0"
"JUMP_TABLE_DEBUG_INFO\0"
"G_SMULO\0"
"G_UMULO\0"
"G_BZERO\0"
"STACKMAP\0"
"G_DEBUGTRAP\0"
"G_UBSANTRAP\0"
"G_TRAP\0"
"G_ATOMICRMW_UDEC_WRAP\0"
"G_ATOMICRMW_UINC_WRAP\0"
"G_BSWAP\0"
"G_SITOFP\0"
"G_UITOFP\0"
"G_FCMP\0"
"G_ICMP\0"
"G_SCMP\0"
"G_UCMP\0"
"JMP\0"
"NOP\0"
"CONVERGENCECTRL_LOOP\0"
"G_CTPOP\0"
"PATCHABLE_OP\0"
"FAULTING_OP\0"
"ADJCALLSTACKUP\0"
"PREALLOCATED_SETUP\0"
"G_FLDEXP\0"
"G_STRICT_FLDEXP\0"
"G_FEXP\0"
"G_FFREXP\0"
"G_BR\0"
"INLINEASM_BR\0"
"G_BLOCK_ADDR\0"
"MEMBARRIER\0"
"G_CONSTANT_FOLD_BARRIER\0"
"PATCHABLE_FUNCTION_ENTER\0"
"G_READCYCLECOUNTER\0"
"G_READSTEADYCOUNTER\0"
"G_READ_REGISTER\0"
"G_WRITE_REGISTER\0"
"G_ASHR\0"
"G_FSHR\0"
"G_LSHR\0"
"CONVERGENCECTRL_ANCHOR\0"
"G_FFLOOR\0"
"G_EXTRACT_SUBVECTOR\0"
"G_INSERT_SUBVECTOR\0"
"G_BUILD_VECTOR\0"
"G_SHUFFLE_VECTOR\0"
"G_SPLAT_VECTOR\0"
"G_VECREDUCE_XOR\0"
"G_XOR\0"
"G_ATOMICRMW_XOR\0"
"G_VECREDUCE_OR\0"
"G_OR\0"
"G_ATOMICRMW_OR\0"
"G_ROTR\0"
"G_INTTOPTR\0"
"G_FABS\0"
"G_ABS\0"
"G_UNMERGE_VALUES\0"
"G_MERGE_VALUES\0"
"G_FACOS\0"
"G_FCOS\0"
"G_CONCAT_VECTORS\0"
"COPY_TO_REGCLASS\0"
"G_IS_FPCLASS\0"
"G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
"G_VECTOR_COMPRESS\0"
"G_INTRINSIC_W_SIDE_EFFECTS\0"
"G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
"G_SSUBSAT\0"
"G_USUBSAT\0"
"G_SADDSAT\0"
"G_UADDSAT\0"
"G_SSHLSAT\0"
"G_USHLSAT\0"
"G_SMULFIXSAT\0"
"G_UMULFIXSAT\0"
"G_SDIVFIXSAT\0"
"G_UDIVFIXSAT\0"
"G_ATOMICRMW_USUB_SAT\0"
"G_FPTOSI_SAT\0"
"G_FPTOUI_SAT\0"
"G_EXTRACT\0"
"G_SELECT\0"
"G_BRINDIRECT\0"
"PATCHABLE_RET\0"
"G_MEMSET\0"
"CORE_SHIFT\0"
"PATCHABLE_FUNCTION_EXIT\0"
"G_BRJT\0"
"G_EXTRACT_VECTOR_ELT\0"
"G_INSERT_VECTOR_ELT\0"
"G_FCONSTANT\0"
"G_CONSTANT\0"
"G_INTRINSIC_CONVERGENT\0"
"STATEPOINT\0"
"PATCHPOINT\0"
"G_PTRTOINT\0"
"G_FRINT\0"
"G_INTRINSIC_LLRINT\0"
"G_INTRINSIC_LRINT\0"
"G_FNEARBYINT\0"
"G_VASTART\0"
"LIFETIME_START\0"
"G_INVOKE_REGION_START\0"
"G_INSERT\0"
"G_FSQRT\0"
"G_STRICT_FSQRT\0"
"G_BITCAST\0"
"G_ADDRSPACE_CAST\0"
"ADDR_SPACE_CAST\0"
"DBG_VALUE_LIST\0"
"CORE_ST\0"
"G_FPEXT\0"
"G_SEXT\0"
"G_ASSERT_SEXT\0"
"G_ANYEXT\0"
"G_ZEXT\0"
"G_ASSERT_ZEXT\0"
"G_FDIV\0"
"G_STRICT_FDIV\0"
"G_SDIV\0"
"G_UDIV\0"
"G_GET_FPENV\0"
"G_RESET_FPENV\0"
"G_SET_FPENV\0"
"XADDW\0"
"LDW\0"
"G_FPOW\0"
"STW\0"
"LD_IND_W\0"
"LD_ABS_W\0"
"G_VECREDUCE_FMAX\0"
"G_ATOMICRMW_FMAX\0"
"G_VECREDUCE_SMAX\0"
"G_SMAX\0"
"G_VECREDUCE_UMAX\0"
"G_UMAX\0"
"G_ATOMICRMW_UMAX\0"
"G_ATOMICRMW_MAX\0"
"G_FRAME_INDEX\0"
"G_SBFX\0"
"G_UBFX\0"
"G_SMULFIX\0"
"G_UMULFIX\0"
"G_SDIVFIX\0"
"G_UDIVFIX\0"
"JALX\0"
"LDBSX\0"
"LDHSX\0"
"LDWSX\0"
"G_MEMCPY\0"
"COPY\0"
"CONVERGENCECTRL_ENTRY\0"
"G_CTLZ\0"
"G_CTTZ\0"
"Select_Ri\0"
"SRA_ri\0"
"SUB_ri\0"
"ADD_ri\0"
"AND_ri\0"
"SMOD_ri\0"
"JSGE_ri\0"
"JUGE_ri\0"
"JSLE_ri\0"
"JULE_ri\0"
"JNE_ri\0"
"FI_ri\0"
"SLL_ri\0"
"SRL_ri\0"
"MUL_ri\0"
"JEQ_ri\0"
"XOR_ri\0"
"JSET_ri\0"
"JSGT_ri\0"
"JUGT_ri\0"
"JSLT_ri\0"
"JULT_ri\0"
"SDIV_ri\0"
"MOV_ri\0"
"STB_imm\0"
"STD_imm\0"
"STH_imm\0"
"STW_imm\0"
"LD_pseudo\0"
"SRA_rr\0"
"SUB_rr\0"
"ADD_rr\0"
"AND_rr\0"
"SMOD_rr\0"
"JSGE_rr\0"
"JUGE_rr\0"
"JSLE_rr\0"
"JULE_rr\0"
"JNE_rr\0"
"SLL_rr\0"
"SRL_rr\0"
"MUL_rr\0"
"JEQ_rr\0"
"XOR_rr\0"
"JSET_rr\0"
"JSGT_rr\0"
"JUGT_rr\0"
"JSLT_rr\0"
"JULT_rr\0"
"SDIV_rr\0"
"MOV_rr\0"
"Select\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif
extern const unsigned BPFInstrNameIndices[] = {
2175U, 2554U, 3233U, 2842U, 2238U, 2219U, 2247U, 2385U,
1972U, 1987U, 1938U, 1925U, 2014U, 3698U, 1773U, 4397U,
1951U, 2171U, 2228U, 1554U, 4806U, 1676U, 4285U, 1352U,
1505U, 1542U, 2953U, 2373U, 4195U, 1465U, 3168U, 2077U,
4184U, 1699U, 3141U, 3128U, 3294U, 4032U, 4066U, 2305U,
2352U, 2325U, 2264U, 1764U, 3259U, 2907U, 4811U, 3412U,
3099U, 1821U, 4435U, 4465U, 2685U, 1226U, 919U, 2493U,
4500U, 4507U, 2520U, 2527U, 2534U, 2544U, 1330U, 3583U,
3546U, 1936U, 2173U, 4706U, 1783U, 1798U, 2390U, 4000U,
3634U, 4322U, 3651U, 3483U, 1007U, 3681U, 4206U, 3610U,
4354U, 1864U, 3270U, 1439U, 981U, 1421U, 4244U, 4225U,
2663U, 3319U, 3338U, 1127U, 1071U, 1101U, 1112U, 1052U,
1082U, 1743U, 1727U, 3728U, 2028U, 2045U, 1242U, 925U,
1336U, 1297U, 3588U, 3552U, 4690U, 2811U, 4673U, 2794U,
1193U, 902U, 4608U, 2729U, 3015U, 2993U, 1380U, 3953U,
1534U, 2094U, 1371U, 4019U, 4300U, 959U, 3776U, 4161U,
3803U, 4449U, 999U, 4150U, 4138U, 4275U, 2069U, 4428U,
2001U, 4458U, 2291U, 3405U, 3391U, 2284U, 3398U, 3603U,
2411U, 3070U, 3063U, 3077U, 3084U, 4010U, 2899U, 1575U,
2883U, 1526U, 2891U, 1567U, 2875U, 1518U, 2937U, 2929U,
2117U, 2109U, 3871U, 3861U, 3851U, 3841U, 3891U, 3881U,
4734U, 4744U, 3901U, 3914U, 4754U, 4764U, 3927U, 3940U,
1151U, 881U, 2435U, 854U, 1045U, 4479U, 2499U, 4562U,
2197U, 3212U, 693U, 9U, 2062U, 685U, 0U, 3187U,
3219U, 1965U, 4420U, 971U, 2179U, 2188U, 3045U, 3054U,
3974U, 3987U, 3621U, 2700U, 3715U, 1873U, 2628U, 2638U,
1624U, 1639U, 2585U, 2617U, 4514U, 4540U, 4526U, 1583U,
1611U, 1596U, 1232U, 2205U, 2763U, 4642U, 2787U, 4666U,
3628U, 1412U, 1402U, 3228U, 4090U, 1654U, 3464U, 3444U,
4118U, 4097U, 3498U, 3515U, 3758U, 4840U, 1907U, 4833U,
1889U, 3120U, 3037U, 1751U, 2297U, 3674U, 2835U, 2656U,
3666U, 2827U, 2648U, 2141U, 2133U, 2125U, 4331U, 3435U,
4217U, 4262U, 4364U, 3246U, 1663U, 1028U, 1842U, 1712U,
1179U, 888U, 2463U, 4486U, 2506U, 860U, 4339U, 3196U,
3358U, 3374U, 4797U, 1683U, 1854U, 4046U, 2945U, 2986U,
2962U, 2974U, 1158U, 2442U, 1134U, 2418U, 4591U, 2712U,
2596U, 2564U, 1210U, 2477U, 1314U, 3568U, 3530U, 4625U,
2746U, 4649U, 2770U, 4720U, 4727U, 2858U, 3153U, 4932U,
4799U, 5235U, 675U, 755U, 168U, 4847U, 188U, 739U,
152U, 4381U, 4871U, 221U, 5084U, 452U, 4878U, 231U,
5091U, 462U, 784U, 40U, 711U, 794U, 62U, 721U,
1288U, 110U, 30U, 701U, 4055U, 4412U, 5014U, 412U,
5221U, 643U, 2215U, 4774U, 1365U, 4959U, 336U, 5166U,
567U, 3091U, 2406U, 4925U, 296U, 5138U, 527U, 4973U,
356U, 5180U, 587U, 4893U, 252U, 5106U, 483U, 4981U,
367U, 5188U, 598U, 4909U, 274U, 5122U, 505U, 4997U,
389U, 5204U, 620U, 4901U, 263U, 5114U, 494U, 4989U,
378U, 5196U, 609U, 4917U, 285U, 5130U, 516U, 5005U,
400U, 5212U, 631U, 873U, 18U, 4779U, 1271U, 2105U,
50U, 4785U, 4558U, 87U, 4791U, 950U, 2162U, 4582U,
941U, 2153U, 4573U, 775U, 5060U, 789U, 45U, 716U,
4886U, 242U, 5099U, 473U, 817U, 663U, 802U, 829U,
843U, 729U, 5021U, 422U, 5228U, 653U, 4952U, 326U,
5159U, 557U, 181U, 768U, 3095U, 4967U, 347U, 5174U,
578U, 4042U, 5013U, 411U, 5220U, 642U, 4938U, 306U,
5145U, 537U, 4885U, 241U, 5098U, 472U, 4857U, 201U,
5070U, 432U, 4945U, 316U, 5152U, 547U, 877U, 24U,
5028U, 1501U, 5036U, 2149U, 56U, 5044U, 4569U, 146U,
5052U, 4864U, 211U, 5077U, 442U, 1265U, 4552U, 79U,
1282U, 102U, 1291U, 113U, 1258U, 70U, 1275U, 93U,
1482U, 121U, 1488U, 129U, 1490U, 131U, 4966U, 346U,
5173U, 577U, 1495U, 138U,
};
static inline void InitBPFMCInstrInfo(MCInstrInfo *II) {
II->InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 492);
}
}
#endif
#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER
namespace llvm {
struct BPFGenInstrInfo : public TargetInstrInfo {
explicit BPFGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
~BPFGenInstrInfo() override = default;
};
}
#endif
#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS
#endif
#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS
#endif
#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR
namespace llvm {
extern const BPFInstrTable BPFDescs;
extern const unsigned BPFInstrNameIndices[];
extern const char BPFInstrNameData[];
BPFGenInstrInfo::BPFGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
: TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 492);
}
}
#endif
#ifdef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_OPERAND_ENUM
namespace llvm {
namespace BPF {
namespace OpName {
enum {
OPERAND_LAST
};
}
}
}
#endif
#ifdef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_NAMED_OPS
namespace llvm {
namespace BPF {
LLVM_READONLY
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
return -1;
}
}
}
#endif
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
namespace llvm {
namespace BPF {
namespace OpTypes {
enum OperandType {
MEMri = 0,
brtarget = 1,
calltarget = 2,
f32imm = 3,
f64imm = 4,
gpr_or_imm = 5,
i1imm = 6,
i8imm = 7,
i16imm = 8,
i32imm = 9,
i64imm = 10,
ptype0 = 11,
ptype1 = 12,
ptype2 = 13,
ptype3 = 14,
ptype4 = 15,
ptype5 = 16,
s16imm = 17,
type0 = 18,
type1 = 19,
type2 = 20,
type3 = 21,
type4 = 22,
type5 = 23,
u64imm = 24,
untyped_imm_0 = 25,
GPR = 26,
GPR32 = 27,
OPERAND_TYPE_LIST_END
};
}
}
}
#endif
#ifdef GET_INSTRINFO_OPERAND_TYPE
#undef GET_INSTRINFO_OPERAND_TYPE
namespace llvm {
namespace BPF {
LLVM_READONLY
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
static const uint16_t Offsets[] = {
0,
1,
1,
1,
2,
3,
4,
5,
5,
8,
12,
13,
14,
18,
21,
21,
21,
21,
21,
22,
24,
26,
26,
27,
28,
32,
34,
36,
36,
42,
43,
44,
47,
47,
49,
50,
50,
50,
50,
50,
50,
52,
55,
55,
55,
55,
56,
57,
58,
60,
61,
64,
67,
70,
73,
76,
79,
82,
85,
88,
91,
95,
99,
102,
105,
108,
109,
110,
112,
114,
119,
121,
124,
126,
130,
132,
134,
136,
138,
140,
142,
144,
146,
148,
151,
153,
155,
157,
159,
161,
162,
163,
165,
167,
169,
174,
179,
184,
186,
191,
196,
200,
203,
206,
209,
212,
215,
218,
221,
224,
227,
230,
233,
236,
239,
242,
245,
248,
251,
254,
257,
259,
263,
265,
266,
266,
267,
268,
269,
270,
272,
274,
276,
278,
279,
282,
284,
287,
289,
292,
295,
298,
302,
306,
309,
312,
316,
320,
323,
326,
330,
334,
339,
343,
348,
352,
357,
361,
366,
370,
374,
377,
380,
383,
386,
389,
392,
395,
398,
402,
406,
410,
414,
418,
422,
426,
430,
433,
436,
439,
443,
447,
450,
453,
456,
459,
461,
463,
465,
467,
469,
471,
474,
477,
479,
481,
483,
485,
487,
489,
491,
493,
495,
497,
500,
503,
505,
508,
511,
514,
517,
520,
523,
524,
525,
525,
526,
527,
527,
530,
533,
536,
539,
542,
545,
547,
549,
551,
552,
555,
557,
561,
564,
568,
571,
575,
577,
581,
583,
585,
587,
589,
591,
593,
595,
597,
599,
601,
603,
605,
607,
609,
611,
613,
615,
617,
619,
621,
623,
625,
627,
629,
632,
633,
634,
637,
640,
643,
646,
649,
653,
655,
658,
660,
662,
666,
669,
673,
677,
680,
680,
680,
681,
684,
687,
689,
691,
693,
695,
697,
699,
701,
703,
705,
707,
709,
711,
713,
715,
717,
721,
725,
727,
729,
732,
736,
742,
748,
754,
760,
766,
772,
778,
784,
788,
791,
794,
797,
800,
803,
806,
809,
812,
814,
816,
818,
820,
822,
824,
827,
830,
834,
838,
842,
846,
849,
852,
855,
858,
859,
860,
861,
864,
867,
870,
873,
874,
875,
878,
881,
884,
887,
890,
893,
896,
899,
902,
905,
908,
911,
914,
917,
920,
923,
926,
929,
932,
935,
938,
941,
944,
947,
950,
953,
956,
959,
962,
965,
968,
971,
974,
977,
980,
983,
986,
989,
992,
995,
998,
1001,
1004,
1007,
1010,
1013,
1016,
1019,
1022,
1025,
1027,
1029,
1031,
1033,
1035,
1037,
1039,
1042,
1044,
1046,
1048,
1051,
1054,
1057,
1060,
1062,
1064,
1066,
1068,
1070,
1072,
1074,
1076,
1078,
1080,
1083,
1086,
1089,
1092,
1094,
1096,
1097,
1100,
1103,
1106,
1109,
1109,
1112,
1115,
1118,
1121,
1124,
1127,
1130,
1133,
1136,
1139,
1142,
1145,
1148,
1151,
1154,
1157,
1160,
1163,
1166,
1169,
1172,
1175,
1178,
1181,
1184,
1187,
1190,
1193,
1196,
1199,
1202,
1205,
1208,
1211,
1214,
1218,
1222,
1226,
1230,
1234,
1238,
1242,
1246,
1250,
1254,
1258,
1262,
1266,
1270,
1274,
1278,
1282,
1285,
1288,
1291,
1294,
1298,
};
using namespace OpTypes;
static const int8_t OpcodeOperandTypes[] = {
-1,
i32imm,
i32imm,
i32imm,
i32imm,
-1, -1, i32imm,
-1, -1, -1, i32imm,
-1,
-1,
-1, -1, -1, i32imm,
-1, -1, i32imm,
-1,
-1, -1,
-1, -1,
i32imm,
i32imm,
i64imm, i64imm, i8imm, i32imm,
-1, -1,
i64imm, i32imm,
-1, i64imm, i32imm, -1, i32imm, i32imm,
-1,
i32imm,
-1, i32imm, i32imm,
-1, i32imm,
-1,
-1, -1,
-1, -1, -1,
i64imm,
-1,
-1,
-1, -1,
-1,
type0, type0, untyped_imm_0,
type0, type0, untyped_imm_0,
type0, type0, untyped_imm_0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0, type0,
type0, type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0,
type0,
type0, -1,
type0, -1,
type0, -1, i32imm, type1, i64imm,
type0, -1,
type0, type1, untyped_imm_0,
type0, type1,
type0, type0, type1, untyped_imm_0,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type0,
type0, type0,
type0, type1, i32imm,
type0, type0,
type0, type0,
type0, type1,
type0, type1,
type0, type0,
type0,
type0,
type0, ptype1,
type0, ptype1,
type0, ptype1,
type0, ptype1, ptype1, type2, -1,
type0, ptype1, ptype1, type2, -1,
type0, ptype1, ptype1, type2, -1,
type0, ptype1,
ptype0, type1, ptype0, ptype2, -1,
type0, type1, type2, type0, type0,
type0, ptype1, type0, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
i32imm, i32imm,
ptype0, i32imm, i32imm, i32imm,
type0, -1,
type0,
-1,
-1,
-1,
-1,
type0, type1,
type0, type1,
type0, -1,
type0, -1,
type0,
type0, type1, -1,
type0, type1,
type0, type0, untyped_imm_0,
type0, type1,
type0, type0, type1,
type0, type0, type1,
type0, type0, type1,
type0, type0, type0, type1,
type0, type0, type0, type1,
type0, type0, type1,
type0, type0, type1,
type0, -1, type1, type1,
type0, -1, type1, type1,
type0, type1, type1,
type0, type1, type1,
type0, type1, type0, type0,
type0, type1, type0, type0,
type0, type1, type0, type0, type1,
type0, type1, type0, type0,
type0, type1, type0, type0, type1,
type0, type1, type0, type0,
type0, type1, type0, type0, type1,
type0, type1, type0, type0,
type0, type1, type0, type0, type1,
type0, type1, type0, type0,
type0, type1, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type1,
type0, type0, type1,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0, type0,
type0, type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type1,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0, type1,
type0, type1, type0,
type0, type0,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type0,
type0, type0, type1,
type0, type1, -1,
type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0,
type0,
type0,
type0,
ptype0, ptype0, type1,
ptype0, ptype0, type1,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0,
type0, type1,
type0, type1,
-1,
ptype0, -1, type1,
type0, -1,
type0, type0, type1, untyped_imm_0,
type0, type0, untyped_imm_0,
type0, type0, type1, type2,
type0, type1, type2,
type0, type1, type1, -1,
type0, type1,
type0, type0, type1, type0,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type1,
type0, -1,
type0, -1,
ptype0, type1, i32imm,
ptype0,
ptype0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0, type0,
type0, type0,
type0, type0, type1,
type0, -1,
-1, type0,
ptype0, ptype1, type2, untyped_imm_0,
ptype0, ptype1, type2,
ptype0, ptype1, type2, untyped_imm_0,
ptype0, type1, type2, untyped_imm_0,
ptype0, type1, untyped_imm_0,
i8imm,
type0, type1, type2,
type0, type1, type2,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type0, type1, type1,
type0, type0, type1, type1,
i64imm, i64imm,
i64imm, i64imm,
GPR, GPR, s16imm,
GPR, GPR, i64imm, i64imm,
GPR, GPR, GPR, i64imm, GPR, GPR,
GPR32, GPR32, GPR32, i32imm, GPR32, GPR32,
GPR, GPR32, GPR32, i32imm, GPR, GPR,
GPR32, GPR, GPR, i64imm, GPR32, GPR32,
GPR, GPR, i64imm, i64imm, GPR, GPR,
GPR32, GPR32, i32imm, i32imm, GPR32, GPR32,
GPR, GPR32, i32imm, i32imm, GPR, GPR,
GPR32, GPR, i64imm, i64imm, GPR32, GPR32,
GPR, GPR, i64imm, i64imm,
GPR, GPR, i64imm,
GPR32, GPR32, i32imm,
GPR, GPR, GPR,
GPR32, GPR32, GPR32,
GPR, GPR, i64imm,
GPR32, GPR32, i32imm,
GPR, GPR, GPR,
GPR32, GPR32, GPR32,
GPR, GPR,
GPR, GPR,
GPR, GPR,
GPR, GPR,
GPR, GPR,
GPR, GPR,
GPR, s16imm, GPR,
GPR, s16imm, GPR32,
GPR32, u64imm, GPR, u64imm,
GPR, u64imm, GPR, u64imm,
GPR, u64imm, GPR, u64imm,
gpr_or_imm, u64imm, GPR, u64imm,
GPR, GPR, i64imm,
GPR32, GPR32, i32imm,
GPR, GPR, GPR,
GPR32, GPR32, GPR32,
calltarget,
GPR,
brtarget,
GPR, i64imm, brtarget,
GPR32, i32imm, brtarget,
GPR, GPR, brtarget,
GPR32, GPR32, brtarget,
brtarget,
brtarget,
GPR, i64imm, brtarget,
GPR32, i32imm, brtarget,
GPR, GPR, brtarget,
GPR32, GPR32, brtarget,
GPR, i64imm, brtarget,
GPR32, i32imm, brtarget,
GPR, GPR, brtarget,
GPR32, GPR32, brtarget,
GPR, i64imm, brtarget,
GPR32, i32imm, brtarget,
GPR, GPR, brtarget,
GPR32, GPR32, brtarget,
GPR, i64imm, brtarget,
GPR32, i32imm, brtarget,
GPR, GPR, brtarget,
GPR32, GPR32, brtarget,
GPR, i64imm, brtarget,
GPR32, i32imm, brtarget,
GPR, GPR, brtarget,
GPR32, GPR32, brtarget,
GPR, i64imm, brtarget,
GPR32, i32imm, brtarget,
GPR, GPR, brtarget,
GPR32, GPR32, brtarget,
GPR, i64imm, brtarget,
GPR32, i32imm, brtarget,
GPR, GPR, brtarget,
GPR32, GPR32, brtarget,
GPR, i64imm, brtarget,
GPR32, i32imm, brtarget,
GPR, GPR, brtarget,
GPR32, GPR32, brtarget,
GPR, i64imm, brtarget,
GPR32, i32imm, brtarget,
GPR, GPR, brtarget,
GPR32, GPR32, brtarget,
GPR, i64imm, brtarget,
GPR32, i32imm, brtarget,
GPR, GPR, brtarget,
GPR32, GPR32, brtarget,
GPR, GPR, s16imm,
GPR32, GPR, s16imm,
GPR, GPR, s16imm,
GPR, GPR, s16imm,
GPR, GPR, s16imm,
GPR32, GPR, s16imm,
GPR, GPR, s16imm,
GPR, GPR, s16imm,
GPR32, GPR, s16imm,
GPR, GPR, s16imm,
GPR, i64imm,
GPR, i64imm,
GPR, i64imm,
GPR, GPR,
GPR, GPR,
GPR, GPR,
GPR, u64imm,
GPR, i64imm, u64imm,
GPR, GPR,
GPR, GPR,
GPR, GPR,
GPR, GPR, i64imm,
GPR32, GPR32, i32imm,
GPR, GPR, GPR,
GPR32, GPR32, GPR32,
GPR, GPR,
GPR, GPR,
GPR32, GPR32,
GPR32, GPR32,
GPR, GPR,
GPR, GPR32,
GPR, i64imm,
GPR32, i32imm,
GPR, GPR,
GPR32, GPR32,
GPR, GPR, i64imm,
GPR32, GPR32, i32imm,
GPR, GPR, GPR,
GPR32, GPR32, GPR32,
GPR32, GPR32,
GPR, GPR,
i32imm,
GPR, GPR, i64imm,
GPR32, GPR32, i32imm,
GPR, GPR, GPR,
GPR32, GPR32, GPR32,
GPR, GPR, i64imm,
GPR32, GPR32, i32imm,
GPR, GPR, GPR,
GPR32, GPR32, GPR32,
GPR, GPR, i64imm,
GPR32, GPR32, i32imm,
GPR, GPR, GPR,
GPR32, GPR32, GPR32,
GPR, GPR, i64imm,
GPR32, GPR32, i32imm,
GPR, GPR, GPR,
GPR32, GPR32, GPR32,
GPR, GPR, i64imm,
GPR32, GPR32, i32imm,
GPR, GPR, GPR,
GPR32, GPR32, GPR32,
GPR, GPR, i64imm,
GPR32, GPR32, i32imm,
GPR, GPR, GPR,
GPR32, GPR32, GPR32,
GPR, GPR, s16imm,
GPR32, GPR, s16imm,
i64imm, GPR, s16imm,
GPR, GPR, s16imm,
i64imm, GPR, s16imm,
GPR, GPR, s16imm,
GPR32, GPR, s16imm,
i64imm, GPR, s16imm,
GPR, GPR, s16imm,
GPR32, GPR, s16imm,
i64imm, GPR, s16imm,
GPR, GPR, i64imm,
GPR32, GPR32, i32imm,
GPR, GPR, GPR,
GPR32, GPR32, GPR32,
GPR, GPR, s16imm, GPR,
GPR, GPR, s16imm, GPR,
GPR32, GPR, s16imm, GPR32,
GPR, GPR, s16imm, GPR,
GPR32, GPR, s16imm, GPR32,
GPR, GPR, s16imm, GPR,
GPR32, GPR, s16imm, GPR32,
GPR, GPR, s16imm, GPR,
GPR32, GPR, s16imm, GPR32,
GPR, GPR, s16imm, GPR,
GPR32, GPR, s16imm, GPR32,
GPR, GPR, s16imm, GPR,
GPR32, GPR, s16imm, GPR32,
GPR, GPR, s16imm, GPR,
GPR32, GPR, s16imm, GPR32,
GPR, GPR, s16imm, GPR,
GPR32, GPR, s16imm, GPR32,
GPR, GPR, i64imm,
GPR32, GPR32, i32imm,
GPR, GPR, GPR,
GPR32, GPR32, GPR32,
GPR, GPR, s16imm, GPR,
GPR32, GPR, s16imm, GPR32,
};
return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
}
}
}
#endif
#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
namespace llvm {
namespace BPF {
LLVM_READONLY
static int getMemOperandSize(int OpType) {
switch (OpType) {
default: return 0;
}
}
}
}
#endif
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
namespace llvm {
namespace BPF {
LLVM_READONLY static unsigned
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
return LogicalOpIdx;
}
LLVM_READONLY static inline unsigned
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
auto S = 0U;
for (auto i = 0U; i < LogicalOpIdx; ++i)
S += getLogicalOperandSize(Opcode, i);
return S;
}
}
}
#endif
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
namespace llvm {
namespace BPF {
LLVM_READONLY static int
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
return -1;
}
}
}
#endif
#ifdef GET_INSTRINFO_MC_HELPER_DECLS
#undef GET_INSTRINFO_MC_HELPER_DECLS
namespace llvm {
class MCInst;
class FeatureBitset;
namespace BPF_MC {
void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
}
}
#endif
#ifdef GET_INSTRINFO_MC_HELPERS
#undef GET_INSTRINFO_MC_HELPERS
namespace llvm {
namespace BPF_MC {
}
}
#endif
#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
defined(GET_AVAILABLE_OPCODE_CHECKER)
#define GET_COMPUTE_FEATURES
#endif
#ifdef GET_COMPUTE_FEATURES
#undef GET_COMPUTE_FEATURES
namespace llvm {
namespace BPF_MC {
enum SubtargetFeatureBits : uint8_t {
};
inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
FeatureBitset Features;
return Features;
}
inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
enum : uint8_t {
CEFBS_None,
};
static constexpr FeatureBitset FeatureBitsets[] = {
{},
};
static constexpr uint8_t RequiredFeaturesRefs[] = {
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
};
assert(Opcode < 492);
return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
}
}
}
#endif
#ifdef GET_AVAILABLE_OPCODE_CHECKER
#undef GET_AVAILABLE_OPCODE_CHECKER
namespace llvm {
namespace BPF_MC {
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
FeatureBitset MissingFeatures =
(AvailableFeatures & RequiredFeatures) ^
RequiredFeatures;
return !MissingFeatures.any();
}
}
}
#endif
#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
#undef ENABLE_INSTR_PREDICATE_VERIFIER
#include <sstream>
namespace llvm {
namespace BPF_MC {
#ifndef NDEBUG
static const char *SubtargetFeatureNames[] = {
nullptr
};
#endif
void verifyInstructionPredicates(
unsigned Opcode, const FeatureBitset &Features) {
#ifndef NDEBUG
FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
FeatureBitset MissingFeatures =
(AvailableFeatures & RequiredFeatures) ^
RequiredFeatures;
if (MissingFeatures.any()) {
std::ostringstream Msg;
Msg << "Attempting to emit " << &BPFInstrNameData[BPFInstrNameIndices[Opcode]]
<< " instruction but the ";
for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
if (MissingFeatures.test(i))
Msg << SubtargetFeatureNames[i] << " ";
Msg << "predicate(s) are not met";
report_fatal_error(Msg.str().c_str());
}
#endif
}
}
}
#endif