llvm/lib/Target/Lanai/LanaiGenInstrInfo.inc

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Instruction Enum Values and Descriptors                             *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
namespace llvm {

namespace Lanai {
  enum { … };

} // end namespace Lanai
} // end namespace llvm
#endif // GET_INSTRINFO_ENUM

#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM
namespace llvm {

namespace Lanai {
namespace Sched {
  enum {
    NoInstrModel	= 0,
    IIC_ALU_WriteALU	= 1,
    IIC_ALU	= 2,
    IIC_LD_WriteLD	= 3,
    IIC_LDSW_WriteLDSW	= 4,
    WriteLD	= 5,
    IIC_ST_WriteST	= 6,
    IIC_STSW_WriteSTSW	= 7,
    SCHED_LIST_END = 8
  };
} // end namespace Sched
} // end namespace Lanai
} // end namespace llvm
#endif // GET_INSTRINFO_SCHED_ENUM

#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
namespace llvm {

struct LanaiInstrTable {
  MCInstrDesc Insts[400];
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
  MCOperandInfo OperandInfo[178];
  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
  MCPhysReg ImplicitOps[8];
};

} // end namespace llvm
#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)

#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC
namespace llvm {

static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
static constexpr unsigned LanaiImpOpBase = sizeof LanaiInstrTable::OperandInfo / (sizeof(MCPhysReg));

extern const LanaiInstrTable LanaiDescs = {
  {
    { 399,	4,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #399 = XOR_R
    { 398,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #398 = XOR_I_LO
    { 397,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #397 = XOR_I_HI
    { 396,	4,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #396 = XOR_F_R
    { 395,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #395 = XOR_F_I_LO
    { 394,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #394 = XOR_F_I_HI
    { 393,	2,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	152,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #393 = TRAILZ
    { 392,	4,	0,	4,	6,	0,	0,	LanaiImpOpBase + 0,	170,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #392 = SW_RR
    { 391,	4,	0,	4,	6,	0,	0,	LanaiImpOpBase + 0,	166,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #391 = SW_RI
    { 390,	4,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #390 = SUB_R
    { 389,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #389 = SUB_I_LO
    { 388,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #388 = SUB_I_HI
    { 387,	4,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #387 = SUB_F_R
    { 386,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #386 = SUB_F_I_LO
    { 385,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #385 = SUB_F_I_HI
    { 384,	4,	1,	4,	1,	1,	0,	LanaiImpOpBase + 6,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #384 = SUBB_R
    { 383,	3,	1,	4,	1,	1,	0,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #383 = SUBB_I_LO
    { 382,	3,	1,	4,	1,	1,	0,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #382 = SUBB_I_HI
    { 381,	4,	1,	4,	1,	1,	1,	LanaiImpOpBase + 4,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #381 = SUBB_F_R
    { 380,	3,	1,	4,	1,	1,	1,	LanaiImpOpBase + 4,	155,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #380 = SUBB_F_I_LO
    { 379,	3,	1,	4,	1,	1,	1,	LanaiImpOpBase + 4,	155,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #379 = SUBB_F_I_HI
    { 378,	4,	0,	4,	6,	0,	0,	LanaiImpOpBase + 0,	170,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #378 = STH_RR
    { 377,	4,	0,	4,	7,	0,	0,	LanaiImpOpBase + 0,	166,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #377 = STH_RI
    { 376,	4,	0,	4,	6,	0,	0,	LanaiImpOpBase + 0,	170,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #376 = STB_RR
    { 375,	4,	0,	4,	7,	0,	0,	LanaiImpOpBase + 0,	166,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #375 = STB_RI
    { 374,	2,	0,	4,	6,	0,	0,	LanaiImpOpBase + 0,	162,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #374 = STADDR
    { 373,	4,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #373 = SRL_R
    { 372,	4,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #372 = SRL_F_R
    { 371,	4,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #371 = SRA_R
    { 370,	4,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #370 = SRA_F_R
    { 369,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #369 = SL_I
    { 368,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #368 = SL_F_I
    { 367,	2,	1,	4,	0,	0,	0,	LanaiImpOpBase + 0,	162,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #367 = SLI
    { 366,	4,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #366 = SHL_R
    { 365,	4,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #365 = SHL_F_R
    { 364,	2,	0,	4,	1,	0,	1,	LanaiImpOpBase + 6,	152,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #364 = SFSUB_F_RR
    { 363,	2,	0,	4,	1,	0,	1,	LanaiImpOpBase + 6,	162,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #363 = SFSUB_F_RI_LO
    { 362,	2,	0,	4,	1,	0,	1,	LanaiImpOpBase + 6,	162,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #362 = SFSUB_F_RI_HI
    { 361,	4,	1,	4,	1,	1,	0,	LanaiImpOpBase + 6,	174,	0|(1ULL<<MCID::Select)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #361 = SELECT
    { 360,	2,	1,	4,	2,	1,	0,	LanaiImpOpBase + 6,	162,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #360 = SCC
    { 359,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #359 = SA_I
    { 358,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #358 = SA_F_I
    { 357,	0,	0,	4,	0,	1,	0,	LanaiImpOpBase + 7,	1,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #357 = RET
    { 356,	2,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	152,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #356 = POPC
    { 355,	4,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #355 = OR_R
    { 354,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #354 = OR_I_LO
    { 353,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #353 = OR_I_HI
    { 352,	4,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #352 = OR_F_R
    { 351,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #351 = OR_F_I_LO
    { 350,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #350 = OR_F_I_HI
    { 349,	0,	0,	4,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #349 = NOP
    { 348,	2,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	162,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #348 = MOVHI
    { 347,	0,	0,	4,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #347 = LOG4
    { 346,	0,	0,	4,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #346 = LOG3
    { 345,	0,	0,	4,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #345 = LOG2
    { 344,	0,	0,	4,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #344 = LOG1
    { 343,	0,	0,	4,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #343 = LOG0
    { 342,	2,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	152,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #342 = LEADZ
    { 341,	4,	1,	4,	5,	0,	0,	LanaiImpOpBase + 0,	170,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #341 = LDWz_RR
    { 340,	4,	1,	4,	5,	0,	0,	LanaiImpOpBase + 0,	170,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #340 = LDW_RR
    { 339,	4,	1,	4,	3,	0,	0,	LanaiImpOpBase + 0,	166,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #339 = LDW_RI
    { 338,	4,	1,	4,	5,	0,	0,	LanaiImpOpBase + 0,	170,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #338 = LDHz_RR
    { 337,	4,	1,	4,	4,	0,	0,	LanaiImpOpBase + 0,	166,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #337 = LDHz_RI
    { 336,	4,	1,	4,	5,	0,	0,	LanaiImpOpBase + 0,	170,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #336 = LDHs_RR
    { 335,	4,	1,	4,	4,	0,	0,	LanaiImpOpBase + 0,	166,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #335 = LDHs_RI
    { 334,	4,	1,	4,	5,	0,	0,	LanaiImpOpBase + 0,	170,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #334 = LDBz_RR
    { 333,	4,	1,	4,	4,	0,	0,	LanaiImpOpBase + 0,	166,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #333 = LDBz_RI
    { 332,	4,	1,	4,	5,	0,	0,	LanaiImpOpBase + 0,	170,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #332 = LDBs_RR
    { 331,	4,	1,	4,	4,	0,	0,	LanaiImpOpBase + 0,	166,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #331 = LDBs_RI
    { 330,	2,	1,	4,	3,	0,	0,	LanaiImpOpBase + 0,	162,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #330 = LDADDR
    { 329,	1,	0,	4,	1,	0,	0,	LanaiImpOpBase + 0,	154,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #329 = JR
    { 328,	1,	0,	4,	2,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #328 = BT
    { 327,	2,	0,	4,	0,	1,	0,	LanaiImpOpBase + 6,	164,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #327 = BRR
    { 326,	3,	0,	4,	1,	1,	0,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #326 = BRIND_CCA
    { 325,	2,	0,	4,	1,	1,	0,	LanaiImpOpBase + 6,	162,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #325 = BRIND_CC
    { 324,	2,	0,	4,	2,	1,	0,	LanaiImpOpBase + 6,	13,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #324 = BRCC
    { 323,	4,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #323 = AND_R
    { 322,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #322 = AND_I_LO
    { 321,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #321 = AND_I_HI
    { 320,	4,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #320 = AND_F_R
    { 319,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #319 = AND_F_I_LO
    { 318,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #318 = AND_F_I_HI
    { 317,	4,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #317 = ADD_R
    { 316,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #316 = ADD_I_LO
    { 315,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #315 = ADD_I_HI
    { 314,	4,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #314 = ADD_F_R
    { 313,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #313 = ADD_F_I_LO
    { 312,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #312 = ADD_F_I_HI
    { 311,	4,	1,	4,	1,	1,	0,	LanaiImpOpBase + 6,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #311 = ADDC_R
    { 310,	3,	1,	4,	1,	1,	0,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #310 = ADDC_I_LO
    { 309,	3,	1,	4,	1,	1,	0,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #309 = ADDC_I_HI
    { 308,	4,	1,	4,	1,	1,	1,	LanaiImpOpBase + 4,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #308 = ADDC_F_R
    { 307,	3,	1,	4,	1,	1,	1,	LanaiImpOpBase + 4,	155,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #307 = ADDC_F_I_LO
    { 306,	3,	1,	4,	1,	1,	1,	LanaiImpOpBase + 4,	155,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #306 = ADDC_F_I_HI
    { 305,	1,	0,	4,	0,	1,	1,	LanaiImpOpBase + 2,	154,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #305 = CALLR
    { 304,	1,	0,	4,	0,	1,	1,	LanaiImpOpBase + 2,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #304 = CALL
    { 303,	2,	1,	4,	0,	1,	1,	LanaiImpOpBase + 0,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #303 = ADJDYNALLOC
    { 302,	2,	0,	4,	0,	1,	1,	LanaiImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #302 = ADJCALLSTACKUP
    { 301,	2,	0,	4,	0,	1,	1,	LanaiImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #301 = ADJCALLSTACKDOWN
    { 300,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #300 = G_UBFX
    { 299,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #299 = G_SBFX
    { 298,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #298 = G_VECREDUCE_UMIN
    { 297,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #297 = G_VECREDUCE_UMAX
    { 296,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #296 = G_VECREDUCE_SMIN
    { 295,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #295 = G_VECREDUCE_SMAX
    { 294,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #294 = G_VECREDUCE_XOR
    { 293,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #293 = G_VECREDUCE_OR
    { 292,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #292 = G_VECREDUCE_AND
    { 291,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #291 = G_VECREDUCE_MUL
    { 290,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #290 = G_VECREDUCE_ADD
    { 289,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #289 = G_VECREDUCE_FMINIMUM
    { 288,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #288 = G_VECREDUCE_FMAXIMUM
    { 287,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #287 = G_VECREDUCE_FMIN
    { 286,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #286 = G_VECREDUCE_FMAX
    { 285,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #285 = G_VECREDUCE_FMUL
    { 284,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #284 = G_VECREDUCE_FADD
    { 283,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #283 = G_VECREDUCE_SEQ_FMUL
    { 282,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #282 = G_VECREDUCE_SEQ_FADD
    { 281,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #281 = G_UBSANTRAP
    { 280,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #280 = G_DEBUGTRAP
    { 279,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #279 = G_TRAP
    { 278,	3,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #278 = G_BZERO
    { 277,	4,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #277 = G_MEMSET
    { 276,	4,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #276 = G_MEMMOVE
    { 275,	3,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #275 = G_MEMCPY_INLINE
    { 274,	4,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #274 = G_MEMCPY
    { 273,	2,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	142,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #273 = G_WRITE_REGISTER
    { 272,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #272 = G_READ_REGISTER
    { 271,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #271 = G_STRICT_FLDEXP
    { 270,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #270 = G_STRICT_FSQRT
    { 269,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #269 = G_STRICT_FMA
    { 268,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #268 = G_STRICT_FREM
    { 267,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #267 = G_STRICT_FDIV
    { 266,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #266 = G_STRICT_FMUL
    { 265,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #265 = G_STRICT_FSUB
    { 264,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #264 = G_STRICT_FADD
    { 263,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #263 = G_STACKRESTORE
    { 262,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #262 = G_STACKSAVE
    { 261,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #261 = G_DYN_STACKALLOC
    { 260,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #260 = G_JUMP_TABLE
    { 259,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #259 = G_BLOCK_ADDR
    { 258,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #258 = G_ADDRSPACE_CAST
    { 257,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #257 = G_FNEARBYINT
    { 256,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #256 = G_FRINT
    { 255,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #255 = G_FFLOOR
    { 254,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #254 = G_FSQRT
    { 253,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #253 = G_FTANH
    { 252,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #252 = G_FSINH
    { 251,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #251 = G_FCOSH
    { 250,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #250 = G_FATAN
    { 249,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #249 = G_FASIN
    { 248,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #248 = G_FACOS
    { 247,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #247 = G_FTAN
    { 246,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #246 = G_FSIN
    { 245,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #245 = G_FCOS
    { 244,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #244 = G_FCEIL
    { 243,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #243 = G_BITREVERSE
    { 242,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #242 = G_BSWAP
    { 241,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #241 = G_CTPOP
    { 240,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #240 = G_CTLZ_ZERO_UNDEF
    { 239,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #239 = G_CTLZ
    { 238,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #238 = G_CTTZ_ZERO_UNDEF
    { 237,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #237 = G_CTTZ
    { 236,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	138,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #236 = G_VECTOR_COMPRESS
    { 235,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #235 = G_SPLAT_VECTOR
    { 234,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	134,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #234 = G_SHUFFLE_VECTOR
    { 233,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #233 = G_EXTRACT_VECTOR_ELT
    { 232,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	127,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #232 = G_INSERT_VECTOR_ELT
    { 231,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #231 = G_EXTRACT_SUBVECTOR
    { 230,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #230 = G_INSERT_SUBVECTOR
    { 229,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #229 = G_VSCALE
    { 228,	3,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	124,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #228 = G_BRJT
    { 227,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #227 = G_BR
    { 226,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #226 = G_LLROUND
    { 225,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #225 = G_LROUND
    { 224,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #224 = G_ABS
    { 223,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #223 = G_UMAX
    { 222,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #222 = G_UMIN
    { 221,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #221 = G_SMAX
    { 220,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #220 = G_SMIN
    { 219,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #219 = G_PTRMASK
    { 218,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #218 = G_PTR_ADD
    { 217,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #217 = G_RESET_FPMODE
    { 216,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #216 = G_SET_FPMODE
    { 215,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #215 = G_GET_FPMODE
    { 214,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #214 = G_RESET_FPENV
    { 213,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #213 = G_SET_FPENV
    { 212,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #212 = G_GET_FPENV
    { 211,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #211 = G_FMAXIMUM
    { 210,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #210 = G_FMINIMUM
    { 209,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #209 = G_FMAXNUM_IEEE
    { 208,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #208 = G_FMINNUM_IEEE
    { 207,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #207 = G_FMAXNUM
    { 206,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #206 = G_FMINNUM
    { 205,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #205 = G_FCANONICALIZE
    { 204,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #204 = G_IS_FPCLASS
    { 203,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #203 = G_FCOPYSIGN
    { 202,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #202 = G_FABS
    { 201,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #201 = G_FPTOUI_SAT
    { 200,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #200 = G_FPTOSI_SAT
    { 199,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #199 = G_UITOFP
    { 198,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #198 = G_SITOFP
    { 197,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #197 = G_FPTOUI
    { 196,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #196 = G_FPTOSI
    { 195,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #195 = G_FPTRUNC
    { 194,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #194 = G_FPEXT
    { 193,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #193 = G_FNEG
    { 192,	3,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #192 = G_FFREXP
    { 191,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #191 = G_FLDEXP
    { 190,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #190 = G_FLOG10
    { 189,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #189 = G_FLOG2
    { 188,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #188 = G_FLOG
    { 187,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #187 = G_FEXP10
    { 186,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #186 = G_FEXP2
    { 185,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #185 = G_FEXP
    { 184,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #184 = G_FPOWI
    { 183,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #183 = G_FPOW
    { 182,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #182 = G_FREM
    { 181,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #181 = G_FDIV
    { 180,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #180 = G_FMAD
    { 179,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #179 = G_FMA
    { 178,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #178 = G_FMUL
    { 177,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #177 = G_FSUB
    { 176,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #176 = G_FADD
    { 175,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #175 = G_UDIVFIXSAT
    { 174,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #174 = G_SDIVFIXSAT
    { 173,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #173 = G_UDIVFIX
    { 172,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #172 = G_SDIVFIX
    { 171,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #171 = G_UMULFIXSAT
    { 170,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #170 = G_SMULFIXSAT
    { 169,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #169 = G_UMULFIX
    { 168,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #168 = G_SMULFIX
    { 167,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #167 = G_SSHLSAT
    { 166,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #166 = G_USHLSAT
    { 165,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #165 = G_SSUBSAT
    { 164,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #164 = G_USUBSAT
    { 163,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #163 = G_SADDSAT
    { 162,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #162 = G_UADDSAT
    { 161,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #161 = G_SMULH
    { 160,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #160 = G_UMULH
    { 159,	4,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #159 = G_SMULO
    { 158,	4,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #158 = G_UMULO
    { 157,	5,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #157 = G_SSUBE
    { 156,	4,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #156 = G_SSUBO
    { 155,	5,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #155 = G_SADDE
    { 154,	4,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #154 = G_SADDO
    { 153,	5,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #153 = G_USUBE
    { 152,	4,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #152 = G_USUBO
    { 151,	5,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #151 = G_UADDE
    { 150,	4,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #150 = G_UADDO
    { 149,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #149 = G_SELECT
    { 148,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #148 = G_UCMP
    { 147,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #147 = G_SCMP
    { 146,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #146 = G_FCMP
    { 145,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #145 = G_ICMP
    { 144,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #144 = G_ROTL
    { 143,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #143 = G_ROTR
    { 142,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #142 = G_FSHR
    { 141,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #141 = G_FSHL
    { 140,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #140 = G_ASHR
    { 139,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #139 = G_LSHR
    { 138,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #138 = G_SHL
    { 137,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #137 = G_ZEXT
    { 136,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #136 = G_SEXT_INREG
    { 135,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #135 = G_SEXT
    { 134,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #134 = G_VAARG
    { 133,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #133 = G_VASTART
    { 132,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #132 = G_FCONSTANT
    { 131,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #131 = G_CONSTANT
    { 130,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #130 = G_TRUNC
    { 129,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #129 = G_ANYEXT
    { 128,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #128 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
    { 127,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #127 = G_INTRINSIC_CONVERGENT
    { 126,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #126 = G_INTRINSIC_W_SIDE_EFFECTS
    { 125,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #125 = G_INTRINSIC
    { 124,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #124 = G_INVOKE_REGION_START
    { 123,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #123 = G_BRINDIRECT
    { 122,	2,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #122 = G_BRCOND
    { 121,	4,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	94,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #121 = G_PREFETCH
    { 120,	2,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	21,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #120 = G_FENCE
    { 119,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #119 = G_ATOMICRMW_USUB_SAT
    { 118,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #118 = G_ATOMICRMW_USUB_COND
    { 117,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #117 = G_ATOMICRMW_UDEC_WRAP
    { 116,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #116 = G_ATOMICRMW_UINC_WRAP
    { 115,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #115 = G_ATOMICRMW_FMIN
    { 114,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #114 = G_ATOMICRMW_FMAX
    { 113,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #113 = G_ATOMICRMW_FSUB
    { 112,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #112 = G_ATOMICRMW_FADD
    { 111,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #111 = G_ATOMICRMW_UMIN
    { 110,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #110 = G_ATOMICRMW_UMAX
    { 109,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #109 = G_ATOMICRMW_MIN
    { 108,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #108 = G_ATOMICRMW_MAX
    { 107,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #107 = G_ATOMICRMW_XOR
    { 106,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #106 = G_ATOMICRMW_OR
    { 105,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #105 = G_ATOMICRMW_NAND
    { 104,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #104 = G_ATOMICRMW_AND
    { 103,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #103 = G_ATOMICRMW_SUB
    { 102,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #102 = G_ATOMICRMW_ADD
    { 101,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #101 = G_ATOMICRMW_XCHG
    { 100,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #100 = G_ATOMIC_CMPXCHG
    { 99,	5,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	82,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #99 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
    { 98,	5,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	77,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #98 = G_INDEXED_STORE
    { 97,	2,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #97 = G_STORE
    { 96,	5,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #96 = G_INDEXED_ZEXTLOAD
    { 95,	5,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #95 = G_INDEXED_SEXTLOAD
    { 94,	5,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #94 = G_INDEXED_LOAD
    { 93,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #93 = G_ZEXTLOAD
    { 92,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #92 = G_SEXTLOAD
    { 91,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #91 = G_LOAD
    { 90,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #90 = G_READSTEADYCOUNTER
    { 89,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #89 = G_READCYCLECOUNTER
    { 88,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #88 = G_INTRINSIC_ROUNDEVEN
    { 87,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #87 = G_INTRINSIC_LLRINT
    { 86,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #86 = G_INTRINSIC_LRINT
    { 85,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #85 = G_INTRINSIC_ROUND
    { 84,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #84 = G_INTRINSIC_TRUNC
    { 83,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #83 = G_INTRINSIC_FPTRUNC_ROUND
    { 82,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #82 = G_CONSTANT_FOLD_BARRIER
    { 81,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #81 = G_FREEZE
    { 80,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #80 = G_BITCAST
    { 79,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #79 = G_INTTOPTR
    { 78,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #78 = G_PTRTOINT
    { 77,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #77 = G_CONCAT_VECTORS
    { 76,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #76 = G_BUILD_VECTOR_TRUNC
    { 75,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #75 = G_BUILD_VECTOR
    { 74,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #74 = G_MERGE_VALUES
    { 73,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #73 = G_INSERT
    { 72,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #72 = G_UNMERGE_VALUES
    { 71,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #71 = G_EXTRACT
    { 70,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #70 = G_CONSTANT_POOL
    { 69,	5,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	53,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #69 = G_PTRAUTH_GLOBAL_VALUE
    { 68,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #68 = G_GLOBAL_VALUE
    { 67,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #67 = G_FRAME_INDEX
    { 66,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #66 = G_PHI
    { 65,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #65 = G_IMPLICIT_DEF
    { 64,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #64 = G_XOR
    { 63,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #63 = G_OR
    { 62,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #62 = G_AND
    { 61,	4,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #61 = G_UDIVREM
    { 60,	4,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #60 = G_SDIVREM
    { 59,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #59 = G_UREM
    { 58,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #58 = G_SREM
    { 57,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #57 = G_UDIV
    { 56,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #56 = G_SDIV
    { 55,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #55 = G_MUL
    { 54,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #54 = G_SUB
    { 53,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #53 = G_ADD
    { 52,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #52 = G_ASSERT_ALIGN
    { 51,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #51 = G_ASSERT_ZEXT
    { 50,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #50 = G_ASSERT_SEXT
    { 49,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #49 = CONVERGENCECTRL_GLUE
    { 48,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #48 = CONVERGENCECTRL_LOOP
    { 47,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #47 = CONVERGENCECTRL_ANCHOR
    { 46,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #46 = CONVERGENCECTRL_ENTRY
    { 45,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #45 = JUMP_TABLE_DEBUG_INFO
    { 44,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #44 = MEMBARRIER
    { 43,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #43 = FAKE_USE
    { 42,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #42 = ICALL_BRANCH_FUNNEL
    { 41,	3,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	37,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #41 = PATCHABLE_TYPED_EVENT_CALL
    { 40,	2,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	35,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #40 = PATCHABLE_EVENT_CALL
    { 39,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #39 = PATCHABLE_TAIL_CALL
    { 38,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #38 = PATCHABLE_FUNCTION_EXIT
    { 37,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #37 = PATCHABLE_RET
    { 36,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #36 = PATCHABLE_FUNCTION_ENTER
    { 35,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #35 = PATCHABLE_OP
    { 34,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #34 = FAULTING_OP
    { 33,	2,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	33,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #33 = LOCAL_ESCAPE
    { 32,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #32 = STATEPOINT
    { 31,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	30,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #31 = PREALLOCATED_ARG
    { 30,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #30 = PREALLOCATED_SETUP
    { 29,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	29,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #29 = LOAD_STACK_GUARD
    { 28,	6,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	23,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #28 = PATCHPOINT
    { 27,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #27 = FENTRY_CALL
    { 26,	2,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #26 = STACKMAP
    { 25,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	19,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #25 = ARITH_FENCE
    { 24,	4,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	15,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #24 = PSEUDO_PROBE
    { 23,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #23 = LIFETIME_END
    { 22,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #22 = LIFETIME_START
    { 21,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #21 = BUNDLE
    { 20,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #20 = COPY
    { 19,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #19 = REG_SEQUENCE
    { 18,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #18 = DBG_LABEL
    { 17,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #17 = DBG_PHI
    { 16,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #16 = DBG_INSTR_REF
    { 15,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #15 = DBG_VALUE_LIST
    { 14,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #14 = DBG_VALUE
    { 13,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #13 = COPY_TO_REGCLASS
    { 12,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #12 = SUBREG_TO_REG
    { 11,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #11 = INIT_UNDEF
    { 10,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #10 = IMPLICIT_DEF
    { 9,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	5,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #9 = INSERT_SUBREG
    { 8,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #8 = EXTRACT_SUBREG
    { 7,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #7 = KILL
    { 6,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #6 = ANNOTATION_LABEL
    { 5,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #5 = GC_LABEL
    { 4,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #4 = EH_LABEL
    { 3,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #3 = CFI_INSTRUCTION
    { 2,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #2 = INLINEASM_BR
    { 1,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1 = INLINEASM
    { 0,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #0 = PHI
  }, {
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 1 */
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
    /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
    /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 152 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 154 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 155 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 158 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 },
    /* 162 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 164 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 166 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 170 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 174 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
  }, {
    /* 0 */
    /* 0 */ Lanai::SP, Lanai::SP,
    /* 2 */ Lanai::SP, Lanai::RCA,
    /* 4 */ Lanai::SR, Lanai::SR,
    /* 6 */ Lanai::SR,
    /* 7 */ Lanai::RCA,
  }
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char LanaiInstrNameData[] = {
  /* 0 */ "G_FLOG10\0"
  /* 9 */ "G_FEXP10\0"
  /* 18 */ "LOG0\0"
  /* 23 */ "LOG1\0"
  /* 28 */ "G_FLOG2\0"
  /* 36 */ "G_FEXP2\0"
  /* 44 */ "LOG3\0"
  /* 49 */ "LOG4\0"
  /* 54 */ "BRIND_CCA\0"
  /* 64 */ "G_FMA\0"
  /* 70 */ "G_STRICT_FMA\0"
  /* 83 */ "G_FSUB\0"
  /* 90 */ "G_STRICT_FSUB\0"
  /* 104 */ "G_ATOMICRMW_FSUB\0"
  /* 121 */ "G_SUB\0"
  /* 127 */ "G_ATOMICRMW_SUB\0"
  /* 143 */ "BRCC\0"
  /* 148 */ "SCC\0"
  /* 152 */ "BRIND_CC\0"
  /* 161 */ "G_INTRINSIC\0"
  /* 173 */ "G_FPTRUNC\0"
  /* 183 */ "G_INTRINSIC_TRUNC\0"
  /* 201 */ "G_TRUNC\0"
  /* 209 */ "G_BUILD_VECTOR_TRUNC\0"
  /* 230 */ "G_DYN_STACKALLOC\0"
  /* 247 */ "ADJDYNALLOC\0"
  /* 259 */ "POPC\0"
  /* 264 */ "G_FMAD\0"
  /* 271 */ "G_INDEXED_SEXTLOAD\0"
  /* 290 */ "G_SEXTLOAD\0"
  /* 301 */ "G_INDEXED_ZEXTLOAD\0"
  /* 320 */ "G_ZEXTLOAD\0"
  /* 331 */ "G_INDEXED_LOAD\0"
  /* 346 */ "G_LOAD\0"
  /* 353 */ "G_VECREDUCE_FADD\0"
  /* 370 */ "G_FADD\0"
  /* 377 */ "G_VECREDUCE_SEQ_FADD\0"
  /* 398 */ "G_STRICT_FADD\0"
  /* 412 */ "G_ATOMICRMW_FADD\0"
  /* 429 */ "G_VECREDUCE_ADD\0"
  /* 445 */ "G_ADD\0"
  /* 451 */ "G_PTR_ADD\0"
  /* 461 */ "G_ATOMICRMW_ADD\0"
  /* 477 */ "G_ATOMICRMW_NAND\0"
  /* 494 */ "G_VECREDUCE_AND\0"
  /* 510 */ "G_AND\0"
  /* 516 */ "G_ATOMICRMW_AND\0"
  /* 532 */ "LIFETIME_END\0"
  /* 545 */ "G_BRCOND\0"
  /* 554 */ "G_ATOMICRMW_USUB_COND\0"
  /* 576 */ "G_LLROUND\0"
  /* 586 */ "G_LROUND\0"
  /* 595 */ "G_INTRINSIC_ROUND\0"
  /* 613 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
  /* 639 */ "LOAD_STACK_GUARD\0"
  /* 656 */ "PSEUDO_PROBE\0"
  /* 669 */ "G_SSUBE\0"
  /* 677 */ "G_USUBE\0"
  /* 685 */ "G_FENCE\0"
  /* 693 */ "ARITH_FENCE\0"
  /* 705 */ "REG_SEQUENCE\0"
  /* 718 */ "G_SADDE\0"
  /* 726 */ "G_UADDE\0"
  /* 734 */ "G_GET_FPMODE\0"
  /* 747 */ "G_RESET_FPMODE\0"
  /* 762 */ "G_SET_FPMODE\0"
  /* 775 */ "G_FMINNUM_IEEE\0"
  /* 790 */ "G_FMAXNUM_IEEE\0"
  /* 805 */ "G_VSCALE\0"
  /* 814 */ "G_JUMP_TABLE\0"
  /* 827 */ "BUNDLE\0"
  /* 834 */ "G_MEMCPY_INLINE\0"
  /* 850 */ "LOCAL_ESCAPE\0"
  /* 863 */ "G_STACKRESTORE\0"
  /* 878 */ "G_INDEXED_STORE\0"
  /* 894 */ "G_STORE\0"
  /* 902 */ "G_BITREVERSE\0"
  /* 915 */ "FAKE_USE\0"
  /* 924 */ "DBG_VALUE\0"
  /* 934 */ "G_GLOBAL_VALUE\0"
  /* 949 */ "G_PTRAUTH_GLOBAL_VALUE\0"
  /* 972 */ "CONVERGENCECTRL_GLUE\0"
  /* 993 */ "G_STACKSAVE\0"
  /* 1005 */ "G_MEMMOVE\0"
  /* 1015 */ "G_FREEZE\0"
  /* 1024 */ "G_FCANONICALIZE\0"
  /* 1040 */ "G_CTLZ_ZERO_UNDEF\0"
  /* 1058 */ "G_CTTZ_ZERO_UNDEF\0"
  /* 1076 */ "INIT_UNDEF\0"
  /* 1087 */ "G_IMPLICIT_DEF\0"
  /* 1102 */ "DBG_INSTR_REF\0"
  /* 1116 */ "G_FNEG\0"
  /* 1123 */ "EXTRACT_SUBREG\0"
  /* 1138 */ "INSERT_SUBREG\0"
  /* 1152 */ "G_SEXT_INREG\0"
  /* 1165 */ "SUBREG_TO_REG\0"
  /* 1179 */ "G_ATOMIC_CMPXCHG\0"
  /* 1196 */ "G_ATOMICRMW_XCHG\0"
  /* 1213 */ "G_FLOG\0"
  /* 1220 */ "G_VAARG\0"
  /* 1228 */ "PREALLOCATED_ARG\0"
  /* 1245 */ "G_PREFETCH\0"
  /* 1256 */ "G_SMULH\0"
  /* 1264 */ "G_UMULH\0"
  /* 1272 */ "G_FTANH\0"
  /* 1280 */ "G_FSINH\0"
  /* 1288 */ "G_FCOSH\0"
  /* 1296 */ "DBG_PHI\0"
  /* 1304 */ "MOVHI\0"
  /* 1310 */ "SFSUB_F_RI_HI\0"
  /* 1324 */ "SUBB_I_HI\0"
  /* 1334 */ "SUB_I_HI\0"
  /* 1343 */ "ADDC_I_HI\0"
  /* 1353 */ "ADD_I_HI\0"
  /* 1362 */ "AND_I_HI\0"
  /* 1371 */ "SUBB_F_I_HI\0"
  /* 1383 */ "SUB_F_I_HI\0"
  /* 1394 */ "ADDC_F_I_HI\0"
  /* 1406 */ "ADD_F_I_HI\0"
  /* 1417 */ "AND_F_I_HI\0"
  /* 1428 */ "XOR_F_I_HI\0"
  /* 1439 */ "XOR_I_HI\0"
  /* 1448 */ "SLI\0"
  /* 1452 */ "STB_RI\0"
  /* 1459 */ "STH_RI\0"
  /* 1466 */ "LDW_RI\0"
  /* 1473 */ "SW_RI\0"
  /* 1479 */ "LDBs_RI\0"
  /* 1487 */ "LDHs_RI\0"
  /* 1495 */ "LDBz_RI\0"
  /* 1503 */ "LDHz_RI\0"
  /* 1511 */ "G_FPTOSI\0"
  /* 1520 */ "G_FPTOUI\0"
  /* 1529 */ "G_FPOWI\0"
  /* 1537 */ "SA_I\0"
  /* 1542 */ "SA_F_I\0"
  /* 1549 */ "SL_F_I\0"
  /* 1556 */ "SL_I\0"
  /* 1561 */ "G_PTRMASK\0"
  /* 1571 */ "GC_LABEL\0"
  /* 1580 */ "DBG_LABEL\0"
  /* 1590 */ "EH_LABEL\0"
  /* 1599 */ "ANNOTATION_LABEL\0"
  /* 1616 */ "ICALL_BRANCH_FUNNEL\0"
  /* 1636 */ "G_FSHL\0"
  /* 1643 */ "G_SHL\0"
  /* 1649 */ "G_FCEIL\0"
  /* 1657 */ "PATCHABLE_TAIL_CALL\0"
  /* 1677 */ "PATCHABLE_TYPED_EVENT_CALL\0"
  /* 1704 */ "PATCHABLE_EVENT_CALL\0"
  /* 1725 */ "FENTRY_CALL\0"
  /* 1737 */ "KILL\0"
  /* 1742 */ "G_CONSTANT_POOL\0"
  /* 1758 */ "G_ROTL\0"
  /* 1765 */ "G_VECREDUCE_FMUL\0"
  /* 1782 */ "G_FMUL\0"
  /* 1789 */ "G_VECREDUCE_SEQ_FMUL\0"
  /* 1810 */ "G_STRICT_FMUL\0"
  /* 1824 */ "G_VECREDUCE_MUL\0"
  /* 1840 */ "G_MUL\0"
  /* 1846 */ "G_FREM\0"
  /* 1853 */ "G_STRICT_FREM\0"
  /* 1867 */ "G_SREM\0"
  /* 1874 */ "G_UREM\0"
  /* 1881 */ "G_SDIVREM\0"
  /* 1891 */ "G_UDIVREM\0"
  /* 1901 */ "INLINEASM\0"
  /* 1911 */ "G_VECREDUCE_FMINIMUM\0"
  /* 1932 */ "G_FMINIMUM\0"
  /* 1943 */ "G_VECREDUCE_FMAXIMUM\0"
  /* 1964 */ "G_FMAXIMUM\0"
  /* 1975 */ "G_FMINNUM\0"
  /* 1985 */ "G_FMAXNUM\0"
  /* 1995 */ "G_FATAN\0"
  /* 2003 */ "G_FTAN\0"
  /* 2010 */ "G_INTRINSIC_ROUNDEVEN\0"
  /* 2032 */ "G_ASSERT_ALIGN\0"
  /* 2047 */ "G_FCOPYSIGN\0"
  /* 2059 */ "G_VECREDUCE_FMIN\0"
  /* 2076 */ "G_ATOMICRMW_FMIN\0"
  /* 2093 */ "G_VECREDUCE_SMIN\0"
  /* 2110 */ "G_SMIN\0"
  /* 2117 */ "G_VECREDUCE_UMIN\0"
  /* 2134 */ "G_UMIN\0"
  /* 2141 */ "G_ATOMICRMW_UMIN\0"
  /* 2158 */ "G_ATOMICRMW_MIN\0"
  /* 2174 */ "G_FASIN\0"
  /* 2182 */ "G_FSIN\0"
  /* 2189 */ "CFI_INSTRUCTION\0"
  /* 2205 */ "ADJCALLSTACKDOWN\0"
  /* 2222 */ "G_SSUBO\0"
  /* 2230 */ "G_USUBO\0"
  /* 2238 */ "G_SADDO\0"
  /* 2246 */ "G_UADDO\0"
  /* 2254 */ "JUMP_TABLE_DEBUG_INFO\0"
  /* 2276 */ "G_SMULO\0"
  /* 2284 */ "G_UMULO\0"
  /* 2292 */ "SFSUB_F_RI_LO\0"
  /* 2306 */ "SUBB_I_LO\0"
  /* 2316 */ "SUB_I_LO\0"
  /* 2325 */ "ADDC_I_LO\0"
  /* 2335 */ "ADD_I_LO\0"
  /* 2344 */ "AND_I_LO\0"
  /* 2353 */ "SUBB_F_I_LO\0"
  /* 2365 */ "SUB_F_I_LO\0"
  /* 2376 */ "ADDC_F_I_LO\0"
  /* 2388 */ "ADD_F_I_LO\0"
  /* 2399 */ "AND_F_I_LO\0"
  /* 2410 */ "XOR_F_I_LO\0"
  /* 2421 */ "XOR_I_LO\0"
  /* 2430 */ "G_BZERO\0"
  /* 2438 */ "STACKMAP\0"
  /* 2447 */ "G_DEBUGTRAP\0"
  /* 2459 */ "G_UBSANTRAP\0"
  /* 2471 */ "G_TRAP\0"
  /* 2478 */ "G_ATOMICRMW_UDEC_WRAP\0"
  /* 2500 */ "G_ATOMICRMW_UINC_WRAP\0"
  /* 2522 */ "G_BSWAP\0"
  /* 2530 */ "G_SITOFP\0"
  /* 2539 */ "G_UITOFP\0"
  /* 2548 */ "G_FCMP\0"
  /* 2555 */ "G_ICMP\0"
  /* 2562 */ "G_SCMP\0"
  /* 2569 */ "G_UCMP\0"
  /* 2576 */ "NOP\0"
  /* 2580 */ "CONVERGENCECTRL_LOOP\0"
  /* 2601 */ "G_CTPOP\0"
  /* 2609 */ "PATCHABLE_OP\0"
  /* 2622 */ "FAULTING_OP\0"
  /* 2634 */ "ADJCALLSTACKUP\0"
  /* 2649 */ "PREALLOCATED_SETUP\0"
  /* 2668 */ "G_FLDEXP\0"
  /* 2677 */ "G_STRICT_FLDEXP\0"
  /* 2693 */ "G_FEXP\0"
  /* 2700 */ "G_FFREXP\0"
  /* 2709 */ "G_BR\0"
  /* 2714 */ "INLINEASM_BR\0"
  /* 2727 */ "LDADDR\0"
  /* 2734 */ "STADDR\0"
  /* 2741 */ "G_BLOCK_ADDR\0"
  /* 2754 */ "MEMBARRIER\0"
  /* 2765 */ "G_CONSTANT_FOLD_BARRIER\0"
  /* 2789 */ "PATCHABLE_FUNCTION_ENTER\0"
  /* 2814 */ "G_READCYCLECOUNTER\0"
  /* 2833 */ "G_READSTEADYCOUNTER\0"
  /* 2853 */ "G_READ_REGISTER\0"
  /* 2869 */ "G_WRITE_REGISTER\0"
  /* 2886 */ "G_ASHR\0"
  /* 2893 */ "G_FSHR\0"
  /* 2900 */ "G_LSHR\0"
  /* 2907 */ "JR\0"
  /* 2910 */ "CALLR\0"
  /* 2916 */ "CONVERGENCECTRL_ANCHOR\0"
  /* 2939 */ "G_FFLOOR\0"
  /* 2948 */ "G_EXTRACT_SUBVECTOR\0"
  /* 2968 */ "G_INSERT_SUBVECTOR\0"
  /* 2987 */ "G_BUILD_VECTOR\0"
  /* 3002 */ "G_SHUFFLE_VECTOR\0"
  /* 3019 */ "G_SPLAT_VECTOR\0"
  /* 3034 */ "G_VECREDUCE_XOR\0"
  /* 3050 */ "G_XOR\0"
  /* 3056 */ "G_ATOMICRMW_XOR\0"
  /* 3072 */ "G_VECREDUCE_OR\0"
  /* 3087 */ "G_OR\0"
  /* 3092 */ "G_ATOMICRMW_OR\0"
  /* 3107 */ "BRR\0"
  /* 3111 */ "STB_RR\0"
  /* 3118 */ "SFSUB_F_RR\0"
  /* 3129 */ "STH_RR\0"
  /* 3136 */ "LDW_RR\0"
  /* 3143 */ "SW_RR\0"
  /* 3149 */ "LDBs_RR\0"
  /* 3157 */ "LDHs_RR\0"
  /* 3165 */ "LDBz_RR\0"
  /* 3173 */ "LDHz_RR\0"
  /* 3181 */ "LDWz_RR\0"
  /* 3189 */ "G_ROTR\0"
  /* 3196 */ "G_INTTOPTR\0"
  /* 3207 */ "SRA_R\0"
  /* 3213 */ "SUBB_R\0"
  /* 3220 */ "SUB_R\0"
  /* 3226 */ "ADDC_R\0"
  /* 3233 */ "ADD_R\0"
  /* 3239 */ "AND_R\0"
  /* 3245 */ "SRA_F_R\0"
  /* 3253 */ "SUBB_F_R\0"
  /* 3262 */ "SUB_F_R\0"
  /* 3270 */ "ADDC_F_R\0"
  /* 3279 */ "ADD_F_R\0"
  /* 3287 */ "AND_F_R\0"
  /* 3295 */ "SHL_F_R\0"
  /* 3303 */ "SRL_F_R\0"
  /* 3311 */ "XOR_F_R\0"
  /* 3319 */ "SHL_R\0"
  /* 3325 */ "SRL_R\0"
  /* 3331 */ "XOR_R\0"
  /* 3337 */ "G_FABS\0"
  /* 3344 */ "G_ABS\0"
  /* 3350 */ "G_UNMERGE_VALUES\0"
  /* 3367 */ "G_MERGE_VALUES\0"
  /* 3382 */ "G_FACOS\0"
  /* 3390 */ "G_FCOS\0"
  /* 3397 */ "G_CONCAT_VECTORS\0"
  /* 3414 */ "COPY_TO_REGCLASS\0"
  /* 3431 */ "G_IS_FPCLASS\0"
  /* 3444 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
  /* 3474 */ "G_VECTOR_COMPRESS\0"
  /* 3492 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
  /* 3519 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
  /* 3557 */ "G_SSUBSAT\0"
  /* 3567 */ "G_USUBSAT\0"
  /* 3577 */ "G_SADDSAT\0"
  /* 3587 */ "G_UADDSAT\0"
  /* 3597 */ "G_SSHLSAT\0"
  /* 3607 */ "G_USHLSAT\0"
  /* 3617 */ "G_SMULFIXSAT\0"
  /* 3630 */ "G_UMULFIXSAT\0"
  /* 3643 */ "G_SDIVFIXSAT\0"
  /* 3656 */ "G_UDIVFIXSAT\0"
  /* 3669 */ "G_ATOMICRMW_USUB_SAT\0"
  /* 3690 */ "G_FPTOSI_SAT\0"
  /* 3703 */ "G_FPTOUI_SAT\0"
  /* 3716 */ "BT\0"
  /* 3719 */ "G_EXTRACT\0"
  /* 3729 */ "G_SELECT\0"
  /* 3738 */ "G_BRINDIRECT\0"
  /* 3751 */ "PATCHABLE_RET\0"
  /* 3765 */ "G_MEMSET\0"
  /* 3774 */ "PATCHABLE_FUNCTION_EXIT\0"
  /* 3798 */ "G_BRJT\0"
  /* 3805 */ "G_EXTRACT_VECTOR_ELT\0"
  /* 3826 */ "G_INSERT_VECTOR_ELT\0"
  /* 3846 */ "G_FCONSTANT\0"
  /* 3858 */ "G_CONSTANT\0"
  /* 3869 */ "G_INTRINSIC_CONVERGENT\0"
  /* 3892 */ "STATEPOINT\0"
  /* 3903 */ "PATCHPOINT\0"
  /* 3914 */ "G_PTRTOINT\0"
  /* 3925 */ "G_FRINT\0"
  /* 3933 */ "G_INTRINSIC_LLRINT\0"
  /* 3952 */ "G_INTRINSIC_LRINT\0"
  /* 3970 */ "G_FNEARBYINT\0"
  /* 3983 */ "G_VASTART\0"
  /* 3993 */ "LIFETIME_START\0"
  /* 4008 */ "G_INVOKE_REGION_START\0"
  /* 4030 */ "G_INSERT\0"
  /* 4039 */ "G_FSQRT\0"
  /* 4047 */ "G_STRICT_FSQRT\0"
  /* 4062 */ "G_BITCAST\0"
  /* 4072 */ "G_ADDRSPACE_CAST\0"
  /* 4089 */ "DBG_VALUE_LIST\0"
  /* 4104 */ "G_FPEXT\0"
  /* 4112 */ "G_SEXT\0"
  /* 4119 */ "G_ASSERT_SEXT\0"
  /* 4133 */ "G_ANYEXT\0"
  /* 4142 */ "G_ZEXT\0"
  /* 4149 */ "G_ASSERT_ZEXT\0"
  /* 4163 */ "G_FDIV\0"
  /* 4170 */ "G_STRICT_FDIV\0"
  /* 4184 */ "G_SDIV\0"
  /* 4191 */ "G_UDIV\0"
  /* 4198 */ "G_GET_FPENV\0"
  /* 4210 */ "G_RESET_FPENV\0"
  /* 4224 */ "G_SET_FPENV\0"
  /* 4236 */ "G_FPOW\0"
  /* 4243 */ "G_VECREDUCE_FMAX\0"
  /* 4260 */ "G_ATOMICRMW_FMAX\0"
  /* 4277 */ "G_VECREDUCE_SMAX\0"
  /* 4294 */ "G_SMAX\0"
  /* 4301 */ "G_VECREDUCE_UMAX\0"
  /* 4318 */ "G_UMAX\0"
  /* 4325 */ "G_ATOMICRMW_UMAX\0"
  /* 4342 */ "G_ATOMICRMW_MAX\0"
  /* 4358 */ "G_FRAME_INDEX\0"
  /* 4372 */ "G_SBFX\0"
  /* 4379 */ "G_UBFX\0"
  /* 4386 */ "G_SMULFIX\0"
  /* 4396 */ "G_UMULFIX\0"
  /* 4406 */ "G_SDIVFIX\0"
  /* 4416 */ "G_UDIVFIX\0"
  /* 4426 */ "G_MEMCPY\0"
  /* 4435 */ "COPY\0"
  /* 4440 */ "CONVERGENCECTRL_ENTRY\0"
  /* 4462 */ "LEADZ\0"
  /* 4468 */ "TRAILZ\0"
  /* 4475 */ "G_CTLZ\0"
  /* 4482 */ "G_CTTZ\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const unsigned LanaiInstrNameIndices[] = {
    1300U, 1901U, 2714U, 2189U, 1590U, 1571U, 1599U, 1737U, 
    1123U, 1138U, 1089U, 1076U, 1165U, 3414U, 924U, 4089U, 
    1102U, 1296U, 1580U, 705U, 4435U, 827U, 3993U, 532U, 
    656U, 693U, 2438U, 1725U, 3903U, 639U, 2649U, 1228U, 
    3892U, 850U, 2622U, 2609U, 2789U, 3751U, 3774U, 1657U, 
    1704U, 1677U, 1616U, 915U, 2754U, 2254U, 4440U, 2916U, 
    2580U, 972U, 4119U, 4149U, 2032U, 445U, 121U, 1840U, 
    4184U, 4191U, 1867U, 1874U, 1881U, 1891U, 510U, 3087U, 
    3050U, 1087U, 1298U, 4358U, 934U, 949U, 1742U, 3719U, 
    3350U, 4030U, 3367U, 2987U, 209U, 3397U, 3914U, 3196U, 
    4062U, 1015U, 2765U, 613U, 183U, 595U, 3952U, 3933U, 
    2010U, 2814U, 2833U, 346U, 290U, 320U, 331U, 271U, 
    301U, 894U, 878U, 3444U, 1179U, 1196U, 461U, 127U, 
    516U, 477U, 3092U, 3056U, 4342U, 2158U, 4325U, 2141U, 
    412U, 104U, 4260U, 2076U, 2500U, 2478U, 554U, 3669U, 
    685U, 1245U, 545U, 3738U, 4008U, 161U, 3492U, 3869U, 
    3519U, 4133U, 201U, 3858U, 3846U, 3983U, 1220U, 4112U, 
    1152U, 4142U, 1643U, 2900U, 2886U, 1636U, 2893U, 3189U, 
    1758U, 2555U, 2548U, 2562U, 2569U, 3729U, 2246U, 726U, 
    2230U, 677U, 2238U, 718U, 2222U, 669U, 2284U, 2276U, 
    1264U, 1256U, 3587U, 3577U, 3567U, 3557U, 3607U, 3597U, 
    4386U, 4396U, 3617U, 3630U, 4406U, 4416U, 3643U, 3656U, 
    370U, 83U, 1782U, 64U, 264U, 4163U, 1846U, 4236U, 
    1529U, 2693U, 36U, 9U, 1213U, 28U, 0U, 2668U, 
    2700U, 1116U, 4104U, 173U, 1511U, 1520U, 2530U, 2539U, 
    3690U, 3703U, 3337U, 2047U, 3431U, 1024U, 1975U, 1985U, 
    775U, 790U, 1932U, 1964U, 4198U, 4224U, 4210U, 734U, 
    762U, 747U, 451U, 1561U, 2110U, 4294U, 2134U, 4318U, 
    3344U, 586U, 576U, 2709U, 3798U, 805U, 2968U, 2948U, 
    3826U, 3805U, 3002U, 3019U, 3474U, 4482U, 1058U, 4475U, 
    1040U, 2601U, 2522U, 902U, 1649U, 3390U, 2182U, 2003U, 
    3382U, 2174U, 1995U, 1288U, 1280U, 1272U, 4039U, 2939U, 
    3925U, 3970U, 4072U, 2741U, 814U, 230U, 993U, 863U, 
    398U, 90U, 1810U, 4170U, 1853U, 70U, 4047U, 2677U, 
    2853U, 2869U, 4426U, 834U, 1005U, 3765U, 2430U, 2471U, 
    2447U, 2459U, 377U, 1789U, 353U, 1765U, 4243U, 2059U, 
    1943U, 1911U, 429U, 1824U, 494U, 3072U, 3034U, 4277U, 
    2093U, 4301U, 2117U, 4372U, 4379U, 2205U, 2634U, 247U, 
    1672U, 2910U, 1394U, 2376U, 3270U, 1343U, 2325U, 3226U, 
    1406U, 2388U, 3279U, 1353U, 2335U, 3233U, 1417U, 2399U, 
    3287U, 1362U, 2344U, 3239U, 143U, 152U, 54U, 3107U, 
    3716U, 2907U, 2727U, 1479U, 3149U, 1495U, 3165U, 1487U, 
    3157U, 1503U, 3173U, 1466U, 3136U, 3181U, 4462U, 18U, 
    23U, 31U, 44U, 49U, 1304U, 2576U, 1429U, 2411U, 
    3312U, 1440U, 2422U, 3332U, 259U, 3761U, 1542U, 1537U, 
    148U, 3731U, 1310U, 2292U, 3118U, 3295U, 3319U, 1448U, 
    1549U, 1556U, 3245U, 3207U, 3303U, 3325U, 2734U, 1452U, 
    3111U, 1459U, 3129U, 1371U, 2353U, 3253U, 1324U, 2306U, 
    3213U, 1383U, 2365U, 3262U, 1334U, 2316U, 3220U, 1473U, 
    3143U, 4468U, 1428U, 2410U, 3311U, 1439U, 2421U, 3331U, 
};

static inline void InitLanaiMCInstrInfo(MCInstrInfo *II) {
  II->InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, 400);
}

} // end namespace llvm
#endif // GET_INSTRINFO_MC_DESC

#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER
namespace llvm {
struct LanaiGenInstrInfo : public TargetInstrInfo {
  explicit LanaiGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
  ~LanaiGenInstrInfo() override = default;

};
} // end namespace llvm
#endif // GET_INSTRINFO_HEADER

#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS


#endif // GET_INSTRINFO_HELPER_DECLS

#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS

#endif // GET_INSTRINFO_HELPERS

#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR
namespace llvm {
extern const LanaiInstrTable LanaiDescs;
extern const unsigned LanaiInstrNameIndices[];
extern const char LanaiInstrNameData[];
LanaiGenInstrInfo::LanaiGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
  InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, 400);
}
} // end namespace llvm
#endif // GET_INSTRINFO_CTOR_DTOR

#ifdef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_OPERAND_ENUM
namespace llvm {
namespace Lanai {
namespace OpName {
enum {
  OPERAND_LAST
};
} // end namespace OpName
} // end namespace Lanai
} // end namespace llvm
#endif //GET_INSTRINFO_OPERAND_ENUM

#ifdef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_NAMED_OPS
namespace llvm {
namespace Lanai {
LLVM_READONLY
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
  return -1;
}
} // end namespace Lanai
} // end namespace llvm
#endif //GET_INSTRINFO_NAMED_OPS

#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
namespace llvm {
namespace Lanai {
namespace OpTypes {
enum OperandType {
  AluOp = 0,
  BrTarget = 1,
  CCOp = 2,
  CallTarget = 3,
  MEMi = 4,
  MEMri = 5,
  MEMrr = 6,
  MEMspls = 7,
  f32imm = 8,
  f64imm = 9,
  i1imm = 10,
  i8imm = 11,
  i16imm = 12,
  i32hi16 = 13,
  i32hi16and = 14,
  i32imm = 15,
  i32lo16and = 16,
  i32lo16s = 17,
  i32lo16z = 18,
  i32lo21 = 19,
  i32neg16 = 20,
  i64imm = 21,
  imm10 = 22,
  immShift = 23,
  pred = 24,
  ptype0 = 25,
  ptype1 = 26,
  ptype2 = 27,
  ptype3 = 28,
  ptype4 = 29,
  ptype5 = 30,
  type0 = 31,
  type1 = 32,
  type2 = 33,
  type3 = 34,
  type4 = 35,
  type5 = 36,
  untyped_imm_0 = 37,
  CCR = 38,
  GPR = 39,
  OPERAND_TYPE_LIST_END
};
} // end namespace OpTypes
} // end namespace Lanai
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM

#ifdef GET_INSTRINFO_OPERAND_TYPE
#undef GET_INSTRINFO_OPERAND_TYPE
namespace llvm {
namespace Lanai {
LLVM_READONLY
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
  static const uint16_t Offsets[] = {
    /* PHI */
    0,
    /* INLINEASM */
    1,
    /* INLINEASM_BR */
    1,
    /* CFI_INSTRUCTION */
    1,
    /* EH_LABEL */
    2,
    /* GC_LABEL */
    3,
    /* ANNOTATION_LABEL */
    4,
    /* KILL */
    5,
    /* EXTRACT_SUBREG */
    5,
    /* INSERT_SUBREG */
    8,
    /* IMPLICIT_DEF */
    12,
    /* INIT_UNDEF */
    13,
    /* SUBREG_TO_REG */
    14,
    /* COPY_TO_REGCLASS */
    18,
    /* DBG_VALUE */
    21,
    /* DBG_VALUE_LIST */
    21,
    /* DBG_INSTR_REF */
    21,
    /* DBG_PHI */
    21,
    /* DBG_LABEL */
    21,
    /* REG_SEQUENCE */
    22,
    /* COPY */
    24,
    /* BUNDLE */
    26,
    /* LIFETIME_START */
    26,
    /* LIFETIME_END */
    27,
    /* PSEUDO_PROBE */
    28,
    /* ARITH_FENCE */
    32,
    /* STACKMAP */
    34,
    /* FENTRY_CALL */
    36,
    /* PATCHPOINT */
    36,
    /* LOAD_STACK_GUARD */
    42,
    /* PREALLOCATED_SETUP */
    43,
    /* PREALLOCATED_ARG */
    44,
    /* STATEPOINT */
    47,
    /* LOCAL_ESCAPE */
    47,
    /* FAULTING_OP */
    49,
    /* PATCHABLE_OP */
    50,
    /* PATCHABLE_FUNCTION_ENTER */
    50,
    /* PATCHABLE_RET */
    50,
    /* PATCHABLE_FUNCTION_EXIT */
    50,
    /* PATCHABLE_TAIL_CALL */
    50,
    /* PATCHABLE_EVENT_CALL */
    50,
    /* PATCHABLE_TYPED_EVENT_CALL */
    52,
    /* ICALL_BRANCH_FUNNEL */
    55,
    /* FAKE_USE */
    55,
    /* MEMBARRIER */
    55,
    /* JUMP_TABLE_DEBUG_INFO */
    55,
    /* CONVERGENCECTRL_ENTRY */
    56,
    /* CONVERGENCECTRL_ANCHOR */
    57,
    /* CONVERGENCECTRL_LOOP */
    58,
    /* CONVERGENCECTRL_GLUE */
    60,
    /* G_ASSERT_SEXT */
    61,
    /* G_ASSERT_ZEXT */
    64,
    /* G_ASSERT_ALIGN */
    67,
    /* G_ADD */
    70,
    /* G_SUB */
    73,
    /* G_MUL */
    76,
    /* G_SDIV */
    79,
    /* G_UDIV */
    82,
    /* G_SREM */
    85,
    /* G_UREM */
    88,
    /* G_SDIVREM */
    91,
    /* G_UDIVREM */
    95,
    /* G_AND */
    99,
    /* G_OR */
    102,
    /* G_XOR */
    105,
    /* G_IMPLICIT_DEF */
    108,
    /* G_PHI */
    109,
    /* G_FRAME_INDEX */
    110,
    /* G_GLOBAL_VALUE */
    112,
    /* G_PTRAUTH_GLOBAL_VALUE */
    114,
    /* G_CONSTANT_POOL */
    119,
    /* G_EXTRACT */
    121,
    /* G_UNMERGE_VALUES */
    124,
    /* G_INSERT */
    126,
    /* G_MERGE_VALUES */
    130,
    /* G_BUILD_VECTOR */
    132,
    /* G_BUILD_VECTOR_TRUNC */
    134,
    /* G_CONCAT_VECTORS */
    136,
    /* G_PTRTOINT */
    138,
    /* G_INTTOPTR */
    140,
    /* G_BITCAST */
    142,
    /* G_FREEZE */
    144,
    /* G_CONSTANT_FOLD_BARRIER */
    146,
    /* G_INTRINSIC_FPTRUNC_ROUND */
    148,
    /* G_INTRINSIC_TRUNC */
    151,
    /* G_INTRINSIC_ROUND */
    153,
    /* G_INTRINSIC_LRINT */
    155,
    /* G_INTRINSIC_LLRINT */
    157,
    /* G_INTRINSIC_ROUNDEVEN */
    159,
    /* G_READCYCLECOUNTER */
    161,
    /* G_READSTEADYCOUNTER */
    162,
    /* G_LOAD */
    163,
    /* G_SEXTLOAD */
    165,
    /* G_ZEXTLOAD */
    167,
    /* G_INDEXED_LOAD */
    169,
    /* G_INDEXED_SEXTLOAD */
    174,
    /* G_INDEXED_ZEXTLOAD */
    179,
    /* G_STORE */
    184,
    /* G_INDEXED_STORE */
    186,
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    191,
    /* G_ATOMIC_CMPXCHG */
    196,
    /* G_ATOMICRMW_XCHG */
    200,
    /* G_ATOMICRMW_ADD */
    203,
    /* G_ATOMICRMW_SUB */
    206,
    /* G_ATOMICRMW_AND */
    209,
    /* G_ATOMICRMW_NAND */
    212,
    /* G_ATOMICRMW_OR */
    215,
    /* G_ATOMICRMW_XOR */
    218,
    /* G_ATOMICRMW_MAX */
    221,
    /* G_ATOMICRMW_MIN */
    224,
    /* G_ATOMICRMW_UMAX */
    227,
    /* G_ATOMICRMW_UMIN */
    230,
    /* G_ATOMICRMW_FADD */
    233,
    /* G_ATOMICRMW_FSUB */
    236,
    /* G_ATOMICRMW_FMAX */
    239,
    /* G_ATOMICRMW_FMIN */
    242,
    /* G_ATOMICRMW_UINC_WRAP */
    245,
    /* G_ATOMICRMW_UDEC_WRAP */
    248,
    /* G_ATOMICRMW_USUB_COND */
    251,
    /* G_ATOMICRMW_USUB_SAT */
    254,
    /* G_FENCE */
    257,
    /* G_PREFETCH */
    259,
    /* G_BRCOND */
    263,
    /* G_BRINDIRECT */
    265,
    /* G_INVOKE_REGION_START */
    266,
    /* G_INTRINSIC */
    266,
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    267,
    /* G_INTRINSIC_CONVERGENT */
    268,
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    269,
    /* G_ANYEXT */
    270,
    /* G_TRUNC */
    272,
    /* G_CONSTANT */
    274,
    /* G_FCONSTANT */
    276,
    /* G_VASTART */
    278,
    /* G_VAARG */
    279,
    /* G_SEXT */
    282,
    /* G_SEXT_INREG */
    284,
    /* G_ZEXT */
    287,
    /* G_SHL */
    289,
    /* G_LSHR */
    292,
    /* G_ASHR */
    295,
    /* G_FSHL */
    298,
    /* G_FSHR */
    302,
    /* G_ROTR */
    306,
    /* G_ROTL */
    309,
    /* G_ICMP */
    312,
    /* G_FCMP */
    316,
    /* G_SCMP */
    320,
    /* G_UCMP */
    323,
    /* G_SELECT */
    326,
    /* G_UADDO */
    330,
    /* G_UADDE */
    334,
    /* G_USUBO */
    339,
    /* G_USUBE */
    343,
    /* G_SADDO */
    348,
    /* G_SADDE */
    352,
    /* G_SSUBO */
    357,
    /* G_SSUBE */
    361,
    /* G_UMULO */
    366,
    /* G_SMULO */
    370,
    /* G_UMULH */
    374,
    /* G_SMULH */
    377,
    /* G_UADDSAT */
    380,
    /* G_SADDSAT */
    383,
    /* G_USUBSAT */
    386,
    /* G_SSUBSAT */
    389,
    /* G_USHLSAT */
    392,
    /* G_SSHLSAT */
    395,
    /* G_SMULFIX */
    398,
    /* G_UMULFIX */
    402,
    /* G_SMULFIXSAT */
    406,
    /* G_UMULFIXSAT */
    410,
    /* G_SDIVFIX */
    414,
    /* G_UDIVFIX */
    418,
    /* G_SDIVFIXSAT */
    422,
    /* G_UDIVFIXSAT */
    426,
    /* G_FADD */
    430,
    /* G_FSUB */
    433,
    /* G_FMUL */
    436,
    /* G_FMA */
    439,
    /* G_FMAD */
    443,
    /* G_FDIV */
    447,
    /* G_FREM */
    450,
    /* G_FPOW */
    453,
    /* G_FPOWI */
    456,
    /* G_FEXP */
    459,
    /* G_FEXP2 */
    461,
    /* G_FEXP10 */
    463,
    /* G_FLOG */
    465,
    /* G_FLOG2 */
    467,
    /* G_FLOG10 */
    469,
    /* G_FLDEXP */
    471,
    /* G_FFREXP */
    474,
    /* G_FNEG */
    477,
    /* G_FPEXT */
    479,
    /* G_FPTRUNC */
    481,
    /* G_FPTOSI */
    483,
    /* G_FPTOUI */
    485,
    /* G_SITOFP */
    487,
    /* G_UITOFP */
    489,
    /* G_FPTOSI_SAT */
    491,
    /* G_FPTOUI_SAT */
    493,
    /* G_FABS */
    495,
    /* G_FCOPYSIGN */
    497,
    /* G_IS_FPCLASS */
    500,
    /* G_FCANONICALIZE */
    503,
    /* G_FMINNUM */
    505,
    /* G_FMAXNUM */
    508,
    /* G_FMINNUM_IEEE */
    511,
    /* G_FMAXNUM_IEEE */
    514,
    /* G_FMINIMUM */
    517,
    /* G_FMAXIMUM */
    520,
    /* G_GET_FPENV */
    523,
    /* G_SET_FPENV */
    524,
    /* G_RESET_FPENV */
    525,
    /* G_GET_FPMODE */
    525,
    /* G_SET_FPMODE */
    526,
    /* G_RESET_FPMODE */
    527,
    /* G_PTR_ADD */
    527,
    /* G_PTRMASK */
    530,
    /* G_SMIN */
    533,
    /* G_SMAX */
    536,
    /* G_UMIN */
    539,
    /* G_UMAX */
    542,
    /* G_ABS */
    545,
    /* G_LROUND */
    547,
    /* G_LLROUND */
    549,
    /* G_BR */
    551,
    /* G_BRJT */
    552,
    /* G_VSCALE */
    555,
    /* G_INSERT_SUBVECTOR */
    557,
    /* G_EXTRACT_SUBVECTOR */
    561,
    /* G_INSERT_VECTOR_ELT */
    564,
    /* G_EXTRACT_VECTOR_ELT */
    568,
    /* G_SHUFFLE_VECTOR */
    571,
    /* G_SPLAT_VECTOR */
    575,
    /* G_VECTOR_COMPRESS */
    577,
    /* G_CTTZ */
    581,
    /* G_CTTZ_ZERO_UNDEF */
    583,
    /* G_CTLZ */
    585,
    /* G_CTLZ_ZERO_UNDEF */
    587,
    /* G_CTPOP */
    589,
    /* G_BSWAP */
    591,
    /* G_BITREVERSE */
    593,
    /* G_FCEIL */
    595,
    /* G_FCOS */
    597,
    /* G_FSIN */
    599,
    /* G_FTAN */
    601,
    /* G_FACOS */
    603,
    /* G_FASIN */
    605,
    /* G_FATAN */
    607,
    /* G_FCOSH */
    609,
    /* G_FSINH */
    611,
    /* G_FTANH */
    613,
    /* G_FSQRT */
    615,
    /* G_FFLOOR */
    617,
    /* G_FRINT */
    619,
    /* G_FNEARBYINT */
    621,
    /* G_ADDRSPACE_CAST */
    623,
    /* G_BLOCK_ADDR */
    625,
    /* G_JUMP_TABLE */
    627,
    /* G_DYN_STACKALLOC */
    629,
    /* G_STACKSAVE */
    632,
    /* G_STACKRESTORE */
    633,
    /* G_STRICT_FADD */
    634,
    /* G_STRICT_FSUB */
    637,
    /* G_STRICT_FMUL */
    640,
    /* G_STRICT_FDIV */
    643,
    /* G_STRICT_FREM */
    646,
    /* G_STRICT_FMA */
    649,
    /* G_STRICT_FSQRT */
    653,
    /* G_STRICT_FLDEXP */
    655,
    /* G_READ_REGISTER */
    658,
    /* G_WRITE_REGISTER */
    660,
    /* G_MEMCPY */
    662,
    /* G_MEMCPY_INLINE */
    666,
    /* G_MEMMOVE */
    669,
    /* G_MEMSET */
    673,
    /* G_BZERO */
    677,
    /* G_TRAP */
    680,
    /* G_DEBUGTRAP */
    680,
    /* G_UBSANTRAP */
    680,
    /* G_VECREDUCE_SEQ_FADD */
    681,
    /* G_VECREDUCE_SEQ_FMUL */
    684,
    /* G_VECREDUCE_FADD */
    687,
    /* G_VECREDUCE_FMUL */
    689,
    /* G_VECREDUCE_FMAX */
    691,
    /* G_VECREDUCE_FMIN */
    693,
    /* G_VECREDUCE_FMAXIMUM */
    695,
    /* G_VECREDUCE_FMINIMUM */
    697,
    /* G_VECREDUCE_ADD */
    699,
    /* G_VECREDUCE_MUL */
    701,
    /* G_VECREDUCE_AND */
    703,
    /* G_VECREDUCE_OR */
    705,
    /* G_VECREDUCE_XOR */
    707,
    /* G_VECREDUCE_SMAX */
    709,
    /* G_VECREDUCE_SMIN */
    711,
    /* G_VECREDUCE_UMAX */
    713,
    /* G_VECREDUCE_UMIN */
    715,
    /* G_SBFX */
    717,
    /* G_UBFX */
    721,
    /* ADJCALLSTACKDOWN */
    725,
    /* ADJCALLSTACKUP */
    727,
    /* ADJDYNALLOC */
    729,
    /* CALL */
    731,
    /* CALLR */
    732,
    /* ADDC_F_I_HI */
    733,
    /* ADDC_F_I_LO */
    736,
    /* ADDC_F_R */
    739,
    /* ADDC_I_HI */
    743,
    /* ADDC_I_LO */
    746,
    /* ADDC_R */
    749,
    /* ADD_F_I_HI */
    753,
    /* ADD_F_I_LO */
    756,
    /* ADD_F_R */
    759,
    /* ADD_I_HI */
    763,
    /* ADD_I_LO */
    766,
    /* ADD_R */
    769,
    /* AND_F_I_HI */
    773,
    /* AND_F_I_LO */
    776,
    /* AND_F_R */
    779,
    /* AND_I_HI */
    783,
    /* AND_I_LO */
    786,
    /* AND_R */
    789,
    /* BRCC */
    793,
    /* BRIND_CC */
    795,
    /* BRIND_CCA */
    797,
    /* BRR */
    800,
    /* BT */
    802,
    /* JR */
    803,
    /* LDADDR */
    804,
    /* LDBs_RI */
    806,
    /* LDBs_RR */
    810,
    /* LDBz_RI */
    814,
    /* LDBz_RR */
    818,
    /* LDHs_RI */
    822,
    /* LDHs_RR */
    826,
    /* LDHz_RI */
    830,
    /* LDHz_RR */
    834,
    /* LDW_RI */
    838,
    /* LDW_RR */
    842,
    /* LDWz_RR */
    846,
    /* LEADZ */
    850,
    /* LOG0 */
    852,
    /* LOG1 */
    852,
    /* LOG2 */
    852,
    /* LOG3 */
    852,
    /* LOG4 */
    852,
    /* MOVHI */
    852,
    /* NOP */
    854,
    /* OR_F_I_HI */
    854,
    /* OR_F_I_LO */
    857,
    /* OR_F_R */
    860,
    /* OR_I_HI */
    864,
    /* OR_I_LO */
    867,
    /* OR_R */
    870,
    /* POPC */
    874,
    /* RET */
    876,
    /* SA_F_I */
    876,
    /* SA_I */
    879,
    /* SCC */
    882,
    /* SELECT */
    884,
    /* SFSUB_F_RI_HI */
    888,
    /* SFSUB_F_RI_LO */
    890,
    /* SFSUB_F_RR */
    892,
    /* SHL_F_R */
    894,
    /* SHL_R */
    898,
    /* SLI */
    902,
    /* SL_F_I */
    904,
    /* SL_I */
    907,
    /* SRA_F_R */
    910,
    /* SRA_R */
    914,
    /* SRL_F_R */
    918,
    /* SRL_R */
    922,
    /* STADDR */
    926,
    /* STB_RI */
    928,
    /* STB_RR */
    932,
    /* STH_RI */
    936,
    /* STH_RR */
    940,
    /* SUBB_F_I_HI */
    944,
    /* SUBB_F_I_LO */
    947,
    /* SUBB_F_R */
    950,
    /* SUBB_I_HI */
    954,
    /* SUBB_I_LO */
    957,
    /* SUBB_R */
    960,
    /* SUB_F_I_HI */
    964,
    /* SUB_F_I_LO */
    967,
    /* SUB_F_R */
    970,
    /* SUB_I_HI */
    974,
    /* SUB_I_LO */
    977,
    /* SUB_R */
    980,
    /* SW_RI */
    984,
    /* SW_RR */
    988,
    /* TRAILZ */
    992,
    /* XOR_F_I_HI */
    994,
    /* XOR_F_I_LO */
    997,
    /* XOR_F_R */
    1000,
    /* XOR_I_HI */
    1004,
    /* XOR_I_LO */
    1007,
    /* XOR_R */
    1010,
  };

  using namespace OpTypes;
  static const int8_t OpcodeOperandTypes[] = {
    
    /* PHI */
    -1, 
    /* INLINEASM */
    /* INLINEASM_BR */
    /* CFI_INSTRUCTION */
    i32imm, 
    /* EH_LABEL */
    i32imm, 
    /* GC_LABEL */
    i32imm, 
    /* ANNOTATION_LABEL */
    i32imm, 
    /* KILL */
    /* EXTRACT_SUBREG */
    -1, -1, i32imm, 
    /* INSERT_SUBREG */
    -1, -1, -1, i32imm, 
    /* IMPLICIT_DEF */
    -1, 
    /* INIT_UNDEF */
    -1, 
    /* SUBREG_TO_REG */
    -1, -1, -1, i32imm, 
    /* COPY_TO_REGCLASS */
    -1, -1, i32imm, 
    /* DBG_VALUE */
    /* DBG_VALUE_LIST */
    /* DBG_INSTR_REF */
    /* DBG_PHI */
    /* DBG_LABEL */
    -1, 
    /* REG_SEQUENCE */
    -1, -1, 
    /* COPY */
    -1, -1, 
    /* BUNDLE */
    /* LIFETIME_START */
    i32imm, 
    /* LIFETIME_END */
    i32imm, 
    /* PSEUDO_PROBE */
    i64imm, i64imm, i8imm, i32imm, 
    /* ARITH_FENCE */
    -1, -1, 
    /* STACKMAP */
    i64imm, i32imm, 
    /* FENTRY_CALL */
    /* PATCHPOINT */
    -1, i64imm, i32imm, -1, i32imm, i32imm, 
    /* LOAD_STACK_GUARD */
    -1, 
    /* PREALLOCATED_SETUP */
    i32imm, 
    /* PREALLOCATED_ARG */
    -1, i32imm, i32imm, 
    /* STATEPOINT */
    /* LOCAL_ESCAPE */
    -1, i32imm, 
    /* FAULTING_OP */
    -1, 
    /* PATCHABLE_OP */
    /* PATCHABLE_FUNCTION_ENTER */
    /* PATCHABLE_RET */
    /* PATCHABLE_FUNCTION_EXIT */
    /* PATCHABLE_TAIL_CALL */
    /* PATCHABLE_EVENT_CALL */
    -1, -1, 
    /* PATCHABLE_TYPED_EVENT_CALL */
    -1, -1, -1, 
    /* ICALL_BRANCH_FUNNEL */
    /* FAKE_USE */
    /* MEMBARRIER */
    /* JUMP_TABLE_DEBUG_INFO */
    i64imm, 
    /* CONVERGENCECTRL_ENTRY */
    -1, 
    /* CONVERGENCECTRL_ANCHOR */
    -1, 
    /* CONVERGENCECTRL_LOOP */
    -1, -1, 
    /* CONVERGENCECTRL_GLUE */
    -1, 
    /* G_ASSERT_SEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ZEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ALIGN */
    type0, type0, untyped_imm_0, 
    /* G_ADD */
    type0, type0, type0, 
    /* G_SUB */
    type0, type0, type0, 
    /* G_MUL */
    type0, type0, type0, 
    /* G_SDIV */
    type0, type0, type0, 
    /* G_UDIV */
    type0, type0, type0, 
    /* G_SREM */
    type0, type0, type0, 
    /* G_UREM */
    type0, type0, type0, 
    /* G_SDIVREM */
    type0, type0, type0, type0, 
    /* G_UDIVREM */
    type0, type0, type0, type0, 
    /* G_AND */
    type0, type0, type0, 
    /* G_OR */
    type0, type0, type0, 
    /* G_XOR */
    type0, type0, type0, 
    /* G_IMPLICIT_DEF */
    type0, 
    /* G_PHI */
    type0, 
    /* G_FRAME_INDEX */
    type0, -1, 
    /* G_GLOBAL_VALUE */
    type0, -1, 
    /* G_PTRAUTH_GLOBAL_VALUE */
    type0, -1, i32imm, type1, i64imm, 
    /* G_CONSTANT_POOL */
    type0, -1, 
    /* G_EXTRACT */
    type0, type1, untyped_imm_0, 
    /* G_UNMERGE_VALUES */
    type0, type1, 
    /* G_INSERT */
    type0, type0, type1, untyped_imm_0, 
    /* G_MERGE_VALUES */
    type0, type1, 
    /* G_BUILD_VECTOR */
    type0, type1, 
    /* G_BUILD_VECTOR_TRUNC */
    type0, type1, 
    /* G_CONCAT_VECTORS */
    type0, type1, 
    /* G_PTRTOINT */
    type0, type1, 
    /* G_INTTOPTR */
    type0, type1, 
    /* G_BITCAST */
    type0, type1, 
    /* G_FREEZE */
    type0, type0, 
    /* G_CONSTANT_FOLD_BARRIER */
    type0, type0, 
    /* G_INTRINSIC_FPTRUNC_ROUND */
    type0, type1, i32imm, 
    /* G_INTRINSIC_TRUNC */
    type0, type0, 
    /* G_INTRINSIC_ROUND */
    type0, type0, 
    /* G_INTRINSIC_LRINT */
    type0, type1, 
    /* G_INTRINSIC_LLRINT */
    type0, type1, 
    /* G_INTRINSIC_ROUNDEVEN */
    type0, type0, 
    /* G_READCYCLECOUNTER */
    type0, 
    /* G_READSTEADYCOUNTER */
    type0, 
    /* G_LOAD */
    type0, ptype1, 
    /* G_SEXTLOAD */
    type0, ptype1, 
    /* G_ZEXTLOAD */
    type0, ptype1, 
    /* G_INDEXED_LOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_SEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_ZEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_STORE */
    type0, ptype1, 
    /* G_INDEXED_STORE */
    ptype0, type1, ptype0, ptype2, -1, 
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    type0, type1, type2, type0, type0, 
    /* G_ATOMIC_CMPXCHG */
    type0, ptype1, type0, type0, 
    /* G_ATOMICRMW_XCHG */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_ADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_SUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_AND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_NAND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_OR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_XOR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FSUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UINC_WRAP */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UDEC_WRAP */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_USUB_COND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_USUB_SAT */
    type0, ptype1, type0, 
    /* G_FENCE */
    i32imm, i32imm, 
    /* G_PREFETCH */
    ptype0, i32imm, i32imm, i32imm, 
    /* G_BRCOND */
    type0, -1, 
    /* G_BRINDIRECT */
    type0, 
    /* G_INVOKE_REGION_START */
    /* G_INTRINSIC */
    -1, 
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    -1, 
    /* G_INTRINSIC_CONVERGENT */
    -1, 
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    -1, 
    /* G_ANYEXT */
    type0, type1, 
    /* G_TRUNC */
    type0, type1, 
    /* G_CONSTANT */
    type0, -1, 
    /* G_FCONSTANT */
    type0, -1, 
    /* G_VASTART */
    type0, 
    /* G_VAARG */
    type0, type1, -1, 
    /* G_SEXT */
    type0, type1, 
    /* G_SEXT_INREG */
    type0, type0, untyped_imm_0, 
    /* G_ZEXT */
    type0, type1, 
    /* G_SHL */
    type0, type0, type1, 
    /* G_LSHR */
    type0, type0, type1, 
    /* G_ASHR */
    type0, type0, type1, 
    /* G_FSHL */
    type0, type0, type0, type1, 
    /* G_FSHR */
    type0, type0, type0, type1, 
    /* G_ROTR */
    type0, type0, type1, 
    /* G_ROTL */
    type0, type0, type1, 
    /* G_ICMP */
    type0, -1, type1, type1, 
    /* G_FCMP */
    type0, -1, type1, type1, 
    /* G_SCMP */
    type0, type1, type1, 
    /* G_UCMP */
    type0, type1, type1, 
    /* G_SELECT */
    type0, type1, type0, type0, 
    /* G_UADDO */
    type0, type1, type0, type0, 
    /* G_UADDE */
    type0, type1, type0, type0, type1, 
    /* G_USUBO */
    type0, type1, type0, type0, 
    /* G_USUBE */
    type0, type1, type0, type0, type1, 
    /* G_SADDO */
    type0, type1, type0, type0, 
    /* G_SADDE */
    type0, type1, type0, type0, type1, 
    /* G_SSUBO */
    type0, type1, type0, type0, 
    /* G_SSUBE */
    type0, type1, type0, type0, type1, 
    /* G_UMULO */
    type0, type1, type0, type0, 
    /* G_SMULO */
    type0, type1, type0, type0, 
    /* G_UMULH */
    type0, type0, type0, 
    /* G_SMULH */
    type0, type0, type0, 
    /* G_UADDSAT */
    type0, type0, type0, 
    /* G_SADDSAT */
    type0, type0, type0, 
    /* G_USUBSAT */
    type0, type0, type0, 
    /* G_SSUBSAT */
    type0, type0, type0, 
    /* G_USHLSAT */
    type0, type0, type1, 
    /* G_SSHLSAT */
    type0, type0, type1, 
    /* G_SMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_FADD */
    type0, type0, type0, 
    /* G_FSUB */
    type0, type0, type0, 
    /* G_FMUL */
    type0, type0, type0, 
    /* G_FMA */
    type0, type0, type0, type0, 
    /* G_FMAD */
    type0, type0, type0, type0, 
    /* G_FDIV */
    type0, type0, type0, 
    /* G_FREM */
    type0, type0, type0, 
    /* G_FPOW */
    type0, type0, type0, 
    /* G_FPOWI */
    type0, type0, type1, 
    /* G_FEXP */
    type0, type0, 
    /* G_FEXP2 */
    type0, type0, 
    /* G_FEXP10 */
    type0, type0, 
    /* G_FLOG */
    type0, type0, 
    /* G_FLOG2 */
    type0, type0, 
    /* G_FLOG10 */
    type0, type0, 
    /* G_FLDEXP */
    type0, type0, type1, 
    /* G_FFREXP */
    type0, type1, type0, 
    /* G_FNEG */
    type0, type0, 
    /* G_FPEXT */
    type0, type1, 
    /* G_FPTRUNC */
    type0, type1, 
    /* G_FPTOSI */
    type0, type1, 
    /* G_FPTOUI */
    type0, type1, 
    /* G_SITOFP */
    type0, type1, 
    /* G_UITOFP */
    type0, type1, 
    /* G_FPTOSI_SAT */
    type0, type1, 
    /* G_FPTOUI_SAT */
    type0, type1, 
    /* G_FABS */
    type0, type0, 
    /* G_FCOPYSIGN */
    type0, type0, type1, 
    /* G_IS_FPCLASS */
    type0, type1, -1, 
    /* G_FCANONICALIZE */
    type0, type0, 
    /* G_FMINNUM */
    type0, type0, type0, 
    /* G_FMAXNUM */
    type0, type0, type0, 
    /* G_FMINNUM_IEEE */
    type0, type0, type0, 
    /* G_FMAXNUM_IEEE */
    type0, type0, type0, 
    /* G_FMINIMUM */
    type0, type0, type0, 
    /* G_FMAXIMUM */
    type0, type0, type0, 
    /* G_GET_FPENV */
    type0, 
    /* G_SET_FPENV */
    type0, 
    /* G_RESET_FPENV */
    /* G_GET_FPMODE */
    type0, 
    /* G_SET_FPMODE */
    type0, 
    /* G_RESET_FPMODE */
    /* G_PTR_ADD */
    ptype0, ptype0, type1, 
    /* G_PTRMASK */
    ptype0, ptype0, type1, 
    /* G_SMIN */
    type0, type0, type0, 
    /* G_SMAX */
    type0, type0, type0, 
    /* G_UMIN */
    type0, type0, type0, 
    /* G_UMAX */
    type0, type0, type0, 
    /* G_ABS */
    type0, type0, 
    /* G_LROUND */
    type0, type1, 
    /* G_LLROUND */
    type0, type1, 
    /* G_BR */
    -1, 
    /* G_BRJT */
    ptype0, -1, type1, 
    /* G_VSCALE */
    type0, -1, 
    /* G_INSERT_SUBVECTOR */
    type0, type0, type1, untyped_imm_0, 
    /* G_EXTRACT_SUBVECTOR */
    type0, type0, untyped_imm_0, 
    /* G_INSERT_VECTOR_ELT */
    type0, type0, type1, type2, 
    /* G_EXTRACT_VECTOR_ELT */
    type0, type1, type2, 
    /* G_SHUFFLE_VECTOR */
    type0, type1, type1, -1, 
    /* G_SPLAT_VECTOR */
    type0, type1, 
    /* G_VECTOR_COMPRESS */
    type0, type0, type1, type0, 
    /* G_CTTZ */
    type0, type1, 
    /* G_CTTZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTLZ */
    type0, type1, 
    /* G_CTLZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTPOP */
    type0, type1, 
    /* G_BSWAP */
    type0, type0, 
    /* G_BITREVERSE */
    type0, type0, 
    /* G_FCEIL */
    type0, type0, 
    /* G_FCOS */
    type0, type0, 
    /* G_FSIN */
    type0, type0, 
    /* G_FTAN */
    type0, type0, 
    /* G_FACOS */
    type0, type0, 
    /* G_FASIN */
    type0, type0, 
    /* G_FATAN */
    type0, type0, 
    /* G_FCOSH */
    type0, type0, 
    /* G_FSINH */
    type0, type0, 
    /* G_FTANH */
    type0, type0, 
    /* G_FSQRT */
    type0, type0, 
    /* G_FFLOOR */
    type0, type0, 
    /* G_FRINT */
    type0, type0, 
    /* G_FNEARBYINT */
    type0, type0, 
    /* G_ADDRSPACE_CAST */
    type0, type1, 
    /* G_BLOCK_ADDR */
    type0, -1, 
    /* G_JUMP_TABLE */
    type0, -1, 
    /* G_DYN_STACKALLOC */
    ptype0, type1, i32imm, 
    /* G_STACKSAVE */
    ptype0, 
    /* G_STACKRESTORE */
    ptype0, 
    /* G_STRICT_FADD */
    type0, type0, type0, 
    /* G_STRICT_FSUB */
    type0, type0, type0, 
    /* G_STRICT_FMUL */
    type0, type0, type0, 
    /* G_STRICT_FDIV */
    type0, type0, type0, 
    /* G_STRICT_FREM */
    type0, type0, type0, 
    /* G_STRICT_FMA */
    type0, type0, type0, type0, 
    /* G_STRICT_FSQRT */
    type0, type0, 
    /* G_STRICT_FLDEXP */
    type0, type0, type1, 
    /* G_READ_REGISTER */
    type0, -1, 
    /* G_WRITE_REGISTER */
    -1, type0, 
    /* G_MEMCPY */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMCPY_INLINE */
    ptype0, ptype1, type2, 
    /* G_MEMMOVE */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMSET */
    ptype0, type1, type2, untyped_imm_0, 
    /* G_BZERO */
    ptype0, type1, untyped_imm_0, 
    /* G_TRAP */
    /* G_DEBUGTRAP */
    /* G_UBSANTRAP */
    i8imm, 
    /* G_VECREDUCE_SEQ_FADD */
    type0, type1, type2, 
    /* G_VECREDUCE_SEQ_FMUL */
    type0, type1, type2, 
    /* G_VECREDUCE_FADD */
    type0, type1, 
    /* G_VECREDUCE_FMUL */
    type0, type1, 
    /* G_VECREDUCE_FMAX */
    type0, type1, 
    /* G_VECREDUCE_FMIN */
    type0, type1, 
    /* G_VECREDUCE_FMAXIMUM */
    type0, type1, 
    /* G_VECREDUCE_FMINIMUM */
    type0, type1, 
    /* G_VECREDUCE_ADD */
    type0, type1, 
    /* G_VECREDUCE_MUL */
    type0, type1, 
    /* G_VECREDUCE_AND */
    type0, type1, 
    /* G_VECREDUCE_OR */
    type0, type1, 
    /* G_VECREDUCE_XOR */
    type0, type1, 
    /* G_VECREDUCE_SMAX */
    type0, type1, 
    /* G_VECREDUCE_SMIN */
    type0, type1, 
    /* G_VECREDUCE_UMAX */
    type0, type1, 
    /* G_VECREDUCE_UMIN */
    type0, type1, 
    /* G_SBFX */
    type0, type0, type1, type1, 
    /* G_UBFX */
    type0, type0, type1, type1, 
    /* ADJCALLSTACKDOWN */
    i32imm, i32imm, 
    /* ADJCALLSTACKUP */
    i32imm, i32imm, 
    /* ADJDYNALLOC */
    GPR, GPR, 
    /* CALL */
    CallTarget, 
    /* CALLR */
    GPR, 
    /* ADDC_F_I_HI */
    GPR, GPR, i32hi16, 
    /* ADDC_F_I_LO */
    GPR, GPR, i32lo16z, 
    /* ADDC_F_R */
    GPR, GPR, GPR, i32imm, 
    /* ADDC_I_HI */
    GPR, GPR, i32hi16, 
    /* ADDC_I_LO */
    GPR, GPR, i32lo16z, 
    /* ADDC_R */
    GPR, GPR, GPR, i32imm, 
    /* ADD_F_I_HI */
    GPR, GPR, i32hi16, 
    /* ADD_F_I_LO */
    GPR, GPR, i32lo16z, 
    /* ADD_F_R */
    GPR, GPR, GPR, i32imm, 
    /* ADD_I_HI */
    GPR, GPR, i32hi16, 
    /* ADD_I_LO */
    GPR, GPR, i32lo16z, 
    /* ADD_R */
    GPR, GPR, GPR, i32imm, 
    /* AND_F_I_HI */
    GPR, GPR, i32hi16and, 
    /* AND_F_I_LO */
    GPR, GPR, i32lo16and, 
    /* AND_F_R */
    GPR, GPR, GPR, i32imm, 
    /* AND_I_HI */
    GPR, GPR, i32hi16and, 
    /* AND_I_LO */
    GPR, GPR, i32lo16and, 
    /* AND_R */
    GPR, GPR, GPR, i32imm, 
    /* BRCC */
    BrTarget, CCOp, 
    /* BRIND_CC */
    GPR, CCOp, 
    /* BRIND_CCA */
    GPR, GPR, CCOp, 
    /* BRR */
    i16imm, CCOp, 
    /* BT */
    BrTarget, 
    /* JR */
    GPR, 
    /* LDADDR */
    GPR, i32lo21, 
    /* LDBs_RI */
    GPR, GPR, imm10, AluOp, 
    /* LDBs_RR */
    GPR, GPR, GPR, AluOp, 
    /* LDBz_RI */
    GPR, GPR, imm10, AluOp, 
    /* LDBz_RR */
    GPR, GPR, GPR, AluOp, 
    /* LDHs_RI */
    GPR, GPR, imm10, AluOp, 
    /* LDHs_RR */
    GPR, GPR, GPR, AluOp, 
    /* LDHz_RI */
    GPR, GPR, imm10, AluOp, 
    /* LDHz_RR */
    GPR, GPR, GPR, AluOp, 
    /* LDW_RI */
    GPR, GPR, i32lo16s, AluOp, 
    /* LDW_RR */
    GPR, GPR, GPR, AluOp, 
    /* LDWz_RR */
    GPR, GPR, GPR, AluOp, 
    /* LEADZ */
    GPR, GPR, 
    /* LOG0 */
    /* LOG1 */
    /* LOG2 */
    /* LOG3 */
    /* LOG4 */
    /* MOVHI */
    GPR, i32hi16, 
    /* NOP */
    /* OR_F_I_HI */
    GPR, GPR, i32hi16, 
    /* OR_F_I_LO */
    GPR, GPR, i32lo16z, 
    /* OR_F_R */
    GPR, GPR, GPR, i32imm, 
    /* OR_I_HI */
    GPR, GPR, i32hi16, 
    /* OR_I_LO */
    GPR, GPR, i32lo16z, 
    /* OR_R */
    GPR, GPR, GPR, i32imm, 
    /* POPC */
    GPR, GPR, 
    /* RET */
    /* SA_F_I */
    GPR, GPR, immShift, 
    /* SA_I */
    GPR, GPR, immShift, 
    /* SCC */
    GPR, CCOp, 
    /* SELECT */
    GPR, GPR, GPR, CCOp, 
    /* SFSUB_F_RI_HI */
    GPR, i32hi16, 
    /* SFSUB_F_RI_LO */
    GPR, i32lo16z, 
    /* SFSUB_F_RR */
    GPR, GPR, 
    /* SHL_F_R */
    GPR, GPR, GPR, i32imm, 
    /* SHL_R */
    GPR, GPR, GPR, i32imm, 
    /* SLI */
    GPR, i32lo21, 
    /* SL_F_I */
    GPR, GPR, immShift, 
    /* SL_I */
    GPR, GPR, immShift, 
    /* SRA_F_R */
    GPR, GPR, GPR, i32imm, 
    /* SRA_R */
    GPR, GPR, GPR, i32imm, 
    /* SRL_F_R */
    GPR, GPR, GPR, i32imm, 
    /* SRL_R */
    GPR, GPR, GPR, i32imm, 
    /* STADDR */
    GPR, i32lo21, 
    /* STB_RI */
    GPR, GPR, imm10, AluOp, 
    /* STB_RR */
    GPR, GPR, GPR, AluOp, 
    /* STH_RI */
    GPR, GPR, imm10, AluOp, 
    /* STH_RR */
    GPR, GPR, GPR, AluOp, 
    /* SUBB_F_I_HI */
    GPR, GPR, i32hi16, 
    /* SUBB_F_I_LO */
    GPR, GPR, i32lo16z, 
    /* SUBB_F_R */
    GPR, GPR, GPR, i32imm, 
    /* SUBB_I_HI */
    GPR, GPR, i32hi16, 
    /* SUBB_I_LO */
    GPR, GPR, i32lo16z, 
    /* SUBB_R */
    GPR, GPR, GPR, i32imm, 
    /* SUB_F_I_HI */
    GPR, GPR, i32hi16, 
    /* SUB_F_I_LO */
    GPR, GPR, i32lo16z, 
    /* SUB_F_R */
    GPR, GPR, GPR, i32imm, 
    /* SUB_I_HI */
    GPR, GPR, i32hi16, 
    /* SUB_I_LO */
    GPR, GPR, i32lo16z, 
    /* SUB_R */
    GPR, GPR, GPR, i32imm, 
    /* SW_RI */
    GPR, GPR, i32lo16s, AluOp, 
    /* SW_RR */
    GPR, GPR, GPR, AluOp, 
    /* TRAILZ */
    GPR, GPR, 
    /* XOR_F_I_HI */
    GPR, GPR, i32hi16, 
    /* XOR_F_I_LO */
    GPR, GPR, i32lo16z, 
    /* XOR_F_R */
    GPR, GPR, GPR, i32imm, 
    /* XOR_I_HI */
    GPR, GPR, i32hi16, 
    /* XOR_I_LO */
    GPR, GPR, i32lo16z, 
    /* XOR_R */
    GPR, GPR, GPR, i32imm, 
  };
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
}
} // end namespace Lanai
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPE

#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
namespace llvm {
namespace Lanai {
LLVM_READONLY
static int getMemOperandSize(int OpType) {
  switch (OpType) {
  default: return 0;
  }
}
} // end namespace Lanai
} // end namespace llvm
#endif // GET_INSTRINFO_MEM_OPERAND_SIZE

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
namespace llvm {
namespace Lanai {
LLVM_READONLY static unsigned
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return LogicalOpIdx;
}
LLVM_READONLY static inline unsigned
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
  auto S = 0U;
  for (auto i = 0U; i < LogicalOpIdx; ++i)
    S += getLogicalOperandSize(Opcode, i);
  return S;
}
} // end namespace Lanai
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
namespace llvm {
namespace Lanai {
LLVM_READONLY static int
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return -1;
}
} // end namespace Lanai
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP

#ifdef GET_INSTRINFO_MC_HELPER_DECLS
#undef GET_INSTRINFO_MC_HELPER_DECLS

namespace llvm {
class MCInst;
class FeatureBitset;

namespace Lanai_MC {

void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);

} // end namespace Lanai_MC
} // end namespace llvm

#endif // GET_INSTRINFO_MC_HELPER_DECLS

#ifdef GET_INSTRINFO_MC_HELPERS
#undef GET_INSTRINFO_MC_HELPERS

namespace llvm {
namespace Lanai_MC {

} // end namespace Lanai_MC
} // end namespace llvm

#endif // GET_GENISTRINFO_MC_HELPERS

#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
    defined(GET_AVAILABLE_OPCODE_CHECKER)
#define GET_COMPUTE_FEATURES
#endif
#ifdef GET_COMPUTE_FEATURES
#undef GET_COMPUTE_FEATURES
namespace llvm {
namespace Lanai_MC {

// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
};

inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
  FeatureBitset Features;
  return Features;
}

inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
  enum : uint8_t {
    CEFBS_None,
  };

  static constexpr FeatureBitset FeatureBitsets[] = {
    {}, // CEFBS_None
  };
  static constexpr uint8_t RequiredFeaturesRefs[] = {
    CEFBS_None, // PHI = 0
    CEFBS_None, // INLINEASM = 1
    CEFBS_None, // INLINEASM_BR = 2
    CEFBS_None, // CFI_INSTRUCTION = 3
    CEFBS_None, // EH_LABEL = 4
    CEFBS_None, // GC_LABEL = 5
    CEFBS_None, // ANNOTATION_LABEL = 6
    CEFBS_None, // KILL = 7
    CEFBS_None, // EXTRACT_SUBREG = 8
    CEFBS_None, // INSERT_SUBREG = 9
    CEFBS_None, // IMPLICIT_DEF = 10
    CEFBS_None, // INIT_UNDEF = 11
    CEFBS_None, // SUBREG_TO_REG = 12
    CEFBS_None, // COPY_TO_REGCLASS = 13
    CEFBS_None, // DBG_VALUE = 14
    CEFBS_None, // DBG_VALUE_LIST = 15
    CEFBS_None, // DBG_INSTR_REF = 16
    CEFBS_None, // DBG_PHI = 17
    CEFBS_None, // DBG_LABEL = 18
    CEFBS_None, // REG_SEQUENCE = 19
    CEFBS_None, // COPY = 20
    CEFBS_None, // BUNDLE = 21
    CEFBS_None, // LIFETIME_START = 22
    CEFBS_None, // LIFETIME_END = 23
    CEFBS_None, // PSEUDO_PROBE = 24
    CEFBS_None, // ARITH_FENCE = 25
    CEFBS_None, // STACKMAP = 26
    CEFBS_None, // FENTRY_CALL = 27
    CEFBS_None, // PATCHPOINT = 28
    CEFBS_None, // LOAD_STACK_GUARD = 29
    CEFBS_None, // PREALLOCATED_SETUP = 30
    CEFBS_None, // PREALLOCATED_ARG = 31
    CEFBS_None, // STATEPOINT = 32
    CEFBS_None, // LOCAL_ESCAPE = 33
    CEFBS_None, // FAULTING_OP = 34
    CEFBS_None, // PATCHABLE_OP = 35
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 36
    CEFBS_None, // PATCHABLE_RET = 37
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 38
    CEFBS_None, // PATCHABLE_TAIL_CALL = 39
    CEFBS_None, // PATCHABLE_EVENT_CALL = 40
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 41
    CEFBS_None, // ICALL_BRANCH_FUNNEL = 42
    CEFBS_None, // FAKE_USE = 43
    CEFBS_None, // MEMBARRIER = 44
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 45
    CEFBS_None, // CONVERGENCECTRL_ENTRY = 46
    CEFBS_None, // CONVERGENCECTRL_ANCHOR = 47
    CEFBS_None, // CONVERGENCECTRL_LOOP = 48
    CEFBS_None, // CONVERGENCECTRL_GLUE = 49
    CEFBS_None, // G_ASSERT_SEXT = 50
    CEFBS_None, // G_ASSERT_ZEXT = 51
    CEFBS_None, // G_ASSERT_ALIGN = 52
    CEFBS_None, // G_ADD = 53
    CEFBS_None, // G_SUB = 54
    CEFBS_None, // G_MUL = 55
    CEFBS_None, // G_SDIV = 56
    CEFBS_None, // G_UDIV = 57
    CEFBS_None, // G_SREM = 58
    CEFBS_None, // G_UREM = 59
    CEFBS_None, // G_SDIVREM = 60
    CEFBS_None, // G_UDIVREM = 61
    CEFBS_None, // G_AND = 62
    CEFBS_None, // G_OR = 63
    CEFBS_None, // G_XOR = 64
    CEFBS_None, // G_IMPLICIT_DEF = 65
    CEFBS_None, // G_PHI = 66
    CEFBS_None, // G_FRAME_INDEX = 67
    CEFBS_None, // G_GLOBAL_VALUE = 68
    CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 69
    CEFBS_None, // G_CONSTANT_POOL = 70
    CEFBS_None, // G_EXTRACT = 71
    CEFBS_None, // G_UNMERGE_VALUES = 72
    CEFBS_None, // G_INSERT = 73
    CEFBS_None, // G_MERGE_VALUES = 74
    CEFBS_None, // G_BUILD_VECTOR = 75
    CEFBS_None, // G_BUILD_VECTOR_TRUNC = 76
    CEFBS_None, // G_CONCAT_VECTORS = 77
    CEFBS_None, // G_PTRTOINT = 78
    CEFBS_None, // G_INTTOPTR = 79
    CEFBS_None, // G_BITCAST = 80
    CEFBS_None, // G_FREEZE = 81
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 82
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 83
    CEFBS_None, // G_INTRINSIC_TRUNC = 84
    CEFBS_None, // G_INTRINSIC_ROUND = 85
    CEFBS_None, // G_INTRINSIC_LRINT = 86
    CEFBS_None, // G_INTRINSIC_LLRINT = 87
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 88
    CEFBS_None, // G_READCYCLECOUNTER = 89
    CEFBS_None, // G_READSTEADYCOUNTER = 90
    CEFBS_None, // G_LOAD = 91
    CEFBS_None, // G_SEXTLOAD = 92
    CEFBS_None, // G_ZEXTLOAD = 93
    CEFBS_None, // G_INDEXED_LOAD = 94
    CEFBS_None, // G_INDEXED_SEXTLOAD = 95
    CEFBS_None, // G_INDEXED_ZEXTLOAD = 96
    CEFBS_None, // G_STORE = 97
    CEFBS_None, // G_INDEXED_STORE = 98
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 99
    CEFBS_None, // G_ATOMIC_CMPXCHG = 100
    CEFBS_None, // G_ATOMICRMW_XCHG = 101
    CEFBS_None, // G_ATOMICRMW_ADD = 102
    CEFBS_None, // G_ATOMICRMW_SUB = 103
    CEFBS_None, // G_ATOMICRMW_AND = 104
    CEFBS_None, // G_ATOMICRMW_NAND = 105
    CEFBS_None, // G_ATOMICRMW_OR = 106
    CEFBS_None, // G_ATOMICRMW_XOR = 107
    CEFBS_None, // G_ATOMICRMW_MAX = 108
    CEFBS_None, // G_ATOMICRMW_MIN = 109
    CEFBS_None, // G_ATOMICRMW_UMAX = 110
    CEFBS_None, // G_ATOMICRMW_UMIN = 111
    CEFBS_None, // G_ATOMICRMW_FADD = 112
    CEFBS_None, // G_ATOMICRMW_FSUB = 113
    CEFBS_None, // G_ATOMICRMW_FMAX = 114
    CEFBS_None, // G_ATOMICRMW_FMIN = 115
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 116
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 117
    CEFBS_None, // G_ATOMICRMW_USUB_COND = 118
    CEFBS_None, // G_ATOMICRMW_USUB_SAT = 119
    CEFBS_None, // G_FENCE = 120
    CEFBS_None, // G_PREFETCH = 121
    CEFBS_None, // G_BRCOND = 122
    CEFBS_None, // G_BRINDIRECT = 123
    CEFBS_None, // G_INVOKE_REGION_START = 124
    CEFBS_None, // G_INTRINSIC = 125
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 126
    CEFBS_None, // G_INTRINSIC_CONVERGENT = 127
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 128
    CEFBS_None, // G_ANYEXT = 129
    CEFBS_None, // G_TRUNC = 130
    CEFBS_None, // G_CONSTANT = 131
    CEFBS_None, // G_FCONSTANT = 132
    CEFBS_None, // G_VASTART = 133
    CEFBS_None, // G_VAARG = 134
    CEFBS_None, // G_SEXT = 135
    CEFBS_None, // G_SEXT_INREG = 136
    CEFBS_None, // G_ZEXT = 137
    CEFBS_None, // G_SHL = 138
    CEFBS_None, // G_LSHR = 139
    CEFBS_None, // G_ASHR = 140
    CEFBS_None, // G_FSHL = 141
    CEFBS_None, // G_FSHR = 142
    CEFBS_None, // G_ROTR = 143
    CEFBS_None, // G_ROTL = 144
    CEFBS_None, // G_ICMP = 145
    CEFBS_None, // G_FCMP = 146
    CEFBS_None, // G_SCMP = 147
    CEFBS_None, // G_UCMP = 148
    CEFBS_None, // G_SELECT = 149
    CEFBS_None, // G_UADDO = 150
    CEFBS_None, // G_UADDE = 151
    CEFBS_None, // G_USUBO = 152
    CEFBS_None, // G_USUBE = 153
    CEFBS_None, // G_SADDO = 154
    CEFBS_None, // G_SADDE = 155
    CEFBS_None, // G_SSUBO = 156
    CEFBS_None, // G_SSUBE = 157
    CEFBS_None, // G_UMULO = 158
    CEFBS_None, // G_SMULO = 159
    CEFBS_None, // G_UMULH = 160
    CEFBS_None, // G_SMULH = 161
    CEFBS_None, // G_UADDSAT = 162
    CEFBS_None, // G_SADDSAT = 163
    CEFBS_None, // G_USUBSAT = 164
    CEFBS_None, // G_SSUBSAT = 165
    CEFBS_None, // G_USHLSAT = 166
    CEFBS_None, // G_SSHLSAT = 167
    CEFBS_None, // G_SMULFIX = 168
    CEFBS_None, // G_UMULFIX = 169
    CEFBS_None, // G_SMULFIXSAT = 170
    CEFBS_None, // G_UMULFIXSAT = 171
    CEFBS_None, // G_SDIVFIX = 172
    CEFBS_None, // G_UDIVFIX = 173
    CEFBS_None, // G_SDIVFIXSAT = 174
    CEFBS_None, // G_UDIVFIXSAT = 175
    CEFBS_None, // G_FADD = 176
    CEFBS_None, // G_FSUB = 177
    CEFBS_None, // G_FMUL = 178
    CEFBS_None, // G_FMA = 179
    CEFBS_None, // G_FMAD = 180
    CEFBS_None, // G_FDIV = 181
    CEFBS_None, // G_FREM = 182
    CEFBS_None, // G_FPOW = 183
    CEFBS_None, // G_FPOWI = 184
    CEFBS_None, // G_FEXP = 185
    CEFBS_None, // G_FEXP2 = 186
    CEFBS_None, // G_FEXP10 = 187
    CEFBS_None, // G_FLOG = 188
    CEFBS_None, // G_FLOG2 = 189
    CEFBS_None, // G_FLOG10 = 190
    CEFBS_None, // G_FLDEXP = 191
    CEFBS_None, // G_FFREXP = 192
    CEFBS_None, // G_FNEG = 193
    CEFBS_None, // G_FPEXT = 194
    CEFBS_None, // G_FPTRUNC = 195
    CEFBS_None, // G_FPTOSI = 196
    CEFBS_None, // G_FPTOUI = 197
    CEFBS_None, // G_SITOFP = 198
    CEFBS_None, // G_UITOFP = 199
    CEFBS_None, // G_FPTOSI_SAT = 200
    CEFBS_None, // G_FPTOUI_SAT = 201
    CEFBS_None, // G_FABS = 202
    CEFBS_None, // G_FCOPYSIGN = 203
    CEFBS_None, // G_IS_FPCLASS = 204
    CEFBS_None, // G_FCANONICALIZE = 205
    CEFBS_None, // G_FMINNUM = 206
    CEFBS_None, // G_FMAXNUM = 207
    CEFBS_None, // G_FMINNUM_IEEE = 208
    CEFBS_None, // G_FMAXNUM_IEEE = 209
    CEFBS_None, // G_FMINIMUM = 210
    CEFBS_None, // G_FMAXIMUM = 211
    CEFBS_None, // G_GET_FPENV = 212
    CEFBS_None, // G_SET_FPENV = 213
    CEFBS_None, // G_RESET_FPENV = 214
    CEFBS_None, // G_GET_FPMODE = 215
    CEFBS_None, // G_SET_FPMODE = 216
    CEFBS_None, // G_RESET_FPMODE = 217
    CEFBS_None, // G_PTR_ADD = 218
    CEFBS_None, // G_PTRMASK = 219
    CEFBS_None, // G_SMIN = 220
    CEFBS_None, // G_SMAX = 221
    CEFBS_None, // G_UMIN = 222
    CEFBS_None, // G_UMAX = 223
    CEFBS_None, // G_ABS = 224
    CEFBS_None, // G_LROUND = 225
    CEFBS_None, // G_LLROUND = 226
    CEFBS_None, // G_BR = 227
    CEFBS_None, // G_BRJT = 228
    CEFBS_None, // G_VSCALE = 229
    CEFBS_None, // G_INSERT_SUBVECTOR = 230
    CEFBS_None, // G_EXTRACT_SUBVECTOR = 231
    CEFBS_None, // G_INSERT_VECTOR_ELT = 232
    CEFBS_None, // G_EXTRACT_VECTOR_ELT = 233
    CEFBS_None, // G_SHUFFLE_VECTOR = 234
    CEFBS_None, // G_SPLAT_VECTOR = 235
    CEFBS_None, // G_VECTOR_COMPRESS = 236
    CEFBS_None, // G_CTTZ = 237
    CEFBS_None, // G_CTTZ_ZERO_UNDEF = 238
    CEFBS_None, // G_CTLZ = 239
    CEFBS_None, // G_CTLZ_ZERO_UNDEF = 240
    CEFBS_None, // G_CTPOP = 241
    CEFBS_None, // G_BSWAP = 242
    CEFBS_None, // G_BITREVERSE = 243
    CEFBS_None, // G_FCEIL = 244
    CEFBS_None, // G_FCOS = 245
    CEFBS_None, // G_FSIN = 246
    CEFBS_None, // G_FTAN = 247
    CEFBS_None, // G_FACOS = 248
    CEFBS_None, // G_FASIN = 249
    CEFBS_None, // G_FATAN = 250
    CEFBS_None, // G_FCOSH = 251
    CEFBS_None, // G_FSINH = 252
    CEFBS_None, // G_FTANH = 253
    CEFBS_None, // G_FSQRT = 254
    CEFBS_None, // G_FFLOOR = 255
    CEFBS_None, // G_FRINT = 256
    CEFBS_None, // G_FNEARBYINT = 257
    CEFBS_None, // G_ADDRSPACE_CAST = 258
    CEFBS_None, // G_BLOCK_ADDR = 259
    CEFBS_None, // G_JUMP_TABLE = 260
    CEFBS_None, // G_DYN_STACKALLOC = 261
    CEFBS_None, // G_STACKSAVE = 262
    CEFBS_None, // G_STACKRESTORE = 263
    CEFBS_None, // G_STRICT_FADD = 264
    CEFBS_None, // G_STRICT_FSUB = 265
    CEFBS_None, // G_STRICT_FMUL = 266
    CEFBS_None, // G_STRICT_FDIV = 267
    CEFBS_None, // G_STRICT_FREM = 268
    CEFBS_None, // G_STRICT_FMA = 269
    CEFBS_None, // G_STRICT_FSQRT = 270
    CEFBS_None, // G_STRICT_FLDEXP = 271
    CEFBS_None, // G_READ_REGISTER = 272
    CEFBS_None, // G_WRITE_REGISTER = 273
    CEFBS_None, // G_MEMCPY = 274
    CEFBS_None, // G_MEMCPY_INLINE = 275
    CEFBS_None, // G_MEMMOVE = 276
    CEFBS_None, // G_MEMSET = 277
    CEFBS_None, // G_BZERO = 278
    CEFBS_None, // G_TRAP = 279
    CEFBS_None, // G_DEBUGTRAP = 280
    CEFBS_None, // G_UBSANTRAP = 281
    CEFBS_None, // G_VECREDUCE_SEQ_FADD = 282
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 283
    CEFBS_None, // G_VECREDUCE_FADD = 284
    CEFBS_None, // G_VECREDUCE_FMUL = 285
    CEFBS_None, // G_VECREDUCE_FMAX = 286
    CEFBS_None, // G_VECREDUCE_FMIN = 287
    CEFBS_None, // G_VECREDUCE_FMAXIMUM = 288
    CEFBS_None, // G_VECREDUCE_FMINIMUM = 289
    CEFBS_None, // G_VECREDUCE_ADD = 290
    CEFBS_None, // G_VECREDUCE_MUL = 291
    CEFBS_None, // G_VECREDUCE_AND = 292
    CEFBS_None, // G_VECREDUCE_OR = 293
    CEFBS_None, // G_VECREDUCE_XOR = 294
    CEFBS_None, // G_VECREDUCE_SMAX = 295
    CEFBS_None, // G_VECREDUCE_SMIN = 296
    CEFBS_None, // G_VECREDUCE_UMAX = 297
    CEFBS_None, // G_VECREDUCE_UMIN = 298
    CEFBS_None, // G_SBFX = 299
    CEFBS_None, // G_UBFX = 300
    CEFBS_None, // ADJCALLSTACKDOWN = 301
    CEFBS_None, // ADJCALLSTACKUP = 302
    CEFBS_None, // ADJDYNALLOC = 303
    CEFBS_None, // CALL = 304
    CEFBS_None, // CALLR = 305
    CEFBS_None, // ADDC_F_I_HI = 306
    CEFBS_None, // ADDC_F_I_LO = 307
    CEFBS_None, // ADDC_F_R = 308
    CEFBS_None, // ADDC_I_HI = 309
    CEFBS_None, // ADDC_I_LO = 310
    CEFBS_None, // ADDC_R = 311
    CEFBS_None, // ADD_F_I_HI = 312
    CEFBS_None, // ADD_F_I_LO = 313
    CEFBS_None, // ADD_F_R = 314
    CEFBS_None, // ADD_I_HI = 315
    CEFBS_None, // ADD_I_LO = 316
    CEFBS_None, // ADD_R = 317
    CEFBS_None, // AND_F_I_HI = 318
    CEFBS_None, // AND_F_I_LO = 319
    CEFBS_None, // AND_F_R = 320
    CEFBS_None, // AND_I_HI = 321
    CEFBS_None, // AND_I_LO = 322
    CEFBS_None, // AND_R = 323
    CEFBS_None, // BRCC = 324
    CEFBS_None, // BRIND_CC = 325
    CEFBS_None, // BRIND_CCA = 326
    CEFBS_None, // BRR = 327
    CEFBS_None, // BT = 328
    CEFBS_None, // JR = 329
    CEFBS_None, // LDADDR = 330
    CEFBS_None, // LDBs_RI = 331
    CEFBS_None, // LDBs_RR = 332
    CEFBS_None, // LDBz_RI = 333
    CEFBS_None, // LDBz_RR = 334
    CEFBS_None, // LDHs_RI = 335
    CEFBS_None, // LDHs_RR = 336
    CEFBS_None, // LDHz_RI = 337
    CEFBS_None, // LDHz_RR = 338
    CEFBS_None, // LDW_RI = 339
    CEFBS_None, // LDW_RR = 340
    CEFBS_None, // LDWz_RR = 341
    CEFBS_None, // LEADZ = 342
    CEFBS_None, // LOG0 = 343
    CEFBS_None, // LOG1 = 344
    CEFBS_None, // LOG2 = 345
    CEFBS_None, // LOG3 = 346
    CEFBS_None, // LOG4 = 347
    CEFBS_None, // MOVHI = 348
    CEFBS_None, // NOP = 349
    CEFBS_None, // OR_F_I_HI = 350
    CEFBS_None, // OR_F_I_LO = 351
    CEFBS_None, // OR_F_R = 352
    CEFBS_None, // OR_I_HI = 353
    CEFBS_None, // OR_I_LO = 354
    CEFBS_None, // OR_R = 355
    CEFBS_None, // POPC = 356
    CEFBS_None, // RET = 357
    CEFBS_None, // SA_F_I = 358
    CEFBS_None, // SA_I = 359
    CEFBS_None, // SCC = 360
    CEFBS_None, // SELECT = 361
    CEFBS_None, // SFSUB_F_RI_HI = 362
    CEFBS_None, // SFSUB_F_RI_LO = 363
    CEFBS_None, // SFSUB_F_RR = 364
    CEFBS_None, // SHL_F_R = 365
    CEFBS_None, // SHL_R = 366
    CEFBS_None, // SLI = 367
    CEFBS_None, // SL_F_I = 368
    CEFBS_None, // SL_I = 369
    CEFBS_None, // SRA_F_R = 370
    CEFBS_None, // SRA_R = 371
    CEFBS_None, // SRL_F_R = 372
    CEFBS_None, // SRL_R = 373
    CEFBS_None, // STADDR = 374
    CEFBS_None, // STB_RI = 375
    CEFBS_None, // STB_RR = 376
    CEFBS_None, // STH_RI = 377
    CEFBS_None, // STH_RR = 378
    CEFBS_None, // SUBB_F_I_HI = 379
    CEFBS_None, // SUBB_F_I_LO = 380
    CEFBS_None, // SUBB_F_R = 381
    CEFBS_None, // SUBB_I_HI = 382
    CEFBS_None, // SUBB_I_LO = 383
    CEFBS_None, // SUBB_R = 384
    CEFBS_None, // SUB_F_I_HI = 385
    CEFBS_None, // SUB_F_I_LO = 386
    CEFBS_None, // SUB_F_R = 387
    CEFBS_None, // SUB_I_HI = 388
    CEFBS_None, // SUB_I_LO = 389
    CEFBS_None, // SUB_R = 390
    CEFBS_None, // SW_RI = 391
    CEFBS_None, // SW_RR = 392
    CEFBS_None, // TRAILZ = 393
    CEFBS_None, // XOR_F_I_HI = 394
    CEFBS_None, // XOR_F_I_LO = 395
    CEFBS_None, // XOR_F_R = 396
    CEFBS_None, // XOR_I_HI = 397
    CEFBS_None, // XOR_I_LO = 398
    CEFBS_None, // XOR_R = 399
  };

  assert(Opcode < 400);
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
}

} // end namespace Lanai_MC
} // end namespace llvm
#endif // GET_COMPUTE_FEATURES

#ifdef GET_AVAILABLE_OPCODE_CHECKER
#undef GET_AVAILABLE_OPCODE_CHECKER
namespace llvm {
namespace Lanai_MC {
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  return !MissingFeatures.any();
}
} // end namespace Lanai_MC
} // end namespace llvm
#endif // GET_AVAILABLE_OPCODE_CHECKER

#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
#undef ENABLE_INSTR_PREDICATE_VERIFIER
#include <sstream>

namespace llvm {
namespace Lanai_MC {

#ifndef NDEBUG
static const char *SubtargetFeatureNames[] = {
  nullptr
};

#endif // NDEBUG

void verifyInstructionPredicates(
    unsigned Opcode, const FeatureBitset &Features) {
#ifndef NDEBUG
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  if (MissingFeatures.any()) {
    std::ostringstream Msg;
    Msg << "Attempting to emit " << &LanaiInstrNameData[LanaiInstrNameIndices[Opcode]]
        << " instruction but the ";
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
      if (MissingFeatures.test(i))
        Msg << SubtargetFeatureNames[i] << " ";
    Msg << "predicate(s) are not met";
    report_fatal_error(Msg.str().c_str());
  }
#endif // NDEBUG
}
} // end namespace Lanai_MC
} // end namespace llvm
#endif // ENABLE_INSTR_PREDICATE_VERIFIER

#ifdef GET_INSTRMAP_INFO
#undef GET_INSTRMAP_INFO
namespace llvm {

namespace Lanai {

enum PostEncoderMethod {
	PostEncoderMethod_adjustPqBitsSpls
};

// splsIdempotent
LLVM_READONLY
int splsIdempotent(uint16_t Opcode) {
static const uint16_t splsIdempotentTable[][2] = {
  { Lanai::LDBs_RI, Lanai::LDBs_RI },
  { Lanai::LDBz_RI, Lanai::LDBz_RI },
  { Lanai::LDHs_RI, Lanai::LDHs_RI },
  { Lanai::LDHz_RI, Lanai::LDHz_RI },
  { Lanai::STB_RI, Lanai::STB_RI },
  { Lanai::STH_RI, Lanai::STH_RI },
}; // End of splsIdempotentTable

  unsigned mid;
  unsigned start = 0;
  unsigned end = 6;
  while (start < end) {
    mid = start + (end - start) / 2;
    if (Opcode == splsIdempotentTable[mid][0]) {
      break;
    }
    if (Opcode < splsIdempotentTable[mid][0])
      end = mid;
    else
      start = mid + 1;
  }
  if (start == end)
    return -1; // Instruction doesn't exist in this table.

  return splsIdempotentTable[mid][1];
}

} // end namespace Lanai
} // end namespace llvm
#endif // GET_INSTRMAP_INFO