/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM namespace llvm { namespace LoongArch { enum { … }; } // end namespace LoongArch } // end namespace llvm #endif // GET_INSTRINFO_ENUM #ifdef GET_INSTRINFO_SCHED_ENUM #undef GET_INSTRINFO_SCHED_ENUM namespace llvm { namespace LoongArch { namespace Sched { enum { NoInstrModel = 0, SCHED_LIST_END = 1 }; } // end namespace Sched } // end namespace LoongArch } // end namespace llvm #endif // GET_INSTRINFO_SCHED_ENUM #if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) namespace llvm { struct LoongArchInstrTable { MCInstrDesc Insts[2435]; static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo"); MCOperandInfo OperandInfo[417]; static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps"); MCPhysReg ImplicitOps[8]; }; } // end namespace llvm #endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) #ifdef GET_INSTRINFO_MC_DESC #undef GET_INSTRINFO_MC_DESC namespace llvm { static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0); static constexpr unsigned LoongArchImpOpBase = sizeof LoongArchInstrTable::OperandInfo / (sizeof(MCPhysReg)); extern const LoongArchInstrTable LoongArchDescs = { { { 2434, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2434 = XVXOR_V { 2433, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2433 = XVXORI_B { 2432, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2432 = XVSUB_W { 2431, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2431 = XVSUB_Q { 2430, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2430 = XVSUB_H { 2429, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2429 = XVSUB_D { 2428, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2428 = XVSUB_B { 2427, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2427 = XVSUBWOD_W_HU { 2426, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2426 = XVSUBWOD_W_H { 2425, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2425 = XVSUBWOD_Q_DU { 2424, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2424 = XVSUBWOD_Q_D { 2423, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2423 = XVSUBWOD_H_BU { 2422, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2422 = XVSUBWOD_H_B { 2421, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2421 = XVSUBWOD_D_WU { 2420, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2420 = XVSUBWOD_D_W { 2419, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2419 = XVSUBWEV_W_HU { 2418, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2418 = XVSUBWEV_W_H { 2417, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2417 = XVSUBWEV_Q_DU { 2416, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2416 = XVSUBWEV_Q_D { 2415, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2415 = XVSUBWEV_H_BU { 2414, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2414 = XVSUBWEV_H_B { 2413, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2413 = XVSUBWEV_D_WU { 2412, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2412 = XVSUBWEV_D_W { 2411, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2411 = XVSUBI_WU { 2410, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2410 = XVSUBI_HU { 2409, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2409 = XVSUBI_DU { 2408, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2408 = XVSUBI_BU { 2407, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 400, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2407 = XVSTX { 2406, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 413, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2406 = XVSTELM_W { 2405, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 413, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2405 = XVSTELM_H { 2404, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 413, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2404 = XVSTELM_D { 2403, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 413, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2403 = XVSTELM_B { 2402, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 397, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2402 = XVST { 2401, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2401 = XVSSUB_WU { 2400, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2400 = XVSSUB_W { 2399, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2399 = XVSSUB_HU { 2398, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2398 = XVSSUB_H { 2397, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2397 = XVSSUB_DU { 2396, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2396 = XVSSUB_D { 2395, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2395 = XVSSUB_BU { 2394, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2394 = XVSSUB_B { 2393, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2393 = XVSSRLRN_W_D { 2392, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2392 = XVSSRLRN_WU_D { 2391, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2391 = XVSSRLRN_H_W { 2390, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2390 = XVSSRLRN_HU_W { 2389, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2389 = XVSSRLRN_B_H { 2388, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2388 = XVSSRLRN_BU_H { 2387, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2387 = XVSSRLRNI_W_D { 2386, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2386 = XVSSRLRNI_WU_D { 2385, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2385 = XVSSRLRNI_H_W { 2384, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2384 = XVSSRLRNI_HU_W { 2383, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2383 = XVSSRLRNI_D_Q { 2382, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2382 = XVSSRLRNI_DU_Q { 2381, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2381 = XVSSRLRNI_B_H { 2380, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2380 = XVSSRLRNI_BU_H { 2379, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2379 = XVSSRLN_W_D { 2378, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2378 = XVSSRLN_WU_D { 2377, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2377 = XVSSRLN_H_W { 2376, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2376 = XVSSRLN_HU_W { 2375, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2375 = XVSSRLN_B_H { 2374, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2374 = XVSSRLN_BU_H { 2373, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2373 = XVSSRLNI_W_D { 2372, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2372 = XVSSRLNI_WU_D { 2371, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2371 = XVSSRLNI_H_W { 2370, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2370 = XVSSRLNI_HU_W { 2369, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2369 = XVSSRLNI_D_Q { 2368, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2368 = XVSSRLNI_DU_Q { 2367, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2367 = XVSSRLNI_B_H { 2366, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2366 = XVSSRLNI_BU_H { 2365, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2365 = XVSSRARN_W_D { 2364, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2364 = XVSSRARN_WU_D { 2363, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2363 = XVSSRARN_H_W { 2362, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2362 = XVSSRARN_HU_W { 2361, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2361 = XVSSRARN_B_H { 2360, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2360 = XVSSRARN_BU_H { 2359, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2359 = XVSSRARNI_W_D { 2358, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2358 = XVSSRARNI_WU_D { 2357, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2357 = XVSSRARNI_H_W { 2356, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2356 = XVSSRARNI_HU_W { 2355, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2355 = XVSSRARNI_D_Q { 2354, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2354 = XVSSRARNI_DU_Q { 2353, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2353 = XVSSRARNI_B_H { 2352, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2352 = XVSSRARNI_BU_H { 2351, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2351 = XVSSRAN_W_D { 2350, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2350 = XVSSRAN_WU_D { 2349, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2349 = XVSSRAN_H_W { 2348, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2348 = XVSSRAN_HU_W { 2347, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2347 = XVSSRAN_B_H { 2346, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2346 = XVSSRAN_BU_H { 2345, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2345 = XVSSRANI_W_D { 2344, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2344 = XVSSRANI_WU_D { 2343, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2343 = XVSSRANI_H_W { 2342, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2342 = XVSSRANI_HU_W { 2341, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2341 = XVSSRANI_D_Q { 2340, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2340 = XVSSRANI_DU_Q { 2339, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2339 = XVSSRANI_B_H { 2338, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2338 = XVSSRANI_BU_H { 2337, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2337 = XVSRL_W { 2336, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2336 = XVSRL_H { 2335, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2335 = XVSRL_D { 2334, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2334 = XVSRL_B { 2333, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2333 = XVSRLR_W { 2332, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2332 = XVSRLR_H { 2331, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2331 = XVSRLR_D { 2330, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2330 = XVSRLR_B { 2329, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2329 = XVSRLRN_W_D { 2328, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2328 = XVSRLRN_H_W { 2327, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2327 = XVSRLRN_B_H { 2326, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2326 = XVSRLRNI_W_D { 2325, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2325 = XVSRLRNI_H_W { 2324, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2324 = XVSRLRNI_D_Q { 2323, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2323 = XVSRLRNI_B_H { 2322, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2322 = XVSRLRI_W { 2321, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2321 = XVSRLRI_H { 2320, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2320 = XVSRLRI_D { 2319, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2319 = XVSRLRI_B { 2318, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2318 = XVSRLN_W_D { 2317, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2317 = XVSRLN_H_W { 2316, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2316 = XVSRLN_B_H { 2315, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2315 = XVSRLNI_W_D { 2314, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2314 = XVSRLNI_H_W { 2313, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2313 = XVSRLNI_D_Q { 2312, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2312 = XVSRLNI_B_H { 2311, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2311 = XVSRLI_W { 2310, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2310 = XVSRLI_H { 2309, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2309 = XVSRLI_D { 2308, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2308 = XVSRLI_B { 2307, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2307 = XVSRA_W { 2306, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2306 = XVSRA_H { 2305, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2305 = XVSRA_D { 2304, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2304 = XVSRA_B { 2303, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2303 = XVSRAR_W { 2302, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2302 = XVSRAR_H { 2301, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2301 = XVSRAR_D { 2300, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2300 = XVSRAR_B { 2299, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2299 = XVSRARN_W_D { 2298, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2298 = XVSRARN_H_W { 2297, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2297 = XVSRARN_B_H { 2296, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2296 = XVSRARNI_W_D { 2295, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2295 = XVSRARNI_H_W { 2294, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2294 = XVSRARNI_D_Q { 2293, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2293 = XVSRARNI_B_H { 2292, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2292 = XVSRARI_W { 2291, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2291 = XVSRARI_H { 2290, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2290 = XVSRARI_D { 2289, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2289 = XVSRARI_B { 2288, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2288 = XVSRAN_W_D { 2287, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2287 = XVSRAN_H_W { 2286, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2286 = XVSRAN_B_H { 2285, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2285 = XVSRANI_W_D { 2284, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2284 = XVSRANI_H_W { 2283, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2283 = XVSRANI_D_Q { 2282, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2282 = XVSRANI_B_H { 2281, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2281 = XVSRAI_W { 2280, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2280 = XVSRAI_H { 2279, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2279 = XVSRAI_D { 2278, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2278 = XVSRAI_B { 2277, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2277 = XVSLT_WU { 2276, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2276 = XVSLT_W { 2275, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2275 = XVSLT_HU { 2274, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2274 = XVSLT_H { 2273, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2273 = XVSLT_DU { 2272, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2272 = XVSLT_D { 2271, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2271 = XVSLT_BU { 2270, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2270 = XVSLT_B { 2269, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2269 = XVSLTI_WU { 2268, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2268 = XVSLTI_W { 2267, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2267 = XVSLTI_HU { 2266, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2266 = XVSLTI_H { 2265, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2265 = XVSLTI_DU { 2264, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2264 = XVSLTI_D { 2263, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2263 = XVSLTI_BU { 2262, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2262 = XVSLTI_B { 2261, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2261 = XVSLL_W { 2260, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2260 = XVSLL_H { 2259, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2259 = XVSLL_D { 2258, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2258 = XVSLL_B { 2257, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2257 = XVSLLWIL_W_H { 2256, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2256 = XVSLLWIL_WU_HU { 2255, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2255 = XVSLLWIL_H_B { 2254, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2254 = XVSLLWIL_HU_BU { 2253, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2253 = XVSLLWIL_D_W { 2252, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2252 = XVSLLWIL_DU_WU { 2251, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2251 = XVSLLI_W { 2250, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2250 = XVSLLI_H { 2249, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2249 = XVSLLI_D { 2248, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2248 = XVSLLI_B { 2247, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2247 = XVSLE_WU { 2246, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2246 = XVSLE_W { 2245, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2245 = XVSLE_HU { 2244, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2244 = XVSLE_H { 2243, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2243 = XVSLE_DU { 2242, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2242 = XVSLE_D { 2241, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2241 = XVSLE_BU { 2240, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2240 = XVSLE_B { 2239, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2239 = XVSLEI_WU { 2238, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2238 = XVSLEI_W { 2237, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2237 = XVSLEI_HU { 2236, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2236 = XVSLEI_H { 2235, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2235 = XVSLEI_DU { 2234, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2234 = XVSLEI_D { 2233, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2233 = XVSLEI_BU { 2232, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2232 = XVSLEI_B { 2231, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2231 = XVSIGNCOV_W { 2230, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2230 = XVSIGNCOV_H { 2229, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2229 = XVSIGNCOV_D { 2228, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2228 = XVSIGNCOV_B { 2227, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2227 = XVSHUF_W { 2226, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2226 = XVSHUF_H { 2225, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2225 = XVSHUF_D { 2224, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #2224 = XVSHUF_B { 2223, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2223 = XVSHUF4I_W { 2222, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2222 = XVSHUF4I_H { 2221, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2221 = XVSHUF4I_D { 2220, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2220 = XVSHUF4I_B { 2219, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2219 = XVSETNEZ_V { 2218, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2218 = XVSETEQZ_V { 2217, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2217 = XVSETANYEQZ_W { 2216, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2216 = XVSETANYEQZ_H { 2215, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2215 = XVSETANYEQZ_D { 2214, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2214 = XVSETANYEQZ_B { 2213, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2213 = XVSETALLNEZ_W { 2212, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2212 = XVSETALLNEZ_H { 2211, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2211 = XVSETALLNEZ_D { 2210, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2210 = XVSETALLNEZ_B { 2209, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2209 = XVSEQ_W { 2208, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2208 = XVSEQ_H { 2207, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2207 = XVSEQ_D { 2206, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2206 = XVSEQ_B { 2205, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2205 = XVSEQI_W { 2204, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2204 = XVSEQI_H { 2203, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2203 = XVSEQI_D { 2202, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2202 = XVSEQI_B { 2201, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2201 = XVSAT_WU { 2200, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2200 = XVSAT_W { 2199, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2199 = XVSAT_HU { 2198, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2198 = XVSAT_H { 2197, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2197 = XVSAT_DU { 2196, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2196 = XVSAT_D { 2195, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2195 = XVSAT_BU { 2194, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2194 = XVSAT_B { 2193, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2193 = XVSADD_WU { 2192, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2192 = XVSADD_W { 2191, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2191 = XVSADD_HU { 2190, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2190 = XVSADD_H { 2189, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2189 = XVSADD_DU { 2188, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2188 = XVSADD_D { 2187, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2187 = XVSADD_BU { 2186, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2186 = XVSADD_B { 2185, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2185 = XVROTR_W { 2184, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2184 = XVROTR_H { 2183, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2183 = XVROTR_D { 2182, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2182 = XVROTR_B { 2181, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2181 = XVROTRI_W { 2180, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2180 = XVROTRI_H { 2179, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2179 = XVROTRI_D { 2178, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2178 = XVROTRI_B { 2177, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 408, 0, 0x0ULL }, // Inst #2177 = XVREPLVE_W { 2176, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 408, 0, 0x0ULL }, // Inst #2176 = XVREPLVE_H { 2175, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 408, 0, 0x0ULL }, // Inst #2175 = XVREPLVE_D { 2174, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 408, 0, 0x0ULL }, // Inst #2174 = XVREPLVE_B { 2173, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2173 = XVREPLVE0_W { 2172, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2172 = XVREPLVE0_Q { 2171, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2171 = XVREPLVE0_H { 2170, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2170 = XVREPLVE0_D { 2169, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2169 = XVREPLVE0_B { 2168, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 406, 0, 0x0ULL }, // Inst #2168 = XVREPLGR2VR_W { 2167, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 406, 0, 0x0ULL }, // Inst #2167 = XVREPLGR2VR_H { 2166, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 406, 0, 0x0ULL }, // Inst #2166 = XVREPLGR2VR_D { 2165, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 406, 0, 0x0ULL }, // Inst #2165 = XVREPLGR2VR_B { 2164, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2164 = XVREPL128VEI_W { 2163, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2163 = XVREPL128VEI_H { 2162, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2162 = XVREPL128VEI_D { 2161, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2161 = XVREPL128VEI_B { 2160, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2160 = XVPICKVE_W { 2159, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2159 = XVPICKVE_D { 2158, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 403, 0, 0x0ULL }, // Inst #2158 = XVPICKVE2GR_WU { 2157, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 403, 0, 0x0ULL }, // Inst #2157 = XVPICKVE2GR_W { 2156, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 403, 0, 0x0ULL }, // Inst #2156 = XVPICKVE2GR_DU { 2155, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 403, 0, 0x0ULL }, // Inst #2155 = XVPICKVE2GR_D { 2154, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2154 = XVPICKOD_W { 2153, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2153 = XVPICKOD_H { 2152, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2152 = XVPICKOD_D { 2151, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2151 = XVPICKOD_B { 2150, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2150 = XVPICKEV_W { 2149, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2149 = XVPICKEV_H { 2148, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2148 = XVPICKEV_D { 2147, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2147 = XVPICKEV_B { 2146, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2146 = XVPERM_W { 2145, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2145 = XVPERMI_W { 2144, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2144 = XVPERMI_Q { 2143, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2143 = XVPERMI_D { 2142, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2142 = XVPCNT_W { 2141, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2141 = XVPCNT_H { 2140, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2140 = XVPCNT_D { 2139, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2139 = XVPCNT_B { 2138, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2138 = XVPACKOD_W { 2137, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2137 = XVPACKOD_H { 2136, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2136 = XVPACKOD_D { 2135, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2135 = XVPACKOD_B { 2134, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2134 = XVPACKEV_W { 2133, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2133 = XVPACKEV_H { 2132, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2132 = XVPACKEV_D { 2131, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2131 = XVPACKEV_B { 2130, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2130 = XVOR_V { 2129, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2129 = XVORN_V { 2128, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2128 = XVORI_B { 2127, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2127 = XVNOR_V { 2126, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2126 = XVNORI_B { 2125, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2125 = XVNEG_W { 2124, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2124 = XVNEG_H { 2123, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2123 = XVNEG_D { 2122, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2122 = XVNEG_B { 2121, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2121 = XVMUL_W { 2120, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2120 = XVMUL_H { 2119, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2119 = XVMUL_D { 2118, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2118 = XVMUL_B { 2117, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2117 = XVMULWOD_W_HU_H { 2116, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2116 = XVMULWOD_W_HU { 2115, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2115 = XVMULWOD_W_H { 2114, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2114 = XVMULWOD_Q_DU_D { 2113, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2113 = XVMULWOD_Q_DU { 2112, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2112 = XVMULWOD_Q_D { 2111, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2111 = XVMULWOD_H_BU_B { 2110, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2110 = XVMULWOD_H_BU { 2109, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2109 = XVMULWOD_H_B { 2108, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2108 = XVMULWOD_D_WU_W { 2107, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2107 = XVMULWOD_D_WU { 2106, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2106 = XVMULWOD_D_W { 2105, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2105 = XVMULWEV_W_HU_H { 2104, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2104 = XVMULWEV_W_HU { 2103, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2103 = XVMULWEV_W_H { 2102, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2102 = XVMULWEV_Q_DU_D { 2101, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2101 = XVMULWEV_Q_DU { 2100, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2100 = XVMULWEV_Q_D { 2099, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2099 = XVMULWEV_H_BU_B { 2098, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2098 = XVMULWEV_H_BU { 2097, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2097 = XVMULWEV_H_B { 2096, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2096 = XVMULWEV_D_WU_W { 2095, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2095 = XVMULWEV_D_WU { 2094, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2094 = XVMULWEV_D_W { 2093, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2093 = XVMUH_WU { 2092, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2092 = XVMUH_W { 2091, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2091 = XVMUH_HU { 2090, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2090 = XVMUH_H { 2089, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2089 = XVMUH_DU { 2088, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2088 = XVMUH_D { 2087, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2087 = XVMUH_BU { 2086, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2086 = XVMUH_B { 2085, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2085 = XVMSUB_W { 2084, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2084 = XVMSUB_H { 2083, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2083 = XVMSUB_D { 2082, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2082 = XVMSUB_B { 2081, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2081 = XVMSKNZ_B { 2080, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2080 = XVMSKLTZ_W { 2079, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2079 = XVMSKLTZ_H { 2078, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2078 = XVMSKLTZ_D { 2077, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2077 = XVMSKLTZ_B { 2076, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2076 = XVMSKGEZ_B { 2075, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2075 = XVMOD_WU { 2074, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2074 = XVMOD_W { 2073, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2073 = XVMOD_HU { 2072, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2072 = XVMOD_H { 2071, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2071 = XVMOD_DU { 2070, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2070 = XVMOD_D { 2069, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2069 = XVMOD_BU { 2068, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2068 = XVMOD_B { 2067, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2067 = XVMIN_WU { 2066, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2066 = XVMIN_W { 2065, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2065 = XVMIN_HU { 2064, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2064 = XVMIN_H { 2063, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2063 = XVMIN_DU { 2062, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2062 = XVMIN_D { 2061, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2061 = XVMIN_BU { 2060, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2060 = XVMIN_B { 2059, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2059 = XVMINI_WU { 2058, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2058 = XVMINI_W { 2057, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2057 = XVMINI_HU { 2056, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2056 = XVMINI_H { 2055, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2055 = XVMINI_DU { 2054, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2054 = XVMINI_D { 2053, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2053 = XVMINI_BU { 2052, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2052 = XVMINI_B { 2051, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2051 = XVMAX_WU { 2050, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2050 = XVMAX_W { 2049, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2049 = XVMAX_HU { 2048, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2048 = XVMAX_H { 2047, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2047 = XVMAX_DU { 2046, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2046 = XVMAX_D { 2045, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2045 = XVMAX_BU { 2044, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2044 = XVMAX_B { 2043, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2043 = XVMAXI_WU { 2042, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2042 = XVMAXI_W { 2041, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2041 = XVMAXI_HU { 2040, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2040 = XVMAXI_H { 2039, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2039 = XVMAXI_DU { 2038, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2038 = XVMAXI_D { 2037, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2037 = XVMAXI_BU { 2036, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2036 = XVMAXI_B { 2035, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2035 = XVMADD_W { 2034, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2034 = XVMADD_H { 2033, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2033 = XVMADD_D { 2032, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2032 = XVMADD_B { 2031, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2031 = XVMADDWOD_W_HU_H { 2030, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2030 = XVMADDWOD_W_HU { 2029, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2029 = XVMADDWOD_W_H { 2028, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2028 = XVMADDWOD_Q_DU_D { 2027, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2027 = XVMADDWOD_Q_DU { 2026, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2026 = XVMADDWOD_Q_D { 2025, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2025 = XVMADDWOD_H_BU_B { 2024, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2024 = XVMADDWOD_H_BU { 2023, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2023 = XVMADDWOD_H_B { 2022, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2022 = XVMADDWOD_D_WU_W { 2021, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2021 = XVMADDWOD_D_WU { 2020, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2020 = XVMADDWOD_D_W { 2019, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2019 = XVMADDWEV_W_HU_H { 2018, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2018 = XVMADDWEV_W_HU { 2017, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2017 = XVMADDWEV_W_H { 2016, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2016 = XVMADDWEV_Q_DU_D { 2015, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2015 = XVMADDWEV_Q_DU { 2014, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2014 = XVMADDWEV_Q_D { 2013, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2013 = XVMADDWEV_H_BU_B { 2012, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2012 = XVMADDWEV_H_BU { 2011, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2011 = XVMADDWEV_H_B { 2010, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2010 = XVMADDWEV_D_WU_W { 2009, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2009 = XVMADDWEV_D_WU { 2008, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2008 = XVMADDWEV_D_W { 2007, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 400, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2007 = XVLDX { 2006, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 397, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2006 = XVLDREPL_W { 2005, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 397, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2005 = XVLDREPL_H { 2004, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 397, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2004 = XVLDREPL_D { 2003, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 397, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2003 = XVLDREPL_B { 2002, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 216, 0, 0x0ULL }, // Inst #2002 = XVLDI { 2001, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 397, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2001 = XVLD { 2000, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2000 = XVINSVE0_W { 1999, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1999 = XVINSVE0_D { 1998, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 212, 0, 0x0ULL }, // Inst #1998 = XVINSGR2VR_W { 1997, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 212, 0, 0x0ULL }, // Inst #1997 = XVINSGR2VR_D { 1996, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1996 = XVILVL_W { 1995, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1995 = XVILVL_H { 1994, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1994 = XVILVL_D { 1993, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1993 = XVILVL_B { 1992, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1992 = XVILVH_W { 1991, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1991 = XVILVH_H { 1990, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1990 = XVILVH_D { 1989, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1989 = XVILVH_B { 1988, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1988 = XVHSUBW_W_H { 1987, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1987 = XVHSUBW_WU_HU { 1986, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1986 = XVHSUBW_Q_D { 1985, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1985 = XVHSUBW_QU_DU { 1984, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1984 = XVHSUBW_H_B { 1983, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1983 = XVHSUBW_HU_BU { 1982, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1982 = XVHSUBW_D_W { 1981, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1981 = XVHSUBW_DU_WU { 1980, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1980 = XVHSELI_D { 1979, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1979 = XVHADDW_W_H { 1978, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1978 = XVHADDW_WU_HU { 1977, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1977 = XVHADDW_Q_D { 1976, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1976 = XVHADDW_QU_DU { 1975, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1975 = XVHADDW_H_B { 1974, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1974 = XVHADDW_HU_BU { 1973, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1973 = XVHADDW_D_W { 1972, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1972 = XVHADDW_DU_WU { 1971, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1971 = XVFTINT_W_S { 1970, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1970 = XVFTINT_W_D { 1969, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1969 = XVFTINT_WU_S { 1968, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1968 = XVFTINT_L_D { 1967, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1967 = XVFTINT_LU_D { 1966, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1966 = XVFTINTRZ_W_S { 1965, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1965 = XVFTINTRZ_W_D { 1964, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1964 = XVFTINTRZ_WU_S { 1963, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1963 = XVFTINTRZ_L_D { 1962, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1962 = XVFTINTRZ_LU_D { 1961, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1961 = XVFTINTRZL_L_S { 1960, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1960 = XVFTINTRZH_L_S { 1959, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1959 = XVFTINTRP_W_S { 1958, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1958 = XVFTINTRP_W_D { 1957, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1957 = XVFTINTRP_L_D { 1956, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1956 = XVFTINTRPL_L_S { 1955, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1955 = XVFTINTRPH_L_S { 1954, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1954 = XVFTINTRNE_W_S { 1953, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1953 = XVFTINTRNE_W_D { 1952, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1952 = XVFTINTRNE_L_D { 1951, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1951 = XVFTINTRNEL_L_S { 1950, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1950 = XVFTINTRNEH_L_S { 1949, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1949 = XVFTINTRM_W_S { 1948, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1948 = XVFTINTRM_W_D { 1947, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1947 = XVFTINTRM_L_D { 1946, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1946 = XVFTINTRML_L_S { 1945, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1945 = XVFTINTRMH_L_S { 1944, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1944 = XVFTINTL_L_S { 1943, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1943 = XVFTINTH_L_S { 1942, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1942 = XVFSUB_S { 1941, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1941 = XVFSUB_D { 1940, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1940 = XVFSQRT_S { 1939, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1939 = XVFSQRT_D { 1938, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #1938 = XVFRSTP_H { 1937, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #1937 = XVFRSTP_B { 1936, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1936 = XVFRSTPI_H { 1935, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1935 = XVFRSTPI_B { 1934, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1934 = XVFRSQRT_S { 1933, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1933 = XVFRSQRT_D { 1932, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1932 = XVFRSQRTE_S { 1931, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1931 = XVFRSQRTE_D { 1930, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1930 = XVFRINT_S { 1929, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1929 = XVFRINT_D { 1928, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1928 = XVFRINTRZ_S { 1927, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1927 = XVFRINTRZ_D { 1926, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1926 = XVFRINTRP_S { 1925, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1925 = XVFRINTRP_D { 1924, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1924 = XVFRINTRNE_S { 1923, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1923 = XVFRINTRNE_D { 1922, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1922 = XVFRINTRM_S { 1921, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1921 = XVFRINTRM_D { 1920, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1920 = XVFRECIP_S { 1919, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1919 = XVFRECIP_D { 1918, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1918 = XVFRECIPE_S { 1917, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1917 = XVFRECIPE_D { 1916, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1916 = XVFNMSUB_S { 1915, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1915 = XVFNMSUB_D { 1914, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1914 = XVFNMADD_S { 1913, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1913 = XVFNMADD_D { 1912, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1912 = XVFMUL_S { 1911, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1911 = XVFMUL_D { 1910, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1910 = XVFMSUB_S { 1909, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1909 = XVFMSUB_D { 1908, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1908 = XVFMIN_S { 1907, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1907 = XVFMIN_D { 1906, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1906 = XVFMINA_S { 1905, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1905 = XVFMINA_D { 1904, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1904 = XVFMAX_S { 1903, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1903 = XVFMAX_D { 1902, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1902 = XVFMAXA_S { 1901, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1901 = XVFMAXA_D { 1900, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1900 = XVFMADD_S { 1899, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1899 = XVFMADD_D { 1898, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1898 = XVFLOGB_S { 1897, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1897 = XVFLOGB_D { 1896, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1896 = XVFFINT_S_WU { 1895, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1895 = XVFFINT_S_W { 1894, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1894 = XVFFINT_S_L { 1893, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1893 = XVFFINT_D_LU { 1892, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1892 = XVFFINT_D_L { 1891, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1891 = XVFFINTL_D_W { 1890, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1890 = XVFFINTH_D_W { 1889, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1889 = XVFDIV_S { 1888, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1888 = XVFDIV_D { 1887, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1887 = XVFCVT_S_D { 1886, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1886 = XVFCVT_H_S { 1885, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1885 = XVFCVTL_S_H { 1884, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1884 = XVFCVTL_D_S { 1883, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1883 = XVFCVTH_S_H { 1882, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1882 = XVFCVTH_D_S { 1881, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1881 = XVFCMP_SUN_S { 1880, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1880 = XVFCMP_SUN_D { 1879, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1879 = XVFCMP_SUNE_S { 1878, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1878 = XVFCMP_SUNE_D { 1877, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1877 = XVFCMP_SULT_S { 1876, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1876 = XVFCMP_SULT_D { 1875, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1875 = XVFCMP_SULE_S { 1874, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1874 = XVFCMP_SULE_D { 1873, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1873 = XVFCMP_SUEQ_S { 1872, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1872 = XVFCMP_SUEQ_D { 1871, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1871 = XVFCMP_SOR_S { 1870, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1870 = XVFCMP_SOR_D { 1869, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1869 = XVFCMP_SNE_S { 1868, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1868 = XVFCMP_SNE_D { 1867, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1867 = XVFCMP_SLT_S { 1866, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1866 = XVFCMP_SLT_D { 1865, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1865 = XVFCMP_SLE_S { 1864, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1864 = XVFCMP_SLE_D { 1863, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1863 = XVFCMP_SEQ_S { 1862, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1862 = XVFCMP_SEQ_D { 1861, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1861 = XVFCMP_SAF_S { 1860, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1860 = XVFCMP_SAF_D { 1859, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1859 = XVFCMP_CUN_S { 1858, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1858 = XVFCMP_CUN_D { 1857, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1857 = XVFCMP_CUNE_S { 1856, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1856 = XVFCMP_CUNE_D { 1855, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1855 = XVFCMP_CULT_S { 1854, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1854 = XVFCMP_CULT_D { 1853, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1853 = XVFCMP_CULE_S { 1852, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1852 = XVFCMP_CULE_D { 1851, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1851 = XVFCMP_CUEQ_S { 1850, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1850 = XVFCMP_CUEQ_D { 1849, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1849 = XVFCMP_COR_S { 1848, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1848 = XVFCMP_COR_D { 1847, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1847 = XVFCMP_CNE_S { 1846, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1846 = XVFCMP_CNE_D { 1845, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1845 = XVFCMP_CLT_S { 1844, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1844 = XVFCMP_CLT_D { 1843, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1843 = XVFCMP_CLE_S { 1842, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1842 = XVFCMP_CLE_D { 1841, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1841 = XVFCMP_CEQ_S { 1840, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1840 = XVFCMP_CEQ_D { 1839, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1839 = XVFCMP_CAF_S { 1838, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1838 = XVFCMP_CAF_D { 1837, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1837 = XVFCLASS_S { 1836, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1836 = XVFCLASS_D { 1835, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1835 = XVFADD_S { 1834, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1834 = XVFADD_D { 1833, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1833 = XVEXTRINS_W { 1832, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1832 = XVEXTRINS_H { 1831, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1831 = XVEXTRINS_D { 1830, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1830 = XVEXTRINS_B { 1829, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1829 = XVEXTL_Q_D { 1828, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1828 = XVEXTL_QU_DU { 1827, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1827 = XVEXTH_W_H { 1826, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1826 = XVEXTH_WU_HU { 1825, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1825 = XVEXTH_Q_D { 1824, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1824 = XVEXTH_QU_DU { 1823, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1823 = XVEXTH_H_B { 1822, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1822 = XVEXTH_HU_BU { 1821, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1821 = XVEXTH_D_W { 1820, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1820 = XVEXTH_DU_WU { 1819, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1819 = XVDIV_WU { 1818, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1818 = XVDIV_W { 1817, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1817 = XVDIV_HU { 1816, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1816 = XVDIV_H { 1815, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1815 = XVDIV_DU { 1814, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1814 = XVDIV_D { 1813, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1813 = XVDIV_BU { 1812, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1812 = XVDIV_B { 1811, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1811 = XVCLZ_W { 1810, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1810 = XVCLZ_H { 1809, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1809 = XVCLZ_D { 1808, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1808 = XVCLZ_B { 1807, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1807 = XVCLO_W { 1806, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1806 = XVCLO_H { 1805, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1805 = XVCLO_D { 1804, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1804 = XVCLO_B { 1803, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1803 = XVBSRL_V { 1802, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1802 = XVBSLL_V { 1801, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1801 = XVBITSET_W { 1800, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1800 = XVBITSET_H { 1799, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1799 = XVBITSET_D { 1798, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1798 = XVBITSET_B { 1797, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1797 = XVBITSETI_W { 1796, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1796 = XVBITSETI_H { 1795, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1795 = XVBITSETI_D { 1794, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1794 = XVBITSETI_B { 1793, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1793 = XVBITSEL_V { 1792, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1792 = XVBITSELI_B { 1791, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1791 = XVBITREV_W { 1790, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1790 = XVBITREV_H { 1789, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1789 = XVBITREV_D { 1788, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1788 = XVBITREV_B { 1787, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1787 = XVBITREVI_W { 1786, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1786 = XVBITREVI_H { 1785, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1785 = XVBITREVI_D { 1784, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1784 = XVBITREVI_B { 1783, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1783 = XVBITCLR_W { 1782, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1782 = XVBITCLR_H { 1781, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1781 = XVBITCLR_D { 1780, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1780 = XVBITCLR_B { 1779, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1779 = XVBITCLRI_W { 1778, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1778 = XVBITCLRI_H { 1777, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1777 = XVBITCLRI_D { 1776, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1776 = XVBITCLRI_B { 1775, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1775 = XVAVG_WU { 1774, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1774 = XVAVG_W { 1773, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1773 = XVAVG_HU { 1772, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1772 = XVAVG_H { 1771, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1771 = XVAVG_DU { 1770, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1770 = XVAVG_D { 1769, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1769 = XVAVG_BU { 1768, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1768 = XVAVG_B { 1767, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1767 = XVAVGR_WU { 1766, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1766 = XVAVGR_W { 1765, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1765 = XVAVGR_HU { 1764, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1764 = XVAVGR_H { 1763, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1763 = XVAVGR_DU { 1762, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1762 = XVAVGR_D { 1761, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1761 = XVAVGR_BU { 1760, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1760 = XVAVGR_B { 1759, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1759 = XVAND_V { 1758, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1758 = XVANDN_V { 1757, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1757 = XVANDI_B { 1756, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1756 = XVADD_W { 1755, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1755 = XVADD_Q { 1754, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1754 = XVADD_H { 1753, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1753 = XVADD_D { 1752, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1752 = XVADD_B { 1751, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1751 = XVADDWOD_W_HU_H { 1750, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1750 = XVADDWOD_W_HU { 1749, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1749 = XVADDWOD_W_H { 1748, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1748 = XVADDWOD_Q_DU_D { 1747, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1747 = XVADDWOD_Q_DU { 1746, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1746 = XVADDWOD_Q_D { 1745, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1745 = XVADDWOD_H_BU_B { 1744, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1744 = XVADDWOD_H_BU { 1743, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1743 = XVADDWOD_H_B { 1742, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1742 = XVADDWOD_D_WU_W { 1741, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1741 = XVADDWOD_D_WU { 1740, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1740 = XVADDWOD_D_W { 1739, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1739 = XVADDWEV_W_HU_H { 1738, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1738 = XVADDWEV_W_HU { 1737, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1737 = XVADDWEV_W_H { 1736, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1736 = XVADDWEV_Q_DU_D { 1735, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1735 = XVADDWEV_Q_DU { 1734, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1734 = XVADDWEV_Q_D { 1733, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1733 = XVADDWEV_H_BU_B { 1732, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1732 = XVADDWEV_H_BU { 1731, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1731 = XVADDWEV_H_B { 1730, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1730 = XVADDWEV_D_WU_W { 1729, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1729 = XVADDWEV_D_WU { 1728, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1728 = XVADDWEV_D_W { 1727, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1727 = XVADDI_WU { 1726, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1726 = XVADDI_HU { 1725, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1725 = XVADDI_DU { 1724, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1724 = XVADDI_BU { 1723, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1723 = XVADDA_W { 1722, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1722 = XVADDA_H { 1721, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1721 = XVADDA_D { 1720, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1720 = XVADDA_B { 1719, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1719 = XVABSD_WU { 1718, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1718 = XVABSD_W { 1717, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1717 = XVABSD_HU { 1716, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1716 = XVABSD_H { 1715, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1715 = XVABSD_DU { 1714, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1714 = XVABSD_D { 1713, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1713 = XVABSD_BU { 1712, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1712 = XVABSD_B { 1711, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1711 = XORI { 1710, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #1710 = XOR { 1709, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1709 = X86XOR_W { 1708, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1708 = X86XOR_H { 1707, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1707 = X86XOR_D { 1706, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1706 = X86XOR_B { 1705, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1705 = X86SUB_WU { 1704, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1704 = X86SUB_W { 1703, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1703 = X86SUB_H { 1702, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1702 = X86SUB_DU { 1701, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1701 = X86SUB_D { 1700, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1700 = X86SUB_B { 1699, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1699 = X86SRL_W { 1698, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1698 = X86SRL_H { 1697, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1697 = X86SRL_D { 1696, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1696 = X86SRL_B { 1695, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1695 = X86SRLI_W { 1694, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1694 = X86SRLI_H { 1693, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1693 = X86SRLI_D { 1692, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1692 = X86SRLI_B { 1691, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1691 = X86SRA_W { 1690, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1690 = X86SRA_H { 1689, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1689 = X86SRA_D { 1688, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1688 = X86SRA_B { 1687, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1687 = X86SRAI_W { 1686, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1686 = X86SRAI_H { 1685, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1685 = X86SRAI_D { 1684, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1684 = X86SRAI_B { 1683, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1683 = X86SLL_W { 1682, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1682 = X86SLL_H { 1681, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1681 = X86SLL_D { 1680, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1680 = X86SLL_B { 1679, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1679 = X86SLLI_W { 1678, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1678 = X86SLLI_H { 1677, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1677 = X86SLLI_D { 1676, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1676 = X86SLLI_B { 1675, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0, 0x0ULL }, // Inst #1675 = X86SETTM { 1674, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 223, 0, 0x0ULL }, // Inst #1674 = X86SETTAG { 1673, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1673 = X86SBC_W { 1672, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1672 = X86SBC_H { 1671, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1671 = X86SBC_D { 1670, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1670 = X86SBC_B { 1669, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1669 = X86ROTR_W { 1668, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1668 = X86ROTR_H { 1667, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1667 = X86ROTR_D { 1666, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1666 = X86ROTR_B { 1665, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1665 = X86ROTRI_W { 1664, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1664 = X86ROTRI_H { 1663, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1663 = X86ROTRI_D { 1662, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1662 = X86ROTRI_B { 1661, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1661 = X86ROTL_W { 1660, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1660 = X86ROTL_H { 1659, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1659 = X86ROTL_D { 1658, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1658 = X86ROTL_B { 1657, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1657 = X86ROTLI_W { 1656, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1656 = X86ROTLI_H { 1655, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1655 = X86ROTLI_D { 1654, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1654 = X86ROTLI_B { 1653, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1653 = X86RCR_W { 1652, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1652 = X86RCR_H { 1651, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1651 = X86RCR_D { 1650, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1650 = X86RCR_B { 1649, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1649 = X86RCRI_W { 1648, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1648 = X86RCRI_H { 1647, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1647 = X86RCRI_D { 1646, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1646 = X86RCRI_B { 1645, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1645 = X86RCL_W { 1644, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1644 = X86RCL_H { 1643, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1643 = X86RCL_D { 1642, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1642 = X86RCL_B { 1641, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1641 = X86RCLI_W { 1640, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1640 = X86RCLI_H { 1639, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1639 = X86RCLI_D { 1638, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1638 = X86RCLI_B { 1637, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1637 = X86OR_W { 1636, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1636 = X86OR_H { 1635, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1635 = X86OR_D { 1634, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1634 = X86OR_B { 1633, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1633 = X86MUL_WU { 1632, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1632 = X86MUL_W { 1631, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1631 = X86MUL_HU { 1630, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1630 = X86MUL_H { 1629, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1629 = X86MUL_DU { 1628, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1628 = X86MUL_D { 1627, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1627 = X86MUL_BU { 1626, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1626 = X86MUL_B { 1625, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0, 0x0ULL }, // Inst #1625 = X86MTTOP { 1624, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1624 = X86MTFLAG { 1623, 1, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1623 = X86MFTOP { 1622, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1622 = X86MFFLAG { 1621, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1621 = X86INC_W { 1620, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1620 = X86INC_H { 1619, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1619 = X86INC_D { 1618, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1618 = X86INC_B { 1617, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0, 0x0ULL }, // Inst #1617 = X86INCTOP { 1616, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1616 = X86DEC_W { 1615, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1615 = X86DEC_H { 1614, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1614 = X86DEC_D { 1613, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1613 = X86DEC_B { 1612, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0, 0x0ULL }, // Inst #1612 = X86DECTOP { 1611, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0, 0x0ULL }, // Inst #1611 = X86CLRTM { 1610, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1610 = X86AND_W { 1609, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1609 = X86AND_H { 1608, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1608 = X86AND_D { 1607, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1607 = X86AND_B { 1606, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1606 = X86ADD_WU { 1605, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1605 = X86ADD_W { 1604, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1604 = X86ADD_H { 1603, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1603 = X86ADD_DU { 1602, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1602 = X86ADD_D { 1601, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1601 = X86ADD_B { 1600, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1600 = X86ADC_W { 1599, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1599 = X86ADC_H { 1598, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1598 = X86ADC_D { 1597, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #1597 = X86ADC_B { 1596, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1596 = VXOR_V { 1595, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1595 = VXORI_B { 1594, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1594 = VSUB_W { 1593, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1593 = VSUB_Q { 1592, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1592 = VSUB_H { 1591, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1591 = VSUB_D { 1590, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1590 = VSUB_B { 1589, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1589 = VSUBWOD_W_HU { 1588, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1588 = VSUBWOD_W_H { 1587, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1587 = VSUBWOD_Q_DU { 1586, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1586 = VSUBWOD_Q_D { 1585, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1585 = VSUBWOD_H_BU { 1584, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1584 = VSUBWOD_H_B { 1583, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1583 = VSUBWOD_D_WU { 1582, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1582 = VSUBWOD_D_W { 1581, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1581 = VSUBWEV_W_HU { 1580, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1580 = VSUBWEV_W_H { 1579, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1579 = VSUBWEV_Q_DU { 1578, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1578 = VSUBWEV_Q_D { 1577, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1577 = VSUBWEV_H_BU { 1576, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1576 = VSUBWEV_H_B { 1575, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1575 = VSUBWEV_D_WU { 1574, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1574 = VSUBWEV_D_W { 1573, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1573 = VSUBI_WU { 1572, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1572 = VSUBI_HU { 1571, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1571 = VSUBI_DU { 1570, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1570 = VSUBI_BU { 1569, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 362, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1569 = VSTX { 1568, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 375, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1568 = VSTELM_W { 1567, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 375, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1567 = VSTELM_H { 1566, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 375, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1566 = VSTELM_D { 1565, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 375, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1565 = VSTELM_B { 1564, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 359, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1564 = VST { 1563, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1563 = VSSUB_WU { 1562, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1562 = VSSUB_W { 1561, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1561 = VSSUB_HU { 1560, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1560 = VSSUB_H { 1559, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1559 = VSSUB_DU { 1558, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1558 = VSSUB_D { 1557, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1557 = VSSUB_BU { 1556, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1556 = VSSUB_B { 1555, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1555 = VSSRLRN_W_D { 1554, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1554 = VSSRLRN_WU_D { 1553, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1553 = VSSRLRN_H_W { 1552, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1552 = VSSRLRN_HU_W { 1551, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1551 = VSSRLRN_B_H { 1550, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1550 = VSSRLRN_BU_H { 1549, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1549 = VSSRLRNI_W_D { 1548, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1548 = VSSRLRNI_WU_D { 1547, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1547 = VSSRLRNI_H_W { 1546, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1546 = VSSRLRNI_HU_W { 1545, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1545 = VSSRLRNI_D_Q { 1544, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1544 = VSSRLRNI_DU_Q { 1543, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1543 = VSSRLRNI_B_H { 1542, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1542 = VSSRLRNI_BU_H { 1541, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1541 = VSSRLN_W_D { 1540, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1540 = VSSRLN_WU_D { 1539, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1539 = VSSRLN_H_W { 1538, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1538 = VSSRLN_HU_W { 1537, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1537 = VSSRLN_B_H { 1536, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1536 = VSSRLN_BU_H { 1535, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1535 = VSSRLNI_W_D { 1534, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1534 = VSSRLNI_WU_D { 1533, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1533 = VSSRLNI_H_W { 1532, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1532 = VSSRLNI_HU_W { 1531, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1531 = VSSRLNI_D_Q { 1530, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1530 = VSSRLNI_DU_Q { 1529, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1529 = VSSRLNI_B_H { 1528, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1528 = VSSRLNI_BU_H { 1527, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1527 = VSSRARN_W_D { 1526, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1526 = VSSRARN_WU_D { 1525, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1525 = VSSRARN_H_W { 1524, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1524 = VSSRARN_HU_W { 1523, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1523 = VSSRARN_B_H { 1522, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1522 = VSSRARN_BU_H { 1521, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1521 = VSSRARNI_W_D { 1520, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1520 = VSSRARNI_WU_D { 1519, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1519 = VSSRARNI_H_W { 1518, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1518 = VSSRARNI_HU_W { 1517, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1517 = VSSRARNI_D_Q { 1516, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1516 = VSSRARNI_DU_Q { 1515, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1515 = VSSRARNI_B_H { 1514, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1514 = VSSRARNI_BU_H { 1513, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1513 = VSSRAN_W_D { 1512, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1512 = VSSRAN_WU_D { 1511, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1511 = VSSRAN_H_W { 1510, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1510 = VSSRAN_HU_W { 1509, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1509 = VSSRAN_B_H { 1508, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1508 = VSSRAN_BU_H { 1507, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1507 = VSSRANI_W_D { 1506, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1506 = VSSRANI_WU_D { 1505, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1505 = VSSRANI_H_W { 1504, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1504 = VSSRANI_HU_W { 1503, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1503 = VSSRANI_D_Q { 1502, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1502 = VSSRANI_DU_Q { 1501, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1501 = VSSRANI_B_H { 1500, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1500 = VSSRANI_BU_H { 1499, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1499 = VSRL_W { 1498, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1498 = VSRL_H { 1497, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1497 = VSRL_D { 1496, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1496 = VSRL_B { 1495, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1495 = VSRLR_W { 1494, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1494 = VSRLR_H { 1493, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1493 = VSRLR_D { 1492, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1492 = VSRLR_B { 1491, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1491 = VSRLRN_W_D { 1490, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1490 = VSRLRN_H_W { 1489, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1489 = VSRLRN_B_H { 1488, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1488 = VSRLRNI_W_D { 1487, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1487 = VSRLRNI_H_W { 1486, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1486 = VSRLRNI_D_Q { 1485, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1485 = VSRLRNI_B_H { 1484, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1484 = VSRLRI_W { 1483, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1483 = VSRLRI_H { 1482, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1482 = VSRLRI_D { 1481, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1481 = VSRLRI_B { 1480, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1480 = VSRLN_W_D { 1479, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1479 = VSRLN_H_W { 1478, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1478 = VSRLN_B_H { 1477, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1477 = VSRLNI_W_D { 1476, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1476 = VSRLNI_H_W { 1475, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1475 = VSRLNI_D_Q { 1474, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1474 = VSRLNI_B_H { 1473, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1473 = VSRLI_W { 1472, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1472 = VSRLI_H { 1471, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1471 = VSRLI_D { 1470, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1470 = VSRLI_B { 1469, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1469 = VSRA_W { 1468, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1468 = VSRA_H { 1467, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1467 = VSRA_D { 1466, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1466 = VSRA_B { 1465, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1465 = VSRAR_W { 1464, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1464 = VSRAR_H { 1463, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1463 = VSRAR_D { 1462, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1462 = VSRAR_B { 1461, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1461 = VSRARN_W_D { 1460, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1460 = VSRARN_H_W { 1459, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1459 = VSRARN_B_H { 1458, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1458 = VSRARNI_W_D { 1457, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1457 = VSRARNI_H_W { 1456, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1456 = VSRARNI_D_Q { 1455, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1455 = VSRARNI_B_H { 1454, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1454 = VSRARI_W { 1453, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1453 = VSRARI_H { 1452, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1452 = VSRARI_D { 1451, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1451 = VSRARI_B { 1450, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1450 = VSRAN_W_D { 1449, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1449 = VSRAN_H_W { 1448, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1448 = VSRAN_B_H { 1447, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1447 = VSRANI_W_D { 1446, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1446 = VSRANI_H_W { 1445, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1445 = VSRANI_D_Q { 1444, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1444 = VSRANI_B_H { 1443, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1443 = VSRAI_W { 1442, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1442 = VSRAI_H { 1441, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1441 = VSRAI_D { 1440, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1440 = VSRAI_B { 1439, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1439 = VSLT_WU { 1438, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1438 = VSLT_W { 1437, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1437 = VSLT_HU { 1436, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1436 = VSLT_H { 1435, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1435 = VSLT_DU { 1434, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1434 = VSLT_D { 1433, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1433 = VSLT_BU { 1432, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1432 = VSLT_B { 1431, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1431 = VSLTI_WU { 1430, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1430 = VSLTI_W { 1429, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1429 = VSLTI_HU { 1428, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1428 = VSLTI_H { 1427, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1427 = VSLTI_DU { 1426, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1426 = VSLTI_D { 1425, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1425 = VSLTI_BU { 1424, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1424 = VSLTI_B { 1423, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1423 = VSLL_W { 1422, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1422 = VSLL_H { 1421, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1421 = VSLL_D { 1420, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1420 = VSLL_B { 1419, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1419 = VSLLWIL_W_H { 1418, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1418 = VSLLWIL_WU_HU { 1417, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1417 = VSLLWIL_H_B { 1416, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1416 = VSLLWIL_HU_BU { 1415, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1415 = VSLLWIL_D_W { 1414, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1414 = VSLLWIL_DU_WU { 1413, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1413 = VSLLI_W { 1412, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1412 = VSLLI_H { 1411, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1411 = VSLLI_D { 1410, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1410 = VSLLI_B { 1409, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1409 = VSLE_WU { 1408, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1408 = VSLE_W { 1407, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1407 = VSLE_HU { 1406, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1406 = VSLE_H { 1405, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1405 = VSLE_DU { 1404, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1404 = VSLE_D { 1403, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1403 = VSLE_BU { 1402, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1402 = VSLE_B { 1401, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1401 = VSLEI_WU { 1400, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1400 = VSLEI_W { 1399, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1399 = VSLEI_HU { 1398, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1398 = VSLEI_H { 1397, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1397 = VSLEI_DU { 1396, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1396 = VSLEI_D { 1395, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1395 = VSLEI_BU { 1394, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1394 = VSLEI_B { 1393, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1393 = VSIGNCOV_W { 1392, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1392 = VSIGNCOV_H { 1391, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1391 = VSIGNCOV_D { 1390, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1390 = VSIGNCOV_B { 1389, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1389 = VSHUF_W { 1388, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1388 = VSHUF_H { 1387, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1387 = VSHUF_D { 1386, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1386 = VSHUF_B { 1385, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1385 = VSHUF4I_W { 1384, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1384 = VSHUF4I_H { 1383, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1383 = VSHUF4I_D { 1382, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1382 = VSHUF4I_B { 1381, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1381 = VSETNEZ_V { 1380, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1380 = VSETEQZ_V { 1379, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1379 = VSETANYEQZ_W { 1378, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1378 = VSETANYEQZ_H { 1377, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1377 = VSETANYEQZ_D { 1376, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1376 = VSETANYEQZ_B { 1375, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1375 = VSETALLNEZ_W { 1374, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1374 = VSETALLNEZ_H { 1373, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1373 = VSETALLNEZ_D { 1372, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1372 = VSETALLNEZ_B { 1371, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1371 = VSEQ_W { 1370, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1370 = VSEQ_H { 1369, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1369 = VSEQ_D { 1368, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1368 = VSEQ_B { 1367, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1367 = VSEQI_W { 1366, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1366 = VSEQI_H { 1365, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1365 = VSEQI_D { 1364, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1364 = VSEQI_B { 1363, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1363 = VSAT_WU { 1362, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1362 = VSAT_W { 1361, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1361 = VSAT_HU { 1360, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1360 = VSAT_H { 1359, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1359 = VSAT_DU { 1358, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1358 = VSAT_D { 1357, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1357 = VSAT_BU { 1356, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1356 = VSAT_B { 1355, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1355 = VSADD_WU { 1354, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1354 = VSADD_W { 1353, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1353 = VSADD_HU { 1352, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1352 = VSADD_H { 1351, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1351 = VSADD_DU { 1350, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1350 = VSADD_D { 1349, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1349 = VSADD_BU { 1348, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1348 = VSADD_B { 1347, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1347 = VROTR_W { 1346, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1346 = VROTR_H { 1345, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1345 = VROTR_D { 1344, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1344 = VROTR_B { 1343, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1343 = VROTRI_W { 1342, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1342 = VROTRI_H { 1341, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1341 = VROTRI_D { 1340, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1340 = VROTRI_B { 1339, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 370, 0, 0x0ULL }, // Inst #1339 = VREPLVE_W { 1338, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 370, 0, 0x0ULL }, // Inst #1338 = VREPLVE_H { 1337, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 370, 0, 0x0ULL }, // Inst #1337 = VREPLVE_D { 1336, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 370, 0, 0x0ULL }, // Inst #1336 = VREPLVE_B { 1335, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1335 = VREPLVEI_W { 1334, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1334 = VREPLVEI_H { 1333, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1333 = VREPLVEI_D { 1332, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1332 = VREPLVEI_B { 1331, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 368, 0, 0x0ULL }, // Inst #1331 = VREPLGR2VR_W { 1330, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 368, 0, 0x0ULL }, // Inst #1330 = VREPLGR2VR_H { 1329, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 368, 0, 0x0ULL }, // Inst #1329 = VREPLGR2VR_D { 1328, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 368, 0, 0x0ULL }, // Inst #1328 = VREPLGR2VR_B { 1327, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1327 = VPICKVE2GR_WU { 1326, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1326 = VPICKVE2GR_W { 1325, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1325 = VPICKVE2GR_HU { 1324, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1324 = VPICKVE2GR_H { 1323, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1323 = VPICKVE2GR_DU { 1322, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1322 = VPICKVE2GR_D { 1321, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1321 = VPICKVE2GR_BU { 1320, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1320 = VPICKVE2GR_B { 1319, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1319 = VPICKOD_W { 1318, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1318 = VPICKOD_H { 1317, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1317 = VPICKOD_D { 1316, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1316 = VPICKOD_B { 1315, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1315 = VPICKEV_W { 1314, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1314 = VPICKEV_H { 1313, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1313 = VPICKEV_D { 1312, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1312 = VPICKEV_B { 1311, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1311 = VPERMI_W { 1310, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1310 = VPCNT_W { 1309, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1309 = VPCNT_H { 1308, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1308 = VPCNT_D { 1307, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1307 = VPCNT_B { 1306, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1306 = VPACKOD_W { 1305, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1305 = VPACKOD_H { 1304, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1304 = VPACKOD_D { 1303, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1303 = VPACKOD_B { 1302, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1302 = VPACKEV_W { 1301, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1301 = VPACKEV_H { 1300, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1300 = VPACKEV_D { 1299, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1299 = VPACKEV_B { 1298, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1298 = VOR_V { 1297, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1297 = VORN_V { 1296, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1296 = VORI_B { 1295, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1295 = VNOR_V { 1294, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1294 = VNORI_B { 1293, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1293 = VNEG_W { 1292, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1292 = VNEG_H { 1291, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1291 = VNEG_D { 1290, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1290 = VNEG_B { 1289, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1289 = VMUL_W { 1288, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1288 = VMUL_H { 1287, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1287 = VMUL_D { 1286, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1286 = VMUL_B { 1285, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1285 = VMULWOD_W_HU_H { 1284, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1284 = VMULWOD_W_HU { 1283, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1283 = VMULWOD_W_H { 1282, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1282 = VMULWOD_Q_DU_D { 1281, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1281 = VMULWOD_Q_DU { 1280, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1280 = VMULWOD_Q_D { 1279, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1279 = VMULWOD_H_BU_B { 1278, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1278 = VMULWOD_H_BU { 1277, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1277 = VMULWOD_H_B { 1276, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1276 = VMULWOD_D_WU_W { 1275, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1275 = VMULWOD_D_WU { 1274, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1274 = VMULWOD_D_W { 1273, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1273 = VMULWEV_W_HU_H { 1272, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1272 = VMULWEV_W_HU { 1271, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1271 = VMULWEV_W_H { 1270, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1270 = VMULWEV_Q_DU_D { 1269, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1269 = VMULWEV_Q_DU { 1268, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1268 = VMULWEV_Q_D { 1267, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1267 = VMULWEV_H_BU_B { 1266, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1266 = VMULWEV_H_BU { 1265, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1265 = VMULWEV_H_B { 1264, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1264 = VMULWEV_D_WU_W { 1263, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1263 = VMULWEV_D_WU { 1262, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1262 = VMULWEV_D_W { 1261, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1261 = VMUH_WU { 1260, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1260 = VMUH_W { 1259, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1259 = VMUH_HU { 1258, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1258 = VMUH_H { 1257, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1257 = VMUH_DU { 1256, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1256 = VMUH_D { 1255, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1255 = VMUH_BU { 1254, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1254 = VMUH_B { 1253, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1253 = VMSUB_W { 1252, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1252 = VMSUB_H { 1251, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1251 = VMSUB_D { 1250, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1250 = VMSUB_B { 1249, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1249 = VMSKNZ_B { 1248, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1248 = VMSKLTZ_W { 1247, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1247 = VMSKLTZ_H { 1246, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1246 = VMSKLTZ_D { 1245, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1245 = VMSKLTZ_B { 1244, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1244 = VMSKGEZ_B { 1243, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1243 = VMOD_WU { 1242, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1242 = VMOD_W { 1241, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1241 = VMOD_HU { 1240, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1240 = VMOD_H { 1239, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1239 = VMOD_DU { 1238, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1238 = VMOD_D { 1237, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1237 = VMOD_BU { 1236, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1236 = VMOD_B { 1235, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1235 = VMIN_WU { 1234, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1234 = VMIN_W { 1233, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1233 = VMIN_HU { 1232, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1232 = VMIN_H { 1231, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1231 = VMIN_DU { 1230, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1230 = VMIN_D { 1229, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1229 = VMIN_BU { 1228, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1228 = VMIN_B { 1227, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1227 = VMINI_WU { 1226, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1226 = VMINI_W { 1225, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1225 = VMINI_HU { 1224, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1224 = VMINI_H { 1223, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1223 = VMINI_DU { 1222, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1222 = VMINI_D { 1221, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1221 = VMINI_BU { 1220, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1220 = VMINI_B { 1219, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1219 = VMAX_WU { 1218, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1218 = VMAX_W { 1217, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1217 = VMAX_HU { 1216, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1216 = VMAX_H { 1215, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1215 = VMAX_DU { 1214, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1214 = VMAX_D { 1213, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1213 = VMAX_BU { 1212, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1212 = VMAX_B { 1211, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1211 = VMAXI_WU { 1210, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1210 = VMAXI_W { 1209, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1209 = VMAXI_HU { 1208, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1208 = VMAXI_H { 1207, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1207 = VMAXI_DU { 1206, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1206 = VMAXI_D { 1205, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1205 = VMAXI_BU { 1204, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1204 = VMAXI_B { 1203, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1203 = VMADD_W { 1202, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1202 = VMADD_H { 1201, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1201 = VMADD_D { 1200, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1200 = VMADD_B { 1199, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1199 = VMADDWOD_W_HU_H { 1198, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1198 = VMADDWOD_W_HU { 1197, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1197 = VMADDWOD_W_H { 1196, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1196 = VMADDWOD_Q_DU_D { 1195, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1195 = VMADDWOD_Q_DU { 1194, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1194 = VMADDWOD_Q_D { 1193, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1193 = VMADDWOD_H_BU_B { 1192, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1192 = VMADDWOD_H_BU { 1191, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1191 = VMADDWOD_H_B { 1190, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1190 = VMADDWOD_D_WU_W { 1189, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1189 = VMADDWOD_D_WU { 1188, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1188 = VMADDWOD_D_W { 1187, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1187 = VMADDWEV_W_HU_H { 1186, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1186 = VMADDWEV_W_HU { 1185, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1185 = VMADDWEV_W_H { 1184, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1184 = VMADDWEV_Q_DU_D { 1183, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1183 = VMADDWEV_Q_DU { 1182, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1182 = VMADDWEV_Q_D { 1181, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1181 = VMADDWEV_H_BU_B { 1180, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1180 = VMADDWEV_H_BU { 1179, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1179 = VMADDWEV_H_B { 1178, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1178 = VMADDWEV_D_WU_W { 1177, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1177 = VMADDWEV_D_WU { 1176, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1176 = VMADDWEV_D_W { 1175, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 362, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1175 = VLDX { 1174, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 359, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1174 = VLDREPL_W { 1173, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 359, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1173 = VLDREPL_H { 1172, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 359, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1172 = VLDREPL_D { 1171, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 359, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1171 = VLDREPL_B { 1170, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1170 = VLDI { 1169, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 359, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1169 = VLD { 1168, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 355, 0, 0x0ULL }, // Inst #1168 = VINSGR2VR_W { 1167, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 355, 0, 0x0ULL }, // Inst #1167 = VINSGR2VR_H { 1166, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 355, 0, 0x0ULL }, // Inst #1166 = VINSGR2VR_D { 1165, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 355, 0, 0x0ULL }, // Inst #1165 = VINSGR2VR_B { 1164, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1164 = VILVL_W { 1163, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1163 = VILVL_H { 1162, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1162 = VILVL_D { 1161, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1161 = VILVL_B { 1160, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1160 = VILVH_W { 1159, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1159 = VILVH_H { 1158, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1158 = VILVH_D { 1157, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1157 = VILVH_B { 1156, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1156 = VHSUBW_W_H { 1155, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1155 = VHSUBW_WU_HU { 1154, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1154 = VHSUBW_Q_D { 1153, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1153 = VHSUBW_QU_DU { 1152, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1152 = VHSUBW_H_B { 1151, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1151 = VHSUBW_HU_BU { 1150, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1150 = VHSUBW_D_W { 1149, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1149 = VHSUBW_DU_WU { 1148, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1148 = VHADDW_W_H { 1147, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1147 = VHADDW_WU_HU { 1146, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1146 = VHADDW_Q_D { 1145, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1145 = VHADDW_QU_DU { 1144, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1144 = VHADDW_H_B { 1143, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1143 = VHADDW_HU_BU { 1142, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1142 = VHADDW_D_W { 1141, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1141 = VHADDW_DU_WU { 1140, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1140 = VFTINT_W_S { 1139, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1139 = VFTINT_W_D { 1138, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1138 = VFTINT_WU_S { 1137, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1137 = VFTINT_L_D { 1136, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1136 = VFTINT_LU_D { 1135, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1135 = VFTINTRZ_W_S { 1134, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1134 = VFTINTRZ_W_D { 1133, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1133 = VFTINTRZ_WU_S { 1132, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1132 = VFTINTRZ_L_D { 1131, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1131 = VFTINTRZ_LU_D { 1130, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1130 = VFTINTRZL_L_S { 1129, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1129 = VFTINTRZH_L_S { 1128, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1128 = VFTINTRP_W_S { 1127, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1127 = VFTINTRP_W_D { 1126, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1126 = VFTINTRP_L_D { 1125, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1125 = VFTINTRPL_L_S { 1124, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1124 = VFTINTRPH_L_S { 1123, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1123 = VFTINTRNE_W_S { 1122, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1122 = VFTINTRNE_W_D { 1121, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1121 = VFTINTRNE_L_D { 1120, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1120 = VFTINTRNEL_L_S { 1119, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1119 = VFTINTRNEH_L_S { 1118, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1118 = VFTINTRM_W_S { 1117, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1117 = VFTINTRM_W_D { 1116, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1116 = VFTINTRM_L_D { 1115, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1115 = VFTINTRML_L_S { 1114, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1114 = VFTINTRMH_L_S { 1113, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1113 = VFTINTL_L_S { 1112, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1112 = VFTINTH_L_S { 1111, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1111 = VFSUB_S { 1110, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1110 = VFSUB_D { 1109, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1109 = VFSQRT_S { 1108, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1108 = VFSQRT_D { 1107, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1107 = VFRSTP_H { 1106, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1106 = VFRSTP_B { 1105, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1105 = VFRSTPI_H { 1104, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1104 = VFRSTPI_B { 1103, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1103 = VFRSQRT_S { 1102, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1102 = VFRSQRT_D { 1101, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1101 = VFRSQRTE_S { 1100, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1100 = VFRSQRTE_D { 1099, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1099 = VFRINT_S { 1098, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1098 = VFRINT_D { 1097, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1097 = VFRINTRZ_S { 1096, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1096 = VFRINTRZ_D { 1095, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1095 = VFRINTRP_S { 1094, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1094 = VFRINTRP_D { 1093, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1093 = VFRINTRNE_S { 1092, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1092 = VFRINTRNE_D { 1091, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1091 = VFRINTRM_S { 1090, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1090 = VFRINTRM_D { 1089, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1089 = VFRECIP_S { 1088, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1088 = VFRECIP_D { 1087, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1087 = VFRECIPE_S { 1086, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1086 = VFRECIPE_D { 1085, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1085 = VFNMSUB_S { 1084, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1084 = VFNMSUB_D { 1083, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1083 = VFNMADD_S { 1082, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1082 = VFNMADD_D { 1081, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1081 = VFMUL_S { 1080, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1080 = VFMUL_D { 1079, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1079 = VFMSUB_S { 1078, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1078 = VFMSUB_D { 1077, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1077 = VFMIN_S { 1076, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1076 = VFMIN_D { 1075, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1075 = VFMINA_S { 1074, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1074 = VFMINA_D { 1073, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1073 = VFMAX_S { 1072, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1072 = VFMAX_D { 1071, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1071 = VFMAXA_S { 1070, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1070 = VFMAXA_D { 1069, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1069 = VFMADD_S { 1068, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1068 = VFMADD_D { 1067, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1067 = VFLOGB_S { 1066, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1066 = VFLOGB_D { 1065, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1065 = VFFINT_S_WU { 1064, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1064 = VFFINT_S_W { 1063, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1063 = VFFINT_S_L { 1062, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1062 = VFFINT_D_LU { 1061, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1061 = VFFINT_D_L { 1060, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1060 = VFFINTL_D_W { 1059, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1059 = VFFINTH_D_W { 1058, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1058 = VFDIV_S { 1057, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1057 = VFDIV_D { 1056, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1056 = VFCVT_S_D { 1055, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1055 = VFCVT_H_S { 1054, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1054 = VFCVTL_S_H { 1053, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1053 = VFCVTL_D_S { 1052, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1052 = VFCVTH_S_H { 1051, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1051 = VFCVTH_D_S { 1050, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1050 = VFCMP_SUN_S { 1049, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1049 = VFCMP_SUN_D { 1048, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1048 = VFCMP_SUNE_S { 1047, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1047 = VFCMP_SUNE_D { 1046, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1046 = VFCMP_SULT_S { 1045, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1045 = VFCMP_SULT_D { 1044, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1044 = VFCMP_SULE_S { 1043, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1043 = VFCMP_SULE_D { 1042, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1042 = VFCMP_SUEQ_S { 1041, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1041 = VFCMP_SUEQ_D { 1040, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1040 = VFCMP_SOR_S { 1039, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1039 = VFCMP_SOR_D { 1038, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1038 = VFCMP_SNE_S { 1037, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1037 = VFCMP_SNE_D { 1036, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1036 = VFCMP_SLT_S { 1035, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1035 = VFCMP_SLT_D { 1034, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1034 = VFCMP_SLE_S { 1033, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1033 = VFCMP_SLE_D { 1032, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1032 = VFCMP_SEQ_S { 1031, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1031 = VFCMP_SEQ_D { 1030, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1030 = VFCMP_SAF_S { 1029, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1029 = VFCMP_SAF_D { 1028, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1028 = VFCMP_CUN_S { 1027, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1027 = VFCMP_CUN_D { 1026, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1026 = VFCMP_CUNE_S { 1025, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1025 = VFCMP_CUNE_D { 1024, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1024 = VFCMP_CULT_S { 1023, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1023 = VFCMP_CULT_D { 1022, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1022 = VFCMP_CULE_S { 1021, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1021 = VFCMP_CULE_D { 1020, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1020 = VFCMP_CUEQ_S { 1019, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1019 = VFCMP_CUEQ_D { 1018, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1018 = VFCMP_COR_S { 1017, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1017 = VFCMP_COR_D { 1016, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1016 = VFCMP_CNE_S { 1015, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1015 = VFCMP_CNE_D { 1014, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1014 = VFCMP_CLT_S { 1013, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1013 = VFCMP_CLT_D { 1012, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1012 = VFCMP_CLE_S { 1011, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1011 = VFCMP_CLE_D { 1010, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1010 = VFCMP_CEQ_S { 1009, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1009 = VFCMP_CEQ_D { 1008, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1008 = VFCMP_CAF_S { 1007, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1007 = VFCMP_CAF_D { 1006, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1006 = VFCLASS_S { 1005, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1005 = VFCLASS_D { 1004, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1004 = VFADD_S { 1003, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1003 = VFADD_D { 1002, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1002 = VEXTRINS_W { 1001, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1001 = VEXTRINS_H { 1000, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1000 = VEXTRINS_D { 999, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #999 = VEXTRINS_B { 998, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #998 = VEXTL_Q_D { 997, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #997 = VEXTL_QU_DU { 996, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #996 = VEXTH_W_H { 995, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #995 = VEXTH_WU_HU { 994, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #994 = VEXTH_Q_D { 993, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #993 = VEXTH_QU_DU { 992, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #992 = VEXTH_H_B { 991, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #991 = VEXTH_HU_BU { 990, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #990 = VEXTH_D_W { 989, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #989 = VEXTH_DU_WU { 988, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #988 = VEXT2XV_W_H { 987, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #987 = VEXT2XV_W_B { 986, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #986 = VEXT2XV_WU_HU { 985, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #985 = VEXT2XV_WU_BU { 984, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #984 = VEXT2XV_H_B { 983, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #983 = VEXT2XV_HU_BU { 982, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #982 = VEXT2XV_D_W { 981, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #981 = VEXT2XV_D_H { 980, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #980 = VEXT2XV_D_B { 979, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #979 = VEXT2XV_DU_WU { 978, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #978 = VEXT2XV_DU_HU { 977, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #977 = VEXT2XV_DU_BU { 976, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #976 = VDIV_WU { 975, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #975 = VDIV_W { 974, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #974 = VDIV_HU { 973, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #973 = VDIV_H { 972, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #972 = VDIV_DU { 971, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #971 = VDIV_D { 970, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #970 = VDIV_BU { 969, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #969 = VDIV_B { 968, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #968 = VCLZ_W { 967, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #967 = VCLZ_H { 966, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #966 = VCLZ_D { 965, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #965 = VCLZ_B { 964, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #964 = VCLO_W { 963, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #963 = VCLO_H { 962, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #962 = VCLO_D { 961, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #961 = VCLO_B { 960, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #960 = VBSRL_V { 959, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #959 = VBSLL_V { 958, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #958 = VBITSET_W { 957, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #957 = VBITSET_H { 956, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #956 = VBITSET_D { 955, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #955 = VBITSET_B { 954, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #954 = VBITSETI_W { 953, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #953 = VBITSETI_H { 952, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #952 = VBITSETI_D { 951, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #951 = VBITSETI_B { 950, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #950 = VBITSEL_V { 949, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #949 = VBITSELI_B { 948, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #948 = VBITREV_W { 947, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #947 = VBITREV_H { 946, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #946 = VBITREV_D { 945, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #945 = VBITREV_B { 944, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #944 = VBITREVI_W { 943, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #943 = VBITREVI_H { 942, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #942 = VBITREVI_D { 941, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #941 = VBITREVI_B { 940, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #940 = VBITCLR_W { 939, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #939 = VBITCLR_H { 938, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #938 = VBITCLR_D { 937, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #937 = VBITCLR_B { 936, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #936 = VBITCLRI_W { 935, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #935 = VBITCLRI_H { 934, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #934 = VBITCLRI_D { 933, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #933 = VBITCLRI_B { 932, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #932 = VAVG_WU { 931, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #931 = VAVG_W { 930, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #930 = VAVG_HU { 929, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #929 = VAVG_H { 928, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #928 = VAVG_DU { 927, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #927 = VAVG_D { 926, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #926 = VAVG_BU { 925, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #925 = VAVG_B { 924, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #924 = VAVGR_WU { 923, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #923 = VAVGR_W { 922, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #922 = VAVGR_HU { 921, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #921 = VAVGR_H { 920, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #920 = VAVGR_DU { 919, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #919 = VAVGR_D { 918, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #918 = VAVGR_BU { 917, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #917 = VAVGR_B { 916, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #916 = VAND_V { 915, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #915 = VANDN_V { 914, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #914 = VANDI_B { 913, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #913 = VADD_W { 912, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #912 = VADD_Q { 911, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #911 = VADD_H { 910, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #910 = VADD_D { 909, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #909 = VADD_B { 908, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #908 = VADDWOD_W_HU_H { 907, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #907 = VADDWOD_W_HU { 906, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #906 = VADDWOD_W_H { 905, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #905 = VADDWOD_Q_DU_D { 904, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #904 = VADDWOD_Q_DU { 903, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #903 = VADDWOD_Q_D { 902, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #902 = VADDWOD_H_BU_B { 901, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #901 = VADDWOD_H_BU { 900, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #900 = VADDWOD_H_B { 899, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #899 = VADDWOD_D_WU_W { 898, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #898 = VADDWOD_D_WU { 897, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #897 = VADDWOD_D_W { 896, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #896 = VADDWEV_W_HU_H { 895, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #895 = VADDWEV_W_HU { 894, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #894 = VADDWEV_W_H { 893, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #893 = VADDWEV_Q_DU_D { 892, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #892 = VADDWEV_Q_DU { 891, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #891 = VADDWEV_Q_D { 890, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #890 = VADDWEV_H_BU_B { 889, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #889 = VADDWEV_H_BU { 888, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #888 = VADDWEV_H_B { 887, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #887 = VADDWEV_D_WU_W { 886, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #886 = VADDWEV_D_WU { 885, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #885 = VADDWEV_D_W { 884, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #884 = VADDI_WU { 883, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #883 = VADDI_HU { 882, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #882 = VADDI_DU { 881, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #881 = VADDI_BU { 880, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #880 = VADDA_W { 879, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #879 = VADDA_H { 878, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #878 = VADDA_D { 877, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #877 = VADDA_B { 876, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #876 = VABSD_WU { 875, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #875 = VABSD_W { 874, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #874 = VABSD_HU { 873, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #873 = VABSD_H { 872, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #872 = VABSD_DU { 871, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #871 = VABSD_D { 870, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #870 = VABSD_BU { 869, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #869 = VABSD_B { 868, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #868 = TLBWR { 867, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #867 = TLBSRCH { 866, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #866 = TLBRD { 865, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #865 = TLBFLUSH { 864, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #864 = TLBFILL { 863, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #863 = TLBCLR { 862, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #862 = SYSCALL { 861, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #861 = SUB_W { 860, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #860 = SUB_D { 859, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #859 = ST_W { 858, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #858 = ST_H { 857, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #857 = ST_D { 856, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #856 = ST_B { 855, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #855 = STX_W { 854, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #854 = STX_H { 853, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #853 = STX_D { 852, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #852 = STX_B { 851, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #851 = STR_W { 850, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #850 = STR_D { 849, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #849 = STPTR_W { 848, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #848 = STPTR_D { 847, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #847 = STL_W { 846, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #846 = STL_D { 845, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #845 = STLE_W { 844, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #844 = STLE_H { 843, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #843 = STLE_D { 842, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #842 = STLE_B { 841, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #841 = STGT_W { 840, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #840 = STGT_H { 839, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #839 = STGT_D { 838, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #838 = STGT_B { 837, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #837 = SRL_W { 836, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #836 = SRL_D { 835, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #835 = SRLI_W { 834, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #834 = SRLI_D { 833, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #833 = SRA_W { 832, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #832 = SRA_D { 831, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #831 = SRAI_W { 830, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #830 = SRAI_D { 829, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #829 = SLTUI { 828, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #828 = SLTU { 827, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #827 = SLTI { 826, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #826 = SLT { 825, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #825 = SLL_W { 824, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #824 = SLL_D { 823, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #823 = SLLI_W { 822, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #822 = SLLI_D { 821, 1, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 332, 0, 0x0ULL }, // Inst #821 = SET_CFR_TRUE { 820, 1, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 332, 0, 0x0ULL }, // Inst #820 = SET_CFR_FALSE { 819, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #819 = SETX86LOOPNE { 818, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #818 = SETX86LOOPE { 817, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #817 = SETX86J { 816, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #816 = SETARMJ { 815, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 243, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #815 = SC_W { 814, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 328, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #814 = SC_Q { 813, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 243, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #813 = SC_D { 812, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 325, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #812 = SCREL_W { 811, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 325, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #811 = SCREL_D { 810, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #810 = SBC_W { 809, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #809 = SBC_H { 808, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #808 = SBC_D { 807, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #807 = SBC_B { 806, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #806 = ROTR_W { 805, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #805 = ROTR_H { 804, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #804 = ROTR_D { 803, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #803 = ROTR_B { 802, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #802 = ROTRI_W { 801, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #801 = ROTRI_H { 800, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #800 = ROTRI_D { 799, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #799 = ROTRI_B { 798, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #798 = REVH_D { 797, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #797 = REVH_2W { 796, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #796 = REVB_D { 795, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #795 = REVB_4H { 794, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #794 = REVB_2W { 793, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #793 = REVB_2H { 792, 2, 2, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #792 = RDTIME_D { 791, 2, 2, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #791 = RDTIMEL_W { 790, 2, 2, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #790 = RDTIMEH_W { 789, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #789 = RCR_W { 788, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #788 = RCR_H { 787, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #787 = RCR_D { 786, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #786 = RCR_B { 785, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #785 = RCRI_W { 784, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #784 = RCRI_H { 783, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #783 = RCRI_D { 782, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #782 = RCRI_B { 781, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 322, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #781 = PRELDX { 780, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 237, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #780 = PRELD { 779, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #779 = PCALAU12I { 778, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #778 = PCADDU18I { 777, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #777 = PCADDU12I { 776, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #776 = PCADDI { 775, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #775 = ORN { 774, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #774 = ORI { 773, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #773 = OR { 772, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #772 = NOR { 771, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #771 = MUL_W { 770, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #770 = MUL_D { 769, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #769 = MULW_D_WU { 768, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #768 = MULW_D_W { 767, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #767 = MULH_WU { 766, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #766 = MULH_W { 765, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #765 = MULH_DU { 764, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #764 = MULH_D { 763, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 320, 0, 0x0ULL }, // Inst #763 = MOVSCR2GR { 762, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 318, 0, 0x0ULL }, // Inst #762 = MOVGR2SCR { 761, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 314, 0, 0x0ULL }, // Inst #761 = MOVGR2FR_W_64 { 760, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 316, 0, 0x0ULL }, // Inst #760 = MOVGR2FR_W { 759, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 314, 0, 0x0ULL }, // Inst #759 = MOVGR2FR_D { 758, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 311, 0, 0x0ULL }, // Inst #758 = MOVGR2FRH_W { 757, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 309, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #757 = MOVGR2FCSR { 756, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #756 = MOVGR2CF { 755, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #755 = MOVFRH2GR_S { 754, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #754 = MOVFR2GR_S_64 { 753, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 305, 0, 0x0ULL }, // Inst #753 = MOVFR2GR_S { 752, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #752 = MOVFR2GR_D { 751, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 301, 0, 0x0ULL }, // Inst #751 = MOVFR2CF_xS { 750, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #750 = MOVFCSR2GR { 749, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 297, 0, 0x0ULL }, // Inst #749 = MOVCF2GR { 748, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 295, 0, 0x0ULL }, // Inst #748 = MOVCF2FR_xS { 747, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #747 = MOD_WU { 746, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #746 = MOD_W { 745, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #745 = MOD_DU { 744, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #744 = MOD_D { 743, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #743 = MASKNEZ { 742, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #742 = MASKEQZ { 741, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #741 = LU52I_D { 740, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 240, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #740 = LU32I_D { 739, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #739 = LU12I_W { 738, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #738 = LL_W { 737, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #737 = LL_D { 736, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #736 = LLACQ_W { 735, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #735 = LLACQ_D { 734, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #734 = LD_WU { 733, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #733 = LD_W { 732, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #732 = LD_HU { 731, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #731 = LD_H { 730, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #730 = LD_D { 729, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #729 = LD_BU { 728, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #728 = LD_B { 727, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #727 = LDX_WU { 726, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #726 = LDX_W { 725, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #725 = LDX_HU { 724, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #724 = LDX_H { 723, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #723 = LDX_D { 722, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #722 = LDX_BU { 721, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #721 = LDX_B { 720, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #720 = LDR_W { 719, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #719 = LDR_D { 718, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #718 = LDPTR_W { 717, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #717 = LDPTR_D { 716, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #716 = LDPTE { 715, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #715 = LDL_W { 714, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #714 = LDL_D { 713, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #713 = LDLE_W { 712, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #712 = LDLE_H { 711, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #711 = LDLE_D { 710, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #710 = LDLE_B { 709, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #709 = LDGT_W { 708, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #708 = LDGT_H { 707, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #707 = LDGT_D { 706, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #706 = LDGT_B { 705, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #705 = LDDIR { 704, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0, 0x0ULL }, // Inst #704 = JISCR1 { 703, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0, 0x0ULL }, // Inst #703 = JISCR0 { 702, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #702 = JIRL { 701, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #701 = IOCSRWR_W { 700, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #700 = IOCSRWR_H { 699, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #699 = IOCSRWR_D { 698, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #698 = IOCSRWR_B { 697, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #697 = IOCSRRD_W { 696, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #696 = IOCSRRD_H { 695, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #695 = IOCSRRD_D { 694, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #694 = IOCSRRD_B { 693, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #693 = INVTLB { 692, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #692 = IDLE { 691, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #691 = IBAR { 690, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #690 = HVCL { 689, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #689 = GTLBFLUSH { 688, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 243, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #688 = GCSRXCHG { 687, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 240, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #687 = GCSRWR { 686, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #686 = GCSRRD { 685, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #685 = FTINT_W_S { 684, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 265, 0, 0x0ULL }, // Inst #684 = FTINT_W_D { 683, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 263, 0, 0x0ULL }, // Inst #683 = FTINT_L_S { 682, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #682 = FTINT_L_D { 681, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #681 = FTINTRZ_W_S { 680, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 265, 0, 0x0ULL }, // Inst #680 = FTINTRZ_W_D { 679, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 263, 0, 0x0ULL }, // Inst #679 = FTINTRZ_L_S { 678, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #678 = FTINTRZ_L_D { 677, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #677 = FTINTRP_W_S { 676, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 265, 0, 0x0ULL }, // Inst #676 = FTINTRP_W_D { 675, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 263, 0, 0x0ULL }, // Inst #675 = FTINTRP_L_S { 674, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #674 = FTINTRP_L_D { 673, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #673 = FTINTRNE_W_S { 672, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 265, 0, 0x0ULL }, // Inst #672 = FTINTRNE_W_D { 671, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 263, 0, 0x0ULL }, // Inst #671 = FTINTRNE_L_S { 670, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #670 = FTINTRNE_L_D { 669, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #669 = FTINTRM_W_S { 668, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 265, 0, 0x0ULL }, // Inst #668 = FTINTRM_W_D { 667, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 263, 0, 0x0ULL }, // Inst #667 = FTINTRM_L_S { 666, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #666 = FTINTRM_L_D { 665, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #665 = FSUB_S { 664, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #664 = FSUB_D { 663, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 276, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #663 = FST_S { 662, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 273, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #662 = FST_D { 661, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 270, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #661 = FSTX_S { 660, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 267, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #660 = FSTX_D { 659, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 270, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #659 = FSTLE_S { 658, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 267, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #658 = FSTLE_D { 657, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 270, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #657 = FSTGT_S { 656, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 267, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #656 = FSTGT_D { 655, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #655 = FSQRT_S { 654, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #654 = FSQRT_D { 653, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 291, 0, 0x0ULL }, // Inst #653 = FSEL_xS { 652, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 287, 0, 0x0ULL }, // Inst #652 = FSEL_xD { 651, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #651 = FSCALEB_S { 650, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #650 = FSCALEB_D { 649, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #649 = FRSQRT_S { 648, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #648 = FRSQRT_D { 647, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #647 = FRSQRTE_S { 646, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #646 = FRSQRTE_D { 645, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #645 = FRINT_S { 644, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #644 = FRINT_D { 643, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #643 = FRECIP_S { 642, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #642 = FRECIP_D { 641, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #641 = FRECIPE_S { 640, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #640 = FRECIPE_D { 639, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 283, 0, 0x0ULL }, // Inst #639 = FNMSUB_S { 638, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 279, 0, 0x0ULL }, // Inst #638 = FNMSUB_D { 637, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 283, 0, 0x0ULL }, // Inst #637 = FNMADD_S { 636, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 279, 0, 0x0ULL }, // Inst #636 = FNMADD_D { 635, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #635 = FNEG_S { 634, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #634 = FNEG_D { 633, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #633 = FMUL_S { 632, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #632 = FMUL_D { 631, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 283, 0, 0x0ULL }, // Inst #631 = FMSUB_S { 630, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 279, 0, 0x0ULL }, // Inst #630 = FMSUB_D { 629, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #629 = FMOV_S { 628, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #628 = FMOV_D { 627, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #627 = FMIN_S { 626, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #626 = FMIN_D { 625, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #625 = FMINA_S { 624, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #624 = FMINA_D { 623, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #623 = FMAX_S { 622, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #622 = FMAX_D { 621, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #621 = FMAXA_S { 620, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #620 = FMAXA_D { 619, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 283, 0, 0x0ULL }, // Inst #619 = FMADD_S { 618, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 279, 0, 0x0ULL }, // Inst #618 = FMADD_D { 617, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #617 = FLOGB_S { 616, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #616 = FLOGB_D { 615, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 276, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #615 = FLD_S { 614, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 273, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #614 = FLD_D { 613, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 270, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #613 = FLDX_S { 612, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 267, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #612 = FLDX_D { 611, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 270, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #611 = FLDLE_S { 610, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 267, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #610 = FLDLE_D { 609, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 270, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #609 = FLDGT_S { 608, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 267, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #608 = FLDGT_D { 607, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #607 = FFINT_S_W { 606, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 265, 0, 0x0ULL }, // Inst #606 = FFINT_S_L { 605, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 263, 0, 0x0ULL }, // Inst #605 = FFINT_D_W { 604, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #604 = FFINT_D_L { 603, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #603 = FDIV_S { 602, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #602 = FDIV_D { 601, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #601 = FCVT_UD_D { 600, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 265, 0, 0x0ULL }, // Inst #600 = FCVT_S_D { 599, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #599 = FCVT_LD_D { 598, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 263, 0, 0x0ULL }, // Inst #598 = FCVT_D_S { 597, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #597 = FCVT_D_LD { 596, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #596 = FCOPYSIGN_S { 595, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #595 = FCOPYSIGN_D { 594, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #594 = FCMP_SUN_S { 593, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #593 = FCMP_SUN_D { 592, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #592 = FCMP_SUNE_S { 591, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #591 = FCMP_SUNE_D { 590, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #590 = FCMP_SULT_S { 589, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #589 = FCMP_SULT_D { 588, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #588 = FCMP_SULE_S { 587, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #587 = FCMP_SULE_D { 586, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #586 = FCMP_SUEQ_S { 585, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #585 = FCMP_SUEQ_D { 584, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #584 = FCMP_SOR_S { 583, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #583 = FCMP_SOR_D { 582, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #582 = FCMP_SNE_S { 581, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #581 = FCMP_SNE_D { 580, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #580 = FCMP_SLT_S { 579, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #579 = FCMP_SLT_D { 578, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #578 = FCMP_SLE_S { 577, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #577 = FCMP_SLE_D { 576, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #576 = FCMP_SEQ_S { 575, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #575 = FCMP_SEQ_D { 574, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #574 = FCMP_SAF_S { 573, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #573 = FCMP_SAF_D { 572, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #572 = FCMP_CUN_S { 571, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #571 = FCMP_CUN_D { 570, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #570 = FCMP_CUNE_S { 569, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #569 = FCMP_CUNE_D { 568, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #568 = FCMP_CULT_S { 567, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #567 = FCMP_CULT_D { 566, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #566 = FCMP_CULE_S { 565, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #565 = FCMP_CULE_D { 564, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #564 = FCMP_CUEQ_S { 563, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #563 = FCMP_CUEQ_D { 562, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #562 = FCMP_COR_S { 561, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #561 = FCMP_COR_D { 560, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #560 = FCMP_CNE_S { 559, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #559 = FCMP_CNE_D { 558, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #558 = FCMP_CLT_S { 557, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #557 = FCMP_CLT_D { 556, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #556 = FCMP_CLE_S { 555, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #555 = FCMP_CLE_D { 554, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #554 = FCMP_CEQ_S { 553, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #553 = FCMP_CEQ_D { 552, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #552 = FCMP_CAF_S { 551, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #551 = FCMP_CAF_D { 550, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #550 = FCLASS_S { 549, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #549 = FCLASS_D { 548, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #548 = FADD_S { 547, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #547 = FADD_D { 546, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #546 = FABS_S { 545, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #545 = FABS_D { 544, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #544 = EXT_W_H { 543, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #543 = EXT_W_B { 542, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #542 = ERTN { 541, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #541 = DIV_WU { 540, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #540 = DIV_W { 539, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #539 = DIV_DU { 538, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #538 = DIV_D { 537, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #537 = DBCL { 536, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #536 = DBAR { 535, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #535 = CTZ_W { 534, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #534 = CTZ_D { 533, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #533 = CTO_W { 532, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #532 = CTO_D { 531, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 243, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #531 = CSRXCHG { 530, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 240, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #530 = CSRWR { 529, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #529 = CSRRD { 528, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #528 = CRC_W_W_W { 527, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #527 = CRC_W_H_W { 526, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #526 = CRC_W_D_W { 525, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #525 = CRC_W_B_W { 524, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #524 = CRCC_W_W_W { 523, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #523 = CRCC_W_H_W { 522, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #522 = CRCC_W_D_W { 521, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #521 = CRCC_W_B_W { 520, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #520 = CPUCFG { 519, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #519 = CLZ_W { 518, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #518 = CLZ_D { 517, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #517 = CLO_W { 516, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #516 = CLO_D { 515, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 237, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #515 = CACOP { 514, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 152, 0, 0x0ULL }, // Inst #514 = BYTEPICK_W { 513, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 152, 0, 0x0ULL }, // Inst #513 = BYTEPICK_D { 512, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 233, 0, 0x0ULL }, // Inst #512 = BSTRPICK_W { 511, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 233, 0, 0x0ULL }, // Inst #511 = BSTRPICK_D { 510, 5, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 228, 0, 0x0ULL }, // Inst #510 = BSTRINS_W { 509, 5, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 228, 0, 0x0ULL }, // Inst #509 = BSTRINS_D { 508, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #508 = BREAK { 507, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #507 = BNEZ { 506, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #506 = BNE { 505, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #505 = BLTU { 504, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #504 = BLT { 503, 1, 0, 4, 0, 0, 1, LoongArchImpOpBase + 3, 0, 0|(1ULL<<MCID::Call), 0x0ULL }, // Inst #503 = BL { 502, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #502 = BITREV_W { 501, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #501 = BITREV_D { 500, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #500 = BITREV_8B { 499, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0, 0x0ULL }, // Inst #499 = BITREV_4B { 498, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #498 = BGEU { 497, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #497 = BGE { 496, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #496 = BEQZ { 495, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #495 = BEQ { 494, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 226, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #494 = BCNEZ { 493, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 226, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #493 = BCEQZ { 492, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #492 = B { 491, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #491 = ASRTLE_D { 490, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #490 = ASRTGT_D { 489, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #489 = ARMXOR_W { 488, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #488 = ARMSUB_W { 487, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #487 = ARMSRL_W { 486, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 223, 0, 0x0ULL }, // Inst #486 = ARMSRLI_W { 485, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #485 = ARMSRA_W { 484, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 223, 0, 0x0ULL }, // Inst #484 = ARMSRAI_W { 483, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #483 = ARMSLL_W { 482, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 223, 0, 0x0ULL }, // Inst #482 = ARMSLLI_W { 481, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #481 = ARMSBC_W { 480, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #480 = ARMRRX_W { 479, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #479 = ARMROTR_W { 478, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 223, 0, 0x0ULL }, // Inst #478 = ARMROTRI_W { 477, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #477 = ARMOR_W { 476, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #476 = ARMNOT_W { 475, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #475 = ARMMTFLAG { 474, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #474 = ARMMOV_W { 473, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #473 = ARMMOV_D { 472, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #472 = ARMMOVE { 471, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #471 = ARMMFFLAG { 470, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #470 = ARMAND_W { 469, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #469 = ARMADD_W { 468, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #468 = ARMADC_W { 467, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #467 = ANDN { 466, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #466 = ANDI { 465, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #465 = AND { 464, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #464 = AMXOR__DB_W { 463, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #463 = AMXOR__DB_D { 462, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #462 = AMXOR_W { 461, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #461 = AMXOR_D { 460, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #460 = AMSWAP__DB_W { 459, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #459 = AMSWAP__DB_H { 458, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #458 = AMSWAP__DB_D { 457, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #457 = AMSWAP__DB_B { 456, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #456 = AMSWAP_W { 455, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #455 = AMSWAP_H { 454, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #454 = AMSWAP_D { 453, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #453 = AMSWAP_B { 452, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #452 = AMOR__DB_W { 451, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #451 = AMOR__DB_D { 450, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #450 = AMOR_W { 449, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #449 = AMOR_D { 448, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #448 = AMMIN__DB_WU { 447, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #447 = AMMIN__DB_W { 446, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #446 = AMMIN__DB_DU { 445, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #445 = AMMIN__DB_D { 444, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #444 = AMMIN_WU { 443, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #443 = AMMIN_W { 442, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #442 = AMMIN_DU { 441, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #441 = AMMIN_D { 440, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #440 = AMMAX__DB_WU { 439, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #439 = AMMAX__DB_W { 438, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #438 = AMMAX__DB_DU { 437, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #437 = AMMAX__DB_D { 436, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #436 = AMMAX_WU { 435, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #435 = AMMAX_W { 434, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #434 = AMMAX_DU { 433, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #433 = AMMAX_D { 432, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #432 = AMCAS__DB_W { 431, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #431 = AMCAS__DB_H { 430, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #430 = AMCAS__DB_D { 429, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #429 = AMCAS__DB_B { 428, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #428 = AMCAS_W { 427, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #427 = AMCAS_H { 426, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #426 = AMCAS_D { 425, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #425 = AMCAS_B { 424, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #424 = AMAND__DB_W { 423, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #423 = AMAND__DB_D { 422, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #422 = AMAND_W { 421, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #421 = AMAND_D { 420, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #420 = AMADD__DB_W { 419, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #419 = AMADD__DB_H { 418, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #418 = AMADD__DB_D { 417, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #417 = AMADD__DB_B { 416, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #416 = AMADD_W { 415, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #415 = AMADD_H { 414, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #414 = AMADD_D { 413, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 220, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #413 = AMADD_B { 412, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 152, 0, 0x0ULL }, // Inst #412 = ALSL_WU { 411, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 152, 0, 0x0ULL }, // Inst #411 = ALSL_W { 410, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 152, 0, 0x0ULL }, // Inst #410 = ALSL_D { 409, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #409 = ADD_W { 408, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #408 = ADD_D { 407, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #407 = ADDU16I_D { 406, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #406 = ADDU12I_W { 405, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #405 = ADDU12I_D { 404, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0, 0x0ULL }, // Inst #404 = ADDI_W { 403, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #403 = ADDI_D { 402, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #402 = ADC_W { 401, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #401 = ADC_H { 400, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #400 = ADC_D { 399, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #399 = ADC_B { 398, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #398 = WRFCSR { 397, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #397 = RDFCSR { 396, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 216, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #396 = PseudoXVREPLI_W { 395, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 216, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #395 = PseudoXVREPLI_H { 394, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 216, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #394 = PseudoXVREPLI_D { 393, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 216, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #393 = PseudoXVREPLI_B { 392, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 212, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #392 = PseudoXVINSGR2VR_H { 391, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 212, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #391 = PseudoXVINSGR2VR_B { 390, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #390 = PseudoXVBZ_W { 389, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #389 = PseudoXVBZ_H { 388, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #388 = PseudoXVBZ_D { 387, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #387 = PseudoXVBZ_B { 386, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #386 = PseudoXVBZ { 385, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #385 = PseudoXVBNZ_W { 384, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #384 = PseudoXVBNZ_H { 383, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #383 = PseudoXVBNZ_D { 382, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #382 = PseudoXVBNZ_B { 381, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #381 = PseudoXVBNZ { 380, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #380 = PseudoVREPLI_W { 379, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #379 = PseudoVREPLI_H { 378, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #378 = PseudoVREPLI_D { 377, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #377 = PseudoVREPLI_B { 376, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 206, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #376 = PseudoVBZ_W { 375, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 206, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #375 = PseudoVBZ_H { 374, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 206, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #374 = PseudoVBZ_D { 373, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 206, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #373 = PseudoVBZ_B { 372, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 206, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #372 = PseudoVBZ { 371, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 206, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #371 = PseudoVBNZ_W { 370, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 206, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #370 = PseudoVBNZ_H { 369, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 206, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #369 = PseudoVBNZ_D { 368, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 206, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #368 = PseudoVBNZ_B { 367, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 206, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #367 = PseudoVBNZ { 366, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #366 = PseudoUNIMP { 365, 1, 0, 4, 0, 1, 0, LoongArchImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #365 = PseudoTAIL_MEDIUM { 364, 1, 0, 4, 0, 1, 0, LoongArchImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #364 = PseudoTAIL_LARGE { 363, 1, 0, 4, 0, 1, 0, LoongArchImpOpBase + 2, 205, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #363 = PseudoTAILIndirect { 362, 2, 0, 4, 0, 1, 0, LoongArchImpOpBase + 2, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #362 = PseudoTAIL36 { 361, 1, 0, 4, 0, 1, 0, LoongArchImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #361 = PseudoTAIL { 360, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 180, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #360 = PseudoST_CFR { 359, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #359 = PseudoRET { 358, 7, 2, 44, 0, 0, 0, LoongArchImpOpBase + 0, 198, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #358 = PseudoMaskedCmpXchg32 { 357, 6, 2, 36, 0, 0, 0, LoongArchImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #357 = PseudoMaskedAtomicSwap32 { 356, 7, 3, 48, 0, 0, 0, LoongArchImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #356 = PseudoMaskedAtomicLoadUMin32 { 355, 7, 3, 48, 0, 0, 0, LoongArchImpOpBase + 0, 191, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #355 = PseudoMaskedAtomicLoadUMax32 { 354, 6, 2, 36, 0, 0, 0, LoongArchImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #354 = PseudoMaskedAtomicLoadSub32 { 353, 6, 2, 36, 0, 0, 0, LoongArchImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #353 = PseudoMaskedAtomicLoadNand32 { 352, 8, 3, 56, 0, 0, 0, LoongArchImpOpBase + 0, 183, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #352 = PseudoMaskedAtomicLoadMin32 { 351, 8, 3, 56, 0, 0, 0, LoongArchImpOpBase + 0, 183, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #351 = PseudoMaskedAtomicLoadMax32 { 350, 6, 2, 36, 0, 0, 0, LoongArchImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #350 = PseudoMaskedAtomicLoadAdd32 { 349, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #349 = PseudoLI_W { 348, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #348 = PseudoLI_D { 347, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 180, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #347 = PseudoLD_CFR { 346, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #346 = PseudoLA_TLS_LE { 345, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #345 = PseudoLA_TLS_LD_LARGE { 344, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #344 = PseudoLA_TLS_LD { 343, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #343 = PseudoLA_TLS_IE_LARGE { 342, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #342 = PseudoLA_TLS_IE { 341, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #341 = PseudoLA_TLS_GD_LARGE { 340, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #340 = PseudoLA_TLS_GD { 339, 3, 1, 4, 0, 0, 2, LoongArchImpOpBase + 6, 177, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #339 = PseudoLA_TLS_DESC_PC_LARGE { 338, 2, 1, 4, 0, 0, 1, LoongArchImpOpBase + 3, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #338 = PseudoLA_TLS_DESC_PC { 337, 3, 1, 4, 0, 0, 1, LoongArchImpOpBase + 3, 177, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #337 = PseudoLA_TLS_DESC_ABS_LARGE { 336, 2, 1, 4, 0, 0, 1, LoongArchImpOpBase + 3, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #336 = PseudoLA_TLS_DESC_ABS { 335, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #335 = PseudoLA_PCREL_LARGE { 334, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #334 = PseudoLA_PCREL { 333, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #333 = PseudoLA_GOT_LARGE { 332, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #332 = PseudoLA_GOT { 331, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 177, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #331 = PseudoLA_ABS_LARGE { 330, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #330 = PseudoLA_ABS { 329, 2, 0, 4, 0, 1, 0, LoongArchImpOpBase + 2, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #329 = PseudoJIRL_TAIL { 328, 2, 0, 4, 0, 0, 1, LoongArchImpOpBase + 3, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #328 = PseudoJIRL_CALL { 327, 3, 1, 4, 0, 1, 1, LoongArchImpOpBase + 4, 177, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #327 = PseudoDESC_CALL { 326, 2, 1, 12, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #326 = PseudoCopyCFR { 325, 6, 2, 36, 0, 0, 0, LoongArchImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #325 = PseudoCmpXchg64 { 324, 6, 2, 36, 0, 0, 0, LoongArchImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #324 = PseudoCmpXchg32 { 323, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #323 = PseudoCTPOP { 322, 1, 0, 4, 0, 0, 1, LoongArchImpOpBase + 3, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #322 = PseudoCALL_MEDIUM { 321, 1, 0, 4, 0, 0, 1, LoongArchImpOpBase + 3, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #321 = PseudoCALL_LARGE { 320, 1, 0, 4, 0, 0, 1, LoongArchImpOpBase + 3, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #320 = PseudoCALLIndirect { 319, 1, 0, 4, 0, 0, 1, LoongArchImpOpBase + 3, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #319 = PseudoCALL36 { 318, 1, 0, 4, 0, 0, 1, LoongArchImpOpBase + 3, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #318 = PseudoCALL { 317, 1, 0, 4, 0, 1, 0, LoongArchImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #317 = PseudoB_TAIL { 316, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #316 = PseudoBRIND { 315, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #315 = PseudoBR { 314, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #314 = PseudoAtomicSwap32 { 313, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #313 = PseudoAtomicStoreW { 312, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #312 = PseudoAtomicStoreD { 311, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #311 = PseudoAtomicLoadXor32 { 310, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #310 = PseudoAtomicLoadSub32 { 309, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #309 = PseudoAtomicLoadOr32 { 308, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #308 = PseudoAtomicLoadNand64 { 307, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #307 = PseudoAtomicLoadNand32 { 306, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #306 = PseudoAtomicLoadAnd32 { 305, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #305 = PseudoAtomicLoadAdd32 { 304, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #304 = PseudoAddTPRel_W { 303, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #303 = PseudoAddTPRel_D { 302, 2, 0, 4, 0, 1, 1, LoongArchImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #302 = ADJCALLSTACKUP { 301, 2, 0, 4, 0, 1, 1, LoongArchImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #301 = ADJCALLSTACKDOWN { 300, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #300 = G_UBFX { 299, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #299 = G_SBFX { 298, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #298 = G_VECREDUCE_UMIN { 297, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #297 = G_VECREDUCE_UMAX { 296, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #296 = G_VECREDUCE_SMIN { 295, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #295 = G_VECREDUCE_SMAX { 294, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #294 = G_VECREDUCE_XOR { 293, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #293 = G_VECREDUCE_OR { 292, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #292 = G_VECREDUCE_AND { 291, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #291 = G_VECREDUCE_MUL { 290, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #290 = G_VECREDUCE_ADD { 289, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #289 = G_VECREDUCE_FMINIMUM { 288, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #288 = G_VECREDUCE_FMAXIMUM { 287, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #287 = G_VECREDUCE_FMIN { 286, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #286 = G_VECREDUCE_FMAX { 285, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #285 = G_VECREDUCE_FMUL { 284, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #284 = G_VECREDUCE_FADD { 283, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #283 = G_VECREDUCE_SEQ_FMUL { 282, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #282 = G_VECREDUCE_SEQ_FADD { 281, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #281 = G_UBSANTRAP { 280, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #280 = G_DEBUGTRAP { 279, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #279 = G_TRAP { 278, 3, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #278 = G_BZERO { 277, 4, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #277 = G_MEMSET { 276, 4, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #276 = G_MEMMOVE { 275, 3, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #275 = G_MEMCPY_INLINE { 274, 4, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #274 = G_MEMCPY { 273, 2, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #273 = G_WRITE_REGISTER { 272, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #272 = G_READ_REGISTER { 271, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #271 = G_STRICT_FLDEXP { 270, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #270 = G_STRICT_FSQRT { 269, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #269 = G_STRICT_FMA { 268, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #268 = G_STRICT_FREM { 267, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #267 = G_STRICT_FDIV { 266, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #266 = G_STRICT_FMUL { 265, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #265 = G_STRICT_FSUB { 264, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #264 = G_STRICT_FADD { 263, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #263 = G_STACKRESTORE { 262, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #262 = G_STACKSAVE { 261, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #261 = G_DYN_STACKALLOC { 260, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #260 = G_JUMP_TABLE { 259, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #259 = G_BLOCK_ADDR { 258, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #258 = G_ADDRSPACE_CAST { 257, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #257 = G_FNEARBYINT { 256, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #256 = G_FRINT { 255, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #255 = G_FFLOOR { 254, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #254 = G_FSQRT { 253, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #253 = G_FTANH { 252, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #252 = G_FSINH { 251, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #251 = G_FCOSH { 250, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #250 = G_FATAN { 249, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #249 = G_FASIN { 248, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #248 = G_FACOS { 247, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #247 = G_FTAN { 246, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #246 = G_FSIN { 245, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #245 = G_FCOS { 244, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #244 = G_FCEIL { 243, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #243 = G_BITREVERSE { 242, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #242 = G_BSWAP { 241, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #241 = G_CTPOP { 240, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #240 = G_CTLZ_ZERO_UNDEF { 239, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #239 = G_CTLZ { 238, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #238 = G_CTTZ_ZERO_UNDEF { 237, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #237 = G_CTTZ { 236, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #236 = G_VECTOR_COMPRESS { 235, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #235 = G_SPLAT_VECTOR { 234, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #234 = G_SHUFFLE_VECTOR { 233, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #233 = G_EXTRACT_VECTOR_ELT { 232, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #232 = G_INSERT_VECTOR_ELT { 231, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #231 = G_EXTRACT_SUBVECTOR { 230, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #230 = G_INSERT_SUBVECTOR { 229, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #229 = G_VSCALE { 228, 3, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #228 = G_BRJT { 227, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #227 = G_BR { 226, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #226 = G_LLROUND { 225, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #225 = G_LROUND { 224, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #224 = G_ABS { 223, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #223 = G_UMAX { 222, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #222 = G_UMIN { 221, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #221 = G_SMAX { 220, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #220 = G_SMIN { 219, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #219 = G_PTRMASK { 218, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #218 = G_PTR_ADD { 217, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #217 = G_RESET_FPMODE { 216, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #216 = G_SET_FPMODE { 215, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #215 = G_GET_FPMODE { 214, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #214 = G_RESET_FPENV { 213, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #213 = G_SET_FPENV { 212, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #212 = G_GET_FPENV { 211, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #211 = G_FMAXIMUM { 210, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #210 = G_FMINIMUM { 209, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #209 = G_FMAXNUM_IEEE { 208, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #208 = G_FMINNUM_IEEE { 207, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #207 = G_FMAXNUM { 206, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #206 = G_FMINNUM { 205, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #205 = G_FCANONICALIZE { 204, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #204 = G_IS_FPCLASS { 203, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #203 = G_FCOPYSIGN { 202, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #202 = G_FABS { 201, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #201 = G_FPTOUI_SAT { 200, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #200 = G_FPTOSI_SAT { 199, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #199 = G_UITOFP { 198, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #198 = G_SITOFP { 197, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #197 = G_FPTOUI { 196, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #196 = G_FPTOSI { 195, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #195 = G_FPTRUNC { 194, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #194 = G_FPEXT { 193, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #193 = G_FNEG { 192, 3, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #192 = G_FFREXP { 191, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #191 = G_FLDEXP { 190, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #190 = G_FLOG10 { 189, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #189 = G_FLOG2 { 188, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #188 = G_FLOG { 187, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #187 = G_FEXP10 { 186, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #186 = G_FEXP2 { 185, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #185 = G_FEXP { 184, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #184 = G_FPOWI { 183, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #183 = G_FPOW { 182, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #182 = G_FREM { 181, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #181 = G_FDIV { 180, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #180 = G_FMAD { 179, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #179 = G_FMA { 178, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #178 = G_FMUL { 177, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #177 = G_FSUB { 176, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #176 = G_FADD { 175, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #175 = G_UDIVFIXSAT { 174, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #174 = G_SDIVFIXSAT { 173, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #173 = G_UDIVFIX { 172, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #172 = G_SDIVFIX { 171, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #171 = G_UMULFIXSAT { 170, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #170 = G_SMULFIXSAT { 169, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #169 = G_UMULFIX { 168, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #168 = G_SMULFIX { 167, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #167 = G_SSHLSAT { 166, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #166 = G_USHLSAT { 165, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #165 = G_SSUBSAT { 164, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #164 = G_USUBSAT { 163, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #163 = G_SADDSAT { 162, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #162 = G_UADDSAT { 161, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #161 = G_SMULH { 160, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #160 = G_UMULH { 159, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #159 = G_SMULO { 158, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #158 = G_UMULO { 157, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #157 = G_SSUBE { 156, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #156 = G_SSUBO { 155, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #155 = G_SADDE { 154, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #154 = G_SADDO { 153, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #153 = G_USUBE { 152, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #152 = G_USUBO { 151, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #151 = G_UADDE { 150, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #150 = G_UADDO { 149, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #149 = G_SELECT { 148, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #148 = G_UCMP { 147, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #147 = G_SCMP { 146, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #146 = G_FCMP { 145, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #145 = G_ICMP { 144, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #144 = G_ROTL { 143, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #143 = G_ROTR { 142, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #142 = G_FSHR { 141, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #141 = G_FSHL { 140, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #140 = G_ASHR { 139, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #139 = G_LSHR { 138, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #138 = G_SHL { 137, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #137 = G_ZEXT { 136, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #136 = G_SEXT_INREG { 135, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #135 = G_SEXT { 134, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #134 = G_VAARG { 133, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #133 = G_VASTART { 132, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #132 = G_FCONSTANT { 131, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #131 = G_CONSTANT { 130, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #130 = G_TRUNC { 129, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #129 = G_ANYEXT { 128, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #128 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS { 127, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #127 = G_INTRINSIC_CONVERGENT { 126, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #126 = G_INTRINSIC_W_SIDE_EFFECTS { 125, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #125 = G_INTRINSIC { 124, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #124 = G_INVOKE_REGION_START { 123, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #123 = G_BRINDIRECT { 122, 2, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #122 = G_BRCOND { 121, 4, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 94, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #121 = G_PREFETCH { 120, 2, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #120 = G_FENCE { 119, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #119 = G_ATOMICRMW_USUB_SAT { 118, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #118 = G_ATOMICRMW_USUB_COND { 117, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #117 = G_ATOMICRMW_UDEC_WRAP { 116, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #116 = G_ATOMICRMW_UINC_WRAP { 115, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #115 = G_ATOMICRMW_FMIN { 114, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #114 = G_ATOMICRMW_FMAX { 113, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #113 = G_ATOMICRMW_FSUB { 112, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #112 = G_ATOMICRMW_FADD { 111, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #111 = G_ATOMICRMW_UMIN { 110, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #110 = G_ATOMICRMW_UMAX { 109, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #109 = G_ATOMICRMW_MIN { 108, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #108 = G_ATOMICRMW_MAX { 107, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #107 = G_ATOMICRMW_XOR { 106, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #106 = G_ATOMICRMW_OR { 105, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #105 = G_ATOMICRMW_NAND { 104, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #104 = G_ATOMICRMW_AND { 103, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #103 = G_ATOMICRMW_SUB { 102, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #102 = G_ATOMICRMW_ADD { 101, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #101 = G_ATOMICRMW_XCHG { 100, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #100 = G_ATOMIC_CMPXCHG { 99, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #99 = G_ATOMIC_CMPXCHG_WITH_SUCCESS { 98, 5, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #98 = G_INDEXED_STORE { 97, 2, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #97 = G_STORE { 96, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #96 = G_INDEXED_ZEXTLOAD { 95, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #95 = G_INDEXED_SEXTLOAD { 94, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #94 = G_INDEXED_LOAD { 93, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #93 = G_ZEXTLOAD { 92, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #92 = G_SEXTLOAD { 91, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #91 = G_LOAD { 90, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #90 = G_READSTEADYCOUNTER { 89, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #89 = G_READCYCLECOUNTER { 88, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #88 = G_INTRINSIC_ROUNDEVEN { 87, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #87 = G_INTRINSIC_LLRINT { 86, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #86 = G_INTRINSIC_LRINT { 85, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #85 = G_INTRINSIC_ROUND { 84, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #84 = G_INTRINSIC_TRUNC { 83, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #83 = G_INTRINSIC_FPTRUNC_ROUND { 82, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #82 = G_CONSTANT_FOLD_BARRIER { 81, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #81 = G_FREEZE { 80, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #80 = G_BITCAST { 79, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #79 = G_INTTOPTR { 78, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #78 = G_PTRTOINT { 77, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #77 = G_CONCAT_VECTORS { 76, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #76 = G_BUILD_VECTOR_TRUNC { 75, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #75 = G_BUILD_VECTOR { 74, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #74 = G_MERGE_VALUES { 73, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #73 = G_INSERT { 72, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #72 = G_UNMERGE_VALUES { 71, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #71 = G_EXTRACT { 70, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #70 = G_CONSTANT_POOL { 69, 5, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #69 = G_PTRAUTH_GLOBAL_VALUE { 68, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #68 = G_GLOBAL_VALUE { 67, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #67 = G_FRAME_INDEX { 66, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #66 = G_PHI { 65, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #65 = G_IMPLICIT_DEF { 64, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #64 = G_XOR { 63, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #63 = G_OR { 62, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #62 = G_AND { 61, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #61 = G_UDIVREM { 60, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #60 = G_SDIVREM { 59, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #59 = G_UREM { 58, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #58 = G_SREM { 57, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #57 = G_UDIV { 56, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #56 = G_SDIV { 55, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #55 = G_MUL { 54, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #54 = G_SUB { 53, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #53 = G_ADD { 52, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #52 = G_ASSERT_ALIGN { 51, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #51 = G_ASSERT_ZEXT { 50, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #50 = G_ASSERT_SEXT { 49, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #49 = CONVERGENCECTRL_GLUE { 48, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #48 = CONVERGENCECTRL_LOOP { 47, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_ANCHOR { 46, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_ENTRY { 45, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #45 = JUMP_TABLE_DEBUG_INFO { 44, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #44 = MEMBARRIER { 43, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #43 = FAKE_USE { 42, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #42 = ICALL_BRANCH_FUNNEL { 41, 3, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #41 = PATCHABLE_TYPED_EVENT_CALL { 40, 2, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #40 = PATCHABLE_EVENT_CALL { 39, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #39 = PATCHABLE_TAIL_CALL { 38, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #38 = PATCHABLE_FUNCTION_EXIT { 37, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #37 = PATCHABLE_RET { 36, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #36 = PATCHABLE_FUNCTION_ENTER { 35, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #35 = PATCHABLE_OP { 34, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #34 = FAULTING_OP { 33, 2, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #33 = LOCAL_ESCAPE { 32, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #32 = STATEPOINT { 31, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #31 = PREALLOCATED_ARG { 30, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #30 = PREALLOCATED_SETUP { 29, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #29 = LOAD_STACK_GUARD { 28, 6, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #28 = PATCHPOINT { 27, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #27 = FENTRY_CALL { 26, 2, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #26 = STACKMAP { 25, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #25 = ARITH_FENCE { 24, 4, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #24 = PSEUDO_PROBE { 23, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #23 = LIFETIME_END { 22, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #22 = LIFETIME_START { 21, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #21 = BUNDLE { 20, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #20 = COPY { 19, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #19 = REG_SEQUENCE { 18, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #18 = DBG_LABEL { 17, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #17 = DBG_PHI { 16, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #16 = DBG_INSTR_REF { 15, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #15 = DBG_VALUE_LIST { 14, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #14 = DBG_VALUE { 13, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #13 = COPY_TO_REGCLASS { 12, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #12 = SUBREG_TO_REG { 11, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #11 = INIT_UNDEF { 10, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #10 = IMPLICIT_DEF { 9, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #9 = INSERT_SUBREG { 8, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG { 7, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #7 = KILL { 6, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL { 5, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #5 = GC_LABEL { 4, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #4 = EH_LABEL { 3, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION { 2, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2 = INLINEASM_BR { 1, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #1 = INLINEASM { 0, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #0 = PHI }, { /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 1 */ /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 152 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 156 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 161 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 164 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 166 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 167 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 169 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 175 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 177 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 180 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 183 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 191 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 198 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 205 */ { LoongArch::GPRTRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 206 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 208 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 210 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 212 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 216 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 218 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 220 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 223 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 226 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 228 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 233 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 237 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 240 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 243 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 247 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 249 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 251 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 254 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 257 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 260 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 263 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 265 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 267 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 270 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 273 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 276 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 279 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 283 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 287 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 291 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 295 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 297 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 299 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FCSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 301 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 303 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 305 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 307 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 309 */ { LoongArch::FCSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 311 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 314 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 316 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 318 */ { LoongArch::SCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 320 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::SCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 322 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 325 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 328 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 332 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 333 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 336 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 339 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 343 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 347 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 349 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 351 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 355 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 359 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 362 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 365 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 368 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 370 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 373 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 375 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 379 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 382 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 385 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 389 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 393 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 397 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 400 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 403 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 406 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 408 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 411 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 413 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }, { /* 0 */ /* 0 */ LoongArch::R3, LoongArch::R3, /* 2 */ LoongArch::R3, /* 3 */ LoongArch::R1, /* 4 */ LoongArch::R4, LoongArch::R4, /* 6 */ LoongArch::R1, LoongArch::R4, } }; #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Woverlength-strings" #endif extern const char LoongArchInstrNameData[] = { /* 0 */ "G_FLOG10\0" /* 9 */ "G_FEXP10\0" /* 18 */ "JISCR0\0" /* 25 */ "JISCR1\0" /* 32 */ "PseudoMaskedAtomicLoadSub32\0" /* 60 */ "PseudoAtomicLoadSub32\0" /* 82 */ "PseudoMaskedAtomicLoadAdd32\0" /* 110 */ "PseudoAtomicLoadAdd32\0" /* 132 */ "PseudoAtomicLoadAnd32\0" /* 154 */ "PseudoMaskedAtomicLoadNand32\0" /* 183 */ "PseudoAtomicLoadNand32\0" /* 206 */ "PseudoMaskedCmpXchg32\0" /* 228 */ "PseudoCmpXchg32\0" /* 244 */ "PseudoMaskedAtomicLoadUMin32\0" /* 273 */ "PseudoMaskedAtomicLoadMin32\0" /* 301 */ "PseudoMaskedAtomicSwap32\0" /* 326 */ "PseudoAtomicSwap32\0" /* 345 */ "PseudoAtomicLoadOr32\0" /* 366 */ "PseudoAtomicLoadXor32\0" /* 388 */ "PseudoMaskedAtomicLoadUMax32\0" /* 417 */ "PseudoMaskedAtomicLoadMax32\0" /* 445 */ "G_FLOG2\0" /* 453 */ "G_FEXP2\0" /* 461 */ "MOVFR2GR_S_64\0" /* 475 */ "MOVGR2FR_W_64\0" /* 489 */ "PseudoAtomicLoadNand64\0" /* 512 */ "PseudoCmpXchg64\0" /* 528 */ "PseudoTAIL36\0" /* 541 */ "PseudoCALL36\0" /* 554 */ "G_FMA\0" /* 560 */ "G_STRICT_FMA\0" /* 573 */ "BITREV_4B\0" /* 583 */ "BITREV_8B\0" /* 593 */ "INVTLB\0" /* 600 */ "G_FSUB\0" /* 607 */ "G_STRICT_FSUB\0" /* 621 */ "G_ATOMICRMW_FSUB\0" /* 638 */ "G_SUB\0" /* 644 */ "G_ATOMICRMW_SUB\0" /* 660 */ "XVREPLVE0_B\0" /* 672 */ "XVADDA_B\0" /* 681 */ "X86SRA_B\0" /* 690 */ "XVSRA_B\0" /* 698 */ "AMADD__DB_B\0" /* 710 */ "AMSWAP__DB_B\0" /* 723 */ "AMCAS__DB_B\0" /* 735 */ "X86SUB_B\0" /* 744 */ "XVMSUB_B\0" /* 753 */ "XVSSUB_B\0" /* 762 */ "XVSUB_B\0" /* 770 */ "X86SBC_B\0" /* 779 */ "X86ADC_B\0" /* 788 */ "X86DEC_B\0" /* 797 */ "X86INC_B\0" /* 806 */ "X86ADD_B\0" /* 815 */ "AMADD_B\0" /* 823 */ "XVMADD_B\0" /* 832 */ "XVSADD_B\0" /* 841 */ "XVADD_B\0" /* 849 */ "LD_B\0" /* 854 */ "X86AND_B\0" /* 863 */ "XVPACKOD_B\0" /* 874 */ "XVPICKOD_B\0" /* 885 */ "XVMOD_B\0" /* 893 */ "IOCSRRD_B\0" /* 903 */ "XVABSD_B\0" /* 912 */ "VEXT2XV_D_B\0" /* 924 */ "LDLE_B\0" /* 931 */ "XVSLE_B\0" /* 939 */ "STLE_B\0" /* 946 */ "XVREPLVE_B\0" /* 957 */ "XVSHUF_B\0" /* 966 */ "XVNEG_B\0" /* 974 */ "XVAVG_B\0" /* 982 */ "XVMUH_B\0" /* 990 */ "XVILVH_B\0" /* 999 */ "XVSUBWOD_H_B\0" /* 1012 */ "XVMADDWOD_H_B\0" /* 1026 */ "XVADDWOD_H_B\0" /* 1039 */ "XVMULWOD_H_B\0" /* 1052 */ "XVEXTH_H_B\0" /* 1063 */ "XVSLLWIL_H_B\0" /* 1076 */ "XVSUBWEV_H_B\0" /* 1089 */ "XVMADDWEV_H_B\0" /* 1103 */ "XVADDWEV_H_B\0" /* 1116 */ "XVMULWEV_H_B\0" /* 1129 */ "VEXT2XV_H_B\0" /* 1141 */ "XVHSUBW_H_B\0" /* 1153 */ "XVHADDW_H_B\0" /* 1165 */ "XVSHUF4I_B\0" /* 1176 */ "X86SRAI_B\0" /* 1186 */ "XVSRAI_B\0" /* 1195 */ "XVANDI_B\0" /* 1204 */ "XVSLEI_B\0" /* 1213 */ "XVREPL128VEI_B\0" /* 1228 */ "VREPLVEI_B\0" /* 1239 */ "X86RCLI_B\0" /* 1249 */ "XVBITSELI_B\0" /* 1261 */ "X86SLLI_B\0" /* 1271 */ "XVSLLI_B\0" /* 1280 */ "PseudoXVREPLI_B\0" /* 1296 */ "PseudoVREPLI_B\0" /* 1311 */ "X86SRLI_B\0" /* 1321 */ "XVSRLI_B\0" /* 1330 */ "X86ROTLI_B\0" /* 1341 */ "XVMINI_B\0" /* 1350 */ "XVFRSTPI_B\0" /* 1361 */ "XVSEQI_B\0" /* 1370 */ "XVSRARI_B\0" /* 1380 */ "X86RCRI_B\0" /* 1390 */ "XVBITCLRI_B\0" /* 1402 */ "XVSRLRI_B\0" /* 1412 */ "XVNORI_B\0" /* 1421 */ "XVORI_B\0" /* 1429 */ "XVXORI_B\0" /* 1438 */ "X86ROTRI_B\0" /* 1449 */ "XVROTRI_B\0" /* 1459 */ "XVBITSETI_B\0" /* 1471 */ "XVSLTI_B\0" /* 1480 */ "XVBITREVI_B\0" /* 1492 */ "XVMAXI_B\0" /* 1501 */ "X86RCL_B\0" /* 1510 */ "X86SLL_B\0" /* 1519 */ "XVSLL_B\0" /* 1527 */ "XVLDREPL_B\0" /* 1538 */ "X86SRL_B\0" /* 1547 */ "XVSRL_B\0" /* 1555 */ "X86ROTL_B\0" /* 1565 */ "X86MUL_B\0" /* 1574 */ "XVMUL_B\0" /* 1582 */ "XVILVL_B\0" /* 1591 */ "XVSTELM_B\0" /* 1601 */ "XVMIN_B\0" /* 1609 */ "XVCLO_B\0" /* 1617 */ "AMSWAP_B\0" /* 1626 */ "XVFRSTP_B\0" /* 1636 */ "XVSEQ_B\0" /* 1644 */ "XVSRAR_B\0" /* 1653 */ "X86RCR_B\0" /* 1662 */ "VPICKVE2GR_B\0" /* 1675 */ "XVAVGR_B\0" /* 1684 */ "XVBITCLR_B\0" /* 1695 */ "XVSRLR_B\0" /* 1704 */ "X86OR_B\0" /* 1712 */ "X86XOR_B\0" /* 1721 */ "X86ROTR_B\0" /* 1731 */ "XVROTR_B\0" /* 1740 */ "XVREPLGR2VR_B\0" /* 1754 */ "PseudoXVINSGR2VR_B\0" /* 1773 */ "IOCSRWR_B\0" /* 1783 */ "AMCAS_B\0" /* 1791 */ "XVEXTRINS_B\0" /* 1803 */ "XVSAT_B\0" /* 1811 */ "XVBITSET_B\0" /* 1822 */ "LDGT_B\0" /* 1829 */ "STGT_B\0" /* 1836 */ "XVSLT_B\0" /* 1844 */ "XVPCNT_B\0" /* 1853 */ "ST_B\0" /* 1858 */ "XVMADDWOD_H_BU_B\0" /* 1875 */ "XVADDWOD_H_BU_B\0" /* 1891 */ "XVMULWOD_H_BU_B\0" /* 1907 */ "XVMADDWEV_H_BU_B\0" /* 1924 */ "XVADDWEV_H_BU_B\0" /* 1940 */ "XVMULWEV_H_BU_B\0" /* 1956 */ "XVPACKEV_B\0" /* 1967 */ "XVPICKEV_B\0" /* 1978 */ "XVBITREV_B\0" /* 1989 */ "XVDIV_B\0" /* 1997 */ "XVSIGNCOV_B\0" /* 2009 */ "EXT_W_B\0" /* 2017 */ "VEXT2XV_W_B\0" /* 2029 */ "XVMAX_B\0" /* 2037 */ "LDX_B\0" /* 2043 */ "STX_B\0" /* 2049 */ "PseudoXVBZ_B\0" /* 2062 */ "PseudoVBZ_B\0" /* 2074 */ "XVMSKGEZ_B\0" /* 2085 */ "XVSETALLNEZ_B\0" /* 2099 */ "XVCLZ_B\0" /* 2107 */ "PseudoXVBNZ_B\0" /* 2121 */ "PseudoVBNZ_B\0" /* 2134 */ "XVMSKNZ_B\0" /* 2144 */ "XVSETANYEQZ_B\0" /* 2158 */ "XVMSKLTZ_B\0" /* 2169 */ "G_INTRINSIC\0" /* 2181 */ "G_FPTRUNC\0" /* 2191 */ "G_INTRINSIC_TRUNC\0" /* 2209 */ "G_TRUNC\0" /* 2217 */ "G_BUILD_VECTOR_TRUNC\0" /* 2238 */ "G_DYN_STACKALLOC\0" /* 2255 */ "PseudoLA_TLS_DESC_PC\0" /* 2276 */ "G_FMAD\0" /* 2283 */ "G_INDEXED_SEXTLOAD\0" /* 2302 */ "G_SEXTLOAD\0" /* 2313 */ "G_INDEXED_ZEXTLOAD\0" /* 2332 */ "G_ZEXTLOAD\0" /* 2343 */ "G_INDEXED_LOAD\0" /* 2358 */ "G_LOAD\0" /* 2365 */ "G_VECREDUCE_FADD\0" /* 2382 */ "G_FADD\0" /* 2389 */ "G_VECREDUCE_SEQ_FADD\0" /* 2410 */ "G_STRICT_FADD\0" /* 2424 */ "G_ATOMICRMW_FADD\0" /* 2441 */ "G_VECREDUCE_ADD\0" /* 2457 */ "G_ADD\0" /* 2463 */ "G_PTR_ADD\0" /* 2473 */ "G_ATOMICRMW_ADD\0" /* 2489 */ "PseudoLA_TLS_GD\0" /* 2505 */ "PRELD\0" /* 2511 */ "XVLD\0" /* 2516 */ "FCVT_D_LD\0" /* 2526 */ "PseudoLA_TLS_LD\0" /* 2542 */ "G_ATOMICRMW_NAND\0" /* 2559 */ "G_VECREDUCE_AND\0" /* 2575 */ "G_AND\0" /* 2581 */ "G_ATOMICRMW_AND\0" /* 2597 */ "LIFETIME_END\0" /* 2610 */ "PseudoBRIND\0" /* 2622 */ "G_BRCOND\0" /* 2631 */ "G_ATOMICRMW_USUB_COND\0" /* 2653 */ "G_LLROUND\0" /* 2663 */ "G_LROUND\0" /* 2672 */ "G_INTRINSIC_ROUND\0" /* 2690 */ "G_INTRINSIC_FPTRUNC_ROUND\0" /* 2716 */ "LOAD_STACK_GUARD\0" /* 2733 */ "TLBRD\0" /* 2739 */ "GCSRRD\0" /* 2746 */ "XVREPLVE0_D\0" /* 2758 */ "XVINSVE0_D\0" /* 2769 */ "XVADDA_D\0" /* 2778 */ "XVFMINA_D\0" /* 2788 */ "X86SRA_D\0" /* 2797 */ "XVSRA_D\0" /* 2805 */ "XVFMAXA_D\0" /* 2815 */ "AMADD__DB_D\0" /* 2827 */ "AMAND__DB_D\0" /* 2839 */ "AMMIN__DB_D\0" /* 2851 */ "AMSWAP__DB_D\0" /* 2864 */ "AMOR__DB_D\0" /* 2875 */ "AMXOR__DB_D\0" /* 2887 */ "AMCAS__DB_D\0" /* 2899 */ "AMMAX__DB_D\0" /* 2911 */ "FSCALEB_D\0" /* 2921 */ "XVFLOGB_D\0" /* 2931 */ "X86SUB_D\0" /* 2940 */ "XVFSUB_D\0" /* 2949 */ "XVFMSUB_D\0" /* 2959 */ "XVFNMSUB_D\0" /* 2970 */ "XVMSUB_D\0" /* 2979 */ "XVSSUB_D\0" /* 2988 */ "XVSUB_D\0" /* 2996 */ "REVB_D\0" /* 3003 */ "X86SBC_D\0" /* 3012 */ "X86ADC_D\0" /* 3021 */ "X86DEC_D\0" /* 3030 */ "X86INC_D\0" /* 3039 */ "SC_D\0" /* 3044 */ "X86ADD_D\0" /* 3053 */ "XVFADD_D\0" /* 3062 */ "AMADD_D\0" /* 3070 */ "XVFMADD_D\0" /* 3080 */ "XVFNMADD_D\0" /* 3091 */ "XVMADD_D\0" /* 3100 */ "XVSADD_D\0" /* 3109 */ "XVADD_D\0" /* 3117 */ "FLD_D\0" /* 3123 */ "FCVT_LD_D\0" /* 3133 */ "X86AND_D\0" /* 3142 */ "AMAND_D\0" /* 3150 */ "XVPACKOD_D\0" /* 3161 */ "XVPICKOD_D\0" /* 3172 */ "XVMOD_D\0" /* 3180 */ "IOCSRRD_D\0" /* 3190 */ "XVABSD_D\0" /* 3199 */ "FCVT_UD_D\0" /* 3209 */ "XVFCMP_CLE_D\0" /* 3222 */ "FLDLE_D\0" /* 3230 */ "XVSLE_D\0" /* 3238 */ "XVFCMP_SLE_D\0" /* 3251 */ "ASRTLE_D\0" /* 3260 */ "FSTLE_D\0" /* 3268 */ "XVFCMP_CULE_D\0" /* 3282 */ "XVFCMP_SULE_D\0" /* 3296 */ "RDTIME_D\0" /* 3305 */ "XVFCMP_CNE_D\0" /* 3318 */ "XVFRINTRNE_D\0" /* 3331 */ "XVFCMP_SNE_D\0" /* 3344 */ "XVFCMP_CUNE_D\0" /* 3358 */ "XVFCMP_SUNE_D\0" /* 3372 */ "XVFRECIPE_D\0" /* 3384 */ "XVFRSQRTE_D\0" /* 3396 */ "XVPICKVE_D\0" /* 3407 */ "XVREPLVE_D\0" /* 3418 */ "XVFCMP_CAF_D\0" /* 3431 */ "XVFCMP_SAF_D\0" /* 3444 */ "XVSHUF_D\0" /* 3453 */ "FNEG_D\0" /* 3460 */ "XVNEG_D\0" /* 3468 */ "XVAVG_D\0" /* 3476 */ "MULH_D\0" /* 3483 */ "XVMUH_D\0" /* 3491 */ "REVH_D\0" /* 3498 */ "XVILVH_D\0" /* 3507 */ "ADDU12I_D\0" /* 3517 */ "LU32I_D\0" /* 3525 */ "LU52I_D\0" /* 3533 */ "XVSHUF4I_D\0" /* 3544 */ "ADDU16I_D\0" /* 3554 */ "X86SRAI_D\0" /* 3564 */ "XVSRAI_D\0" /* 3573 */ "ADDI_D\0" /* 3580 */ "XVSLEI_D\0" /* 3589 */ "XVREPL128VEI_D\0" /* 3604 */ "VREPLVEI_D\0" /* 3615 */ "X86RCLI_D\0" /* 3625 */ "XVHSELI_D\0" /* 3635 */ "X86SLLI_D\0" /* 3645 */ "XVSLLI_D\0" /* 3654 */ "PseudoXVREPLI_D\0" /* 3670 */ "PseudoVREPLI_D\0" /* 3685 */ "X86SRLI_D\0" /* 3695 */ "XVSRLI_D\0" /* 3704 */ "X86ROTLI_D\0" /* 3715 */ "PseudoLI_D\0" /* 3726 */ "XVPERMI_D\0" /* 3736 */ "XVMINI_D\0" /* 3745 */ "XVSEQI_D\0" /* 3754 */ "XVSRARI_D\0" /* 3764 */ "X86RCRI_D\0" /* 3774 */ "XVBITCLRI_D\0" /* 3786 */ "XVSRLRI_D\0" /* 3796 */ "X86ROTRI_D\0" /* 3807 */ "XVROTRI_D\0" /* 3817 */ "XVBITSETI_D\0" /* 3829 */ "XVSLTI_D\0" /* 3838 */ "XVBITREVI_D\0" /* 3850 */ "XVMAXI_D\0" /* 3859 */ "BYTEPICK_D\0" /* 3870 */ "BSTRPICK_D\0" /* 3881 */ "X86RCL_D\0" /* 3890 */ "LDL_D\0" /* 3896 */ "SCREL_D\0" /* 3904 */ "X86SLL_D\0" /* 3913 */ "XVSLL_D\0" /* 3921 */ "XVLDREPL_D\0" /* 3932 */ "X86SRL_D\0" /* 3941 */ "XVSRL_D\0" /* 3949 */ "ALSL_D\0" /* 3956 */ "X86ROTL_D\0" /* 3966 */ "STL_D\0" /* 3972 */ "X86MUL_D\0" /* 3981 */ "XVFMUL_D\0" /* 3990 */ "XVMUL_D\0" /* 3998 */ "XVILVL_D\0" /* 4007 */ "XVFTINTRNE_L_D\0" /* 4022 */ "XVFTINTRM_L_D\0" /* 4036 */ "XVFTINTRP_L_D\0" /* 4050 */ "XVFTINT_L_D\0" /* 4062 */ "XVFTINTRZ_L_D\0" /* 4076 */ "XVSTELM_D\0" /* 4086 */ "XVFRINTRM_D\0" /* 4098 */ "FCOPYSIGN_D\0" /* 4110 */ "XVFMIN_D\0" /* 4119 */ "AMMIN_D\0" /* 4127 */ "XVMIN_D\0" /* 4135 */ "XVFCMP_CUN_D\0" /* 4148 */ "XVFCMP_SUN_D\0" /* 4161 */ "XVCLO_D\0" /* 4169 */ "CTO_D\0" /* 4175 */ "AMSWAP_D\0" /* 4184 */ "XVFRECIP_D\0" /* 4195 */ "XVFRINTRP_D\0" /* 4207 */ "LLACQ_D\0" /* 4215 */ "XVFCMP_CEQ_D\0" /* 4228 */ "XVSEQ_D\0" /* 4236 */ "XVFCMP_SEQ_D\0" /* 4249 */ "XVFCMP_CUEQ_D\0" /* 4263 */ "XVFCMP_SUEQ_D\0" /* 4277 */ "XVSUBWOD_Q_D\0" /* 4290 */ "XVMADDWOD_Q_D\0" /* 4304 */ "XVADDWOD_Q_D\0" /* 4317 */ "XVMULWOD_Q_D\0" /* 4330 */ "XVEXTH_Q_D\0" /* 4341 */ "XVEXTL_Q_D\0" /* 4352 */ "XVSUBWEV_Q_D\0" /* 4365 */ "XVMADDWEV_Q_D\0" /* 4379 */ "XVADDWEV_Q_D\0" /* 4392 */ "XVMULWEV_Q_D\0" /* 4405 */ "XVHSUBW_Q_D\0" /* 4417 */ "XVHADDW_Q_D\0" /* 4429 */ "XVSRAR_D\0" /* 4438 */ "X86RCR_D\0" /* 4447 */ "LDR_D\0" /* 4453 */ "MOVGR2FR_D\0" /* 4464 */ "XVPICKVE2GR_D\0" /* 4478 */ "MOVFR2GR_D\0" /* 4489 */ "XVAVGR_D\0" /* 4498 */ "XVBITCLR_D\0" /* 4509 */ "XVSRLR_D\0" /* 4518 */ "X86OR_D\0" /* 4526 */ "XVFCMP_COR_D\0" /* 4539 */ "AMOR_D\0" /* 4546 */ "XVFCMP_SOR_D\0" /* 4559 */ "X86XOR_D\0" /* 4568 */ "AMXOR_D\0" /* 4576 */ "X86ROTR_D\0" /* 4586 */ "XVROTR_D\0" /* 4595 */ "LDPTR_D\0" /* 4603 */ "STPTR_D\0" /* 4611 */ "STR_D\0" /* 4617 */ "XVREPLGR2VR_D\0" /* 4631 */ "XVINSGR2VR_D\0" /* 4644 */ "IOCSRWR_D\0" /* 4654 */ "AMCAS_D\0" /* 4662 */ "FABS_D\0" /* 4669 */ "BSTRINS_D\0" /* 4679 */ "XVEXTRINS_D\0" /* 4691 */ "XVFCLASS_D\0" /* 4702 */ "XVFCVT_S_D\0" /* 4713 */ "XVSAT_D\0" /* 4721 */ "XVBITSET_D\0" /* 4732 */ "FLDGT_D\0" /* 4740 */ "ASRTGT_D\0" /* 4749 */ "FSTGT_D\0" /* 4757 */ "XVFCMP_CLT_D\0" /* 4770 */ "XVSLT_D\0" /* 4778 */ "XVFCMP_SLT_D\0" /* 4791 */ "XVFCMP_CULT_D\0" /* 4805 */ "XVFCMP_SULT_D\0" /* 4819 */ "XVPCNT_D\0" /* 4828 */ "XVFRINT_D\0" /* 4838 */ "XVFSQRT_D\0" /* 4848 */ "XVFRSQRT_D\0" /* 4859 */ "FST_D\0" /* 4865 */ "XVMADDWOD_Q_DU_D\0" /* 4882 */ "XVADDWOD_Q_DU_D\0" /* 4898 */ "XVMULWOD_Q_DU_D\0" /* 4914 */ "XVMADDWEV_Q_DU_D\0" /* 4931 */ "XVADDWEV_Q_DU_D\0" /* 4947 */ "XVMULWEV_Q_DU_D\0" /* 4963 */ "XVFTINT_LU_D\0" /* 4976 */ "XVFTINTRZ_LU_D\0" /* 4991 */ "XVSSRANI_WU_D\0" /* 5005 */ "XVSSRLNI_WU_D\0" /* 5019 */ "XVSSRARNI_WU_D\0" /* 5034 */ "XVSSRLRNI_WU_D\0" /* 5049 */ "XVSSRAN_WU_D\0" /* 5062 */ "XVSSRLN_WU_D\0" /* 5075 */ "XVSSRARN_WU_D\0" /* 5089 */ "XVSSRLRN_WU_D\0" /* 5103 */ "XVPACKEV_D\0" /* 5114 */ "XVPICKEV_D\0" /* 5125 */ "XVBITREV_D\0" /* 5136 */ "XVFDIV_D\0" /* 5145 */ "XVDIV_D\0" /* 5153 */ "XVSIGNCOV_D\0" /* 5165 */ "FMOV_D\0" /* 5172 */ "ARMMOV_D\0" /* 5181 */ "XVFTINTRNE_W_D\0" /* 5196 */ "XVSSRANI_W_D\0" /* 5209 */ "XVSRANI_W_D\0" /* 5221 */ "XVSSRLNI_W_D\0" /* 5234 */ "XVSRLNI_W_D\0" /* 5246 */ "XVSSRARNI_W_D\0" /* 5260 */ "XVSRARNI_W_D\0" /* 5273 */ "XVSSRLRNI_W_D\0" /* 5287 */ "XVSRLRNI_W_D\0" /* 5300 */ "XVFTINTRM_W_D\0" /* 5314 */ "XVSSRAN_W_D\0" /* 5326 */ "XVSRAN_W_D\0" /* 5337 */ "XVSSRLN_W_D\0" /* 5349 */ "XVSRLN_W_D\0" /* 5360 */ "XVSSRARN_W_D\0" /* 5373 */ "XVSRARN_W_D\0" /* 5385 */ "XVSSRLRN_W_D\0" /* 5398 */ "XVSRLRN_W_D\0" /* 5410 */ "XVFTINTRP_W_D\0" /* 5424 */ "XVFTINT_W_D\0" /* 5436 */ "XVFTINTRZ_W_D\0" /* 5450 */ "XVFMAX_D\0" /* 5459 */ "AMMAX_D\0" /* 5467 */ "XVMAX_D\0" /* 5475 */ "FLDX_D\0" /* 5482 */ "FSTX_D\0" /* 5489 */ "PseudoXVBZ_D\0" /* 5502 */ "PseudoVBZ_D\0" /* 5514 */ "XVSETALLNEZ_D\0" /* 5528 */ "XVCLZ_D\0" /* 5536 */ "PseudoXVBNZ_D\0" /* 5550 */ "PseudoVBNZ_D\0" /* 5563 */ "XVSETANYEQZ_D\0" /* 5577 */ "XVFRINTRZ_D\0" /* 5589 */ "CTZ_D\0" /* 5595 */ "XVMSKLTZ_D\0" /* 5606 */ "PseudoAddTPRel_D\0" /* 5623 */ "PseudoAtomicStoreD\0" /* 5642 */ "FSEL_xD\0" /* 5650 */ "PSEUDO_PROBE\0" /* 5663 */ "G_SSUBE\0" /* 5671 */ "G_USUBE\0" /* 5679 */ "G_FENCE\0" /* 5687 */ "ARITH_FENCE\0" /* 5699 */ "REG_SEQUENCE\0" /* 5712 */ "G_SADDE\0" /* 5720 */ "G_UADDE\0" /* 5728 */ "G_GET_FPMODE\0" /* 5741 */ "G_RESET_FPMODE\0" /* 5756 */ "G_SET_FPMODE\0" /* 5769 */ "G_FMINNUM_IEEE\0" /* 5784 */ "G_FMAXNUM_IEEE\0" /* 5799 */ "BGE\0" /* 5803 */ "PseudoLA_TLS_DESC_PC_LARGE\0" /* 5830 */ "PseudoLA_TLS_GD_LARGE\0" /* 5852 */ "PseudoLA_TLS_LD_LARGE\0" /* 5874 */ "PseudoLA_TLS_IE_LARGE\0" /* 5896 */ "PseudoLA_PCREL_LARGE\0" /* 5917 */ "PseudoTAIL_LARGE\0" /* 5934 */ "PseudoCALL_LARGE\0" /* 5951 */ "PseudoLA_ABS_LARGE\0" /* 5970 */ "PseudoLA_TLS_DESC_ABS_LARGE\0" /* 5998 */ "PseudoLA_GOT_LARGE\0" /* 6017 */ "PseudoLA_TLS_IE\0" /* 6033 */ "G_VSCALE\0" /* 6042 */ "G_JUMP_TABLE\0" /* 6055 */ "IDLE\0" /* 6060 */ "BUNDLE\0" /* 6067 */ "PseudoLA_TLS_LE\0" /* 6083 */ "BNE\0" /* 6087 */ "G_MEMCPY_INLINE\0" /* 6103 */ "SETX86LOOPNE\0" /* 6116 */ "LOCAL_ESCAPE\0" /* 6129 */ "SETX86LOOPE\0" /* 6141 */ "G_STACKRESTORE\0" /* 6156 */ "G_INDEXED_STORE\0" /* 6172 */ "G_STORE\0" /* 6180 */ "SET_CFR_FALSE\0" /* 6194 */ "G_BITREVERSE\0" /* 6207 */ "FAKE_USE\0" /* 6216 */ "LDPTE\0" /* 6222 */ "DBG_VALUE\0" /* 6232 */ "G_GLOBAL_VALUE\0" /* 6247 */ "G_PTRAUTH_GLOBAL_VALUE\0" /* 6270 */ "CONVERGENCECTRL_GLUE\0" /* 6291 */ "SET_CFR_TRUE\0" /* 6304 */ "G_STACKSAVE\0" /* 6316 */ "G_MEMMOVE\0" /* 6326 */ "ARMMOVE\0" /* 6334 */ "G_FREEZE\0" /* 6343 */ "G_FCANONICALIZE\0" /* 6359 */ "MOVGR2CF\0" /* 6368 */ "G_CTLZ_ZERO_UNDEF\0" /* 6386 */ "G_CTTZ_ZERO_UNDEF\0" /* 6404 */ "INIT_UNDEF\0" /* 6415 */ "G_IMPLICIT_DEF\0" /* 6430 */ "DBG_INSTR_REF\0" /* 6444 */ "X86MFFLAG\0" /* 6454 */ "ARMMFFLAG\0" /* 6464 */ "X86MTFLAG\0" /* 6474 */ "ARMMTFLAG\0" /* 6484 */ "X86SETTAG\0" /* 6494 */ "G_FNEG\0" /* 6501 */ "EXTRACT_SUBREG\0" /* 6516 */ "INSERT_SUBREG\0" /* 6530 */ "G_SEXT_INREG\0" /* 6543 */ "SUBREG_TO_REG\0" /* 6557 */ "CPUCFG\0" /* 6564 */ "G_ATOMIC_CMPXCHG\0" /* 6581 */ "GCSRXCHG\0" /* 6590 */ "G_ATOMICRMW_XCHG\0" /* 6607 */ "G_FLOG\0" /* 6614 */ "G_VAARG\0" /* 6622 */ "PREALLOCATED_ARG\0" /* 6639 */ "REVB_2H\0" /* 6647 */ "REVB_4H\0" /* 6655 */ "TLBSRCH\0" /* 6663 */ "G_PREFETCH\0" /* 6674 */ "G_SMULH\0" /* 6682 */ "G_UMULH\0" /* 6690 */ "G_FTANH\0" /* 6698 */ "G_FSINH\0" /* 6706 */ "G_FCOSH\0" /* 6714 */ "GTLBFLUSH\0" /* 6724 */ "XVREPLVE0_H\0" /* 6736 */ "XVADDA_H\0" /* 6745 */ "X86SRA_H\0" /* 6754 */ "XVSRA_H\0" /* 6762 */ "AMADD__DB_H\0" /* 6774 */ "AMSWAP__DB_H\0" /* 6787 */ "AMCAS__DB_H\0" /* 6799 */ "X86SUB_H\0" /* 6808 */ "XVMSUB_H\0" /* 6817 */ "XVSSUB_H\0" /* 6826 */ "XVSUB_H\0" /* 6834 */ "XVSSRANI_B_H\0" /* 6847 */ "XVSRANI_B_H\0" /* 6859 */ "XVSSRLNI_B_H\0" /* 6872 */ "XVSRLNI_B_H\0" /* 6884 */ "XVSSRARNI_B_H\0" /* 6898 */ "XVSRARNI_B_H\0" /* 6911 */ "XVSSRLRNI_B_H\0" /* 6925 */ "XVSRLRNI_B_H\0" /* 6938 */ "XVSSRAN_B_H\0" /* 6950 */ "XVSRAN_B_H\0" /* 6961 */ "XVSSRLN_B_H\0" /* 6973 */ "XVSRLN_B_H\0" /* 6984 */ "XVSSRARN_B_H\0" /* 6997 */ "XVSRARN_B_H\0" /* 7009 */ "XVSSRLRN_B_H\0" /* 7022 */ "XVSRLRN_B_H\0" /* 7034 */ "X86SBC_H\0" /* 7043 */ "X86ADC_H\0" /* 7052 */ "X86DEC_H\0" /* 7061 */ "X86INC_H\0" /* 7070 */ "X86ADD_H\0" /* 7079 */ "AMADD_H\0" /* 7087 */ "XVMADD_H\0" /* 7096 */ "XVSADD_H\0" /* 7105 */ "XVADD_H\0" /* 7113 */ "LD_H\0" /* 7118 */ "X86AND_H\0" /* 7127 */ "XVPACKOD_H\0" /* 7138 */ "XVPICKOD_H\0" /* 7149 */ "XVMOD_H\0" /* 7157 */ "IOCSRRD_H\0" /* 7167 */ "XVABSD_H\0" /* 7176 */ "VEXT2XV_D_H\0" /* 7188 */ "LDLE_H\0" /* 7195 */ "XVSLE_H\0" /* 7203 */ "STLE_H\0" /* 7210 */ "XVREPLVE_H\0" /* 7221 */ "XVSHUF_H\0" /* 7230 */ "XVNEG_H\0" /* 7238 */ "XVAVG_H\0" /* 7246 */ "XVMUH_H\0" /* 7254 */ "XVILVH_H\0" /* 7263 */ "XVSHUF4I_H\0" /* 7274 */ "X86SRAI_H\0" /* 7284 */ "XVSRAI_H\0" /* 7293 */ "XVSLEI_H\0" /* 7302 */ "XVREPL128VEI_H\0" /* 7317 */ "VREPLVEI_H\0" /* 7328 */ "X86RCLI_H\0" /* 7338 */ "X86SLLI_H\0" /* 7348 */ "XVSLLI_H\0" /* 7357 */ "PseudoXVREPLI_H\0" /* 7373 */ "PseudoVREPLI_H\0" /* 7388 */ "X86SRLI_H\0" /* 7398 */ "XVSRLI_H\0" /* 7407 */ "X86ROTLI_H\0" /* 7418 */ "XVMINI_H\0" /* 7427 */ "XVFRSTPI_H\0" /* 7438 */ "XVSEQI_H\0" /* 7447 */ "XVSRARI_H\0" /* 7457 */ "X86RCRI_H\0" /* 7467 */ "XVBITCLRI_H\0" /* 7479 */ "XVSRLRI_H\0" /* 7489 */ "X86ROTRI_H\0" /* 7500 */ "XVROTRI_H\0" /* 7510 */ "XVBITSETI_H\0" /* 7522 */ "XVSLTI_H\0" /* 7531 */ "XVBITREVI_H\0" /* 7543 */ "XVMAXI_H\0" /* 7552 */ "X86RCL_H\0" /* 7561 */ "X86SLL_H\0" /* 7570 */ "XVSLL_H\0" /* 7578 */ "XVLDREPL_H\0" /* 7589 */ "X86SRL_H\0" /* 7598 */ "XVSRL_H\0" /* 7606 */ "X86ROTL_H\0" /* 7616 */ "X86MUL_H\0" /* 7625 */ "XVMUL_H\0" /* 7633 */ "XVILVL_H\0" /* 7642 */ "XVSTELM_H\0" /* 7652 */ "XVMIN_H\0" /* 7660 */ "XVCLO_H\0" /* 7668 */ "AMSWAP_H\0" /* 7677 */ "XVFRSTP_H\0" /* 7687 */ "XVSEQ_H\0" /* 7695 */ "XVSRAR_H\0" /* 7704 */ "X86RCR_H\0" /* 7713 */ "VPICKVE2GR_H\0" /* 7726 */ "XVAVGR_H\0" /* 7735 */ "XVBITCLR_H\0" /* 7746 */ "XVSRLR_H\0" /* 7755 */ "X86OR_H\0" /* 7763 */ "X86XOR_H\0" /* 7772 */ "X86ROTR_H\0" /* 7782 */ "XVROTR_H\0" /* 7791 */ "XVREPLGR2VR_H\0" /* 7805 */ "PseudoXVINSGR2VR_H\0" /* 7824 */ "IOCSRWR_H\0" /* 7834 */ "AMCAS_H\0" /* 7842 */ "XVEXTRINS_H\0" /* 7854 */ "XVFCVTH_S_H\0" /* 7866 */ "XVFCVTL_S_H\0" /* 7878 */ "XVSAT_H\0" /* 7886 */ "XVBITSET_H\0" /* 7897 */ "LDGT_H\0" /* 7904 */ "STGT_H\0" /* 7911 */ "XVSLT_H\0" /* 7919 */ "XVPCNT_H\0" /* 7928 */ "ST_H\0" /* 7933 */ "XVSSRANI_BU_H\0" /* 7947 */ "XVSSRLNI_BU_H\0" /* 7961 */ "XVSSRARNI_BU_H\0" /* 7976 */ "XVSSRLRNI_BU_H\0" /* 7991 */ "XVSSRAN_BU_H\0" /* 8004 */ "XVSSRLN_BU_H\0" /* 8017 */ "XVSSRARN_BU_H\0" /* 8031 */ "XVSSRLRN_BU_H\0" /* 8045 */ "XVMADDWOD_W_HU_H\0" /* 8062 */ "XVADDWOD_W_HU_H\0" /* 8078 */ "XVMULWOD_W_HU_H\0" /* 8094 */ "XVMADDWEV_W_HU_H\0" /* 8111 */ "XVADDWEV_W_HU_H\0" /* 8127 */ "XVMULWEV_W_HU_H\0" /* 8143 */ "XVPACKEV_H\0" /* 8154 */ "XVPICKEV_H\0" /* 8165 */ "XVBITREV_H\0" /* 8176 */ "XVDIV_H\0" /* 8184 */ "XVSIGNCOV_H\0" /* 8196 */ "XVSUBWOD_W_H\0" /* 8209 */ "XVMADDWOD_W_H\0" /* 8223 */ "XVADDWOD_W_H\0" /* 8236 */ "XVMULWOD_W_H\0" /* 8249 */ "XVEXTH_W_H\0" /* 8260 */ "XVSLLWIL_W_H\0" /* 8273 */ "EXT_W_H\0" /* 8281 */ "XVSUBWEV_W_H\0" /* 8294 */ "XVMADDWEV_W_H\0" /* 8308 */ "XVADDWEV_W_H\0" /* 8321 */ "XVMULWEV_W_H\0" /* 8334 */ "VEXT2XV_W_H\0" /* 8346 */ "XVHSUBW_W_H\0" /* 8358 */ "XVHADDW_W_H\0" /* 8370 */ "XVMAX_H\0" /* 8378 */ "LDX_H\0" /* 8384 */ "STX_H\0" /* 8390 */ "PseudoXVBZ_H\0" /* 8403 */ "PseudoVBZ_H\0" /* 8415 */ "XVSETALLNEZ_H\0" /* 8429 */ "XVCLZ_H\0" /* 8437 */ "PseudoXVBNZ_H\0" /* 8451 */ "PseudoVBNZ_H\0" /* 8464 */ "XVSETANYEQZ_H\0" /* 8478 */ "XVMSKLTZ_H\0" /* 8489 */ "PCALAU12I\0" /* 8499 */ "PCADDU12I\0" /* 8509 */ "PCADDU18I\0" /* 8519 */ "PCADDI\0" /* 8526 */ "XVLDI\0" /* 8532 */ "ANDI\0" /* 8537 */ "DBG_PHI\0" /* 8545 */ "XORI\0" /* 8550 */ "G_FPTOSI\0" /* 8559 */ "SLTI\0" /* 8564 */ "G_FPTOUI\0" /* 8573 */ "SLTUI\0" /* 8579 */ "G_FPOWI\0" /* 8587 */ "SETX86J\0" /* 8595 */ "SETARMJ\0" /* 8603 */ "BREAK\0" /* 8609 */ "G_PTRMASK\0" /* 8619 */ "BL\0" /* 8622 */ "DBCL\0" /* 8627 */ "HVCL\0" /* 8632 */ "GC_LABEL\0" /* 8641 */ "DBG_LABEL\0" /* 8651 */ "EH_LABEL\0" /* 8660 */ "ANNOTATION_LABEL\0" /* 8677 */ "ICALL_BRANCH_FUNNEL\0" /* 8697 */ "PseudoLA_PCREL\0" /* 8712 */ "G_FSHL\0" /* 8719 */ "G_SHL\0" /* 8725 */ "PseudoB_TAIL\0" /* 8738 */ "PseudoJIRL_TAIL\0" /* 8754 */ "PseudoTAIL\0" /* 8765 */ "G_FCEIL\0" /* 8773 */ "SYSCALL\0" /* 8781 */ "PseudoDESC_CALL\0" /* 8797 */ "PATCHABLE_TAIL_CALL\0" /* 8817 */ "PseudoJIRL_CALL\0" /* 8833 */ "PATCHABLE_TYPED_EVENT_CALL\0" /* 8860 */ "PATCHABLE_EVENT_CALL\0" /* 8881 */ "FENTRY_CALL\0" /* 8893 */ "PseudoCALL\0" /* 8904 */ "TLBFILL\0" /* 8912 */ "KILL\0" /* 8917 */ "G_CONSTANT_POOL\0" /* 8933 */ "JIRL\0" /* 8938 */ "G_ROTL\0" /* 8945 */ "G_VECREDUCE_FMUL\0" /* 8962 */ "G_FMUL\0" /* 8969 */ "G_VECREDUCE_SEQ_FMUL\0" /* 8990 */ "G_STRICT_FMUL\0" /* 9004 */ "G_VECREDUCE_MUL\0" /* 9020 */ "G_MUL\0" /* 9026 */ "XVFFINT_D_L\0" /* 9038 */ "XVFFINT_S_L\0" /* 9050 */ "G_FREM\0" /* 9057 */ "G_STRICT_FREM\0" /* 9071 */ "G_SREM\0" /* 9078 */ "G_UREM\0" /* 9085 */ "G_SDIVREM\0" /* 9095 */ "G_UDIVREM\0" /* 9105 */ "INLINEASM\0" /* 9115 */ "X86CLRTM\0" /* 9124 */ "X86SETTM\0" /* 9133 */ "PseudoTAIL_MEDIUM\0" /* 9151 */ "PseudoCALL_MEDIUM\0" /* 9169 */ "G_VECREDUCE_FMINIMUM\0" /* 9190 */ "G_FMINIMUM\0" /* 9201 */ "G_VECREDUCE_FMAXIMUM\0" /* 9222 */ "G_FMAXIMUM\0" /* 9233 */ "G_FMINNUM\0" /* 9243 */ "G_FMAXNUM\0" /* 9253 */ "G_FATAN\0" /* 9261 */ "G_FTAN\0" /* 9268 */ "ANDN\0" /* 9273 */ "G_INTRINSIC_ROUNDEVEN\0" /* 9295 */ "G_ASSERT_ALIGN\0" /* 9310 */ "G_FCOPYSIGN\0" /* 9322 */ "G_VECREDUCE_FMIN\0" /* 9339 */ "G_ATOMICRMW_FMIN\0" /* 9356 */ "G_VECREDUCE_SMIN\0" /* 9373 */ "G_SMIN\0" /* 9380 */ "G_VECREDUCE_UMIN\0" /* 9397 */ "G_UMIN\0" /* 9404 */ "G_ATOMICRMW_UMIN\0" /* 9421 */ "G_ATOMICRMW_MIN\0" /* 9437 */ "G_FASIN\0" /* 9445 */ "G_FSIN\0" /* 9452 */ "CFI_INSTRUCTION\0" /* 9468 */ "ORN\0" /* 9472 */ "ERTN\0" /* 9477 */ "ADJCALLSTACKDOWN\0" /* 9494 */ "G_SSUBO\0" /* 9502 */ "G_USUBO\0" /* 9510 */ "G_SADDO\0" /* 9518 */ "G_UADDO\0" /* 9526 */ "JUMP_TABLE_DEBUG_INFO\0" /* 9548 */ "G_SMULO\0" /* 9556 */ "G_UMULO\0" /* 9564 */ "G_BZERO\0" /* 9572 */ "STACKMAP\0" /* 9581 */ "G_DEBUGTRAP\0" /* 9593 */ "G_UBSANTRAP\0" /* 9605 */ "G_TRAP\0" /* 9612 */ "G_ATOMICRMW_UDEC_WRAP\0" /* 9634 */ "G_ATOMICRMW_UINC_WRAP\0" /* 9656 */ "G_BSWAP\0" /* 9664 */ "G_SITOFP\0" /* 9673 */ "G_UITOFP\0" /* 9682 */ "G_FCMP\0" /* 9689 */ "G_ICMP\0" /* 9696 */ "G_SCMP\0" /* 9703 */ "G_UCMP\0" /* 9710 */ "PseudoUNIMP\0" /* 9722 */ "CACOP\0" /* 9728 */ "CONVERGENCECTRL_LOOP\0" /* 9749 */ "G_CTPOP\0" /* 9757 */ "PseudoCTPOP\0" /* 9769 */ "X86DECTOP\0" /* 9779 */ "X86INCTOP\0" /* 9789 */ "X86MFTOP\0" /* 9798 */ "X86MTTOP\0" /* 9807 */ "PATCHABLE_OP\0" /* 9820 */ "FAULTING_OP\0" /* 9832 */ "ADJCALLSTACKUP\0" /* 9847 */ "PREALLOCATED_SETUP\0" /* 9866 */ "G_FLDEXP\0" /* 9875 */ "G_STRICT_FLDEXP\0" /* 9891 */ "G_FEXP\0" /* 9898 */ "G_FFREXP\0" /* 9907 */ "BEQ\0" /* 9911 */ "XVREPLVE0_Q\0" /* 9923 */ "XVSUB_Q\0" /* 9931 */ "SC_Q\0" /* 9936 */ "XVADD_Q\0" /* 9944 */ "XVSSRANI_D_Q\0" /* 9957 */ "XVSRANI_D_Q\0" /* 9969 */ "XVSSRLNI_D_Q\0" /* 9982 */ "XVSRLNI_D_Q\0" /* 9994 */ "XVSSRARNI_D_Q\0" /* 10008 */ "XVSRARNI_D_Q\0" /* 10021 */ "XVSSRLRNI_D_Q\0" /* 10035 */ "XVSRLRNI_D_Q\0" /* 10048 */ "XVPERMI_Q\0" /* 10058 */ "XVSSRANI_DU_Q\0" /* 10072 */ "XVSSRLNI_DU_Q\0" /* 10086 */ "XVSSRARNI_DU_Q\0" /* 10101 */ "XVSSRLRNI_DU_Q\0" /* 10116 */ "DBAR\0" /* 10121 */ "IBAR\0" /* 10126 */ "G_BR\0" /* 10131 */ "INLINEASM_BR\0" /* 10144 */ "PseudoBR\0" /* 10153 */ "MOVGR2SCR\0" /* 10163 */ "G_BLOCK_ADDR\0" /* 10176 */ "MEMBARRIER\0" /* 10187 */ "G_CONSTANT_FOLD_BARRIER\0" /* 10211 */ "PATCHABLE_FUNCTION_ENTER\0" /* 10236 */ "G_READCYCLECOUNTER\0" /* 10255 */ "G_READSTEADYCOUNTER\0" /* 10275 */ "G_READ_REGISTER\0" /* 10291 */ "G_WRITE_REGISTER\0" /* 10308 */ "PseudoLD_CFR\0" /* 10321 */ "PseudoST_CFR\0" /* 10334 */ "PseudoCopyCFR\0" /* 10348 */ "MOVCF2GR\0" /* 10357 */ "MOVSCR2GR\0" /* 10367 */ "MOVFCSR2GR\0" /* 10378 */ "G_ASHR\0" /* 10385 */ "G_FSHR\0" /* 10392 */ "G_LSHR\0" /* 10399 */ "LDDIR\0" /* 10405 */ "TLBCLR\0" /* 10412 */ "CONVERGENCECTRL_ANCHOR\0" /* 10435 */ "NOR\0" /* 10439 */ "G_FFLOOR\0" /* 10448 */ "G_EXTRACT_SUBVECTOR\0" /* 10468 */ "G_INSERT_SUBVECTOR\0" /* 10487 */ "G_BUILD_VECTOR\0" /* 10502 */ "G_SHUFFLE_VECTOR\0" /* 10519 */ "G_SPLAT_VECTOR\0" /* 10534 */ "G_VECREDUCE_XOR\0" /* 10550 */ "G_XOR\0" /* 10556 */ "G_ATOMICRMW_XOR\0" /* 10572 */ "G_VECREDUCE_OR\0" /* 10587 */ "G_OR\0" /* 10592 */ "G_ATOMICRMW_OR\0" /* 10607 */ "MOVGR2FCSR\0" /* 10618 */ "RDFCSR\0" /* 10625 */ "WRFCSR\0" /* 10632 */ "G_ROTR\0" /* 10639 */ "G_INTTOPTR\0" /* 10650 */ "TLBWR\0" /* 10656 */ "GCSRWR\0" /* 10663 */ "G_FABS\0" /* 10670 */ "PseudoLA_ABS\0" /* 10683 */ "PseudoLA_TLS_DESC_ABS\0" /* 10705 */ "G_ABS\0" /* 10711 */ "G_UNMERGE_VALUES\0" /* 10728 */ "G_MERGE_VALUES\0" /* 10743 */ "G_FACOS\0" /* 10751 */ "G_FCOS\0" /* 10758 */ "G_CONCAT_VECTORS\0" /* 10775 */ "COPY_TO_REGCLASS\0" /* 10792 */ "G_IS_FPCLASS\0" /* 10805 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0" /* 10835 */ "G_VECTOR_COMPRESS\0" /* 10853 */ "G_INTRINSIC_W_SIDE_EFFECTS\0" /* 10880 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0" /* 10918 */ "XVFMINA_S\0" /* 10928 */ "XVFMAXA_S\0" /* 10938 */ "FSCALEB_S\0" /* 10948 */ "XVFLOGB_S\0" /* 10958 */ "XVFSUB_S\0" /* 10967 */ "XVFMSUB_S\0" /* 10977 */ "XVFNMSUB_S\0" /* 10988 */ "XVFADD_S\0" /* 10997 */ "XVFMADD_S\0" /* 11007 */ "XVFNMADD_S\0" /* 11018 */ "FLD_S\0" /* 11024 */ "XVFCVTH_D_S\0" /* 11036 */ "XVFCVTL_D_S\0" /* 11048 */ "FCVT_D_S\0" /* 11057 */ "XVFCMP_CLE_S\0" /* 11070 */ "FLDLE_S\0" /* 11078 */ "XVFCMP_SLE_S\0" /* 11091 */ "FSTLE_S\0" /* 11099 */ "XVFCMP_CULE_S\0" /* 11113 */ "XVFCMP_SULE_S\0" /* 11127 */ "XVFCMP_CNE_S\0" /* 11140 */ "XVFRINTRNE_S\0" /* 11153 */ "XVFCMP_SNE_S\0" /* 11166 */ "XVFCMP_CUNE_S\0" /* 11180 */ "XVFCMP_SUNE_S\0" /* 11194 */ "XVFRECIPE_S\0" /* 11206 */ "XVFRSQRTE_S\0" /* 11218 */ "XVFCMP_CAF_S\0" /* 11231 */ "XVFCMP_SAF_S\0" /* 11244 */ "FNEG_S\0" /* 11251 */ "XVFCVT_H_S\0" /* 11262 */ "XVFMUL_S\0" /* 11271 */ "FTINTRNE_L_S\0" /* 11284 */ "XVFTINTRNEH_L_S\0" /* 11300 */ "XVFTINTRMH_L_S\0" /* 11315 */ "XVFTINTRPH_L_S\0" /* 11330 */ "XVFTINTH_L_S\0" /* 11343 */ "XVFTINTRZH_L_S\0" /* 11358 */ "XVFTINTRNEL_L_S\0" /* 11374 */ "XVFTINTRML_L_S\0" /* 11389 */ "XVFTINTRPL_L_S\0" /* 11404 */ "XVFTINTL_L_S\0" /* 11417 */ "XVFTINTRZL_L_S\0" /* 11432 */ "FTINTRM_L_S\0" /* 11444 */ "FTINTRP_L_S\0" /* 11456 */ "FTINT_L_S\0" /* 11466 */ "FTINTRZ_L_S\0" /* 11478 */ "XVFRINTRM_S\0" /* 11490 */ "FCOPYSIGN_S\0" /* 11502 */ "XVFMIN_S\0" /* 11511 */ "XVFCMP_CUN_S\0" /* 11524 */ "XVFCMP_SUN_S\0" /* 11537 */ "XVFRECIP_S\0" /* 11548 */ "XVFRINTRP_S\0" /* 11560 */ "XVFCMP_CEQ_S\0" /* 11573 */ "XVFCMP_SEQ_S\0" /* 11586 */ "XVFCMP_CUEQ_S\0" /* 11600 */ "XVFCMP_SUEQ_S\0" /* 11614 */ "MOVFRH2GR_S\0" /* 11626 */ "MOVFR2GR_S\0" /* 11637 */ "XVFCMP_COR_S\0" /* 11650 */ "XVFCMP_SOR_S\0" /* 11663 */ "FABS_S\0" /* 11670 */ "XVFCLASS_S\0" /* 11681 */ "FLDGT_S\0" /* 11689 */ "FSTGT_S\0" /* 11697 */ "XVFCMP_CLT_S\0" /* 11710 */ "XVFCMP_SLT_S\0" /* 11723 */ "XVFCMP_CULT_S\0" /* 11737 */ "XVFCMP_SULT_S\0" /* 11751 */ "XVFRINT_S\0" /* 11761 */ "XVFSQRT_S\0" /* 11771 */ "XVFRSQRT_S\0" /* 11782 */ "FST_S\0" /* 11788 */ "XVFTINT_WU_S\0" /* 11801 */ "XVFTINTRZ_WU_S\0" /* 11816 */ "XVFDIV_S\0" /* 11825 */ "FMOV_S\0" /* 11832 */ "XVFTINTRNE_W_S\0" /* 11847 */ "XVFTINTRM_W_S\0" /* 11861 */ "XVFTINTRP_W_S\0" /* 11875 */ "XVFTINT_W_S\0" /* 11887 */ "XVFTINTRZ_W_S\0" /* 11901 */ "XVFMAX_S\0" /* 11910 */ "FLDX_S\0" /* 11917 */ "FSTX_S\0" /* 11924 */ "XVFRINTRZ_S\0" /* 11936 */ "MOVFR2CF_xS\0" /* 11948 */ "FSEL_xS\0" /* 11956 */ "MOVCF2FR_xS\0" /* 11968 */ "G_SSUBSAT\0" /* 11978 */ "G_USUBSAT\0" /* 11988 */ "G_SADDSAT\0" /* 11998 */ "G_UADDSAT\0" /* 12008 */ "G_SSHLSAT\0" /* 12018 */ "G_USHLSAT\0" /* 12028 */ "G_SMULFIXSAT\0" /* 12041 */ "G_UMULFIXSAT\0" /* 12054 */ "G_SDIVFIXSAT\0" /* 12067 */ "G_UDIVFIXSAT\0" /* 12080 */ "G_ATOMICRMW_USUB_SAT\0" /* 12101 */ "G_FPTOSI_SAT\0" /* 12114 */ "G_FPTOUI_SAT\0" /* 12127 */ "G_EXTRACT\0" /* 12137 */ "G_SELECT\0" /* 12146 */ "G_BRINDIRECT\0" /* 12159 */ "PATCHABLE_RET\0" /* 12173 */ "PseudoRET\0" /* 12183 */ "G_MEMSET\0" /* 12192 */ "PATCHABLE_FUNCTION_EXIT\0" /* 12216 */ "G_BRJT\0" /* 12223 */ "BLT\0" /* 12227 */ "G_EXTRACT_VECTOR_ELT\0" /* 12248 */ "G_INSERT_VECTOR_ELT\0" /* 12268 */ "SLT\0" /* 12272 */ "G_FCONSTANT\0" /* 12284 */ "G_CONSTANT\0" /* 12295 */ "G_INTRINSIC_CONVERGENT\0" /* 12318 */ "STATEPOINT\0" /* 12329 */ "PATCHPOINT\0" /* 12340 */ "G_PTRTOINT\0" /* 12351 */ "G_FRINT\0" /* 12359 */ "G_INTRINSIC_LLRINT\0" /* 12378 */ "G_INTRINSIC_LRINT\0" /* 12396 */ "G_FNEARBYINT\0" /* 12409 */ "PseudoLA_GOT\0" /* 12422 */ "G_VASTART\0" /* 12432 */ "LIFETIME_START\0" /* 12447 */ "G_INVOKE_REGION_START\0" /* 12469 */ "G_INSERT\0" /* 12478 */ "G_FSQRT\0" /* 12486 */ "G_STRICT_FSQRT\0" /* 12501 */ "G_BITCAST\0" /* 12511 */ "G_ADDRSPACE_CAST\0" /* 12528 */ "DBG_VALUE_LIST\0" /* 12543 */ "XVST\0" /* 12548 */ "G_FPEXT\0" /* 12556 */ "G_SEXT\0" /* 12563 */ "G_ASSERT_SEXT\0" /* 12577 */ "G_ANYEXT\0" /* 12586 */ "G_ZEXT\0" /* 12593 */ "G_ASSERT_ZEXT\0" /* 12607 */ "XVSSUB_BU\0" /* 12617 */ "XVSADD_BU\0" /* 12627 */ "LD_BU\0" /* 12633 */ "XVMOD_BU\0" /* 12642 */ "XVABSD_BU\0" /* 12652 */ "XVSLE_BU\0" /* 12661 */ "XVAVG_BU\0" /* 12670 */ "XVMUH_BU\0" /* 12679 */ "XVSUBWOD_H_BU\0" /* 12693 */ "XVMADDWOD_H_BU\0" /* 12708 */ "XVADDWOD_H_BU\0" /* 12722 */ "XVMULWOD_H_BU\0" /* 12736 */ "XVSUBWEV_H_BU\0" /* 12750 */ "XVMADDWEV_H_BU\0" /* 12765 */ "XVADDWEV_H_BU\0" /* 12779 */ "XVMULWEV_H_BU\0" /* 12793 */ "XVSUBI_BU\0" /* 12803 */ "XVADDI_BU\0" /* 12813 */ "XVSLEI_BU\0" /* 12823 */ "XVMINI_BU\0" /* 12833 */ "XVSLTI_BU\0" /* 12843 */ "XVMAXI_BU\0" /* 12853 */ "X86MUL_BU\0" /* 12863 */ "XVMIN_BU\0" /* 12872 */ "VPICKVE2GR_BU\0" /* 12886 */ "XVAVGR_BU\0" /* 12896 */ "XVSAT_BU\0" /* 12905 */ "XVSLT_BU\0" /* 12914 */ "VEXT2XV_DU_BU\0" /* 12928 */ "XVEXTH_HU_BU\0" /* 12941 */ "XVSLLWIL_HU_BU\0" /* 12956 */ "VEXT2XV_HU_BU\0" /* 12970 */ "XVHSUBW_HU_BU\0" /* 12984 */ "XVHADDW_HU_BU\0" /* 12998 */ "VEXT2XV_WU_BU\0" /* 13012 */ "XVDIV_BU\0" /* 13021 */ "XVMAX_BU\0" /* 13030 */ "LDX_BU\0" /* 13037 */ "AMMIN__DB_DU\0" /* 13050 */ "AMMAX__DB_DU\0" /* 13063 */ "X86SUB_DU\0" /* 13073 */ "XVSSUB_DU\0" /* 13083 */ "X86ADD_DU\0" /* 13093 */ "XVSADD_DU\0" /* 13103 */ "XVMOD_DU\0" /* 13112 */ "XVABSD_DU\0" /* 13122 */ "XVSLE_DU\0" /* 13131 */ "XVAVG_DU\0" /* 13140 */ "MULH_DU\0" /* 13148 */ "XVMUH_DU\0" /* 13157 */ "XVSUBI_DU\0" /* 13167 */ "XVADDI_DU\0" /* 13177 */ "XVSLEI_DU\0" /* 13187 */ "XVMINI_DU\0" /* 13197 */ "XVSLTI_DU\0" /* 13207 */ "XVMAXI_DU\0" /* 13217 */ "X86MUL_DU\0" /* 13227 */ "AMMIN_DU\0" /* 13236 */ "XVMIN_DU\0" /* 13245 */ "XVSUBWOD_Q_DU\0" /* 13259 */ "XVMADDWOD_Q_DU\0" /* 13274 */ "XVADDWOD_Q_DU\0" /* 13288 */ "XVMULWOD_Q_DU\0" /* 13302 */ "XVSUBWEV_Q_DU\0" /* 13316 */ "XVMADDWEV_Q_DU\0" /* 13331 */ "XVADDWEV_Q_DU\0" /* 13345 */ "XVMULWEV_Q_DU\0" /* 13359 */ "XVPICKVE2GR_DU\0" /* 13374 */ "XVAVGR_DU\0" /* 13384 */ "XVSAT_DU\0" /* 13393 */ "XVSLT_DU\0" /* 13402 */ "XVEXTH_QU_DU\0" /* 13415 */ "XVEXTL_QU_DU\0" /* 13428 */ "XVHSUBW_QU_DU\0" /* 13442 */ "XVHADDW_QU_DU\0" /* 13456 */ "XVDIV_DU\0" /* 13465 */ "AMMAX_DU\0" /* 13474 */ "XVMAX_DU\0" /* 13483 */ "BGEU\0" /* 13488 */ "XVSSUB_HU\0" /* 13498 */ "XVSADD_HU\0" /* 13508 */ "LD_HU\0" /* 13514 */ "XVMOD_HU\0" /* 13523 */ "XVABSD_HU\0" /* 13533 */ "XVSLE_HU\0" /* 13542 */ "XVAVG_HU\0" /* 13551 */ "XVMUH_HU\0" /* 13560 */ "XVSUBI_HU\0" /* 13570 */ "XVADDI_HU\0" /* 13580 */ "XVSLEI_HU\0" /* 13590 */ "XVMINI_HU\0" /* 13600 */ "XVSLTI_HU\0" /* 13610 */ "XVMAXI_HU\0" /* 13620 */ "X86MUL_HU\0" /* 13630 */ "XVMIN_HU\0" /* 13639 */ "VPICKVE2GR_HU\0" /* 13653 */ "XVAVGR_HU\0" /* 13663 */ "XVSAT_HU\0" /* 13672 */ "XVSLT_HU\0" /* 13681 */ "VEXT2XV_DU_HU\0" /* 13695 */ "XVEXTH_WU_HU\0" /* 13708 */ "XVSLLWIL_WU_HU\0" /* 13723 */ "VEXT2XV_WU_HU\0" /* 13737 */ "XVHSUBW_WU_HU\0" /* 13751 */ "XVHADDW_WU_HU\0" /* 13765 */ "XVDIV_HU\0" /* 13774 */ "XVSUBWOD_W_HU\0" /* 13788 */ "XVMADDWOD_W_HU\0" /* 13803 */ "XVADDWOD_W_HU\0" /* 13817 */ "XVMULWOD_W_HU\0" /* 13831 */ "XVSUBWEV_W_HU\0" /* 13845 */ "XVMADDWEV_W_HU\0" /* 13860 */ "XVADDWEV_W_HU\0" /* 13874 */ "XVMULWEV_W_HU\0" /* 13888 */ "XVMAX_HU\0" /* 13897 */ "LDX_HU\0" /* 13904 */ "XVFFINT_D_LU\0" /* 13917 */ "BLTU\0" /* 13922 */ "SLTU\0" /* 13927 */ "AMMIN__DB_WU\0" /* 13940 */ "AMMAX__DB_WU\0" /* 13953 */ "X86SUB_WU\0" /* 13963 */ "XVSSUB_WU\0" /* 13973 */ "X86ADD_WU\0" /* 13983 */ "XVSADD_WU\0" /* 13993 */ "LD_WU\0" /* 13999 */ "XVMOD_WU\0" /* 14008 */ "XVABSD_WU\0" /* 14018 */ "XVSUBWOD_D_WU\0" /* 14032 */ "XVMADDWOD_D_WU\0" /* 14047 */ "XVADDWOD_D_WU\0" /* 14061 */ "XVMULWOD_D_WU\0" /* 14075 */ "XVSUBWEV_D_WU\0" /* 14089 */ "XVMADDWEV_D_WU\0" /* 14104 */ "XVADDWEV_D_WU\0" /* 14118 */ "XVMULWEV_D_WU\0" /* 14132 */ "MULW_D_WU\0" /* 14142 */ "XVSLE_WU\0" /* 14151 */ "XVAVG_WU\0" /* 14160 */ "MULH_WU\0" /* 14168 */ "XVMUH_WU\0" /* 14177 */ "XVSUBI_WU\0" /* 14187 */ "XVADDI_WU\0" /* 14197 */ "XVSLEI_WU\0" /* 14207 */ "XVMINI_WU\0" /* 14217 */ "XVSLTI_WU\0" /* 14227 */ "XVMAXI_WU\0" /* 14237 */ "ALSL_WU\0" /* 14245 */ "X86MUL_WU\0" /* 14255 */ "AMMIN_WU\0" /* 14264 */ "XVMIN_WU\0" /* 14273 */ "XVPICKVE2GR_WU\0" /* 14288 */ "XVAVGR_WU\0" /* 14298 */ "XVFFINT_S_WU\0" /* 14311 */ "XVSAT_WU\0" /* 14320 */ "XVSLT_WU\0" /* 14329 */ "XVEXTH_DU_WU\0" /* 14342 */ "XVSLLWIL_DU_WU\0" /* 14357 */ "VEXT2XV_DU_WU\0" /* 14371 */ "XVHSUBW_DU_WU\0" /* 14385 */ "XVHADDW_DU_WU\0" /* 14399 */ "XVDIV_WU\0" /* 14408 */ "AMMAX_WU\0" /* 14417 */ "XVMAX_WU\0" /* 14426 */ "LDX_WU\0" /* 14433 */ "G_FDIV\0" /* 14440 */ "G_STRICT_FDIV\0" /* 14454 */ "G_SDIV\0" /* 14461 */ "G_UDIV\0" /* 14468 */ "G_GET_FPENV\0" /* 14480 */ "G_RESET_FPENV\0" /* 14494 */ "G_SET_FPENV\0" /* 14506 */ "XVAND_V\0" /* 14514 */ "XVBITSEL_V\0" /* 14525 */ "XVBSLL_V\0" /* 14534 */ "XVBSRL_V\0" /* 14543 */ "XVANDN_V\0" /* 14552 */ "XVORN_V\0" /* 14560 */ "XVNOR_V\0" /* 14568 */ "XVOR_V\0" /* 14575 */ "XVXOR_V\0" /* 14583 */ "XVSETNEZ_V\0" /* 14594 */ "XVSETEQZ_V\0" /* 14605 */ "REVB_2W\0" /* 14613 */ "REVH_2W\0" /* 14621 */ "G_FPOW\0" /* 14628 */ "XVREPLVE0_W\0" /* 14640 */ "XVINSVE0_W\0" /* 14651 */ "XVADDA_W\0" /* 14660 */ "X86SRA_W\0" /* 14669 */ "ARMSRA_W\0" /* 14678 */ "XVSRA_W\0" /* 14686 */ "AMADD__DB_W\0" /* 14698 */ "AMAND__DB_W\0" /* 14710 */ "AMMIN__DB_W\0" /* 14722 */ "AMSWAP__DB_W\0" /* 14735 */ "AMOR__DB_W\0" /* 14746 */ "AMXOR__DB_W\0" /* 14758 */ "AMCAS__DB_W\0" /* 14770 */ "AMMAX__DB_W\0" /* 14782 */ "X86SUB_W\0" /* 14791 */ "ARMSUB_W\0" /* 14800 */ "XVMSUB_W\0" /* 14809 */ "XVSSUB_W\0" /* 14818 */ "XVSUB_W\0" /* 14826 */ "CRCC_W_B_W\0" /* 14837 */ "CRC_W_B_W\0" /* 14847 */ "X86SBC_W\0" /* 14856 */ "ARMSBC_W\0" /* 14865 */ "X86ADC_W\0" /* 14874 */ "ARMADC_W\0" /* 14883 */ "X86DEC_W\0" /* 14892 */ "X86INC_W\0" /* 14901 */ "SC_W\0" /* 14906 */ "X86ADD_W\0" /* 14915 */ "AMADD_W\0" /* 14923 */ "ARMADD_W\0" /* 14932 */ "XVMADD_W\0" /* 14941 */ "XVSADD_W\0" /* 14950 */ "XVADD_W\0" /* 14958 */ "LD_W\0" /* 14963 */ "X86AND_W\0" /* 14972 */ "AMAND_W\0" /* 14980 */ "ARMAND_W\0" /* 14989 */ "XVPACKOD_W\0" /* 15000 */ "XVPICKOD_W\0" /* 15011 */ "XVMOD_W\0" /* 15019 */ "IOCSRRD_W\0" /* 15029 */ "XVABSD_W\0" /* 15038 */ "XVSUBWOD_D_W\0" /* 15051 */ "XVMADDWOD_D_W\0" /* 15065 */ "XVADDWOD_D_W\0" /* 15078 */ "XVMULWOD_D_W\0" /* 15091 */ "XVFFINTH_D_W\0" /* 15104 */ "XVEXTH_D_W\0" /* 15115 */ "XVSLLWIL_D_W\0" /* 15128 */ "XVFFINTL_D_W\0" /* 15141 */ "FFINT_D_W\0" /* 15151 */ "XVSUBWEV_D_W\0" /* 15164 */ "XVMADDWEV_D_W\0" /* 15178 */ "XVADDWEV_D_W\0" /* 15191 */ "XVMULWEV_D_W\0" /* 15204 */ "VEXT2XV_D_W\0" /* 15216 */ "XVHSUBW_D_W\0" /* 15228 */ "XVHADDW_D_W\0" /* 15240 */ "MULW_D_W\0" /* 15249 */ "CRCC_W_D_W\0" /* 15260 */ "CRC_W_D_W\0" /* 15270 */ "LDLE_W\0" /* 15277 */ "XVSLE_W\0" /* 15285 */ "STLE_W\0" /* 15292 */ "XVPICKVE_W\0" /* 15303 */ "XVREPLVE_W\0" /* 15314 */ "XVSHUF_W\0" /* 15323 */ "XVNEG_W\0" /* 15331 */ "XVAVG_W\0" /* 15339 */ "RDTIMEH_W\0" /* 15349 */ "MULH_W\0" /* 15356 */ "MOVGR2FRH_W\0" /* 15368 */ "XVMUH_W\0" /* 15376 */ "XVILVH_W\0" /* 15385 */ "XVSSRANI_H_W\0" /* 15398 */ "XVSRANI_H_W\0" /* 15410 */ "XVSSRLNI_H_W\0" /* 15423 */ "XVSRLNI_H_W\0" /* 15435 */ "XVSSRARNI_H_W\0" /* 15449 */ "XVSRARNI_H_W\0" /* 15462 */ "XVSSRLRNI_H_W\0" /* 15476 */ "XVSRLRNI_H_W\0" /* 15489 */ "XVSSRAN_H_W\0" /* 15501 */ "XVSRAN_H_W\0" /* 15512 */ "XVSSRLN_H_W\0" /* 15524 */ "XVSRLN_H_W\0" /* 15535 */ "XVSSRARN_H_W\0" /* 15548 */ "XVSRARN_H_W\0" /* 15560 */ "XVSSRLRN_H_W\0" /* 15573 */ "XVSRLRN_H_W\0" /* 15585 */ "CRCC_W_H_W\0" /* 15596 */ "CRC_W_H_W\0" /* 15606 */ "ADDU12I_W\0" /* 15616 */ "LU12I_W\0" /* 15624 */ "XVSHUF4I_W\0" /* 15635 */ "X86SRAI_W\0" /* 15645 */ "ARMSRAI_W\0" /* 15655 */ "XVSRAI_W\0" /* 15664 */ "ADDI_W\0" /* 15671 */ "XVSLEI_W\0" /* 15680 */ "XVREPL128VEI_W\0" /* 15695 */ "VREPLVEI_W\0" /* 15706 */ "X86RCLI_W\0" /* 15716 */ "X86SLLI_W\0" /* 15726 */ "ARMSLLI_W\0" /* 15736 */ "XVSLLI_W\0" /* 15745 */ "PseudoXVREPLI_W\0" /* 15761 */ "PseudoVREPLI_W\0" /* 15776 */ "X86SRLI_W\0" /* 15786 */ "ARMSRLI_W\0" /* 15796 */ "XVSRLI_W\0" /* 15805 */ "X86ROTLI_W\0" /* 15816 */ "PseudoLI_W\0" /* 15827 */ "XVPERMI_W\0" /* 15837 */ "XVMINI_W\0" /* 15846 */ "XVSEQI_W\0" /* 15855 */ "XVSRARI_W\0" /* 15865 */ "X86RCRI_W\0" /* 15875 */ "XVBITCLRI_W\0" /* 15887 */ "XVSRLRI_W\0" /* 15897 */ "X86ROTRI_W\0" /* 15908 */ "ARMROTRI_W\0" /* 15919 */ "XVROTRI_W\0" /* 15929 */ "XVBITSETI_W\0" /* 15941 */ "XVSLTI_W\0" /* 15950 */ "XVBITREVI_W\0" /* 15962 */ "XVMAXI_W\0" /* 15971 */ "BYTEPICK_W\0" /* 15982 */ "BSTRPICK_W\0" /* 15993 */ "X86RCL_W\0" /* 16002 */ "LDL_W\0" /* 16008 */ "RDTIMEL_W\0" /* 16018 */ "SCREL_W\0" /* 16026 */ "X86SLL_W\0" /* 16035 */ "ARMSLL_W\0" /* 16044 */ "XVSLL_W\0" /* 16052 */ "XVLDREPL_W\0" /* 16063 */ "X86SRL_W\0" /* 16072 */ "ARMSRL_W\0" /* 16081 */ "XVSRL_W\0" /* 16089 */ "ALSL_W\0" /* 16096 */ "X86ROTL_W\0" /* 16106 */ "STL_W\0" /* 16112 */ "X86MUL_W\0" /* 16121 */ "XVMUL_W\0" /* 16129 */ "XVILVL_W\0" /* 16138 */ "XVSTELM_W\0" /* 16148 */ "XVPERM_W\0" /* 16157 */ "AMMIN_W\0" /* 16165 */ "XVMIN_W\0" /* 16173 */ "XVCLO_W\0" /* 16181 */ "CTO_W\0" /* 16187 */ "AMSWAP_W\0" /* 16196 */ "LLACQ_W\0" /* 16204 */ "XVSEQ_W\0" /* 16212 */ "XVSRAR_W\0" /* 16221 */ "X86RCR_W\0" /* 16230 */ "LDR_W\0" /* 16236 */ "MOVGR2FR_W\0" /* 16247 */ "XVPICKVE2GR_W\0" /* 16261 */ "XVAVGR_W\0" /* 16270 */ "XVBITCLR_W\0" /* 16281 */ "XVSRLR_W\0" /* 16290 */ "X86OR_W\0" /* 16298 */ "AMOR_W\0" /* 16305 */ "ARMOR_W\0" /* 16313 */ "X86XOR_W\0" /* 16322 */ "AMXOR_W\0" /* 16330 */ "ARMXOR_W\0" /* 16339 */ "X86ROTR_W\0" /* 16349 */ "ARMROTR_W\0" /* 16359 */ "XVROTR_W\0" /* 16368 */ "LDPTR_W\0" /* 16376 */ "STPTR_W\0" /* 16384 */ "STR_W\0" /* 16390 */ "XVREPLGR2VR_W\0" /* 16404 */ "XVINSGR2VR_W\0" /* 16417 */ "IOCSRWR_W\0" /* 16427 */ "AMCAS_W\0" /* 16435 */ "BSTRINS_W\0" /* 16445 */ "XVEXTRINS_W\0" /* 16457 */ "XVFFINT_S_W\0" /* 16469 */ "XVSAT_W\0" /* 16477 */ "XVBITSET_W\0" /* 16488 */ "LDGT_W\0" /* 16495 */ "STGT_W\0" /* 16502 */ "XVSLT_W\0" /* 16510 */ "XVPCNT_W\0" /* 16519 */ "ARMNOT_W\0" /* 16528 */ "ST_W\0" /* 16533 */ "XVSSRANI_HU_W\0" /* 16547 */ "XVSSRLNI_HU_W\0" /* 16561 */ "XVSSRARNI_HU_W\0" /* 16576 */ "XVSSRLRNI_HU_W\0" /* 16591 */ "XVSSRAN_HU_W\0" /* 16604 */ "XVSSRLN_HU_W\0" /* 16617 */ "XVSSRARN_HU_W\0" /* 16631 */ "XVSSRLRN_HU_W\0" /* 16645 */ "XVMADDWOD_D_WU_W\0" /* 16662 */ "XVADDWOD_D_WU_W\0" /* 16678 */ "XVMULWOD_D_WU_W\0" /* 16694 */ "XVMADDWEV_D_WU_W\0" /* 16711 */ "XVADDWEV_D_WU_W\0" /* 16727 */ "XVMULWEV_D_WU_W\0" /* 16743 */ "XVPACKEV_W\0" /* 16754 */ "XVPICKEV_W\0" /* 16765 */ "XVBITREV_W\0" /* 16776 */ "XVDIV_W\0" /* 16784 */ "XVSIGNCOV_W\0" /* 16796 */ "ARMMOV_W\0" /* 16805 */ "CRCC_W_W_W\0" /* 16816 */ "CRC_W_W_W\0" /* 16826 */ "AMMAX_W\0" /* 16834 */ "XVMAX_W\0" /* 16842 */ "LDX_W\0" /* 16848 */ "ARMRRX_W\0" /* 16857 */ "STX_W\0" /* 16863 */ "PseudoXVBZ_W\0" /* 16876 */ "PseudoVBZ_W\0" /* 16888 */ "XVSETALLNEZ_W\0" /* 16902 */ "XVCLZ_W\0" /* 16910 */ "PseudoXVBNZ_W\0" /* 16924 */ "PseudoVBNZ_W\0" /* 16937 */ "XVSETANYEQZ_W\0" /* 16951 */ "CTZ_W\0" /* 16957 */ "XVMSKLTZ_W\0" /* 16968 */ "PseudoAddTPRel_W\0" /* 16985 */ "PseudoAtomicStoreW\0" /* 17004 */ "G_VECREDUCE_FMAX\0" /* 17021 */ "G_ATOMICRMW_FMAX\0" /* 17038 */ "G_VECREDUCE_SMAX\0" /* 17055 */ "G_SMAX\0" /* 17062 */ "G_VECREDUCE_UMAX\0" /* 17079 */ "G_UMAX\0" /* 17086 */ "G_ATOMICRMW_UMAX\0" /* 17103 */ "G_ATOMICRMW_MAX\0" /* 17119 */ "PRELDX\0" /* 17126 */ "XVLDX\0" /* 17132 */ "G_FRAME_INDEX\0" /* 17146 */ "G_SBFX\0" /* 17153 */ "G_UBFX\0" /* 17160 */ "G_SMULFIX\0" /* 17170 */ "G_UMULFIX\0" /* 17180 */ "G_SDIVFIX\0" /* 17190 */ "G_UDIVFIX\0" /* 17200 */ "XVSTX\0" /* 17206 */ "G_MEMCPY\0" /* 17215 */ "COPY\0" /* 17220 */ "CONVERGENCECTRL_ENTRY\0" /* 17242 */ "PseudoXVBZ\0" /* 17253 */ "PseudoVBZ\0" /* 17263 */ "BNEZ\0" /* 17268 */ "BCNEZ\0" /* 17274 */ "MASKNEZ\0" /* 17282 */ "G_CTLZ\0" /* 17289 */ "PseudoXVBNZ\0" /* 17301 */ "PseudoVBNZ\0" /* 17312 */ "BEQZ\0" /* 17317 */ "BCEQZ\0" /* 17323 */ "MASKEQZ\0" /* 17331 */ "G_CTTZ\0" /* 17338 */ "PseudoTAILIndirect\0" /* 17357 */ "PseudoCALLIndirect\0" }; #ifdef __GNUC__ #pragma GCC diagnostic pop #endif extern const unsigned LoongArchInstrNameIndices[] = { 8541U, 9105U, 10131U, 9452U, 8651U, 8632U, 8660U, 8912U, 6501U, 6516U, 6417U, 6404U, 6543U, 10775U, 6222U, 12528U, 6430U, 8537U, 8641U, 5699U, 17215U, 6060U, 12432U, 2597U, 5650U, 5687U, 9572U, 8881U, 12329U, 2716U, 9847U, 6622U, 12318U, 6116U, 9820U, 9807U, 10211U, 12159U, 12192U, 8797U, 8860U, 8833U, 8677U, 6207U, 10176U, 9526U, 17220U, 10412U, 9728U, 6270U, 12563U, 12593U, 9295U, 2457U, 638U, 9020U, 14454U, 14461U, 9071U, 9078U, 9085U, 9095U, 2575U, 10587U, 10550U, 6415U, 8539U, 17132U, 6232U, 6247U, 8917U, 12127U, 10711U, 12469U, 10728U, 10487U, 2217U, 10758U, 12340U, 10639U, 12501U, 6334U, 10187U, 2690U, 2191U, 2672U, 12378U, 12359U, 9273U, 10236U, 10255U, 2358U, 2302U, 2332U, 2343U, 2283U, 2313U, 6172U, 6156U, 10805U, 6564U, 6590U, 2473U, 644U, 2581U, 2542U, 10592U, 10556U, 17103U, 9421U, 17086U, 9404U, 2424U, 621U, 17021U, 9339U, 9634U, 9612U, 2631U, 12080U, 5679U, 6663U, 2622U, 12146U, 12447U, 2169U, 10853U, 12295U, 10880U, 12577U, 2209U, 12284U, 12272U, 12422U, 6614U, 12556U, 6530U, 12586U, 8719U, 10392U, 10378U, 8712U, 10385U, 10632U, 8938U, 9689U, 9682U, 9696U, 9703U, 12137U, 9518U, 5720U, 9502U, 5671U, 9510U, 5712U, 9494U, 5663U, 9556U, 9548U, 6682U, 6674U, 11998U, 11988U, 11978U, 11968U, 12018U, 12008U, 17160U, 17170U, 12028U, 12041U, 17180U, 17190U, 12054U, 12067U, 2382U, 600U, 8962U, 554U, 2276U, 14433U, 9050U, 14621U, 8579U, 9891U, 453U, 9U, 6607U, 445U, 0U, 9866U, 9898U, 6494U, 12548U, 2181U, 8550U, 8564U, 9664U, 9673U, 12101U, 12114U, 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15314U, 1997U, 5153U, 8184U, 16784U, 1204U, 12813U, 3580U, 13177U, 7293U, 13580U, 15671U, 14197U, 931U, 12652U, 3230U, 13122U, 7195U, 13533U,<TRUNCATED>#endif // GET_INSTRINFO_MC_DESC#ifdef GET_INSTRINFO_HEADER#undef GET_INSTRINFO_HEADER#endif // GET_INSTRINFO_HEADER#ifdef GET_INSTRINFO_HELPER_DECLS#undef GET_INSTRINFO_HELPER_DECLS#endif // GET_INSTRINFO_HELPER_DECLS#ifdef GET_INSTRINFO_HELPERS#undef GET_INSTRINFO_HELPERS#endif // GET_INSTRINFO_HELPERS#ifdef GET_INSTRINFO_CTOR_DTOR#undef GET_INSTRINFO_CTOR_DTOR#endif // GET_INSTRINFO_CTOR_DTOR#ifdef GET_INSTRINFO_OPERAND_ENUM#undef GET_INSTRINFO_OPERAND_ENUM#endif //GET_INSTRINFO_OPERAND_ENUM#ifdef GET_INSTRINFO_NAMED_OPS#undef GET_INSTRINFO_NAMED_OPS#endif //GET_INSTRINFO_NAMED_OPS#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM#undef GET_INSTRINFO_OPERAND_TYPES_ENUM#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM#ifdef GET_INSTRINFO_OPERAND_TYPE#undef GET_INSTRINFO_OPERAND_TYPE#endif // GET_INSTRINFO_OPERAND_TYPE#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE#undef GET_INSTRINFO_MEM_OPERAND_SIZE#endif // GET_INSTRINFO_MEM_OPERAND_SIZE#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP#ifdef GET_INSTRINFO_MC_HELPER_DECLS#undef GET_INSTRINFO_MC_HELPER_DECLSclass MCInstclass FeatureBitsetvoid verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features)#endif // GET_INSTRINFO_MC_HELPER_DECLS#ifdef GET_INSTRINFO_MC_HELPERS#undef GET_INSTRINFO_MC_HELPERS#endif // GET_GENISTRINFO_MC_HELPERS#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\ defined(GET_AVAILABLE_OPCODE_CHECKER)#define GET_COMPUTE_FEATURES#endif#ifdef GET_COMPUTE_FEATURES#undef GET_COMPUTE_FEATURES#endif // GET_COMPUTE_FEATURES#ifdef GET_AVAILABLE_OPCODE_CHECKER#undef GET_AVAILABLE_OPCODE_CHECKER#endif // GET_AVAILABLE_OPCODE_CHECKER#ifdef ENABLE_INSTR_PREDICATE_VERIFIER#undef ENABLE_INSTR_PREDICATE_VERIFIER#include <sstream>#ifndef NDEBUG#endif // NDEBUG#ifndef NDEBUG#endif // NDEBUG#endif // ENABLE_INSTR_PREDICATE_VERIFIER
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