llvm/lib/Target/Mips/MipsGenGlobalISel.inc

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Global Instruction Selector for the Mips target                            *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_GLOBALISEL_PREDICATE_BITSET
const unsigned MAX_SUBTARGET_PREDICATES = …;
PredicateBitset;
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET

#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
  mutable MatcherState State;
  typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
  typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
  const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
  static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
  static MipsInstructionSelector::CustomRendererFn CustomRenderers[];
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
  const uint8_t *getMatchTable() const override;
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
  bool testSimplePredicate(unsigned PredicateID) const override;
  bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL

#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
, State(0),
ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT

#ifdef GET_GLOBALISEL_IMPL
// LLT Objects.
enum {
  GILLT_s16,
  GILLT_s32,
  GILLT_s64,
  GILLT_v2s16,
  GILLT_v2s64,
  GILLT_v4s8,
  GILLT_v4s32,
  GILLT_v8s16,
  GILLT_v16s8,
};
const static size_t NumTypeObjects = 9;
const static LLT TypeObjects[] = {
  LLT::scalar(16),
  LLT::scalar(32),
  LLT::scalar(64),
  LLT::vector(ElementCount::getFixed(2), 16),
  LLT::vector(ElementCount::getFixed(2), 64),
  LLT::vector(ElementCount::getFixed(4), 8),
  LLT::vector(ElementCount::getFixed(4), 32),
  LLT::vector(ElementCount::getFixed(8), 16),
  LLT::vector(ElementCount::getFixed(16), 8),
};

// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
  Feature_HasMips2Bit = 7,
  Feature_HasMips3Bit = 17,
  Feature_HasMips4_32Bit = 27,
  Feature_NotMips4_32Bit = 28,
  Feature_HasMips4_32r2Bit = 18,
  Feature_HasMips32Bit = 3,
  Feature_HasMips32r2Bit = 6,
  Feature_HasMips32r6Bit = 29,
  Feature_NotMips32r6Bit = 4,
  Feature_IsGP64bitBit = 22,
  Feature_IsPTR64bitBit = 24,
  Feature_HasMips64Bit = 25,
  Feature_HasMips64r2Bit = 23,
  Feature_HasMips64r6Bit = 30,
  Feature_NotMips64r6Bit = 5,
  Feature_InMips16ModeBit = 31,
  Feature_NotInMips16ModeBit = 0,
  Feature_HasCnMipsBit = 26,
  Feature_NotCnMipsBit = 8,
  Feature_IsSym32Bit = 38,
  Feature_IsSym64Bit = 39,
  Feature_IsN64Bit = 40,
  Feature_RelocNotPICBit = 9,
  Feature_RelocPICBit = 37,
  Feature_NoNaNsFPMathBit = 21,
  Feature_UseAbsBit = 14,
  Feature_HasStdEncBit = 1,
  Feature_NotDSPBit = 11,
  Feature_InMicroMipsBit = 35,
  Feature_NotInMicroMipsBit = 2,
  Feature_IsLEBit = 42,
  Feature_IsBEBit = 43,
  Feature_IsNotNaClBit = 19,
  Feature_HasEVABit = 36,
  Feature_HasMSABit = 34,
  Feature_HasMadd4Bit = 20,
  Feature_UseIndirectJumpsHazardBit = 12,
  Feature_NoIndirectJumpGuardsBit = 10,
  Feature_AllowFPOpFusionBit = 41,
  Feature_IsFP64bitBit = 16,
  Feature_NotFP64bitBit = 15,
  Feature_IsNotSoftFloatBit = 13,
  Feature_HasDSPBit = 32,
  Feature_HasDSPR2Bit = 33,
};

PredicateBitset MipsInstructionSelector::
computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const {
  PredicateBitset Features{};
  if (Subtarget->hasMips2())
    Features.set(Feature_HasMips2Bit);
  if (Subtarget->hasMips3())
    Features.set(Feature_HasMips3Bit);
  if (Subtarget->hasMips4_32())
    Features.set(Feature_HasMips4_32Bit);
  if (!Subtarget->hasMips4_32())
    Features.set(Feature_NotMips4_32Bit);
  if (Subtarget->hasMips4_32r2())
    Features.set(Feature_HasMips4_32r2Bit);
  if (Subtarget->hasMips32())
    Features.set(Feature_HasMips32Bit);
  if (Subtarget->hasMips32r2())
    Features.set(Feature_HasMips32r2Bit);
  if (Subtarget->hasMips32r6())
    Features.set(Feature_HasMips32r6Bit);
  if (!Subtarget->hasMips32r6())
    Features.set(Feature_NotMips32r6Bit);
  if (Subtarget->isGP64bit())
    Features.set(Feature_IsGP64bitBit);
  if (Subtarget->isABI_N64())
    Features.set(Feature_IsPTR64bitBit);
  if (Subtarget->hasMips64())
    Features.set(Feature_HasMips64Bit);
  if (Subtarget->hasMips64r2())
    Features.set(Feature_HasMips64r2Bit);
  if (Subtarget->hasMips64r6())
    Features.set(Feature_HasMips64r6Bit);
  if (!Subtarget->hasMips64r6())
    Features.set(Feature_NotMips64r6Bit);
  if (Subtarget->inMips16Mode())
    Features.set(Feature_InMips16ModeBit);
  if (!Subtarget->inMips16Mode())
    Features.set(Feature_NotInMips16ModeBit);
  if (Subtarget->hasCnMips())
    Features.set(Feature_HasCnMipsBit);
  if (!Subtarget->hasCnMips())
    Features.set(Feature_NotCnMipsBit);
  if (Subtarget->hasSym32())
    Features.set(Feature_IsSym32Bit);
  if (!Subtarget->hasSym32())
    Features.set(Feature_IsSym64Bit);
  if (Subtarget->isABI_N64())
    Features.set(Feature_IsN64Bit);
  if (!TM.isPositionIndependent())
    Features.set(Feature_RelocNotPICBit);
  if (TM.isPositionIndependent())
    Features.set(Feature_RelocPICBit);
  if (TM.Options.NoNaNsFPMath)
    Features.set(Feature_NoNaNsFPMathBit);
  if (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)
    Features.set(Feature_UseAbsBit);
  if (Subtarget->hasStandardEncoding())
    Features.set(Feature_HasStdEncBit);
  if (!Subtarget->hasDSP())
    Features.set(Feature_NotDSPBit);
  if (Subtarget->inMicroMipsMode())
    Features.set(Feature_InMicroMipsBit);
  if (!Subtarget->inMicroMipsMode())
    Features.set(Feature_NotInMicroMipsBit);
  if (Subtarget->isLittle())
    Features.set(Feature_IsLEBit);
  if (!Subtarget->isLittle())
    Features.set(Feature_IsBEBit);
  if (!Subtarget->isTargetNaCl())
    Features.set(Feature_IsNotNaClBit);
  if (Subtarget->hasEVA())
    Features.set(Feature_HasEVABit);
  if (Subtarget->hasMSA())
    Features.set(Feature_HasMSABit);
  if (!Subtarget->disableMadd4())
    Features.set(Feature_HasMadd4Bit);
  if (Subtarget->useIndirectJumpsHazard())
    Features.set(Feature_UseIndirectJumpsHazardBit);
  if (!Subtarget->useIndirectJumpsHazard())
    Features.set(Feature_NoIndirectJumpGuardsBit);
  if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast)
    Features.set(Feature_AllowFPOpFusionBit);
  if (Subtarget->isFP64bit())
    Features.set(Feature_IsFP64bitBit);
  if (!Subtarget->isFP64bit())
    Features.set(Feature_NotFP64bitBit);
  if (!Subtarget->useSoftFloat())
    Features.set(Feature_IsNotSoftFloatBit);
  if (Subtarget->hasDSP())
    Features.set(Feature_HasDSPBit);
  if (Subtarget->hasDSPR2())
    Features.set(Feature_HasDSPR2Bit);
  return Features;
}

void MipsInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
  AvailableFunctionFeatures = computeAvailableFunctionFeatures((const MipsSubtarget *)&MF.getSubtarget(), &MF);
}
PredicateBitset MipsInstructionSelector::
computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const {
  PredicateBitset Features{};
  return Features;
}

// Feature bitsets.
enum {
  GIFBS_Invalid,
  GIFBS_HasCnMips,
  GIFBS_HasDSP,
  GIFBS_HasDSPR2,
  GIFBS_HasMSA,
  GIFBS_InMicroMips,
  GIFBS_InMips16Mode,
  GIFBS_IsFP64bit,
  GIFBS_NotFP64bit,
  GIFBS_HasDSP_InMicroMips,
  GIFBS_HasDSP_NotInMicroMips,
  GIFBS_HasDSPR2_InMicroMips,
  GIFBS_HasMSA_HasStdEnc,
  GIFBS_HasMSA_IsBE,
  GIFBS_HasMSA_IsLE,
  GIFBS_HasMips32r6_HasStdEnc,
  GIFBS_HasMips32r6_InMicroMips,
  GIFBS_HasMips64r2_HasStdEnc,
  GIFBS_HasMips64r6_HasStdEnc,
  GIFBS_HasStdEnc_IsNotSoftFloat,
  GIFBS_HasStdEnc_NotInMicroMips,
  GIFBS_HasStdEnc_NotMips4_32,
  GIFBS_InMicroMips_IsFP64bit,
  GIFBS_InMicroMips_IsNotSoftFloat,
  GIFBS_InMicroMips_NotFP64bit,
  GIFBS_InMicroMips_NotMips32r6,
  GIFBS_IsGP64bit_NotInMips16Mode,
  GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
  GIFBS_HasMSA_HasMips64_HasStdEnc,
  GIFBS_HasMips3_HasStdEnc_IsGP64bit,
  GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
  GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
  GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
  GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
  GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips,
  GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
  GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
  GIFBS_HasStdEnc_IsFP64bit_NotMips4_32,
  GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
  GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
  GIFBS_HasStdEnc_NotFP64bit_NotMips4_32,
  GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
  GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
  GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
  GIFBS_InMicroMips_IsNotSoftFloat_UseAbs,
  GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
  GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
  GIFBS_InMicroMips_NotMips32r6_RelocPIC,
  GIFBS_IsFP64bit_IsNotSoftFloat_NotInMips16Mode,
  GIFBS_IsNotSoftFloat_NotFP64bit_NotInMips16Mode,
  GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6,
  GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
  GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
  GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
  GIFBS_HasMips32_HasStdEnc_NotMips32r6_NotMips64r6,
  GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
  GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
  GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
  GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
  GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
  GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips_UseAbs,
  GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6,
  GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
  GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
  GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
  GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
  GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6,
  GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_UseAbs,
  GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_UseAbs,
  GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
  GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
  GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
};
constexpr static PredicateBitset FeatureBitsets[] {
  {}, // GIFBS_Invalid
  {Feature_HasCnMipsBit, },
  {Feature_HasDSPBit, },
  {Feature_HasDSPR2Bit, },
  {Feature_HasMSABit, },
  {Feature_InMicroMipsBit, },
  {Feature_InMips16ModeBit, },
  {Feature_IsFP64bitBit, },
  {Feature_NotFP64bitBit, },
  {Feature_HasDSPBit, Feature_InMicroMipsBit, },
  {Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
  {Feature_HasDSPR2Bit, Feature_InMicroMipsBit, },
  {Feature_HasMSABit, Feature_HasStdEncBit, },
  {Feature_HasMSABit, Feature_IsBEBit, },
  {Feature_HasMSABit, Feature_IsLEBit, },
  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, },
  {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, },
  {Feature_HasMips64r2Bit, Feature_HasStdEncBit, },
  {Feature_HasMips64r6Bit, Feature_HasStdEncBit, },
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
  {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
  {Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
  {Feature_InMicroMipsBit, Feature_IsFP64bitBit, },
  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
  {Feature_InMicroMipsBit, Feature_NotFP64bitBit, },
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
  {Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, },
  {Feature_AllowFPOpFusionBit, Feature_HasMSABit, Feature_HasStdEncBit, },
  {Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, },
  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
  {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
  {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
  {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
  {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, },
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
  {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, },
  {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, },
  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_UseAbsBit, },
  {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, },
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, },
  {Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMips16ModeBit, },
  {Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMips16ModeBit, },
  {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotMips32r6Bit, },
  {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
  {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
  {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
  {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
  {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
  {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMips64Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips64r6Bit, },
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
};

// ComplexPattern predicates.
enum {
  GICP_Invalid,
};
// See constructor for table contents

MipsInstructionSelector::ComplexMatcherMemFn
MipsInstructionSelector::ComplexPredicateFns[] = {
  nullptr, // GICP_Invalid
};

// PatFrag predicates.
bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
  const MachineFunction &MF = *MI.getParent()->getParent();
  const MachineRegisterInfo &MRI = MF.getRegInfo();
  const auto &Operands = State.RecordedOperands;
  (void)Operands;
  (void)MRI;
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
enum {
  GICXXPred_I64_Predicate_immLi16 = GICXXPred_Invalid + 1,
  GICXXPred_I64_Predicate_immSExt6,
  GICXXPred_I64_Predicate_immSExt10,
  GICXXPred_I64_Predicate_immSExtAddiur2,
  GICXXPred_I64_Predicate_immSExtAddius5,
  GICXXPred_I64_Predicate_immZExt1,
  GICXXPred_I64_Predicate_immZExt1Ptr,
  GICXXPred_I64_Predicate_immZExt2,
  GICXXPred_I64_Predicate_immZExt2Lsa,
  GICXXPred_I64_Predicate_immZExt2Ptr,
  GICXXPred_I64_Predicate_immZExt2Shift,
  GICXXPred_I64_Predicate_immZExt3,
  GICXXPred_I64_Predicate_immZExt3Ptr,
  GICXXPred_I64_Predicate_immZExt4,
  GICXXPred_I64_Predicate_immZExt4Ptr,
  GICXXPred_I64_Predicate_immZExt5,
  GICXXPred_I64_Predicate_immZExt5_64,
  GICXXPred_I64_Predicate_immZExt6,
  GICXXPred_I64_Predicate_immZExt8,
  GICXXPred_I64_Predicate_immZExt10,
  GICXXPred_I64_Predicate_immZExtAndi16,
  GICXXPred_I64_Predicate_immi32Cst7,
  GICXXPred_I64_Predicate_immi32Cst15,
  GICXXPred_I64_Predicate_immi32Cst31,
  GICXXPred_I64_Predicate_timmSExt6,
  GICXXPred_I64_Predicate_timmZExt1,
  GICXXPred_I64_Predicate_timmZExt1Ptr,
  GICXXPred_I64_Predicate_timmZExt2,
  GICXXPred_I64_Predicate_timmZExt2Ptr,
  GICXXPred_I64_Predicate_timmZExt3,
  GICXXPred_I64_Predicate_timmZExt3Ptr,
  GICXXPred_I64_Predicate_timmZExt4,
  GICXXPred_I64_Predicate_timmZExt4Ptr,
  GICXXPred_I64_Predicate_timmZExt5,
  GICXXPred_I64_Predicate_timmZExt6,
  GICXXPred_I64_Predicate_timmZExt8,
  GICXXPred_I64_Predicate_timmZExt10,
};
bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
  switch (PredicateID) {
  case GICXXPred_I64_Predicate_immLi16: {
    return Imm >= -1 && Imm <= 126;
  }
  case GICXXPred_I64_Predicate_immSExt6: {
    return isInt<6>(Imm);
  }
  case GICXXPred_I64_Predicate_immSExt10: {
    return isInt<10>(Imm);
  }
  case GICXXPred_I64_Predicate_immSExtAddiur2: {
    return Imm == 1 || Imm == -1 ||
                                               ((Imm % 4 == 0) &&
                                                Imm < 28 && Imm > 0);
  }
  case GICXXPred_I64_Predicate_immSExtAddius5: {
    return Imm >= -8 && Imm <= 7;
  }
  case GICXXPred_I64_Predicate_immZExt1: {
    return isUInt<1>(Imm);
  }
  case GICXXPred_I64_Predicate_immZExt1Ptr: {
    return isUInt<1>(Imm);
  }
  case GICXXPred_I64_Predicate_immZExt2: {
    return isUInt<2>(Imm);
  }
  case GICXXPred_I64_Predicate_immZExt2Lsa: {
    return isUInt<2>(Imm - 1);
  }
  case GICXXPred_I64_Predicate_immZExt2Ptr: {
    return isUInt<2>(Imm);
  }
  case GICXXPred_I64_Predicate_immZExt2Shift: {
    return Imm >= 1 && Imm <= 8;
  }
  case GICXXPred_I64_Predicate_immZExt3: {
    return isUInt<3>(Imm);
  }
  case GICXXPred_I64_Predicate_immZExt3Ptr: {
    return isUInt<3>(Imm);
  }
  case GICXXPred_I64_Predicate_immZExt4: {
    return isUInt<4>(Imm);
  }
  case GICXXPred_I64_Predicate_immZExt4Ptr: {
    return isUInt<4>(Imm);
  }
  case GICXXPred_I64_Predicate_immZExt5: {
    return Imm == (Imm & 0x1f);
  }
  case GICXXPred_I64_Predicate_immZExt5_64: {
     return Imm == (Imm & 0x1f); 
  }
  case GICXXPred_I64_Predicate_immZExt6: {
    return Imm == (Imm & 0x3f);
  }
  case GICXXPred_I64_Predicate_immZExt8: {
    return isUInt<8>(Imm);
  }
  case GICXXPred_I64_Predicate_immZExt10: {
    return isUInt<10>(Imm);
  }
  case GICXXPred_I64_Predicate_immZExtAndi16: {
    return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
                Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
                Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
  }
  case GICXXPred_I64_Predicate_immi32Cst7: {
    return isUInt<32>(Imm) && Imm == 7;
  }
  case GICXXPred_I64_Predicate_immi32Cst15: {
    return isUInt<32>(Imm) && Imm == 15;
  }
  case GICXXPred_I64_Predicate_immi32Cst31: {
    return isUInt<32>(Imm) && Imm == 31;
  }
  case GICXXPred_I64_Predicate_timmSExt6: {
    return isInt<6>(Imm);
  }
  case GICXXPred_I64_Predicate_timmZExt1: {
    return isUInt<1>(Imm);
  }
  case GICXXPred_I64_Predicate_timmZExt1Ptr: {
    return isUInt<1>(Imm);
  }
  case GICXXPred_I64_Predicate_timmZExt2: {
    return isUInt<2>(Imm);
  }
  case GICXXPred_I64_Predicate_timmZExt2Ptr: {
    return isUInt<2>(Imm);
  }
  case GICXXPred_I64_Predicate_timmZExt3: {
    return isUInt<3>(Imm);
  }
  case GICXXPred_I64_Predicate_timmZExt3Ptr: {
    return isUInt<3>(Imm);
  }
  case GICXXPred_I64_Predicate_timmZExt4: {
    return isUInt<4>(Imm);
  }
  case GICXXPred_I64_Predicate_timmZExt4Ptr: {
    return isUInt<4>(Imm);
  }
  case GICXXPred_I64_Predicate_timmZExt5: {
    return Imm == (Imm & 0x1f);
  }
  case GICXXPred_I64_Predicate_timmZExt6: {
    return Imm == (Imm & 0x3f);
  }
  case GICXXPred_I64_Predicate_timmZExt8: {
    return isUInt<8>(Imm);
  }
  case GICXXPred_I64_Predicate_timmZExt10: {
    return isUInt<10>(Imm);
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
enum {
  GICXXPred_APInt_Predicate_imm32SExt16 = GICXXPred_Invalid + 1,
  GICXXPred_APInt_Predicate_imm32ZExt16,
};
bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
  switch (PredicateID) {
  case GICXXPred_APInt_Predicate_imm32SExt16: {
     return isInt<16>(Imm.getSExtValue()); 
  }
  case GICXXPred_APInt_Predicate_imm32ZExt16: {
    
      return (uint32_t)Imm.getZExtValue() == (unsigned short)Imm.getZExtValue();
    
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
bool MipsInstructionSelector::testSimplePredicate(unsigned) const {
    llvm_unreachable("MipsInstructionSelector does not support simple predicates!");
  return false;
}
// Custom renderers.
enum {
  GICR_Invalid,
};
MipsInstructionSelector::CustomRendererFn
MipsInstructionSelector::CustomRenderers[] = {
  nullptr, // GICR_Invalid
};

bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
  MachineIRBuilder B(I);
  State.MIs.clear();
  State.MIs.push_back(&I);

  if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
    return true;
  }

  return false;
}

bool MipsInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const {
    llvm_unreachable("MipsInstructionSelector does not support custom C++ actions!");
}
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
#define GIMT_Encode2 …
#define GIMT_Encode4 …
#define GIMT_Encode8 …
#else
#define GIMT_Encode2 …
#define GIMT_Encode4 …
#define GIMT_Encode8 …
#endif
const uint8_t *MipsInstructionSelector::getMatchTable() const {
  constexpr static uint8_t MatchTable0[] = {
    GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(53), GIMT_Encode2(280), /*)*//*default:*//*Label 64*/ GIMT_Encode4(66631),
    /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(918),
    /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(2216),
    /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(2907),
    /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(3388),
    /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(3657),
    /*TargetOpcode::G_SREM*//*Label 5*/ GIMT_Encode4(3926),
    /*TargetOpcode::G_UREM*//*Label 6*/ GIMT_Encode4(4195), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_AND*//*Label 7*/ GIMT_Encode4(4464),
    /*TargetOpcode::G_OR*//*Label 8*/ GIMT_Encode4(5020),
    /*TargetOpcode::G_XOR*//*Label 9*/ GIMT_Encode4(5424), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_MERGE_VALUES*//*Label 10*/ GIMT_Encode4(6316),
    /*TargetOpcode::G_BUILD_VECTOR*//*Label 11*/ GIMT_Encode4(6389), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_BITCAST*//*Label 12*/ GIMT_Encode4(6730), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_LOAD*//*Label 13*/ GIMT_Encode4(10921),
    /*TargetOpcode::G_SEXTLOAD*//*Label 14*/ GIMT_Encode4(10986),
    /*TargetOpcode::G_ZEXTLOAD*//*Label 15*/ GIMT_Encode4(11054), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_BRCOND*//*Label 16*/ GIMT_Encode4(11122), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_INTRINSIC*//*Label 17*/ GIMT_Encode4(15843),
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 18*/ GIMT_Encode4(30108), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_ANYEXT*//*Label 19*/ GIMT_Encode4(34766),
    /*TargetOpcode::G_TRUNC*//*Label 20*/ GIMT_Encode4(34832),
    /*TargetOpcode::G_CONSTANT*//*Label 21*/ GIMT_Encode4(34896), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_SEXT*//*Label 22*/ GIMT_Encode4(34957), GIMT_Encode4(0),
    /*TargetOpcode::G_ZEXT*//*Label 23*/ GIMT_Encode4(36421),
    /*TargetOpcode::G_SHL*//*Label 24*/ GIMT_Encode4(36622),
    /*TargetOpcode::G_LSHR*//*Label 25*/ GIMT_Encode4(38419),
    /*TargetOpcode::G_ASHR*//*Label 26*/ GIMT_Encode4(40216), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_ROTR*//*Label 27*/ GIMT_Encode4(41971), GIMT_Encode4(0),
    /*TargetOpcode::G_ICMP*//*Label 28*/ GIMT_Encode4(42259),
    /*TargetOpcode::G_FCMP*//*Label 29*/ GIMT_Encode4(44790), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_SELECT*//*Label 30*/ GIMT_Encode4(46496), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_UMULH*//*Label 31*/ GIMT_Encode4(58534),
    /*TargetOpcode::G_SMULH*//*Label 32*/ GIMT_Encode4(58643), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_FADD*//*Label 33*/ GIMT_Encode4(58752),
    /*TargetOpcode::G_FSUB*//*Label 34*/ GIMT_Encode4(59665),
    /*TargetOpcode::G_FMUL*//*Label 35*/ GIMT_Encode4(60277),
    /*TargetOpcode::G_FMA*//*Label 36*/ GIMT_Encode4(60764), GIMT_Encode4(0),
    /*TargetOpcode::G_FDIV*//*Label 37*/ GIMT_Encode4(60870), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_FEXP2*//*Label 38*/ GIMT_Encode4(61169), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_FLOG2*//*Label 39*/ GIMT_Encode4(61247), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_FNEG*//*Label 40*/ GIMT_Encode4(61325),
    /*TargetOpcode::G_FPEXT*//*Label 41*/ GIMT_Encode4(62694),
    /*TargetOpcode::G_FPTRUNC*//*Label 42*/ GIMT_Encode4(62872),
    /*TargetOpcode::G_FPTOSI*//*Label 43*/ GIMT_Encode4(63035),
    /*TargetOpcode::G_FPTOUI*//*Label 44*/ GIMT_Encode4(63113),
    /*TargetOpcode::G_SITOFP*//*Label 45*/ GIMT_Encode4(63191),
    /*TargetOpcode::G_UITOFP*//*Label 46*/ GIMT_Encode4(63444), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_FABS*//*Label 47*/ GIMT_Encode4(63522), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_FCANONICALIZE*//*Label 48*/ GIMT_Encode4(63762), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_FMINNUM_IEEE*//*Label 49*/ GIMT_Encode4(63836),
    /*TargetOpcode::G_FMAXNUM_IEEE*//*Label 50*/ GIMT_Encode4(63908), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_SMIN*//*Label 51*/ GIMT_Encode4(63980),
    /*TargetOpcode::G_SMAX*//*Label 52*/ GIMT_Encode4(64148),
    /*TargetOpcode::G_UMIN*//*Label 53*/ GIMT_Encode4(64316),
    /*TargetOpcode::G_UMAX*//*Label 54*/ GIMT_Encode4(64484), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_BR*//*Label 55*/ GIMT_Encode4(64652), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 56*/ GIMT_Encode4(64776),
    /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 57*/ GIMT_Encode4(65340), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_CTLZ*//*Label 58*/ GIMT_Encode4(65392), GIMT_Encode4(0),
    /*TargetOpcode::G_CTPOP*//*Label 59*/ GIMT_Encode4(65897),
    /*TargetOpcode::G_BSWAP*//*Label 60*/ GIMT_Encode4(66103), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_FSQRT*//*Label 61*/ GIMT_Encode4(66267), GIMT_Encode4(0),
    /*TargetOpcode::G_FRINT*//*Label 62*/ GIMT_Encode4(66507), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_TRAP*//*Label 63*/ GIMT_Encode4(66585),
    // Label 0: @918
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 73*/ GIMT_Encode4(2215),
    /*GILLT_s32*//*Label 65*/ GIMT_Encode4(961),
    /*GILLT_s64*//*Label 66*/ GIMT_Encode4(1369),
    /*GILLT_v2s16*//*Label 67*/ GIMT_Encode4(1535),
    /*GILLT_v2s64*//*Label 68*/ GIMT_Encode4(1567),
    /*GILLT_v4s8*//*Label 69*/ GIMT_Encode4(1721),
    /*GILLT_v4s32*//*Label 70*/ GIMT_Encode4(1753),
    /*GILLT_v8s16*//*Label 71*/ GIMT_Encode4(1907),
    /*GILLT_v16s8*//*Label 72*/ GIMT_Encode4(2061),
    // Label 65: @961
    GIM_Try, /*On fail goto*//*Label 74*/ GIMT_Encode4(1368),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 75*/ GIMT_Encode4(1039), // Rule ID 2389 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_CheckIsSafeToFold, /*NumInsns*/2,
        // (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR32Opnd:{ *:[i32] }:$rt)  =>  (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LSA),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 2389,
        GIR_EraseRootFromParent_Done,
      // Label 75: @1039
      GIM_Try, /*On fail goto*//*Label 76*/ GIMT_Encode4(1106), // Rule ID 834 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/2,
        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa))  =>  (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LSA),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
        GIR_RootToRootCopy, /*OpIdx*/1, // rt
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 834,
        GIR_EraseRootFromParent_Done,
      // Label 76: @1106
      GIM_Try, /*On fail goto*//*Label 77*/ GIMT_Encode4(1148), // Rule ID 40 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32SExt16),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm16)  =>  (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDiu),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/1, // rs
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 40,
        GIR_EraseRootFromParent_Done,
      // Label 77: @1148
      GIM_Try, /*On fail goto*//*Label 78*/ GIMT_Encode4(1190), // Rule ID 2158 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExtAddiur2),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)  =>  (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDIUR2_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/1, // src
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 2158,
        GIR_EraseRootFromParent_Done,
      // Label 78: @1190
      GIM_Try, /*On fail goto*//*Label 79*/ GIMT_Encode4(1232), // Rule ID 2159 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExtAddius5),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)  =>  (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDIUS5_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
        GIR_RootToRootCopy, /*OpIdx*/1, // src
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 2159,
        GIR_EraseRootFromParent_Done,
      // Label 79: @1232
      GIM_Try, /*On fail goto*//*Label 80*/ GIMT_Encode4(1259), // Rule ID 1208 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU16_MMR6),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1208,
        GIR_Done,
      // Label 80: @1259
      GIM_Try, /*On fail goto*//*Label 81*/ GIMT_Encode4(1286), // Rule ID 46 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDu),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 46,
        GIR_Done,
      // Label 81: @1286
      GIM_Try, /*On fail goto*//*Label 82*/ GIMT_Encode4(1313), // Rule ID 1060 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU16_MM),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1060,
        GIR_Done,
      // Label 82: @1313
      GIM_Try, /*On fail goto*//*Label 83*/ GIMT_Encode4(1340), // Rule ID 1072 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDu_MM),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1072,
        GIR_Done,
      // Label 83: @1340
      GIM_Try, /*On fail goto*//*Label 84*/ GIMT_Encode4(1367), // Rule ID 1818 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        // (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AdduRxRyRz16),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1818,
        GIR_Done,
      // Label 84: @1367
      GIM_Reject,
    // Label 74: @1368
    GIM_Reject,
    // Label 66: @1369
    GIM_Try, /*On fail goto*//*Label 85*/ GIMT_Encode4(1534),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_Try, /*On fail goto*//*Label 86*/ GIMT_Encode4(1447), // Rule ID 2390 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
        GIM_CheckIsSafeToFold, /*NumInsns*/2,
        // (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR64Opnd:{ *:[i64] }:$rt)  =>  (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DLSA),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 2390,
        GIR_EraseRootFromParent_Done,
      // Label 86: @1447
      GIM_Try, /*On fail goto*//*Label 87*/ GIMT_Encode4(1510), // Rule ID 835 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/2,
        // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa))  =>  (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DLSA),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
        GIR_RootToRootCopy, /*OpIdx*/1, // rt
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 835,
        GIR_EraseRootFromParent_Done,
      // Label 87: @1510
      GIM_Try, /*On fail goto*//*Label 88*/ GIMT_Encode4(1533), // Rule ID 202 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
        // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DADDu),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 202,
        GIR_Done,
      // Label 88: @1533
      GIM_Reject,
    // Label 85: @1534
    GIM_Reject,
    // Label 67: @1535
    GIM_Try, /*On fail goto*//*Label 89*/ GIMT_Encode4(1566), // Rule ID 1917 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
      // (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDQ_PH),
      GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(RegState::Dead),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1917,
      GIR_Done,
    // Label 89: @1566
    GIM_Reject,
    // Label 68: @1567
    GIM_Try, /*On fail goto*//*Label 90*/ GIMT_Encode4(1720),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      GIM_Try, /*On fail goto*//*Label 91*/ GIMT_Encode4(1639), // Rule ID 2394 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in)  =>  (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 2394,
        GIR_EraseRootFromParent_Done,
      // Label 91: @1639
      GIM_Try, /*On fail goto*//*Label 92*/ GIMT_Encode4(1696), // Rule ID 843 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt))  =>  (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 843,
        GIR_EraseRootFromParent_Done,
      // Label 92: @1696
      GIM_Try, /*On fail goto*//*Label 93*/ GIMT_Encode4(1719), // Rule ID 510 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_D),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 510,
        GIR_Done,
      // Label 93: @1719
      GIM_Reject,
    // Label 90: @1720
    GIM_Reject,
    // Label 69: @1721
    GIM_Try, /*On fail goto*//*Label 94*/ GIMT_Encode4(1752), // Rule ID 1923 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
      // (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU_QB),
      GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(RegState::Dead),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1923,
      GIR_Done,
    // Label 94: @1752
    GIM_Reject,
    // Label 70: @1753
    GIM_Try, /*On fail goto*//*Label 95*/ GIMT_Encode4(1906),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      GIM_Try, /*On fail goto*//*Label 96*/ GIMT_Encode4(1825), // Rule ID 2393 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in)  =>  (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 2393,
        GIR_EraseRootFromParent_Done,
      // Label 96: @1825
      GIM_Try, /*On fail goto*//*Label 97*/ GIMT_Encode4(1882), // Rule ID 842 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt))  =>  (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 842,
        GIR_EraseRootFromParent_Done,
      // Label 97: @1882
      GIM_Try, /*On fail goto*//*Label 98*/ GIMT_Encode4(1905), // Rule ID 509 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_W),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 509,
        GIR_Done,
      // Label 98: @1905
      GIM_Reject,
    // Label 95: @1906
    GIM_Reject,
    // Label 71: @1907
    GIM_Try, /*On fail goto*//*Label 99*/ GIMT_Encode4(2060),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      GIM_Try, /*On fail goto*//*Label 100*/ GIMT_Encode4(1979), // Rule ID 2392 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in)  =>  (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 2392,
        GIR_EraseRootFromParent_Done,
      // Label 100: @1979
      GIM_Try, /*On fail goto*//*Label 101*/ GIMT_Encode4(2036), // Rule ID 841 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt))  =>  (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 841,
        GIR_EraseRootFromParent_Done,
      // Label 101: @2036
      GIM_Try, /*On fail goto*//*Label 102*/ GIMT_Encode4(2059), // Rule ID 508 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_H),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 508,
        GIR_Done,
      // Label 102: @2059
      GIM_Reject,
    // Label 99: @2060
    GIM_Reject,
    // Label 72: @2061
    GIM_Try, /*On fail goto*//*Label 103*/ GIMT_Encode4(2214),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      GIM_Try, /*On fail goto*//*Label 104*/ GIMT_Encode4(2133), // Rule ID 2391 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in)  =>  (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 2391,
        GIR_EraseRootFromParent_Done,
      // Label 104: @2133
      GIM_Try, /*On fail goto*//*Label 105*/ GIMT_Encode4(2190), // Rule ID 840 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt))  =>  (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 840,
        GIR_EraseRootFromParent_Done,
      // Label 105: @2190
      GIM_Try, /*On fail goto*//*Label 106*/ GIMT_Encode4(2213), // Rule ID 507 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_B),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 507,
        GIR_Done,
      // Label 106: @2213
      GIM_Reject,
    // Label 103: @2214
    GIM_Reject,
    // Label 73: @2215
    GIM_Reject,
    // Label 1: @2216
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 115*/ GIMT_Encode4(2906),
    /*GILLT_s32*//*Label 107*/ GIMT_Encode4(2259),
    /*GILLT_s64*//*Label 108*/ GIMT_Encode4(2436),
    /*GILLT_v2s16*//*Label 109*/ GIMT_Encode4(2470),
    /*GILLT_v2s64*//*Label 110*/ GIMT_Encode4(2502),
    /*GILLT_v4s8*//*Label 111*/ GIMT_Encode4(2595),
    /*GILLT_v4s32*//*Label 112*/ GIMT_Encode4(2627),
    /*GILLT_v8s16*//*Label 113*/ GIMT_Encode4(2720),
    /*GILLT_v16s8*//*Label 114*/ GIMT_Encode4(2813),
    // Label 107: @2259
    GIM_Try, /*On fail goto*//*Label 116*/ GIMT_Encode4(2435),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 117*/ GIMT_Encode4(2299), // Rule ID 1817 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        // (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r)  =>  (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NegRxRy16),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
        GIR_RootToRootCopy, /*OpIdx*/2, // r
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1817,
        GIR_EraseRootFromParent_Done,
      // Label 117: @2299
      GIM_Try, /*On fail goto*//*Label 118*/ GIMT_Encode4(2326), // Rule ID 1210 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU16_MMR6),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1210,
        GIR_Done,
      // Label 118: @2326
      GIM_Try, /*On fail goto*//*Label 119*/ GIMT_Encode4(2353), // Rule ID 47 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBu),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 47,
        GIR_Done,
      // Label 119: @2353
      GIM_Try, /*On fail goto*//*Label 120*/ GIMT_Encode4(2380), // Rule ID 1064 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU16_MM),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1064,
        GIR_Done,
      // Label 120: @2380
      GIM_Try, /*On fail goto*//*Label 121*/ GIMT_Encode4(2407), // Rule ID 1073 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBu_MM),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1073,
        GIR_Done,
      // Label 121: @2407
      GIM_Try, /*On fail goto*//*Label 122*/ GIMT_Encode4(2434), // Rule ID 1822 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        // (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SubuRxRyRz16),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1822,
        GIR_Done,
      // Label 122: @2434
      GIM_Reject,
    // Label 116: @2435
    GIM_Reject,
    // Label 108: @2436
    GIM_Try, /*On fail goto*//*Label 123*/ GIMT_Encode4(2469), // Rule ID 203 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      // (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSUBu),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 203,
      GIR_Done,
    // Label 123: @2469
    GIM_Reject,
    // Label 109: @2470
    GIM_Try, /*On fail goto*//*Label 124*/ GIMT_Encode4(2501), // Rule ID 1919 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
      // (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBQ_PH),
      GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(RegState::Dead),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1919,
      GIR_Done,
    // Label 124: @2501
    GIM_Reject,
    // Label 110: @2502
    GIM_Try, /*On fail goto*//*Label 125*/ GIMT_Encode4(2594),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      GIM_Try, /*On fail goto*//*Label 126*/ GIMT_Encode4(2574), // Rule ID 899 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt))  =>  (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 899,
        GIR_EraseRootFromParent_Done,
      // Label 126: @2574
      GIM_Try, /*On fail goto*//*Label 127*/ GIMT_Encode4(2593), // Rule ID 1028 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_D),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1028,
        GIR_Done,
      // Label 127: @2593
      GIM_Reject,
    // Label 125: @2594
    GIM_Reject,
    // Label 111: @2595
    GIM_Try, /*On fail goto*//*Label 128*/ GIMT_Encode4(2626), // Rule ID 1925 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
      // (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU_QB),
      GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(RegState::Dead),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1925,
      GIR_Done,
    // Label 128: @2626
    GIM_Reject,
    // Label 112: @2627
    GIM_Try, /*On fail goto*//*Label 129*/ GIMT_Encode4(2719),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      GIM_Try, /*On fail goto*//*Label 130*/ GIMT_Encode4(2699), // Rule ID 898 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt))  =>  (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 898,
        GIR_EraseRootFromParent_Done,
      // Label 130: @2699
      GIM_Try, /*On fail goto*//*Label 131*/ GIMT_Encode4(2718), // Rule ID 1027 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_W),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1027,
        GIR_Done,
      // Label 131: @2718
      GIM_Reject,
    // Label 129: @2719
    GIM_Reject,
    // Label 113: @2720
    GIM_Try, /*On fail goto*//*Label 132*/ GIMT_Encode4(2812),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      GIM_Try, /*On fail goto*//*Label 133*/ GIMT_Encode4(2792), // Rule ID 897 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt))  =>  (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 897,
        GIR_EraseRootFromParent_Done,
      // Label 133: @2792
      GIM_Try, /*On fail goto*//*Label 134*/ GIMT_Encode4(2811), // Rule ID 1026 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_H),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1026,
        GIR_Done,
      // Label 134: @2811
      GIM_Reject,
    // Label 132: @2812
    GIM_Reject,
    // Label 114: @2813
    GIM_Try, /*On fail goto*//*Label 135*/ GIMT_Encode4(2905),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      GIM_Try, /*On fail goto*//*Label 136*/ GIMT_Encode4(2885), // Rule ID 896 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt))  =>  (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 896,
        GIR_EraseRootFromParent_Done,
      // Label 136: @2885
      GIM_Try, /*On fail goto*//*Label 137*/ GIMT_Encode4(2904), // Rule ID 1025 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_B),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1025,
        GIR_Done,
      // Label 137: @2904
      GIM_Reject,
    // Label 135: @2905
    GIM_Reject,
    // Label 115: @2906
    GIM_Reject,
    // Label 2: @2907
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 145*/ GIMT_Encode4(3387),
    /*GILLT_s32*//*Label 138*/ GIMT_Encode4(2950),
    /*GILLT_s64*//*Label 139*/ GIMT_Encode4(3134),
    /*GILLT_v2s16*//*Label 140*/ GIMT_Encode4(3219),
    /*GILLT_v2s64*//*Label 141*/ GIMT_Encode4(3251), GIMT_Encode4(0),
    /*GILLT_v4s32*//*Label 142*/ GIMT_Encode4(3285),
    /*GILLT_v8s16*//*Label 143*/ GIMT_Encode4(3319),
    /*GILLT_v16s8*//*Label 144*/ GIMT_Encode4(3353),
    // Label 138: @2950
    GIM_Try, /*On fail goto*//*Label 146*/ GIMT_Encode4(3133),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 147*/ GIMT_Encode4(3000), // Rule ID 48 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(RegState::Dead),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(RegState::Dead),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 48,
        GIR_Done,
      // Label 147: @3000
      GIM_Try, /*On fail goto*//*Label 148*/ GIMT_Encode4(3027), // Rule ID 332 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_R6),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 332,
        GIR_Done,
      // Label 148: @3027
      GIM_Try, /*On fail goto*//*Label 149*/ GIMT_Encode4(3066), // Rule ID 1074 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_MM),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(RegState::Dead),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(RegState::Dead),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1074,
        GIR_Done,
      // Label 149: @3066
      GIM_Try, /*On fail goto*//*Label 150*/ GIMT_Encode4(3093), // Rule ID 1179 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_MMR6),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1179,
        GIR_Done,
      // Label 150: @3093
      GIM_Try, /*On fail goto*//*Label 151*/ GIMT_Encode4(3132), // Rule ID 1820 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        // (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MultRxRyRz16),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(RegState::Dead),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(RegState::Dead),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1820,
        GIR_Done,
      // Label 151: @3132
      GIM_Reject,
    // Label 146: @3133
    GIM_Reject,
    // Label 139: @3134
    GIM_Try, /*On fail goto*//*Label 152*/ GIMT_Encode4(3218),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_Try, /*On fail goto*//*Label 153*/ GIMT_Encode4(3202), // Rule ID 274 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
        // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUL),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(RegState::Dead),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(RegState::Dead),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P0), GIMT_Encode2(RegState::Dead),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P1), GIMT_Encode2(RegState::Dead),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P2), GIMT_Encode2(RegState::Dead),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 274,
        GIR_Done,
      // Label 153: @3202
      GIM_Try, /*On fail goto*//*Label 154*/ GIMT_Encode4(3217), // Rule ID 347 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
        // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUL_R6),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 347,
        GIR_Done,
      // Label 154: @3217
      GIM_Reject,
    // Label 152: @3218
    GIM_Reject,
    // Label 140: @3219
    GIM_Try, /*On fail goto*//*Label 155*/ GIMT_Encode4(3250), // Rule ID 1921 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
      // (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_PH),
      GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag21), GIMT_Encode2(RegState::Dead),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1921,
      GIR_Done,
    // Label 155: @3250
    GIM_Reject,
    // Label 141: @3251
    GIM_Try, /*On fail goto*//*Label 156*/ GIMT_Encode4(3284), // Rule ID 907 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_D),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 907,
      GIR_Done,
    // Label 156: @3284
    GIM_Reject,
    // Label 142: @3285
    GIM_Try, /*On fail goto*//*Label 157*/ GIMT_Encode4(3318), // Rule ID 906 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_W),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 906,
      GIR_Done,
    // Label 157: @3318
    GIM_Reject,
    // Label 143: @3319
    GIM_Try, /*On fail goto*//*Label 158*/ GIMT_Encode4(3352), // Rule ID 905 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_H),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 905,
      GIR_Done,
    // Label 158: @3352
    GIM_Reject,
    // Label 144: @3353
    GIM_Try, /*On fail goto*//*Label 159*/ GIMT_Encode4(3386), // Rule ID 904 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      // (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_B),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 904,
      GIR_Done,
    // Label 159: @3386
    GIM_Reject,
    // Label 145: @3387
    GIM_Reject,
    // Label 3: @3388
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 166*/ GIMT_Encode4(3656),
    /*GILLT_s32*//*Label 160*/ GIMT_Encode4(3431),
    /*GILLT_s64*//*Label 161*/ GIMT_Encode4(3486), GIMT_Encode4(0),
    /*GILLT_v2s64*//*Label 162*/ GIMT_Encode4(3520), GIMT_Encode4(0),
    /*GILLT_v4s32*//*Label 163*/ GIMT_Encode4(3554),
    /*GILLT_v8s16*//*Label 164*/ GIMT_Encode4(3588),
    /*GILLT_v16s8*//*Label 165*/ GIMT_Encode4(3622),
    // Label 160: @3431
    GIM_Try, /*On fail goto*//*Label 167*/ GIMT_Encode4(3485),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_Try, /*On fail goto*//*Label 168*/ GIMT_Encode4(3469), // Rule ID 326 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
        // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 326,
        GIR_Done,
      // Label 168: @3469
      GIM_Try, /*On fail goto*//*Label 169*/ GIMT_Encode4(3484), // Rule ID 1172 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
        // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_MMR6),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1172,
        GIR_Done,
      // Label 169: @3484
      GIM_Reject,
    // Label 167: @3485
    GIM_Reject,
    // Label 161: @3486
    GIM_Try, /*On fail goto*//*Label 170*/ GIMT_Encode4(3519), // Rule ID 341 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      // (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DDIV),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 341,
      GIR_Done,
    // Label 170: @3519
    GIM_Reject,
    // Label 162: @3520
    GIM_Try, /*On fail goto*//*Label 171*/ GIMT_Encode4(3553), // Rule ID 647 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_D),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 647,
      GIR_Done,
    // Label 171: @3553
    GIM_Reject,
    // Label 163: @3554
    GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(3587), // Rule ID 646 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_W),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 646,
      GIR_Done,
    // Label 172: @3587
    GIM_Reject,
    // Label 164: @3588
    GIM_Try, /*On fail goto*//*Label 173*/ GIMT_Encode4(3621), // Rule ID 645 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_H),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 645,
      GIR_Done,
    // Label 173: @3621
    GIM_Reject,
    // Label 165: @3622
    GIM_Try, /*On fail goto*//*Label 174*/ GIMT_Encode4(3655), // Rule ID 644 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      // (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_B),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 644,
      GIR_Done,
    // Label 174: @3655
    GIM_Reject,
    // Label 166: @3656
    GIM_Reject,
    // Label 4: @3657
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 181*/ GIMT_Encode4(3925),
    /*GILLT_s32*//*Label 175*/ GIMT_Encode4(3700),
    /*GILLT_s64*//*Label 176*/ GIMT_Encode4(3755), GIMT_Encode4(0),
    /*GILLT_v2s64*//*Label 177*/ GIMT_Encode4(3789), GIMT_Encode4(0),
    /*GILLT_v4s32*//*Label 178*/ GIMT_Encode4(3823),
    /*GILLT_v8s16*//*Label 179*/ GIMT_Encode4(3857),
    /*GILLT_v16s8*//*Label 180*/ GIMT_Encode4(3891),
    // Label 175: @3700
    GIM_Try, /*On fail goto*//*Label 182*/ GIMT_Encode4(3754),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_Try, /*On fail goto*//*Label 183*/ GIMT_Encode4(3738), // Rule ID 327 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
        // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIVU),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 327,
        GIR_Done,
      // Label 183: @3738
      GIM_Try, /*On fail goto*//*Label 184*/ GIMT_Encode4(3753), // Rule ID 1173 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
        // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIVU_MMR6),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1173,
        GIR_Done,
      // Label 184: @3753
      GIM_Reject,
    // Label 182: @3754
    GIM_Reject,
    // Label 176: @3755
    GIM_Try, /*On fail goto*//*Label 185*/ GIMT_Encode4(3788), // Rule ID 342 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      // (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DDIVU),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 342,
      GIR_Done,
    // Label 185: @3788
    GIM_Reject,
    // Label 177: @3789
    GIM_Try, /*On fail goto*//*Label 186*/ GIMT_Encode4(3822), // Rule ID 651 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_D),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 651,
      GIR_Done,
    // Label 186: @3822
    GIM_Reject,
    // Label 178: @3823
    GIM_Try, /*On fail goto*//*Label 187*/ GIMT_Encode4(3856), // Rule ID 650 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_W),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 650,
      GIR_Done,
    // Label 187: @3856
    GIM_Reject,
    // Label 179: @3857
    GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(3890), // Rule ID 649 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_H),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 649,
      GIR_Done,
    // Label 188: @3890
    GIM_Reject,
    // Label 180: @3891
    GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(3924), // Rule ID 648 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      // (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_B),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 648,
      GIR_Done,
    // Label 189: @3924
    GIM_Reject,
    // Label 181: @3925
    GIM_Reject,
    // Label 5: @3926
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 196*/ GIMT_Encode4(4194),
    /*GILLT_s32*//*Label 190*/ GIMT_Encode4(3969),
    /*GILLT_s64*//*Label 191*/ GIMT_Encode4(4024), GIMT_Encode4(0),
    /*GILLT_v2s64*//*Label 192*/ GIMT_Encode4(4058), GIMT_Encode4(0),
    /*GILLT_v4s32*//*Label 193*/ GIMT_Encode4(4092),
    /*GILLT_v8s16*//*Label 194*/ GIMT_Encode4(4126),
    /*GILLT_v16s8*//*Label 195*/ GIMT_Encode4(4160),
    // Label 190: @3969
    GIM_Try, /*On fail goto*//*Label 197*/ GIMT_Encode4(4023),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(4007), // Rule ID 328 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
        // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 328,
        GIR_Done,
      // Label 198: @4007
      GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(4022), // Rule ID 1177 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
        // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_MMR6),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1177,
        GIR_Done,
      // Label 199: @4022
      GIM_Reject,
    // Label 197: @4023
    GIM_Reject,
    // Label 191: @4024
    GIM_Try, /*On fail goto*//*Label 200*/ GIMT_Encode4(4057), // Rule ID 343 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      // (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMOD),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 343,
      GIR_Done,
    // Label 200: @4057
    GIM_Reject,
    // Label 192: @4058
    GIM_Try, /*On fail goto*//*Label 201*/ GIMT_Encode4(4091), // Rule ID 887 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_D),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 887,
      GIR_Done,
    // Label 201: @4091
    GIM_Reject,
    // Label 193: @4092
    GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(4125), // Rule ID 886 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_W),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 886,
      GIR_Done,
    // Label 202: @4125
    GIM_Reject,
    // Label 194: @4126
    GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(4159), // Rule ID 885 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_H),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 885,
      GIR_Done,
    // Label 203: @4159
    GIM_Reject,
    // Label 195: @4160
    GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(4193), // Rule ID 884 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      // (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_B),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 884,
      GIR_Done,
    // Label 204: @4193
    GIM_Reject,
    // Label 196: @4194
    GIM_Reject,
    // Label 6: @4195
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 211*/ GIMT_Encode4(4463),
    /*GILLT_s32*//*Label 205*/ GIMT_Encode4(4238),
    /*GILLT_s64*//*Label 206*/ GIMT_Encode4(4293), GIMT_Encode4(0),
    /*GILLT_v2s64*//*Label 207*/ GIMT_Encode4(4327), GIMT_Encode4(0),
    /*GILLT_v4s32*//*Label 208*/ GIMT_Encode4(4361),
    /*GILLT_v8s16*//*Label 209*/ GIMT_Encode4(4395),
    /*GILLT_v16s8*//*Label 210*/ GIMT_Encode4(4429),
    // Label 205: @4238
    GIM_Try, /*On fail goto*//*Label 212*/ GIMT_Encode4(4292),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_Try, /*On fail goto*//*Label 213*/ GIMT_Encode4(4276), // Rule ID 329 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
        // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MODU),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 329,
        GIR_Done,
      // Label 213: @4276
      GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(4291), // Rule ID 1178 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
        // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MODU_MMR6),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1178,
        GIR_Done,
      // Label 214: @4291
      GIM_Reject,
    // Label 212: @4292
    GIM_Reject,
    // Label 206: @4293
    GIM_Try, /*On fail goto*//*Label 215*/ GIMT_Encode4(4326), // Rule ID 344 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      // (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMODU),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 344,
      GIR_Done,
    // Label 215: @4326
    GIM_Reject,
    // Label 207: @4327
    GIM_Try, /*On fail goto*//*Label 216*/ GIMT_Encode4(4360), // Rule ID 891 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_D),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 891,
      GIR_Done,
    // Label 216: @4360
    GIM_Reject,
    // Label 208: @4361
    GIM_Try, /*On fail goto*//*Label 217*/ GIMT_Encode4(4394), // Rule ID 890 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_W),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 890,
      GIR_Done,
    // Label 217: @4394
    GIM_Reject,
    // Label 209: @4395
    GIM_Try, /*On fail goto*//*Label 218*/ GIMT_Encode4(4428), // Rule ID 889 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_H),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 889,
      GIR_Done,
    // Label 218: @4428
    GIM_Reject,
    // Label 210: @4429
    GIM_Try, /*On fail goto*//*Label 219*/ GIMT_Encode4(4462), // Rule ID 888 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      // (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_B),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 888,
      GIR_Done,
    // Label 219: @4462
    GIM_Reject,
    // Label 211: @4463
    GIM_Reject,
    // Label 7: @4464
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 226*/ GIMT_Encode4(5019),
    /*GILLT_s32*//*Label 220*/ GIMT_Encode4(4507),
    /*GILLT_s64*//*Label 221*/ GIMT_Encode4(4781), GIMT_Encode4(0),
    /*GILLT_v2s64*//*Label 222*/ GIMT_Encode4(4883), GIMT_Encode4(0),
    /*GILLT_v4s32*//*Label 223*/ GIMT_Encode4(4917),
    /*GILLT_v8s16*//*Label 224*/ GIMT_Encode4(4951),
    /*GILLT_v16s8*//*Label 225*/ GIMT_Encode4(4985),
    // Label 220: @4507
    GIM_Try, /*On fail goto*//*Label 227*/ GIMT_Encode4(4780),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 228*/ GIMT_Encode4(4560), // Rule ID 41 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16)  =>  (ANDi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDi),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/1, // rs
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 41,
        GIR_EraseRootFromParent_Done,
      // Label 228: @4560
      GIM_Try, /*On fail goto*//*Label 229*/ GIMT_Encode4(4602), // Rule ID 2161 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExtAndi16),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)  =>  (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDI16_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/1, // src
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 2161,
        GIR_EraseRootFromParent_Done,
      // Label 229: @4602
      GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(4644), // Rule ID 2320 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExtAndi16),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)  =>  (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDI16_MMR6),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/1, // src
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 2320,
        GIR_EraseRootFromParent_Done,
      // Label 230: @4644
      GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(4671), // Rule ID 51 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 51,
        GIR_Done,
      // Label 231: @4671
      GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(4698), // Rule ID 1061 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        // (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND16_MM),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1061,
        GIR_Done,
      // Label 232: @4698
      GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(4725), // Rule ID 1077 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_MM),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1077,
        GIR_Done,
      // Label 233: @4725
      GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(4752), // Rule ID 1170 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_MMR6),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1170,
        GIR_Done,
      // Label 234: @4752
      GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(4779), // Rule ID 1819 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        // (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AndRxRxRy16),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1819,
        GIR_Done,
      // Label 235: @4779
      GIM_Reject,
    // Label 227: @4780
    GIM_Reject,
    // Label 221: @4781
    GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(4882),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(4858), // Rule ID 269 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] })  =>  (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BADDu),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 269,
        GIR_EraseRootFromParent_Done,
      // Label 237: @4858
      GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(4881), // Rule ID 206 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
        // (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND64),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 206,
        GIR_Done,
      // Label 238: @4881
      GIM_Reject,
    // Label 236: @4882
    GIM_Reject,
    // Label 222: @4883
    GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(4916), // Rule ID 518 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_D_PSEUDO),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 518,
      GIR_Done,
    // Label 239: @4916
    GIM_Reject,
    // Label 223: @4917
    GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(4950), // Rule ID 517 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_W_PSEUDO),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 517,
      GIR_Done,
    // Label 240: @4950
    GIM_Reject,
    // Label 224: @4951
    GIM_Try, /*On fail goto*//*Label 241*/ GIMT_Encode4(4984), // Rule ID 516 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_H_PSEUDO),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 516,
      GIR_Done,
    // Label 241: @4984
    GIM_Reject,
    // Label 225: @4985
    GIM_Try, /*On fail goto*//*Label 242*/ GIMT_Encode4(5018), // Rule ID 515 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      // (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 515,
      GIR_Done,
    // Label 242: @5018
    GIM_Reject,
    // Label 226: @5019
    GIM_Reject,
    // Label 8: @5020
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 249*/ GIMT_Encode4(5423),
    /*GILLT_s32*//*Label 243*/ GIMT_Encode4(5063),
    /*GILLT_s64*//*Label 244*/ GIMT_Encode4(5253), GIMT_Encode4(0),
    /*GILLT_v2s64*//*Label 245*/ GIMT_Encode4(5287), GIMT_Encode4(0),
    /*GILLT_v4s32*//*Label 246*/ GIMT_Encode4(5321),
    /*GILLT_v8s16*//*Label 247*/ GIMT_Encode4(5355),
    /*GILLT_v16s8*//*Label 248*/ GIMT_Encode4(5389),
    // Label 243: @5063
    GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(5252),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 251*/ GIMT_Encode4(5116), // Rule ID 42 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16)  =>  (ORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ORi),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/1, // rs
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 42,
        GIR_EraseRootFromParent_Done,
      // Label 251: @5116
      GIM_Try, /*On fail goto*//*Label 252*/ GIMT_Encode4(5143), // Rule ID 52 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 52,
        GIR_Done,
      // Label 252: @5143
      GIM_Try, /*On fail goto*//*Label 253*/ GIMT_Encode4(5170), // Rule ID 1063 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        // (or:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (OR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR16_MM),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1063,
        GIR_Done,
      // Label 253: @5170
      GIM_Try, /*On fail goto*//*Label 254*/ GIMT_Encode4(5197), // Rule ID 1078 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_MM),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1078,
        GIR_Done,
      // Label 254: @5197
      GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(5224), // Rule ID 1183 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_MMR6),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1183,
        GIR_Done,
      // Label 255: @5224
      GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(5251), // Rule ID 1821 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        // (or:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (OrRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OrRxRxRy16),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1821,
        GIR_Done,
      // Label 256: @5251
      GIM_Reject,
    // Label 250: @5252
    GIM_Reject,
    // Label 244: @5253
    GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(5286), // Rule ID 207 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      // (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (OR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR64),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 207,
      GIR_Done,
    // Label 257: @5286
    GIM_Reject,
    // Label 245: @5287
    GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(5320), // Rule ID 924 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (OR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_D_PSEUDO),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 924,
      GIR_Done,
    // Label 258: @5320
    GIM_Reject,
    // Label 246: @5321
    GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(5354), // Rule ID 923 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (OR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_W_PSEUDO),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 923,
      GIR_Done,
    // Label 259: @5354
    GIM_Reject,
    // Label 247: @5355
    GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(5388), // Rule ID 922 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (OR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_H_PSEUDO),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 922,
      GIR_Done,
    // Label 260: @5388
    GIM_Reject,
    // Label 248: @5389
    GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(5422), // Rule ID 921 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      // (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (OR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 921,
      GIR_Done,
    // Label 261: @5422
    GIM_Reject,
    // Label 249: @5423
    GIM_Reject,
    // Label 9: @5424
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 268*/ GIMT_Encode4(6315),
    /*GILLT_s32*//*Label 262*/ GIMT_Encode4(5467),
    /*GILLT_s64*//*Label 263*/ GIMT_Encode4(6084), GIMT_Encode4(0),
    /*GILLT_v2s64*//*Label 264*/ GIMT_Encode4(6179), GIMT_Encode4(0),
    /*GILLT_v4s32*//*Label 265*/ GIMT_Encode4(6213),
    /*GILLT_v8s16*//*Label 266*/ GIMT_Encode4(6247),
    /*GILLT_v16s8*//*Label 267*/ GIMT_Encode4(6281),
    // Label 262: @5467
    GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(6083),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(5537), // Rule ID 54 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 54,
        GIR_EraseRootFromParent_Done,
      // Label 270: @5537
      GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(5596), // Rule ID 1080 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1080,
        GIR_EraseRootFromParent_Done,
      // Label 271: @5596
      GIM_Try, /*On fail goto*//*Label 272*/ GIMT_Encode4(5655), // Rule ID 1182 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1182,
        GIR_EraseRootFromParent_Done,
      // Label 272: @5655
      GIM_Try, /*On fail goto*//*Label 273*/ GIMT_Encode4(5684), // Rule ID 1209 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })  =>  (NOT16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MMR6),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/1, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1209,
        GIR_EraseRootFromParent_Done,
      // Label 273: @5684
      GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(5713), // Rule ID 1062 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })  =>  (NOT16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/1, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1062,
        GIR_EraseRootFromParent_Done,
      // Label 274: @5713
      GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(5748), // Rule ID 1397 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/1, // in
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1397,
        GIR_EraseRootFromParent_Done,
      // Label 275: @5748
      GIM_Try, /*On fail goto*//*Label 276*/ GIMT_Encode4(5777), // Rule ID 1816 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, -1:{ *:[i32] })  =>  (NotRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NotRxRy16),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
        GIR_RootToRootCopy, /*OpIdx*/1, // r
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1816,
        GIR_EraseRootFromParent_Done,
      // Label 276: @5777
      GIM_Try, /*On fail goto*//*Label 277*/ GIMT_Encode4(5806), // Rule ID 2156 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOT16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/1, // in
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 2156,
        GIR_EraseRootFromParent_Done,
      // Label 277: @5806
      GIM_Try, /*On fail goto*//*Label 278*/ GIMT_Encode4(5841), // Rule ID 2157 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/1, // in
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 2157,
        GIR_EraseRootFromParent_Done,
      // Label 278: @5841
      GIM_Try, /*On fail goto*//*Label 279*/ GIMT_Encode4(5870), // Rule ID 2323 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOT16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MMR6),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/1, // in
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 2323,
        GIR_EraseRootFromParent_Done,
      // Label 279: @5870
      GIM_Try, /*On fail goto*//*Label 280*/ GIMT_Encode4(5905), // Rule ID 2324 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/1, // in
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 2324,
        GIR_EraseRootFromParent_Done,
      // Label 280: @5905
      GIM_Try, /*On fail goto*//*Label 281*/ GIMT_Encode4(5947), // Rule ID 43 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16)  =>  (XORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/1, // rs
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 43,
        GIR_EraseRootFromParent_Done,
      // Label 281: @5947
      GIM_Try, /*On fail goto*//*Label 282*/ GIMT_Encode4(5974), // Rule ID 53 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 53,
        GIR_Done,
      // Label 282: @5974
      GIM_Try, /*On fail goto*//*Label 283*/ GIMT_Encode4(6001), // Rule ID 1065 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
        // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (XOR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR16_MM),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1065,
        GIR_Done,
      // Label 283: @6001
      GIM_Try, /*On fail goto*//*Label 284*/ GIMT_Encode4(6028), // Rule ID 1079 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1079,
        GIR_Done,
      // Label 284: @6028
      GIM_Try, /*On fail goto*//*Label 285*/ GIMT_Encode4(6055), // Rule ID 1186 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_MMR6),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1186,
        GIR_Done,
      // Label 285: @6055
      GIM_Try, /*On fail goto*//*Label 286*/ GIMT_Encode4(6082), // Rule ID 1823 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
        // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1823,
        GIR_Done,
      // Label 286: @6082
      GIM_Reject,
    // Label 269: @6083
    GIM_Reject,
    // Label 263: @6084
    GIM_Try, /*On fail goto*//*Label 287*/ GIMT_Encode4(6178),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_Try, /*On fail goto*//*Label 288*/ GIMT_Encode4(6154), // Rule ID 209 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), -1:{ *:[i64] })  =>  (NOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR64),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 209,
        GIR_EraseRootFromParent_Done,
      // Label 288: @6154
      GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(6177), // Rule ID 208 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
        // (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (XOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR64),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 208,
        GIR_Done,
      // Label 289: @6177
      GIM_Reject,
    // Label 287: @6178
    GIM_Reject,
    // Label 264: @6179
    GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(6212), // Rule ID 1040 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (XOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_D_PSEUDO),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1040,
      GIR_Done,
    // Label 290: @6212
    GIM_Reject,
    // Label 265: @6213
    GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(6246), // Rule ID 1039 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (XOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_W_PSEUDO),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1039,
      GIR_Done,
    // Label 291: @6246
    GIM_Reject,
    // Label 266: @6247
    GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(6280), // Rule ID 1038 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (XOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_H_PSEUDO),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1038,
      GIR_Done,
    // Label 292: @6280
    GIM_Reject,
    // Label 267: @6281
    GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(6314), // Rule ID 1037 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      // (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1037,
      GIR_Done,
    // Label 293: @6314
    GIM_Reject,
    // Label 268: @6315
    GIM_Reject,
    // Label 10: @6316
    GIM_Try, /*On fail goto*//*Label 294*/ GIMT_Encode4(6388),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
      GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 295*/ GIMT_Encode4(6360), // Rule ID 180 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotSoftFloat_NotFP64bit_NotInMips16Mode),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)  =>  (BuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BuildPairF64),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 180,
        GIR_Done,
      // Label 295: @6360
      GIM_Try, /*On fail goto*//*Label 296*/ GIMT_Encode4(6387), // Rule ID 181 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit_IsNotSoftFloat_NotInMips16Mode),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)  =>  (BuildPairF64_64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BuildPairF64_64),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 181,
        GIR_Done,
      // Label 296: @6387
      GIM_Reject,
    // Label 294: @6388
    GIM_Reject,
    // Label 11: @6389
    GIM_Try, /*On fail goto*//*Label 297*/ GIMT_Encode4(6460),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
      GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(6433), // Rule ID 719 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
        // MIs[0] rs
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
        // (build_vector:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rs)  =>  (FILL_D:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/1, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 719,
        GIR_EraseRootFromParent_Done,
      // Label 298: @6433
      GIM_Try, /*On fail goto*//*Label 299*/ GIMT_Encode4(6459), // Rule ID 721 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
        // MIs[0] fs
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
        // (build_vector:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs, FGR64:{ *:[f64] }:$fs)  =>  (FILL_FD_PSEUDO:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_FD_PSEUDO),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/1, // fs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 721,
        GIR_EraseRootFromParent_Done,
      // Label 299: @6459
      GIM_Reject,
    // Label 297: @6460
    GIM_Try, /*On fail goto*//*Label 300*/ GIMT_Encode4(6551),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
      GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      GIM_Try, /*On fail goto*//*Label 301*/ GIMT_Encode4(6514), // Rule ID 718 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // MIs[0] rs
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
        // MIs[0] rs
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
        // MIs[0] rs
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
        // (build_vector:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs)  =>  (FILL_W:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/1, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 718,
        GIR_EraseRootFromParent_Done,
      // Label 301: @6514
      GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(6550), // Rule ID 720 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
        // MIs[0] fs
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
        // MIs[0] fs
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
        // MIs[0] fs
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
        // (build_vector:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs)  =>  (FILL_FW_PSEUDO:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_FW_PSEUDO),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/1, // fs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 720,
        GIR_EraseRootFromParent_Done,
      // Label 302: @6550
      GIM_Reject,
    // Label 300: @6551
    GIM_Try, /*On fail goto*//*Label 303*/ GIMT_Encode4(6620), // Rule ID 717 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/9,
      GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1,
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1,
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1,
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1,
      // (build_vector:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs)  =>  (FILL_H:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_H),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
      GIR_RootToRootCopy, /*OpIdx*/1, // rs
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 717,
      GIR_EraseRootFromParent_Done,
    // Label 303: @6620
    GIM_Try, /*On fail goto*//*Label 304*/ GIMT_Encode4(6729), // Rule ID 716 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/17,
      GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1,
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1,
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1,
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1,
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/9, /*OtherMI*/0, /*OtherOpIdx*/1,
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/10, /*OtherMI*/0, /*OtherOpIdx*/1,
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/11, /*OtherMI*/0, /*OtherOpIdx*/1,
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/12, /*OtherMI*/0, /*OtherOpIdx*/1,
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/13, /*OtherMI*/0, /*OtherOpIdx*/1,
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/14, /*OtherMI*/0, /*OtherOpIdx*/1,
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/15, /*OtherMI*/0, /*OtherOpIdx*/1,
      // MIs[0] rs
      GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/16, /*OtherMI*/0, /*OtherOpIdx*/1,
      // (build_vector:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs)  =>  (FILL_B:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_B),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
      GIR_RootToRootCopy, /*OpIdx*/1, // rs
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 716,
      GIR_EraseRootFromParent_Done,
    // Label 304: @6729
    GIM_Reject,
    // Label 12: @6730
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 313*/ GIMT_Encode4(10920),
    /*GILLT_s32*//*Label 305*/ GIMT_Encode4(6773),
    /*GILLT_s64*//*Label 306*/ GIMT_Encode4(7050),
    /*GILLT_v2s16*//*Label 307*/ GIMT_Encode4(7106),
    /*GILLT_v2s64*//*Label 308*/ GIMT_Encode4(7166),
    /*GILLT_v4s8*//*Label 309*/ GIMT_Encode4(8265),
    /*GILLT_v4s32*//*Label 310*/ GIMT_Encode4(8325),
    /*GILLT_v8s16*//*Label 311*/ GIMT_Encode4(9364),
    /*GILLT_v16s8*//*Label 312*/ GIMT_Encode4(10259),
    // Label 305: @6773
    GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(6799), // Rule ID 135 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
      // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 135,
      GIR_Done,
    // Label 314: @6799
    GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(6825), // Rule ID 136 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 136,
      GIR_Done,
    // Label 315: @6825
    GIM_Try, /*On fail goto*//*Label 316*/ GIMT_Encode4(6851), // Rule ID 1160 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
      // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1_MM:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1_MM),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1160,
      GIR_Done,
    // Label 316: @6851
    GIM_Try, /*On fail goto*//*Label 317*/ GIMT_Encode4(6877), // Rule ID 1161 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1_MM:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1_MM),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1161,
      GIR_Done,
    // Label 317: @6877
    GIM_Try, /*On fail goto*//*Label 318*/ GIMT_Encode4(6903), // Rule ID 1175 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1_MMR6:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1_MMR6),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1175,
      GIR_Done,
    // Label 318: @6903
    GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(6929), // Rule ID 1176 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
      // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1_MMR6),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1176,
      GIR_Done,
    // Label 319: @6929
    GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(6959), // Rule ID 1904 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
      // (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$src, GPR32:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR32RegClassID),
      // GIR_Coverage, 1904,
      GIR_Done,
    // Label 320: @6959
    GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(6989), // Rule ID 1905 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
      // (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$src, GPR32:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR32RegClassID),
      // GIR_Coverage, 1905,
      GIR_Done,
    // Label 321: @6989
    GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(7019), // Rule ID 1908 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
      // (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v2i16] }:$src, FGR32:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
      // GIR_Coverage, 1908,
      GIR_Done,
    // Label 322: @7019
    GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(7049), // Rule ID 1909 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
      GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
      // (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4i8] }:$src, FGR32:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
      // GIR_Coverage, 1909,
      GIR_Done,
    // Label 323: @7049
    GIM_Reject,
    // Label 306: @7050
    GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(7105),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 325*/ GIMT_Encode4(7081), // Rule ID 137 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
        // (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMTC1),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 137,
        GIR_Done,
      // Label 325: @7081
      GIM_Try, /*On fail goto*//*Label 326*/ GIMT_Encode4(7104), // Rule ID 138 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
        // (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMFC1),
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 138,
        GIR_Done,
      // Label 326: @7104
      GIM_Reject,
    // Label 324: @7105
    GIM_Reject,
    // Label 307: @7106
    GIM_Try, /*On fail goto*//*Label 327*/ GIMT_Encode4(7165),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
      GIM_Try, /*On fail goto*//*Label 328*/ GIMT_Encode4(7141), // Rule ID 1906 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
        // GIR_Coverage, 1906,
        GIR_Done,
      // Label 328: @7141
      GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(7164), // Rule ID 1910 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
        // (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
        // GIR_Coverage, 1910,
        GIR_Done,
      // Label 329: @7164
      GIM_Reject,
    // Label 327: @7165
    GIM_Reject,
    // Label 308: @7166
    GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(7192), // Rule ID 1991 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src, MSA128D:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 1991,
      GIR_Done,
    // Label 330: @7192
    GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(7218), // Rule ID 1994 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src, MSA128D:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 1994,
      GIR_Done,
    // Label 331: @7218
    GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(7244), // Rule ID 2011 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 2011,
      GIR_Done,
    // Label 332: @7244
    GIM_Try, /*On fail goto*//*Label 333*/ GIMT_Encode4(7270), // Rule ID 2012 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 2012,
      GIR_Done,
    // Label 333: @7270
    GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(7296), // Rule ID 2013 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 2013,
      GIR_Done,
    // Label 334: @7296
    GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(7322), // Rule ID 2014 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 2014,
      GIR_Done,
    // Label 335: @7322
    GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(7348), // Rule ID 2015 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 2015,
      GIR_Done,
    // Label 336: @7348
    GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(7374), // Rule ID 2021 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 2021,
      GIR_Done,
    // Label 337: @7374
    GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(7400), // Rule ID 2022 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 2022,
      GIR_Done,
    // Label 338: @7400
    GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(7426), // Rule ID 2023 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 2023,
      GIR_Done,
    // Label 339: @7426
    GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(7452), // Rule ID 2024 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 2024,
      GIR_Done,
    // Label 340: @7452
    GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(7478), // Rule ID 2025 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 2025,
      GIR_Done,
    // Label 341: @7478
    GIM_Try, /*On fail goto*//*Label 342*/ GIMT_Encode4(7589), // Rule ID 2030 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
      GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 2030,
      GIR_EraseRootFromParent_Done,
    // Label 342: @7589
    GIM_Try, /*On fail goto*//*Label 343*/ GIMT_Encode4(7700), // Rule ID 2031 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
      GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 2031,
      GIR_EraseRootFromParent_Done,
    // Label 343: @7700
    GIM_Try, /*On fail goto*//*Label 344*/ GIMT_Encode4(7767), // Rule ID 2035 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 2035,
      GIR_EraseRootFromParent_Done,
    // Label 344: @7767
    GIM_Try, /*On fail goto*//*Label 345*/ GIMT_Encode4(7834), // Rule ID 2036 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 2036,
      GIR_EraseRootFromParent_Done,
    // Label 345: @7834
    GIM_Try, /*On fail goto*//*Label 346*/ GIMT_Encode4(7901), // Rule ID 2040 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 2040,
      GIR_EraseRootFromParent_Done,
    // Label 346: @7901
    GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(7968), // Rule ID 2041 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 2041,
      GIR_EraseRootFromParent_Done,
    // Label 347: @7968
    GIM_Try, /*On fail goto*//*Label 348*/ GIMT_Encode4(8042), // Rule ID 2045 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 2045,
      GIR_EraseRootFromParent_Done,
    // Label 348: @8042
    GIM_Try, /*On fail goto*//*Label 349*/ GIMT_Encode4(8116), // Rule ID 2046 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 2046,
      GIR_EraseRootFromParent_Done,
    // Label 349: @8116
    GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(8190), // Rule ID 2050 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 2050,
      GIR_EraseRootFromParent_Done,
    // Label 350: @8190
    GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(8264), // Rule ID 2051 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
      // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
      // GIR_Coverage, 2051,
      GIR_EraseRootFromParent_Done,
    // Label 351: @8264
    GIM_Reject,
    // Label 309: @8265
    GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(8324),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
      GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(8300), // Rule ID 1907 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
        // GIR_Coverage, 1907,
        GIR_Done,
      // Label 353: @8300
      GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(8323), // Rule ID 1911 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
        // (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
        // GIR_Coverage, 1911,
        GIR_Done,
      // Label 354: @8323
      GIM_Reject,
    // Label 352: @8324
    GIM_Reject,
    // Label 310: @8325
    GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(8351), // Rule ID 1990 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 1990,
      GIR_Done,
    // Label 355: @8351
    GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(8377), // Rule ID 1993 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 1993,
      GIR_Done,
    // Label 356: @8377
    GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(8403), // Rule ID 2006 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 2006,
      GIR_Done,
    // Label 357: @8403
    GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(8429), // Rule ID 2007 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 2007,
      GIR_Done,
    // Label 358: @8429
    GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(8455), // Rule ID 2008 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 2008,
      GIR_Done,
    // Label 359: @8455
    GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(8481), // Rule ID 2009 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 2009,
      GIR_Done,
    // Label 360: @8481
    GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(8507), // Rule ID 2010 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 2010,
      GIR_Done,
    // Label 361: @8507
    GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(8533), // Rule ID 2016 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 2016,
      GIR_Done,
    // Label 362: @8533
    GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(8559), // Rule ID 2017 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 2017,
      GIR_Done,
    // Label 363: @8559
    GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(8585), // Rule ID 2018 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 2018,
      GIR_Done,
    // Label 364: @8585
    GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(8611), // Rule ID 2019 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 2019,
      GIR_Done,
    // Label 365: @8611
    GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(8637), // Rule ID 2020 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 2020,
      GIR_Done,
    // Label 366: @8637
    GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(8704), // Rule ID 2028 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 2028,
      GIR_EraseRootFromParent_Done,
    // Label 367: @8704
    GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(8771), // Rule ID 2029 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 2029,
      GIR_EraseRootFromParent_Done,
    // Label 368: @8771
    GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(8845), // Rule ID 2033 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 2033,
      GIR_EraseRootFromParent_Done,
    // Label 369: @8845
    GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(8919), // Rule ID 2034 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 2034,
      GIR_EraseRootFromParent_Done,
    // Label 370: @8919
    GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(8993), // Rule ID 2038 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 2038,
      GIR_EraseRootFromParent_Done,
    // Label 371: @8993
    GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(9067), // Rule ID 2039 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 2039,
      GIR_EraseRootFromParent_Done,
    // Label 372: @9067
    GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(9141), // Rule ID 2055 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 2055,
      GIR_EraseRootFromParent_Done,
    // Label 373: @9141
    GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(9215), // Rule ID 2056 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 2056,
      GIR_EraseRootFromParent_Done,
    // Label 374: @9215
    GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(9289), // Rule ID 2060 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 2060,
      GIR_EraseRootFromParent_Done,
    // Label 375: @9289
    GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(9363), // Rule ID 2061 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
      // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
      // GIR_Coverage, 2061,
      GIR_EraseRootFromParent_Done,
    // Label 376: @9363
    GIM_Reject,
    // Label 311: @9364
    GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(9390), // Rule ID 1989 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (bitconvert:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
      // GIR_Coverage, 1989,
      GIR_Done,
    // Label 377: @9390
    GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(9416), // Rule ID 1992 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (bitconvert:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
      // GIR_Coverage, 1992,
      GIR_Done,
    // Label 378: @9416
    GIM_Try, /*On fail goto*//*Label 379*/ GIMT_Encode4(9442), // Rule ID 2001 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
      // GIR_Coverage, 2001,
      GIR_Done,
    // Label 379: @9442
    GIM_Try, /*On fail goto*//*Label 380*/ GIMT_Encode4(9468), // Rule ID 2002 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
      // GIR_Coverage, 2002,
      GIR_Done,
    // Label 380: @9468
    GIM_Try, /*On fail goto*//*Label 381*/ GIMT_Encode4(9494), // Rule ID 2003 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
      // GIR_Coverage, 2003,
      GIR_Done,
    // Label 381: @9494
    GIM_Try, /*On fail goto*//*Label 382*/ GIMT_Encode4(9520), // Rule ID 2004 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
      // GIR_Coverage, 2004,
      GIR_Done,
    // Label 382: @9520
    GIM_Try, /*On fail goto*//*Label 383*/ GIMT_Encode4(9546), // Rule ID 2005 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
      // GIR_Coverage, 2005,
      GIR_Done,
    // Label 383: @9546
    GIM_Try, /*On fail goto*//*Label 384*/ GIMT_Encode4(9620), // Rule ID 2026 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
      // GIR_Coverage, 2026,
      GIR_EraseRootFromParent_Done,
    // Label 384: @9620
    GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(9694), // Rule ID 2027 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
      // GIR_Coverage, 2027,
      GIR_EraseRootFromParent_Done,
    // Label 385: @9694
    GIM_Try, /*On fail goto*//*Label 386*/ GIMT_Encode4(9768), // Rule ID 2043 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
      // GIR_Coverage, 2043,
      GIR_EraseRootFromParent_Done,
    // Label 386: @9768
    GIM_Try, /*On fail goto*//*Label 387*/ GIMT_Encode4(9842), // Rule ID 2044 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
      // GIR_Coverage, 2044,
      GIR_EraseRootFromParent_Done,
    // Label 387: @9842
    GIM_Try, /*On fail goto*//*Label 388*/ GIMT_Encode4(9916), // Rule ID 2048 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
      // GIR_Coverage, 2048,
      GIR_EraseRootFromParent_Done,
    // Label 388: @9916
    GIM_Try, /*On fail goto*//*Label 389*/ GIMT_Encode4(9990), // Rule ID 2049 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
      // GIR_Coverage, 2049,
      GIR_EraseRootFromParent_Done,
    // Label 389: @9990
    GIM_Try, /*On fail goto*//*Label 390*/ GIMT_Encode4(10057), // Rule ID 2053 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
      // GIR_Coverage, 2053,
      GIR_EraseRootFromParent_Done,
    // Label 390: @10057
    GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(10124), // Rule ID 2054 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
      // GIR_Coverage, 2054,
      GIR_EraseRootFromParent_Done,
    // Label 391: @10124
    GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(10191), // Rule ID 2058 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
      // GIR_Coverage, 2058,
      GIR_EraseRootFromParent_Done,
    // Label 392: @10191
    GIM_Try, /*On fail goto*//*Label 393*/ GIMT_Encode4(10258), // Rule ID 2059 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
      // (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
      // GIR_Coverage, 2059,
      GIR_EraseRootFromParent_Done,
    // Label 393: @10258
    GIM_Reject,
    // Label 312: @10259
    GIM_Try, /*On fail goto*//*Label 394*/ GIMT_Encode4(10285), // Rule ID 1995 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
      // GIR_Coverage, 1995,
      GIR_Done,
    // Label 394: @10285
    GIM_Try, /*On fail goto*//*Label 395*/ GIMT_Encode4(10311), // Rule ID 1996 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
      // GIR_Coverage, 1996,
      GIR_Done,
    // Label 395: @10311
    GIM_Try, /*On fail goto*//*Label 396*/ GIMT_Encode4(10337), // Rule ID 1997 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
      // GIR_Coverage, 1997,
      GIR_Done,
    // Label 396: @10337
    GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(10363), // Rule ID 1998 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
      // GIR_Coverage, 1998,
      GIR_Done,
    // Label 397: @10363
    GIM_Try, /*On fail goto*//*Label 398*/ GIMT_Encode4(10389), // Rule ID 1999 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
      // GIR_Coverage, 1999,
      GIR_Done,
    // Label 398: @10389
    GIM_Try, /*On fail goto*//*Label 399*/ GIMT_Encode4(10415), // Rule ID 2000 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] })
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
      // GIR_Coverage, 2000,
      GIR_Done,
    // Label 399: @10415
    GIM_Try, /*On fail goto*//*Label 400*/ GIMT_Encode4(10489), // Rule ID 2032 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
      // GIR_Coverage, 2032,
      GIR_EraseRootFromParent_Done,
    // Label 400: @10489
    GIM_Try, /*On fail goto*//*Label 401*/ GIMT_Encode4(10563), // Rule ID 2037 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
      // GIR_Coverage, 2037,
      GIR_EraseRootFromParent_Done,
    // Label 401: @10563
    GIM_Try, /*On fail goto*//*Label 402*/ GIMT_Encode4(10630), // Rule ID 2042 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
      // GIR_Coverage, 2042,
      GIR_EraseRootFromParent_Done,
    // Label 402: @10630
    GIM_Try, /*On fail goto*//*Label 403*/ GIMT_Encode4(10697), // Rule ID 2047 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
      // GIR_Coverage, 2047,
      GIR_EraseRootFromParent_Done,
    // Label 403: @10697
    GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(10808), // Rule ID 2052 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
      GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
      // GIR_Coverage, 2052,
      GIR_EraseRootFromParent_Done,
    // Label 404: @10808
    GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(10919), // Rule ID 2057 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
      GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
      // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
      GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
      // GIR_Coverage, 2057,
      GIR_EraseRootFromParent_Done,
    // Label 405: @10919
    GIM_Reject,
    // Label 313: @10920
    GIM_Reject,
    // Label 13: @10921
    GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(10985), // Rule ID 1980 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
      GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] Operand 1
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LWX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LWX),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1980,
      GIR_EraseRootFromParent_Done,
    // Label 406: @10985
    GIM_Reject,
    // Label 14: @10986
    GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(11053), // Rule ID 1979 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
      GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] Operand 1
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LHX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LHX),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1979,
      GIR_EraseRootFromParent_Done,
    // Label 407: @11053
    GIM_Reject,
    // Label 15: @11054
    GIM_Try, /*On fail goto*//*Label 408*/ GIMT_Encode4(11121), // Rule ID 1978 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
      GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] Operand 1
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (LBUX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LBUX),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1978,
      GIR_EraseRootFromParent_Done,
    // Label 408: @11121
    GIM_Reject,
    // Label 16: @11122
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 411*/ GIMT_Encode4(15842),
    /*GILLT_s32*//*Label 409*/ GIMT_Encode4(11141),
    /*GILLT_s64*//*Label 410*/ GIMT_Encode4(15808),
    // Label 409: @11141
    GIM_Try, /*On fail goto*//*Label 412*/ GIMT_Encode4(11249), // Rule ID 2354 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
      GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
      GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
      GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
      GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
      GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
      GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
      GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
      GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
      GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
      // MIs[4] Operand 1
      // No operand predicates
      GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/4,
      // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BBIT0 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT0),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 2354,
      GIR_EraseRootFromParent_Done,
    // Label 412: @11249
    GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(11364), // Rule ID 2355 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
      GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
      GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
      GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
      GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
      GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
      GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
      GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
      GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
      GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
      // MIs[4] Operand 1
      // No operand predicates
      GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/4,
      // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BBIT032 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT032),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 2355,
      GIR_EraseRootFromParent_Done,
    // Label 413: @11364
    GIM_Try, /*On fail goto*//*Label 414*/ GIMT_Encode4(11472), // Rule ID 2356 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
      GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
      GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
      GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
      GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
      GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
      GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
      GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
      GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
      GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
      // MIs[4] Operand 1
      // No operand predicates
      GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/4,
      // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BBIT1 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT1),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 2356,
      GIR_EraseRootFromParent_Done,
    // Label 414: @11472
    GIM_Try, /*On fail goto*//*Label 415*/ GIMT_Encode4(11587), // Rule ID 2357 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
      GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
      GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
      GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
      GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
      GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
      GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
      GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
      GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
      GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
      // MIs[4] Operand 1
      // No operand predicates
      GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/4,
      // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BBIT132 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT132),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 2357,
      GIR_EraseRootFromParent_Done,
    // Label 415: @11587
    GIM_Try, /*On fail goto*//*Label 416*/ GIMT_Encode4(11695), // Rule ID 270 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
      GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
      GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
      GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
      GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
      GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
      GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
      GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
      GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
      // MIs[4] Operand 1
      // No operand predicates
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/4,
      // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BBIT0 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT0),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 270,
      GIR_EraseRootFromParent_Done,
    // Label 416: @11695
    GIM_Try, /*On fail goto*//*Label 417*/ GIMT_Encode4(11810), // Rule ID 271 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
      GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
      GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
      GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
      GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
      GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
      GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
      GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
      GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
      // MIs[4] Operand 1
      // No operand predicates
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/4,
      // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BBIT032 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT032),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 271,
      GIR_EraseRootFromParent_Done,
    // Label 417: @11810
    GIM_Try, /*On fail goto*//*Label 418*/ GIMT_Encode4(11918), // Rule ID 272 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
      GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
      GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
      GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
      GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
      GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
      GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
      GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
      GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
      // MIs[4] Operand 1
      // No operand predicates
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/4,
      // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BBIT1 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT1),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 272,
      GIR_EraseRootFromParent_Done,
    // Label 418: @11918
    GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(12033), // Rule ID 273 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
      GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
      GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
      GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
      GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
      GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
      GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
      GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
      GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
      // MIs[4] Operand 1
      // No operand predicates
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/4,
      // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BBIT132 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT132),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 273,
      GIR_EraseRootFromParent_Done,
    // Label 419: @12033
    GIM_Try, /*On fail goto*//*Label 420*/ GIMT_Encode4(12090), // Rule ID 94 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGEZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 94,
      GIR_EraseRootFromParent_Done,
    // Label 420: @12090
    GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(12147), // Rule ID 95 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGTZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 95,
      GIR_EraseRootFromParent_Done,
    // Label 421: @12147
    GIM_Try, /*On fail goto*//*Label 422*/ GIMT_Encode4(12204), // Rule ID 96 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLEZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 96,
      GIR_EraseRootFromParent_Done,
    // Label 422: @12204
    GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(12261), // Rule ID 97 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLTZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 97,
      GIR_EraseRootFromParent_Done,
    // Label 423: @12261
    GIM_Try, /*On fail goto*//*Label 424*/ GIMT_Encode4(12318), // Rule ID 245 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGEZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 245,
      GIR_EraseRootFromParent_Done,
    // Label 424: @12318
    GIM_Try, /*On fail goto*//*Label 425*/ GIMT_Encode4(12375), // Rule ID 246 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGTZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 246,
      GIR_EraseRootFromParent_Done,
    // Label 425: @12375
    GIM_Try, /*On fail goto*//*Label 426*/ GIMT_Encode4(12432), // Rule ID 247 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLEZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 247,
      GIR_EraseRootFromParent_Done,
    // Label 426: @12432
    GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(12489), // Rule ID 248 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLTZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 248,
      GIR_EraseRootFromParent_Done,
    // Label 427: @12489
    GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(12546), // Rule ID 1109 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGEZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ_MM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1109,
      GIR_EraseRootFromParent_Done,
    // Label 428: @12546
    GIM_Try, /*On fail goto*//*Label 429*/ GIMT_Encode4(12603), // Rule ID 1110 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGTZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ_MM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1110,
      GIR_EraseRootFromParent_Done,
    // Label 429: @12603
    GIM_Try, /*On fail goto*//*Label 430*/ GIMT_Encode4(12660), // Rule ID 1111 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLEZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ_MM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1111,
      GIR_EraseRootFromParent_Done,
    // Label 430: @12660
    GIM_Try, /*On fail goto*//*Label 431*/ GIMT_Encode4(12717), // Rule ID 1112 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLTZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ_MM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1112,
      GIR_EraseRootFromParent_Done,
    // Label 431: @12717
    GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(12780), // Rule ID 1402 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BNE GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1402,
      GIR_EraseRootFromParent_Done,
    // Label 432: @12780
    GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(12843), // Rule ID 1403 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1403,
      GIR_EraseRootFromParent_Done,
    // Label 433: @12843
    GIM_Try, /*On fail goto*//*Label 434*/ GIMT_Encode4(12906), // Rule ID 1546 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BNE64 GPR64:{ *:[i64] }:$lhs, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1546,
      GIR_EraseRootFromParent_Done,
    // Label 434: @12906
    GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(12969), // Rule ID 1547 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ64 GPR64:{ *:[i64] }:$lhs, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1547,
      GIR_EraseRootFromParent_Done,
    // Label 435: @12969
    GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(13023), // Rule ID 1847 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] targ16
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$targ16)  =>  (BeqzRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BeqzRxImm16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
      GIR_RootToRootCopy, /*OpIdx*/1, // targ16
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1847,
      GIR_EraseRootFromParent_Done,
    // Label 436: @13023
    GIM_Try, /*On fail goto*//*Label 437*/ GIMT_Encode4(13077), // Rule ID 1856 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] targ16
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$targ16)  =>  (BnezRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BnezRxImm16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
      GIR_RootToRootCopy, /*OpIdx*/1, // targ16
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1856,
      GIR_EraseRootFromParent_Done,
    // Label 437: @13077
    GIM_Try, /*On fail goto*//*Label 438*/ GIMT_Encode4(13140), // Rule ID 2184 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BNE_MM GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 2184,
      GIR_EraseRootFromParent_Done,
    // Label 438: @13140
    GIM_Try, /*On fail goto*//*Label 439*/ GIMT_Encode4(13203), // Rule ID 2185 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ_MM GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 2185,
      GIR_EraseRootFromParent_Done,
    // Label 439: @13203
    GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(13260), // Rule ID 2331 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BNEZC_MMR6 GPR32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNEZC_MMR6),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 2331,
      GIR_EraseRootFromParent_Done,
    // Label 440: @13260
    GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(13317), // Rule ID 2332 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQZC_MMR6 GPR32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 2332,
      GIR_EraseRootFromParent_Done,
    // Label 441: @13317
    GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(13369), // Rule ID 1413 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BLEZ i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1413,
      GIR_EraseRootFromParent_Done,
    // Label 442: @13369
    GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(13421), // Rule ID 1414 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BGEZ i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1414,
      GIR_EraseRootFromParent_Done,
    // Label 443: @13421
    GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(13473), // Rule ID 1557 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$lhs, 1:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BLEZ64 i64:{ *:[i64] }:$lhs, (bb:{ *:[Other] }):$dst)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1557,
      GIR_EraseRootFromParent_Done,
    // Label 444: @13473
    GIM_Try, /*On fail goto*//*Label 445*/ GIMT_Encode4(13525), // Rule ID 1558 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$lhs, -1:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BGEZ64 i64:{ *:[i64] }:$lhs, (bb:{ *:[Other] }):$dst)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1558,
      GIR_EraseRootFromParent_Done,
    // Label 445: @13525
    GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(13577), // Rule ID 2195 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BLEZ_MM i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ_MM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 2195,
      GIR_EraseRootFromParent_Done,
    // Label 446: @13577
    GIM_Try, /*On fail goto*//*Label 447*/ GIMT_Encode4(13629), // Rule ID 2196 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BGEZ_MM i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ_MM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 2196,
      GIR_EraseRootFromParent_Done,
    // Label 447: @13629
    GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(13691), // Rule ID 92 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BEQ GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 92,
      GIR_EraseRootFromParent_Done,
    // Label 448: @13691
    GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(13753), // Rule ID 93 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BNE GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 93,
      GIR_EraseRootFromParent_Done,
    // Label 449: @13753
    GIM_Try, /*On fail goto*//*Label 450*/ GIMT_Encode4(13815), // Rule ID 243 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BEQ64 GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 243,
      GIR_EraseRootFromParent_Done,
    // Label 450: @13815
    GIM_Try, /*On fail goto*//*Label 451*/ GIMT_Encode4(13877), // Rule ID 244 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BNE64 GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 244,
      GIR_EraseRootFromParent_Done,
    // Label 451: @13877
    GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(13939), // Rule ID 1107 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BEQ_MM GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1107,
      GIR_EraseRootFromParent_Done,
    // Label 452: @13939
    GIM_Try, /*On fail goto*//*Label 453*/ GIMT_Encode4(14001), // Rule ID 1108 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] offset
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BNE_MM GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
      GIR_RootToRootCopy, /*OpIdx*/1, // offset
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1108,
      GIR_EraseRootFromParent_Done,
    // Label 453: @14001
    GIM_Try, /*On fail goto*//*Label 454*/ GIMT_Encode4(14086), // Rule ID 1404 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1404,
      GIR_EraseRootFromParent_Done,
    // Label 454: @14086
    GIM_Try, /*On fail goto*//*Label 455*/ GIMT_Encode4(14171), // Rule ID 1405 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1405,
      GIR_EraseRootFromParent_Done,
    // Label 455: @14171
    GIM_Try, /*On fail goto*//*Label 456*/ GIMT_Encode4(14256), // Rule ID 1410 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1410,
      GIR_EraseRootFromParent_Done,
    // Label 456: @14256
    GIM_Try, /*On fail goto*//*Label 457*/ GIMT_Encode4(14341), // Rule ID 1411 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1411,
      GIR_EraseRootFromParent_Done,
    // Label 457: @14341
    GIM_Try, /*On fail goto*//*Label 458*/ GIMT_Encode4(14426), // Rule ID 1548 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1548,
      GIR_EraseRootFromParent_Done,
    // Label 458: @14426
    GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(14511), // Rule ID 1549 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1549,
      GIR_EraseRootFromParent_Done,
    // Label 459: @14511
    GIM_Try, /*On fail goto*//*Label 460*/ GIMT_Encode4(14596), // Rule ID 1554 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1554,
      GIR_EraseRootFromParent_Done,
    // Label 460: @14596
    GIM_Try, /*On fail goto*//*Label 461*/ GIMT_Encode4(14681), // Rule ID 1555 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1555,
      GIR_EraseRootFromParent_Done,
    // Label 461: @14681
    GIM_Try, /*On fail goto*//*Label 462*/ GIMT_Encode4(14740), // Rule ID 1845 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
      // MIs[0] imm16
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$imm16)  =>  (BteqzT8CmpX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8CmpX16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
      GIR_RootToRootCopy, /*OpIdx*/1, // imm16
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1845,
      GIR_EraseRootFromParent_Done,
    // Label 462: @14740
    GIM_Try, /*On fail goto*//*Label 463*/ GIMT_Encode4(14799), // Rule ID 1848 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
      // MIs[0] imm16
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$imm16)  =>  (BtnezT8SltX16 CPU16Regs:{ *:[i32] }:$ry, CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$imm16)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8SltX16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
      GIR_RootToRootCopy, /*OpIdx*/1, // imm16
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1848,
      GIR_EraseRootFromParent_Done,
    // Label 463: @14799
    GIM_Try, /*On fail goto*//*Label 464*/ GIMT_Encode4(14858), // Rule ID 1849 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
      // MIs[0] imm16
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16)  =>  (BteqzT8SltX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8SltX16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
      GIR_RootToRootCopy, /*OpIdx*/1, // imm16
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1849,
      GIR_EraseRootFromParent_Done,
    // Label 464: @14858
    GIM_Try, /*On fail goto*//*Label 465*/ GIMT_Encode4(14917), // Rule ID 1851 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
      // MIs[0] imm16
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$imm16)  =>  (BtnezT8SltX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8SltX16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
      GIR_RootToRootCopy, /*OpIdx*/1, // imm16
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1851,
      GIR_EraseRootFromParent_Done,
    // Label 465: @14917
    GIM_Try, /*On fail goto*//*Label 466*/ GIMT_Encode4(14976), // Rule ID 1853 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
      // MIs[0] imm16
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16)  =>  (BteqzT8SltX16 CPU16Regs:{ *:[i32] }:$ry, CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$imm16)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8SltX16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
      GIR_RootToRootCopy, /*OpIdx*/1, // imm16
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1853,
      GIR_EraseRootFromParent_Done,
    // Label 466: @14976
    GIM_Try, /*On fail goto*//*Label 467*/ GIMT_Encode4(15035), // Rule ID 1854 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
      // MIs[0] imm16
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16)  =>  (BtnezT8CmpX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8CmpX16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
      GIR_RootToRootCopy, /*OpIdx*/1, // imm16
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1854,
      GIR_EraseRootFromParent_Done,
    // Label 467: @15035
    GIM_Try, /*On fail goto*//*Label 468*/ GIMT_Encode4(15120), // Rule ID 2186 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ_MM (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 2186,
      GIR_EraseRootFromParent_Done,
    // Label 468: @15120
    GIM_Try, /*On fail goto*//*Label 469*/ GIMT_Encode4(15205), // Rule ID 2187 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ_MM (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 2187,
      GIR_EraseRootFromParent_Done,
    // Label 469: @15205
    GIM_Try, /*On fail goto*//*Label 470*/ GIMT_Encode4(15290), // Rule ID 2192 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ_MM (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 2192,
      GIR_EraseRootFromParent_Done,
    // Label 470: @15290
    GIM_Try, /*On fail goto*//*Label 471*/ GIMT_Encode4(15375), // Rule ID 2193 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ_MM (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 2193,
      GIR_EraseRootFromParent_Done,
    // Label 471: @15375
    GIM_Try, /*On fail goto*//*Label 472*/ GIMT_Encode4(15454), // Rule ID 2333 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQZC_MMR6 (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), (bb:{ *:[Other] }):$dst)
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 2333,
      GIR_EraseRootFromParent_Done,
    // Label 472: @15454
    GIM_Try, /*On fail goto*//*Label 473*/ GIMT_Encode4(15533), // Rule ID 2334 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQZC_MMR6 (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), (bb:{ *:[Other] }):$dst)
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 2334,
      GIR_EraseRootFromParent_Done,
    // Label 473: @15533
    GIM_Try, /*On fail goto*//*Label 474*/ GIMT_Encode4(15612), // Rule ID 2339 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQZC_MMR6 (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), (bb:{ *:[Other] }):$dst)
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 2339,
      GIR_EraseRootFromParent_Done,
    // Label 474: @15612
    GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(15691), // Rule ID 2340 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
      // MIs[1] Operand 1
      GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      GIM_CheckIsSafeToFold, /*NumInsns*/1,
      // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQZC_MMR6 (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), (bb:{ *:[Other] }):$dst)
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 2340,
      GIR_EraseRootFromParent_Done,
    // Label 475: @15691
    GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(15724), // Rule ID 1412 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst)  =>  (BNE GPR32:{ *:[i32] }:$cond, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
      GIR_RootToRootCopy, /*OpIdx*/0, // cond
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1412,
      GIR_EraseRootFromParent_Done,
    // Label 476: @15724
    GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(15746), // Rule ID 1857 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
      // MIs[0] targ16
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      // (brcond CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)  =>  (BnezRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BnezRxImm16),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1857,
      GIR_Done,
    // Label 477: @15746
    GIM_Try, /*On fail goto*//*Label 478*/ GIMT_Encode4(15779), // Rule ID 2194 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst)  =>  (BNE_MM GPR32:{ *:[i32] }:$cond, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
      GIR_RootToRootCopy, /*OpIdx*/0, // cond
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 2194,
      GIR_EraseRootFromParent_Done,
    // Label 478: @15779
    GIM_Try, /*On fail goto*//*Label 479*/ GIMT_Encode4(15807), // Rule ID 2341 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst)  =>  (BNEZC_MMR6 GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BNEZC_MMR6),
      GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(RegState::Dead),
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 2341,
      GIR_Done,
    // Label 479: @15807
    GIM_Reject,
    // Label 410: @15808
    GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(15841), // Rule ID 1556 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
      // MIs[0] dst
      GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
      // (brcond GPR64:{ *:[i64] }:$cond, (bb:{ *:[Other] }):$dst)  =>  (BNE64 GPR64:{ *:[i64] }:$cond, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
      GIR_RootToRootCopy, /*OpIdx*/0, // cond
      GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
      GIR_RootToRootCopy, /*OpIdx*/1, // dst
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 1556,
      GIR_EraseRootFromParent_Done,
    // Label 480: @15841
    GIM_Reject,
    // Label 411: @15842
    GIM_Reject,
    // Label 17: @15843
    GIM_Try, /*On fail goto*//*Label 481*/ GIMT_Encode4(17840),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
      GIM_Try, /*On fail goto*//*Label 482*/ GIMT_Encode4(15898), // Rule ID 428 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt8),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (intrinsic_wo_chain:{ *:[v4i8] } 7748:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm)  =>  (REPL_QB:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 428,
        GIR_EraseRootFromParent_Done,
      // Label 482: @15898
      GIM_Try, /*On fail goto*//*Label 483*/ GIMT_Encode4(15945), // Rule ID 429 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExt10),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (intrinsic_wo_chain:{ *:[v2i16] } 7747:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm)  =>  (REPL_PH:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 429,
        GIR_EraseRootFromParent_Done,
      // Label 483: @15945
      GIM_Try, /*On fail goto*//*Label 484*/ GIMT_Encode4(15992), // Rule ID 1288 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExt10),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (intrinsic_wo_chain:{ *:[v2i16] } 7747:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm)  =>  (REPL_PH_MM:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_PH_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1288,
        GIR_EraseRootFromParent_Done,
      // Label 484: @15992
      GIM_Try, /*On fail goto*//*Label 485*/ GIMT_Encode4(16039), // Rule ID 1289 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt8),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (intrinsic_wo_chain:{ *:[v4i8] } 7748:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm)  =>  (REPL_QB_MM:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_QB_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1289,
        GIR_EraseRootFromParent_Done,
      // Label 485: @16039
      GIM_Try, /*On fail goto*//*Label 486*/ GIMT_Encode4(16075), // Rule ID 362 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_raddu_w_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 7745:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (RADDU_W_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RADDU_W_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 362,
        GIR_EraseRootFromParent_Done,
      // Label 486: @16075
      GIM_Try, /*On fail goto*//*Label 487*/ GIMT_Encode4(16111), // Rule ID 369 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phl),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 7727:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHL),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 369,
        GIR_EraseRootFromParent_Done,
      // Label 487: @16111
      GIM_Try, /*On fail goto*//*Label 488*/ GIMT_Encode4(16147), // Rule ID 370 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phr),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 7728:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECEQ_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHR),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 370,
        GIR_EraseRootFromParent_Done,
      // Label 488: @16147
      GIM_Try, /*On fail goto*//*Label 489*/ GIMT_Encode4(16183), // Rule ID 371 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbl),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7729:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBL),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 371,
        GIR_EraseRootFromParent_Done,
      // Label 489: @16183
      GIM_Try, /*On fail goto*//*Label 490*/ GIMT_Encode4(16219), // Rule ID 372 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbr),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7731:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBR),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 372,
        GIR_EraseRootFromParent_Done,
      // Label 490: @16219
      GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(16255), // Rule ID 373 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbla),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7730:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBLA),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 373,
        GIR_EraseRootFromParent_Done,
      // Label 491: @16255
      GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(16291), // Rule ID 374 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbra),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7732:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBRA),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 374,
        GIR_EraseRootFromParent_Done,
      // Label 492: @16291
      GIM_Try, /*On fail goto*//*Label 493*/ GIMT_Encode4(16327), // Rule ID 375 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbl),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7733:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBL),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 375,
        GIR_EraseRootFromParent_Done,
      // Label 493: @16327
      GIM_Try, /*On fail goto*//*Label 494*/ GIMT_Encode4(16363), // Rule ID 376 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbr),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7735:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBR),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 376,
        GIR_EraseRootFromParent_Done,
      // Label 494: @16363
      GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(16399), // Rule ID 377 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbla),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7734:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBLA),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 377,
        GIR_EraseRootFromParent_Done,
      // Label 495: @16399
      GIM_Try, /*On fail goto*//*Label 496*/ GIMT_Encode4(16435), // Rule ID 378 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbra),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7736:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBRA),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 378,
        GIR_EraseRootFromParent_Done,
      // Label 496: @16435
      GIM_Try, /*On fail goto*//*Label 497*/ GIMT_Encode4(16471), // Rule ID 426 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bitrev),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 7301:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (BITREV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BITREV),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 426,
        GIR_EraseRootFromParent_Done,
      // Label 497: @16471
      GIM_Try, /*On fail goto*//*Label 498*/ GIMT_Encode4(16507), // Rule ID 430 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7748:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (REPLV_QB:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 430,
        GIR_EraseRootFromParent_Done,
      // Label 498: @16507
      GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(16543), // Rule ID 431 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7747:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (REPLV_PH:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 431,
        GIR_EraseRootFromParent_Done,
      // Label 499: @16543
      GIM_Try, /*On fail goto*//*Label 500*/ GIMT_Encode4(16579), // Rule ID 680 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fclass_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7453:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FCLASS_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCLASS_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 680,
        GIR_EraseRootFromParent_Done,
      // Label 500: @16579
      GIM_Try, /*On fail goto*//*Label 501*/ GIMT_Encode4(16615), // Rule ID 681 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fclass_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7452:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FCLASS_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCLASS_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 681,
        GIR_EraseRootFromParent_Done,
      // Label 501: @16615
      GIM_Try, /*On fail goto*//*Label 502*/ GIMT_Encode4(16651), // Rule ID 704 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupl_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v4f32] } 7479:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws)  =>  (FEXUPL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPL_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 704,
        GIR_EraseRootFromParent_Done,
      // Label 502: @16651
      GIM_Try, /*On fail goto*//*Label 503*/ GIMT_Encode4(16687), // Rule ID 705 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupl_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v2f64] } 7478:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FEXUPL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPL_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 705,
        GIR_EraseRootFromParent_Done,
      // Label 503: @16687
      GIM_Try, /*On fail goto*//*Label 504*/ GIMT_Encode4(16723), // Rule ID 706 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupr_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v4f32] } 7481:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws)  =>  (FEXUPR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPR_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 706,
        GIR_EraseRootFromParent_Done,
      // Label 504: @16723
      GIM_Try, /*On fail goto*//*Label 505*/ GIMT_Encode4(16759), // Rule ID 707 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupr_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v2f64] } 7480:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FEXUPR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPR_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 707,
        GIR_EraseRootFromParent_Done,
      // Label 505: @16759
      GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(16795), // Rule ID 712 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffql_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v4f32] } 7487:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (FFQL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQL_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 712,
        GIR_EraseRootFromParent_Done,
      // Label 506: @16795
      GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(16831), // Rule ID 713 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffql_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v2f64] } 7486:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (FFQL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQL_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 713,
        GIR_EraseRootFromParent_Done,
      // Label 507: @16831
      GIM_Try, /*On fail goto*//*Label 508*/ GIMT_Encode4(16867), // Rule ID 714 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffqr_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v4f32] } 7489:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (FFQR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQR_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 714,
        GIR_EraseRootFromParent_Done,
      // Label 508: @16867
      GIM_Try, /*On fail goto*//*Label 509*/ GIMT_Encode4(16903), // Rule ID 715 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffqr_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v2f64] } 7488:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (FFQR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQR_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 715,
        GIR_EraseRootFromParent_Done,
      // Label 509: @16903
      GIM_Try, /*On fail goto*//*Label 510*/ GIMT_Encode4(16939), // Rule ID 740 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frcp_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4f32] } 7511:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FRCP_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRCP_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 740,
        GIR_EraseRootFromParent_Done,
      // Label 510: @16939
      GIM_Try, /*On fail goto*//*Label 511*/ GIMT_Encode4(16975), // Rule ID 741 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frcp_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2f64] } 7510:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FRCP_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRCP_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 741,
        GIR_EraseRootFromParent_Done,
      // Label 511: @16975
      GIM_Try, /*On fail goto*//*Label 512*/ GIMT_Encode4(17011), // Rule ID 742 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frsqrt_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4f32] } 7515:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FRSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRSQRT_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 742,
        GIR_EraseRootFromParent_Done,
      // Label 512: @17011
      GIM_Try, /*On fail goto*//*Label 513*/ GIMT_Encode4(17047), // Rule ID 743 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frsqrt_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2f64] } 7514:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FRSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRSQRT_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 743,
        GIR_EraseRootFromParent_Done,
      // Label 513: @17047
      GIM_Try, /*On fail goto*//*Label 514*/ GIMT_Encode4(17083), // Rule ID 770 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7543:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FTINT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_S_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 770,
        GIR_EraseRootFromParent_Done,
      // Label 514: @17083
      GIM_Try, /*On fail goto*//*Label 515*/ GIMT_Encode4(17119), // Rule ID 771 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_s_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7542:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FTINT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_S_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 771,
        GIR_EraseRootFromParent_Done,
      // Label 515: @17119
      GIM_Try, /*On fail goto*//*Label 516*/ GIMT_Encode4(17155), // Rule ID 772 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_u_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7545:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FTINT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_U_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 772,
        GIR_EraseRootFromParent_Done,
      // Label 516: @17155
      GIM_Try, /*On fail goto*//*Label 517*/ GIMT_Encode4(17191), // Rule ID 773 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_u_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7544:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FTINT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_U_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 773,
        GIR_EraseRootFromParent_Done,
      // Label 517: @17191
      GIM_Try, /*On fail goto*//*Label 518*/ GIMT_Encode4(17227), // Rule ID 908 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7700:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws)  =>  (NLOC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 908,
        GIR_EraseRootFromParent_Done,
      // Label 518: @17227
      GIM_Try, /*On fail goto*//*Label 519*/ GIMT_Encode4(17263), // Rule ID 909 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7702:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (NLOC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 909,
        GIR_EraseRootFromParent_Done,
      // Label 519: @17263
      GIM_Try, /*On fail goto*//*Label 520*/ GIMT_Encode4(17299), // Rule ID 910 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7703:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (NLOC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 910,
        GIR_EraseRootFromParent_Done,
      // Label 520: @17299
      GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(17335), // Rule ID 911 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7701:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws)  =>  (NLOC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 911,
        GIR_EraseRootFromParent_Done,
      // Label 521: @17335
      GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(17371), // Rule ID 1251 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phl),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 7727:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs)  =>  (PRECEQ_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHL_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1251,
        GIR_EraseRootFromParent_Done,
      // Label 522: @17371
      GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(17407), // Rule ID 1252 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phr),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 7728:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs)  =>  (PRECEQ_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHR_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1252,
        GIR_EraseRootFromParent_Done,
      // Label 523: @17407
      GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(17443), // Rule ID 1253 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbl),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7729:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEQU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBL_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1253,
        GIR_EraseRootFromParent_Done,
      // Label 524: @17443
      GIM_Try, /*On fail goto*//*Label 525*/ GIMT_Encode4(17479), // Rule ID 1254 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbla),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7730:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEQU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBLA_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1254,
        GIR_EraseRootFromParent_Done,
      // Label 525: @17479
      GIM_Try, /*On fail goto*//*Label 526*/ GIMT_Encode4(17515), // Rule ID 1255 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbr),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7731:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEQU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBR_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1255,
        GIR_EraseRootFromParent_Done,
      // Label 526: @17515
      GIM_Try, /*On fail goto*//*Label 527*/ GIMT_Encode4(17551), // Rule ID 1256 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbra),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7732:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEQU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBRA_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1256,
        GIR_EraseRootFromParent_Done,
      // Label 527: @17551
      GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(17587), // Rule ID 1257 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbl),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7733:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBL_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1257,
        GIR_EraseRootFromParent_Done,
      // Label 528: @17587
      GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(17623), // Rule ID 1258 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbla),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7734:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBLA_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1258,
        GIR_EraseRootFromParent_Done,
      // Label 529: @17623
      GIM_Try, /*On fail goto*//*Label 530*/ GIMT_Encode4(17659), // Rule ID 1259 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbr),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7735:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBR_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1259,
        GIR_EraseRootFromParent_Done,
      // Label 530: @17659
      GIM_Try, /*On fail goto*//*Label 531*/ GIMT_Encode4(17695), // Rule ID 1260 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbra),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7736:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBRA_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1260,
        GIR_EraseRootFromParent_Done,
      // Label 531: @17695
      GIM_Try, /*On fail goto*//*Label 532*/ GIMT_Encode4(17731), // Rule ID 1286 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_raddu_w_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 7745:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (RADDU_W_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RADDU_W_QB_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1286,
        GIR_EraseRootFromParent_Done,
      // Label 532: @17731
      GIM_Try, /*On fail goto*//*Label 533*/ GIMT_Encode4(17767), // Rule ID 1290 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7747:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs)  =>  (REPLV_PH_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_PH_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1290,
        GIR_EraseRootFromParent_Done,
      // Label 533: @17767
      GIM_Try, /*On fail goto*//*Label 534*/ GIMT_Encode4(17803), // Rule ID 1291 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7748:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs)  =>  (REPLV_QB_MM:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_QB_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1291,
        GIR_EraseRootFromParent_Done,
      // Label 534: @17803
      GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(17839), // Rule ID 1301 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bitrev),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 7301:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs)  =>  (BITREV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BITREV_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1301,
        GIR_EraseRootFromParent_Done,
      // Label 535: @17839
      GIM_Reject,
    // Label 481: @17840
    GIM_Try, /*On fail goto*//*Label 536*/ GIMT_Encode4(27593),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
      GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(17894), // Rule ID 938 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // MIs[0] m
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7749:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m)  =>  (SAT_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // m
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 938,
        GIR_EraseRootFromParent_Done,
      // Label 537: @17894
      GIM_Try, /*On fail goto*//*Label 538*/ GIMT_Encode4(17940), // Rule ID 939 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // MIs[0] m
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7751:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m)  =>  (SAT_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // m
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 939,
        GIR_EraseRootFromParent_Done,
      // Label 538: @17940
      GIM_Try, /*On fail goto*//*Label 539*/ GIMT_Encode4(17986), // Rule ID 940 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // MIs[0] m
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7752:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m)  =>  (SAT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // m
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 940,
        GIR_EraseRootFromParent_Done,
      // Label 539: @17986
      GIM_Try, /*On fail goto*//*Label 540*/ GIMT_Encode4(18032), // Rule ID 941 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // MIs[0] m
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7750:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m)  =>  (SAT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // m
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 941,
        GIR_EraseRootFromParent_Done,
      // Label 540: @18032
      GIM_Try, /*On fail goto*//*Label 541*/ GIMT_Encode4(18078), // Rule ID 942 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // MIs[0] m
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7753:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m)  =>  (SAT_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // m
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 942,
        GIR_EraseRootFromParent_Done,
      // Label 541: @18078
      GIM_Try, /*On fail goto*//*Label 542*/ GIMT_Encode4(18124), // Rule ID 943 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // MIs[0] m
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7755:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m)  =>  (SAT_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // m
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 943,
        GIR_EraseRootFromParent_Done,
      // Label 542: @18124
      GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(18170), // Rule ID 944 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // MIs[0] m
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7756:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m)  =>  (SAT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // m
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 944,
        GIR_EraseRootFromParent_Done,
      // Label 543: @18170
      GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(18216), // Rule ID 945 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // MIs[0] m
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7754:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m)  =>  (SAT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // m
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 945,
        GIR_EraseRootFromParent_Done,
      // Label 544: @18216
      GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(18262), // Rule ID 985 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // MIs[0] m
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7808:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m)  =>  (SRARI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // m
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 985,
        GIR_EraseRootFromParent_Done,
      // Label 545: @18262
      GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(18308), // Rule ID 986 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // MIs[0] m
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7810:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m)  =>  (SRARI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // m
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 986,
        GIR_EraseRootFromParent_Done,
      // Label 546: @18308
      GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(18354), // Rule ID 987 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // MIs[0] m
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7811:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m)  =>  (SRARI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // m
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 987,
        GIR_EraseRootFromParent_Done,
      // Label 547: @18354
      GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(18400), // Rule ID 988 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // MIs[0] m
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7809:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m)  =>  (SRARI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // m
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 988,
        GIR_EraseRootFromParent_Done,
      // Label 548: @18400
      GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(18446), // Rule ID 1001 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // MIs[0] m
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7824:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m)  =>  (SRLRI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // m
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1001,
        GIR_EraseRootFromParent_Done,
      // Label 549: @18446
      GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(18492), // Rule ID 1002 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // MIs[0] m
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7826:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m)  =>  (SRLRI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // m
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1002,
        GIR_EraseRootFromParent_Done,
      // Label 550: @18492
      GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(18538), // Rule ID 1003 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // MIs[0] m
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7827:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m)  =>  (SRLRI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // m
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1003,
        GIR_EraseRootFromParent_Done,
      // Label 551: @18538
      GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(18584), // Rule ID 1004 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // MIs[0] m
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7825:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m)  =>  (SRLRI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // m
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1004,
        GIR_EraseRootFromParent_Done,
      // Label 552: @18584
      GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(18640), // Rule ID 385 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (intrinsic_wo_chain:{ *:[v2i16] } 7767:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa)  =>  (SHRA_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 385,
        GIR_EraseRootFromParent_Done,
      // Label 553: @18640
      GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(18696), // Rule ID 389 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (intrinsic_wo_chain:{ *:[i32] } 7769:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa)  =>  (SHRA_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 389,
        GIR_EraseRootFromParent_Done,
      // Label 554: @18696
      GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(18752), // Rule ID 480 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (intrinsic_wo_chain:{ *:[v4i8] } 7768:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$rs_sa)  =>  (SHRA_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] }):$rs_sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 480,
        GIR_EraseRootFromParent_Done,
      // Label 555: @18752
      GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(18808), // Rule ID 1245 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (intrinsic_wo_chain:{ *:[v2i16] } 7767:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa)  =>  (SHRA_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_PH_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1245,
        GIR_EraseRootFromParent_Done,
      // Label 556: @18808
      GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(18864), // Rule ID 1249 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (intrinsic_wo_chain:{ *:[i32] } 7769:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa)  =>  (SHRA_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_W_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1249,
        GIR_EraseRootFromParent_Done,
      // Label 557: @18864
      GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(18920), // Rule ID 1324 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (intrinsic_wo_chain:{ *:[v4i8] } 7768:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$sa)  =>  (SHRA_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] }):$sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_QB_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1324,
        GIR_EraseRootFromParent_Done,
      // Label 558: @18920
      GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(18972), // Rule ID 1934 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (intrinsic_wo_chain:{ *:[v2i16] } 7765:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)  =>  (SHRA_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // a
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1934,
        GIR_EraseRootFromParent_Done,
      // Label 559: @18972
      GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(19024), // Rule ID 1935 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (intrinsic_wo_chain:{ *:[v2i16] } 7770:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)  =>  (SHRL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRL_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // a
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1935,
        GIR_EraseRootFromParent_Done,
      // Label 560: @19024
      GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(19076), // Rule ID 1940 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (intrinsic_wo_chain:{ *:[v4i8] } 7766:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)  =>  (SHRA_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // a
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1940,
        GIR_EraseRootFromParent_Done,
      // Label 561: @19076
      GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(19128), // Rule ID 1941 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (intrinsic_wo_chain:{ *:[v4i8] } 7771:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)  =>  (SHRL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRL_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // a
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1941,
        GIR_EraseRootFromParent_Done,
      // Label 562: @19128
      GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(19176), // Rule ID 355 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7237:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 355,
        GIR_EraseRootFromParent_Done,
      // Label 563: @19176
      GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(19224), // Rule ID 356 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7860:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 356,
        GIR_EraseRootFromParent_Done,
      // Label 564: @19224
      GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(19272), // Rule ID 357 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7215:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 357,
        GIR_EraseRootFromParent_Done,
      // Label 565: @19272
      GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(19320), // Rule ID 358 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7835:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 358,
        GIR_EraseRootFromParent_Done,
      // Label 566: @19320
      GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(19365), // Rule ID 361 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_modsub),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 7665:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODSUB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MODSUB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 361,
        GIR_EraseRootFromParent_Done,
      // Label 567: @19365
      GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(19410), // Rule ID 365 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_qb_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7741:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECRQ_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_QB_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 365,
        GIR_EraseRootFromParent_Done,
      // Label 568: @19410
      GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(19455), // Rule ID 366 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_ph_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7740:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (PRECRQ_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_PH_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 366,
        GIR_EraseRootFromParent_Done,
      // Label 569: @19455
      GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(19500), // Rule ID 380 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7771:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 380,
        GIR_EraseRootFromParent_Done,
      // Label 570: @19500
      GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(19545), // Rule ID 384 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7765:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRAV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 384,
        GIR_EraseRootFromParent_Done,
      // Label 571: @19545
      GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(19590), // Rule ID 386 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7767:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRAV_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 386,
        GIR_EraseRootFromParent_Done,
      // Label 572: @19590
      GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(19635), // Rule ID 390 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 7769:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRAV_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 390,
        GIR_EraseRootFromParent_Done,
      // Label 573: @19635
      GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(19680), // Rule ID 427 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_packrl_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7712:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PACKRL_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PACKRL_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 427,
        GIR_EraseRootFromParent_Done,
      // Label 574: @19680
      GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(19725), // Rule ID 451 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7238:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 451,
        GIR_EraseRootFromParent_Done,
      // Label 575: @19725
      GIM_Try, /*On fail goto*//*Label 576*/ GIMT_Encode4(19770), // Rule ID 452 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_r_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7239:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_R_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 452,
        GIR_EraseRootFromParent_Done,
      // Label 576: @19770
      GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(19815), // Rule ID 453 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7861:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 453,
        GIR_EraseRootFromParent_Done,
      // Label 577: @19815
      GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(19860), // Rule ID 454 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_r_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7862:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_R_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 454,
        GIR_EraseRootFromParent_Done,
      // Label 578: @19860
      GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(19905), // Rule ID 455 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7217:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 455,
        GIR_EraseRootFromParent_Done,
      // Label 579: @19905
      GIM_Try, /*On fail goto*//*Label 580*/ GIMT_Encode4(19950), // Rule ID 456 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7218:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 456,
        GIR_EraseRootFromParent_Done,
      // Label 580: @19950
      GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(19995), // Rule ID 457 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7837:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 457,
        GIR_EraseRootFromParent_Done,
      // Label 581: @19995
      GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(20040), // Rule ID 458 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7838:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 458,
        GIR_EraseRootFromParent_Done,
      // Label 582: @20040
      GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(20085), // Rule ID 459 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 7220:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 459,
        GIR_EraseRootFromParent_Done,
      // Label 583: @20085
      GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(20130), // Rule ID 460 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 7219:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 460,
        GIR_EraseRootFromParent_Done,
      // Label 584: @20130
      GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(20175), // Rule ID 461 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 7840:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 461,
        GIR_EraseRootFromParent_Done,
      // Label 585: @20175
      GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(20220), // Rule ID 462 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 7839:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 462,
        GIR_EraseRootFromParent_Done,
      // Label 586: @20220
      GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(20265), // Rule ID 479 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7766:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRAV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 479,
        GIR_EraseRootFromParent_Done,
      // Label 587: @20265
      GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(20310), // Rule ID 481 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7768:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRAV_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 481,
        GIR_EraseRootFromParent_Done,
      // Label 588: @20310
      GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(20355), // Rule ID 482 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7770:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 482,
        GIR_EraseRootFromParent_Done,
      // Label 589: @20355
      GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(20400), // Rule ID 491 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7210:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADD_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 491,
        GIR_EraseRootFromParent_Done,
      // Label 590: @20400
      GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(20445), // Rule ID 492 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7212:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADD_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 492,
        GIR_EraseRootFromParent_Done,
      // Label 591: @20445
      GIM_Try, /*On fail goto*//*Label 592*/ GIMT_Encode4(20490), // Rule ID 493 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7213:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADD_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 493,
        GIR_EraseRootFromParent_Done,
      // Label 592: @20490
      GIM_Try, /*On fail goto*//*Label 593*/ GIMT_Encode4(20535), // Rule ID 494 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7211:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADD_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 494,
        GIR_EraseRootFromParent_Done,
      // Label 593: @20535
      GIM_Try, /*On fail goto*//*Label 594*/ GIMT_Encode4(20580), // Rule ID 495 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7221:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADDS_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 495,
        GIR_EraseRootFromParent_Done,
      // Label 594: @20580
      GIM_Try, /*On fail goto*//*Label 595*/ GIMT_Encode4(20625), // Rule ID 496 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7223:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADDS_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 496,
        GIR_EraseRootFromParent_Done,
      // Label 595: @20625
      GIM_Try, /*On fail goto*//*Label 596*/ GIMT_Encode4(20670), // Rule ID 497 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7224:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADDS_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 497,
        GIR_EraseRootFromParent_Done,
      // Label 596: @20670
      GIM_Try, /*On fail goto*//*Label 597*/ GIMT_Encode4(20715), // Rule ID 498 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7222:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADDS_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 498,
        GIR_EraseRootFromParent_Done,
      // Label 597: @20715
      GIM_Try, /*On fail goto*//*Label 598*/ GIMT_Encode4(20760), // Rule ID 499 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7225:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADDS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 499,
        GIR_EraseRootFromParent_Done,
      // Label 598: @20760
      GIM_Try, /*On fail goto*//*Label 599*/ GIMT_Encode4(20805), // Rule ID 500 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7227:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADDS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 500,
        GIR_EraseRootFromParent_Done,
      // Label 599: @20805
      GIM_Try, /*On fail goto*//*Label 600*/ GIMT_Encode4(20850), // Rule ID 501 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7228:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADDS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 501,
        GIR_EraseRootFromParent_Done,
      // Label 600: @20850
      GIM_Try, /*On fail goto*//*Label 601*/ GIMT_Encode4(20895), // Rule ID 502 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7226:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADDS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 502,
        GIR_EraseRootFromParent_Done,
      // Label 601: @20895
      GIM_Try, /*On fail goto*//*Label 602*/ GIMT_Encode4(20940), // Rule ID 503 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7229:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADDS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 503,
        GIR_EraseRootFromParent_Done,
      // Label 602: @20940
      GIM_Try, /*On fail goto*//*Label 603*/ GIMT_Encode4(20985), // Rule ID 504 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7231:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADDS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 504,
        GIR_EraseRootFromParent_Done,
      // Label 603: @20985
      GIM_Try, /*On fail goto*//*Label 604*/ GIMT_Encode4(21030), // Rule ID 505 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7232:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADDS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 505,
        GIR_EraseRootFromParent_Done,
      // Label 604: @21030
      GIM_Try, /*On fail goto*//*Label 605*/ GIMT_Encode4(21075), // Rule ID 506 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7230:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADDS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 506,
        GIR_EraseRootFromParent_Done,
      // Label 605: @21075
      GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(21120), // Rule ID 520 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7252:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ASUB_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 520,
        GIR_EraseRootFromParent_Done,
      // Label 606: @21120
      GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(21165), // Rule ID 521 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7254:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ASUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 521,
        GIR_EraseRootFromParent_Done,
      // Label 607: @21165
      GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(21210), // Rule ID 522 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7255:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ASUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 522,
        GIR_EraseRootFromParent_Done,
      // Label 608: @21210
      GIM_Try, /*On fail goto*//*Label 609*/ GIMT_Encode4(21255), // Rule ID 523 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7253:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ASUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 523,
        GIR_EraseRootFromParent_Done,
      // Label 609: @21255
      GIM_Try, /*On fail goto*//*Label 610*/ GIMT_Encode4(21300), // Rule ID 524 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7256:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ASUB_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 524,
        GIR_EraseRootFromParent_Done,
      // Label 610: @21300
      GIM_Try, /*On fail goto*//*Label 611*/ GIMT_Encode4(21345), // Rule ID 525 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7258:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ASUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 525,
        GIR_EraseRootFromParent_Done,
      // Label 611: @21345
      GIM_Try, /*On fail goto*//*Label 612*/ GIMT_Encode4(21390), // Rule ID 526 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7259:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ASUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 526,
        GIR_EraseRootFromParent_Done,
      // Label 612: @21390
      GIM_Try, /*On fail goto*//*Label 613*/ GIMT_Encode4(21435), // Rule ID 527 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7257:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ASUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 527,
        GIR_EraseRootFromParent_Done,
      // Label 613: @21435
      GIM_Try, /*On fail goto*//*Label 614*/ GIMT_Encode4(21480), // Rule ID 528 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7260:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AVE_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 528,
        GIR_EraseRootFromParent_Done,
      // Label 614: @21480
      GIM_Try, /*On fail goto*//*Label 615*/ GIMT_Encode4(21525), // Rule ID 529 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7262:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AVE_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 529,
        GIR_EraseRootFromParent_Done,
      // Label 615: @21525
      GIM_Try, /*On fail goto*//*Label 616*/ GIMT_Encode4(21570), // Rule ID 530 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7263:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AVE_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 530,
        GIR_EraseRootFromParent_Done,
      // Label 616: @21570
      GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(21615), // Rule ID 531 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7261:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AVE_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 531,
        GIR_EraseRootFromParent_Done,
      // Label 617: @21615
      GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(21660), // Rule ID 532 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7264:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AVE_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 532,
        GIR_EraseRootFromParent_Done,
      // Label 618: @21660
      GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(21705), // Rule ID 533 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7266:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AVE_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 533,
        GIR_EraseRootFromParent_Done,
      // Label 619: @21705
      GIM_Try, /*On fail goto*//*Label 620*/ GIMT_Encode4(21750), // Rule ID 534 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7267:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AVE_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 534,
        GIR_EraseRootFromParent_Done,
      // Label 620: @21750
      GIM_Try, /*On fail goto*//*Label 621*/ GIMT_Encode4(21795), // Rule ID 535 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7265:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AVE_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 535,
        GIR_EraseRootFromParent_Done,
      // Label 621: @21795
      GIM_Try, /*On fail goto*//*Label 622*/ GIMT_Encode4(21840), // Rule ID 536 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7268:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AVER_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 536,
        GIR_EraseRootFromParent_Done,
      // Label 622: @21840
      GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(21885), // Rule ID 537 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7270:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AVER_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 537,
        GIR_EraseRootFromParent_Done,
      // Label 623: @21885
      GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(21930), // Rule ID 538 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7271:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AVER_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 538,
        GIR_EraseRootFromParent_Done,
      // Label 624: @21930
      GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(21975), // Rule ID 539 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7269:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AVER_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 539,
        GIR_EraseRootFromParent_Done,
      // Label 625: @21975
      GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(22020), // Rule ID 540 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7272:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AVER_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 540,
        GIR_EraseRootFromParent_Done,
      // Label 626: @22020
      GIM_Try, /*On fail goto*//*Label 627*/ GIMT_Encode4(22065), // Rule ID 541 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7274:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AVER_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 541,
        GIR_EraseRootFromParent_Done,
      // Label 627: @22065
      GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(22110), // Rule ID 542 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7275:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AVER_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 542,
        GIR_EraseRootFromParent_Done,
      // Label 628: @22110
      GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(22155), // Rule ID 543 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7273:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AVER_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 543,
        GIR_EraseRootFromParent_Done,
      // Label 629: @22155
      GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(22200), // Rule ID 652 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7407:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DOTP_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 652,
        GIR_EraseRootFromParent_Done,
      // Label 630: @22200
      GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(22245), // Rule ID 653 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7408:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DOTP_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 653,
        GIR_EraseRootFromParent_Done,
      // Label 631: @22245
      GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(22290), // Rule ID 654 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7406:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DOTP_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 654,
        GIR_EraseRootFromParent_Done,
      // Label 632: @22290
      GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(22335), // Rule ID 655 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7410:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DOTP_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 655,
        GIR_EraseRootFromParent_Done,
      // Label 633: @22335
      GIM_Try, /*On fail goto*//*Label 634*/ GIMT_Encode4(22380), // Rule ID 656 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7411:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DOTP_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 656,
        GIR_EraseRootFromParent_Done,
      // Label 634: @22380
      GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(22425), // Rule ID 657 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7409:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DOTP_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 657,
        GIR_EraseRootFromParent_Done,
      // Label 635: @22425
      GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(22470), // Rule ID 672 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fcaf_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7449:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FCAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCAF_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 672,
        GIR_EraseRootFromParent_Done,
      // Label 636: @22470
      GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(22515), // Rule ID 673 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fcaf_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7448:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FCAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCAF_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 673,
        GIR_EraseRootFromParent_Done,
      // Label 637: @22515
      GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(22560), // Rule ID 698 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexdo_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v8f16] } 7474:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FEXDO_H:{ *:[v8f16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXDO_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 698,
        GIR_EraseRootFromParent_Done,
      // Label 638: @22560
      GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(22605), // Rule ID 699 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexdo_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v4f32] } 7475:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FEXDO_W:{ *:[v4f32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXDO_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 699,
        GIR_EraseRootFromParent_Done,
      // Label 639: @22605
      GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(22650), // Rule ID 726 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4f32] } 7501:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMAX_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 726,
        GIR_EraseRootFromParent_Done,
      // Label 640: @22650
      GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(22695), // Rule ID 727 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2f64] } 7500:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMAX_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 727,
        GIR_EraseRootFromParent_Done,
      // Label 641: @22695
      GIM_Try, /*On fail goto*//*Label 642*/ GIMT_Encode4(22740), // Rule ID 728 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_a_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4f32] } 7499:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMAX_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_A_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 728,
        GIR_EraseRootFromParent_Done,
      // Label 642: @22740
      GIM_Try, /*On fail goto*//*Label 643*/ GIMT_Encode4(22785), // Rule ID 729 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_a_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2f64] } 7498:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMAX_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_A_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 729,
        GIR_EraseRootFromParent_Done,
      // Label 643: @22785
      GIM_Try, /*On fail goto*//*Label 644*/ GIMT_Encode4(22830), // Rule ID 730 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4f32] } 7505:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMIN_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 730,
        GIR_EraseRootFromParent_Done,
      // Label 644: @22830
      GIM_Try, /*On fail goto*//*Label 645*/ GIMT_Encode4(22875), // Rule ID 731 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2f64] } 7504:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMIN_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 731,
        GIR_EraseRootFromParent_Done,
      // Label 645: @22875
      GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(22920), // Rule ID 732 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_a_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4f32] } 7503:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMIN_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_A_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 732,
        GIR_EraseRootFromParent_Done,
      // Label 646: @22920
      GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(22965), // Rule ID 733 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_a_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2f64] } 7502:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMIN_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_A_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 733,
        GIR_EraseRootFromParent_Done,
      // Label 647: @22965
      GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(23010), // Rule ID 744 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsaf_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7517:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSAF_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 744,
        GIR_EraseRootFromParent_Done,
      // Label 648: @23010
      GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(23055), // Rule ID 745 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsaf_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7516:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSAF_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 745,
        GIR_EraseRootFromParent_Done,
      // Label 649: @23055
      GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(23100), // Rule ID 746 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fseq_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7519:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSEQ_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 746,
        GIR_EraseRootFromParent_Done,
      // Label 650: @23100
      GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(23145), // Rule ID 747 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fseq_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7518:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSEQ_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 747,
        GIR_EraseRootFromParent_Done,
      // Label 651: @23145
      GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(23190), // Rule ID 748 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsle_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7521:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSLE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLE_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 748,
        GIR_EraseRootFromParent_Done,
      // Label 652: @23190
      GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(23235), // Rule ID 749 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsle_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7520:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSLE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLE_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 749,
        GIR_EraseRootFromParent_Done,
      // Label 653: @23235
      GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(23280), // Rule ID 750 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fslt_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7523:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSLT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLT_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 750,
        GIR_EraseRootFromParent_Done,
      // Label 654: @23280
      GIM_Try, /*On fail goto*//*Label 655*/ GIMT_Encode4(23325), // Rule ID 751 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fslt_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7522:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSLT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLT_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 751,
        GIR_EraseRootFromParent_Done,
      // Label 655: @23325
      GIM_Try, /*On fail goto*//*Label 656*/ GIMT_Encode4(23370), // Rule ID 752 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsne_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7525:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSNE_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 752,
        GIR_EraseRootFromParent_Done,
      // Label 656: @23370
      GIM_Try, /*On fail goto*//*Label 657*/ GIMT_Encode4(23415), // Rule ID 753 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsne_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7524:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSNE_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 753,
        GIR_EraseRootFromParent_Done,
      // Label 657: @23415
      GIM_Try, /*On fail goto*//*Label 658*/ GIMT_Encode4(23460), // Rule ID 754 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsor_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7527:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSOR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSOR_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 754,
        GIR_EraseRootFromParent_Done,
      // Label 658: @23460
      GIM_Try, /*On fail goto*//*Label 659*/ GIMT_Encode4(23505), // Rule ID 755 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsor_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7526:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSOR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSOR_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 755,
        GIR_EraseRootFromParent_Done,
      // Label 659: @23505
      GIM_Try, /*On fail goto*//*Label 660*/ GIMT_Encode4(23550), // Rule ID 760 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsueq_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7533:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSUEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUEQ_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 760,
        GIR_EraseRootFromParent_Done,
      // Label 660: @23550
      GIM_Try, /*On fail goto*//*Label 661*/ GIMT_Encode4(23595), // Rule ID 761 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsueq_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7532:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSUEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUEQ_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 761,
        GIR_EraseRootFromParent_Done,
      // Label 661: @23595
      GIM_Try, /*On fail goto*//*Label 662*/ GIMT_Encode4(23640), // Rule ID 762 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsule_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7535:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSULE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULE_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 762,
        GIR_EraseRootFromParent_Done,
      // Label 662: @23640
      GIM_Try, /*On fail goto*//*Label 663*/ GIMT_Encode4(23685), // Rule ID 763 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsule_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7534:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSULE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULE_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 763,
        GIR_EraseRootFromParent_Done,
      // Label 663: @23685
      GIM_Try, /*On fail goto*//*Label 664*/ GIMT_Encode4(23730), // Rule ID 764 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsult_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7537:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSULT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULT_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 764,
        GIR_EraseRootFromParent_Done,
      // Label 664: @23730
      GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(23775), // Rule ID 765 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsult_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7536:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSULT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULT_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 765,
        GIR_EraseRootFromParent_Done,
      // Label 665: @23775
      GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(23820), // Rule ID 766 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsun_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7539:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSUN_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUN_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 766,
        GIR_EraseRootFromParent_Done,
      // Label 666: @23820
      GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(23865), // Rule ID 767 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsun_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7538:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSUN_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUN_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 767,
        GIR_EraseRootFromParent_Done,
      // Label 667: @23865
      GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(23910), // Rule ID 768 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsune_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7541:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSUNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUNE_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 768,
        GIR_EraseRootFromParent_Done,
      // Label 668: @23910
      GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(23955), // Rule ID 769 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsune_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7540:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSUNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUNE_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 769,
        GIR_EraseRootFromParent_Done,
      // Label 669: @23955
      GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(24000), // Rule ID 774 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftq_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7546:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FTQ_H:{ *:[v8i16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTQ_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 774,
        GIR_EraseRootFromParent_Done,
      // Label 670: @24000
      GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(24045), // Rule ID 775 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftq_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7547:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FTQ_W:{ *:[v4i32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTQ_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 775,
        GIR_EraseRootFromParent_Done,
      // Label 671: @24045
      GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(24090), // Rule ID 780 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7553:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (HADD_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 780,
        GIR_EraseRootFromParent_Done,
      // Label 672: @24090
      GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(24135), // Rule ID 781 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7554:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (HADD_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 781,
        GIR_EraseRootFromParent_Done,
      // Label 673: @24135
      GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(24180), // Rule ID 782 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7552:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (HADD_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 782,
        GIR_EraseRootFromParent_Done,
      // Label 674: @24180
      GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(24225), // Rule ID 783 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7556:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (HADD_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 783,
        GIR_EraseRootFromParent_Done,
      // Label 675: @24225
      GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(24270), // Rule ID 784 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7557:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (HADD_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 784,
        GIR_EraseRootFromParent_Done,
      // Label 676: @24270
      GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(24315), // Rule ID 785 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7555:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (HADD_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 785,
        GIR_EraseRootFromParent_Done,
      // Label 677: @24315
      GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(24360), // Rule ID 786 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7559:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (HSUB_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 786,
        GIR_EraseRootFromParent_Done,
      // Label 678: @24360
      GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(24405), // Rule ID 787 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7560:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (HSUB_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 787,
        GIR_EraseRootFromParent_Done,
      // Label 679: @24405
      GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(24450), // Rule ID 788 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7558:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (HSUB_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 788,
        GIR_EraseRootFromParent_Done,
      // Label 680: @24450
      GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(24495), // Rule ID 789 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7562:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (HSUB_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 789,
        GIR_EraseRootFromParent_Done,
      // Label 681: @24495
      GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(24540), // Rule ID 790 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7563:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (HSUB_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 790,
        GIR_EraseRootFromParent_Done,
      // Label 682: @24540
      GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(24585), // Rule ID 791 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7561:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (HSUB_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 791,
        GIR_EraseRootFromParent_Done,
      // Label 683: @24585
      GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(24630), // Rule ID 844 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7617:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MAX_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 844,
        GIR_EraseRootFromParent_Done,
      // Label 684: @24630
      GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(24675), // Rule ID 845 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7619:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MAX_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 845,
        GIR_EraseRootFromParent_Done,
      // Label 685: @24675
      GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(24720), // Rule ID 846 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7620:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MAX_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 846,
        GIR_EraseRootFromParent_Done,
      // Label 686: @24720
      GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(24765), // Rule ID 847 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7618:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MAX_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 847,
        GIR_EraseRootFromParent_Done,
      // Label 687: @24765
      GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(24810), // Rule ID 864 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7637:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MIN_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 864,
        GIR_EraseRootFromParent_Done,
      // Label 688: @24810
      GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(24855), // Rule ID 865 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7639:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MIN_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 865,
        GIR_EraseRootFromParent_Done,
      // Label 689: @24855
      GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(24900), // Rule ID 866 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7640:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MIN_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 866,
        GIR_EraseRootFromParent_Done,
      // Label 690: @24900
      GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(24945), // Rule ID 867 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7638:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MIN_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 867,
        GIR_EraseRootFromParent_Done,
      // Label 691: @24945
      GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(24990), // Rule ID 900 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_q_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7679:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MUL_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_Q_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 900,
        GIR_EraseRootFromParent_Done,
      // Label 692: @24990
      GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(25035), // Rule ID 901 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_q_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7680:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MUL_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_Q_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 901,
        GIR_EraseRootFromParent_Done,
      // Label 693: @25035
      GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(25080), // Rule ID 902 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulr_q_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7690:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MULR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULR_Q_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 902,
        GIR_EraseRootFromParent_Done,
      // Label 694: @25080
      GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(25125), // Rule ID 903 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulr_q_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7691:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MULR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULR_Q_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 903,
        GIR_EraseRootFromParent_Done,
      // Label 695: @25125
      GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(25170), // Rule ID 981 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7804:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SRAR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 981,
        GIR_EraseRootFromParent_Done,
      // Label 696: @25170
      GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(25215), // Rule ID 982 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7806:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SRAR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 982,
        GIR_EraseRootFromParent_Done,
      // Label 697: @25215
      GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(25260), // Rule ID 983 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7807:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SRAR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 983,
        GIR_EraseRootFromParent_Done,
      // Label 698: @25260
      GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(25305), // Rule ID 984 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7805:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SRAR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 984,
        GIR_EraseRootFromParent_Done,
      // Label 699: @25305
      GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(25350), // Rule ID 997 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7820:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SRLR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 997,
        GIR_EraseRootFromParent_Done,
      // Label 700: @25350
      GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(25395), // Rule ID 998 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7822:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SRLR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 998,
        GIR_EraseRootFromParent_Done,
      // Label 701: @25395
      GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(25440), // Rule ID 999 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7823:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SRLR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 999,
        GIR_EraseRootFromParent_Done,
      // Label 702: @25440
      GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(25485), // Rule ID 1000 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7821:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SRLR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1000,
        GIR_EraseRootFromParent_Done,
      // Label 703: @25485
      GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(25530), // Rule ID 1009 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7841:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1009,
        GIR_EraseRootFromParent_Done,
      // Label 704: @25530
      GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(25575), // Rule ID 1010 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7843:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1010,
        GIR_EraseRootFromParent_Done,
      // Label 705: @25575
      GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(25620), // Rule ID 1011 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7844:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1011,
        GIR_EraseRootFromParent_Done,
      // Label 706: @25620
      GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(25665), // Rule ID 1012 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7842:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1012,
        GIR_EraseRootFromParent_Done,
      // Label 707: @25665
      GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(25710), // Rule ID 1013 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7845:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1013,
        GIR_EraseRootFromParent_Done,
      // Label 708: @25710
      GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(25755), // Rule ID 1014 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7847:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1014,
        GIR_EraseRootFromParent_Done,
      // Label 709: @25755
      GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(25800), // Rule ID 1015 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7848:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1015,
        GIR_EraseRootFromParent_Done,
      // Label 710: @25800
      GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(25845), // Rule ID 1016 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7846:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1016,
        GIR_EraseRootFromParent_Done,
      // Label 711: @25845
      GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(25890), // Rule ID 1017 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7849:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBSUS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1017,
        GIR_EraseRootFromParent_Done,
      // Label 712: @25890
      GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(25935), // Rule ID 1018 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7851:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBSUS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1018,
        GIR_EraseRootFromParent_Done,
      // Label 713: @25935
      GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(25980), // Rule ID 1019 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7852:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBSUS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1019,
        GIR_EraseRootFromParent_Done,
      // Label 714: @25980
      GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(26025), // Rule ID 1020 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7850:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBSUS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1020,
        GIR_EraseRootFromParent_Done,
      // Label 715: @26025
      GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(26070), // Rule ID 1021 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7853:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBSUU_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1021,
        GIR_EraseRootFromParent_Done,
      // Label 716: @26070
      GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(26115), // Rule ID 1022 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7855:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBSUU_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1022,
        GIR_EraseRootFromParent_Done,
      // Label 717: @26115
      GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(26160), // Rule ID 1023 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7856:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBSUU_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1023,
        GIR_EraseRootFromParent_Done,
      // Label 718: @26160
      GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(26205), // Rule ID 1024 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7854:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBSUU_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // ws
        GIR_RootToRootCopy, /*OpIdx*/3, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1024,
        GIR_EraseRootFromParent_Done,
      // Label 719: @26205
      GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(26253), // Rule ID 1223 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7215:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_PH_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1223,
        GIR_EraseRootFromParent_Done,
      // Label 720: @26253
      GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(26301), // Rule ID 1225 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7237:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_QB_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1225,
        GIR_EraseRootFromParent_Done,
      // Label 721: @26301
      GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(26346), // Rule ID 1246 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7765:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRAV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_PH_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1246,
        GIR_EraseRootFromParent_Done,
      // Label 722: @26346
      GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(26391), // Rule ID 1247 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7767:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRAV_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_PH_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1247,
        GIR_EraseRootFromParent_Done,
      // Label 723: @26391
      GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(26436), // Rule ID 1248 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 7769:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRAV_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_W_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1248,
        GIR_EraseRootFromParent_Done,
      // Label 724: @26436
      GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(26481), // Rule ID 1250 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7771:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_QB_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1250,
        GIR_EraseRootFromParent_Done,
      // Label 725: @26481
      GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(26529), // Rule ID 1261 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7835:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_PH_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1261,
        GIR_EraseRootFromParent_Done,
      // Label 726: @26529
      GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(26577), // Rule ID 1263 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7860:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_QB_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1263,
        GIR_EraseRootFromParent_Done,
      // Label 727: @26577
      GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(26622), // Rule ID 1273 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_ph_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7740:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (PRECRQ_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_PH_W_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1273,
        GIR_EraseRootFromParent_Done,
      // Label 728: @26622
      GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(26667), // Rule ID 1274 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_qb_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7741:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECRQ_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_QB_PH_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1274,
        GIR_EraseRootFromParent_Done,
      // Label 729: @26667
      GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(26712), // Rule ID 1293 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_packrl_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7712:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PACKRL_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PACKRL_PH_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1293,
        GIR_EraseRootFromParent_Done,
      // Label 730: @26712
      GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(26757), // Rule ID 1299 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_modsub),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 7665:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODSUB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MODSUB_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1299,
        GIR_EraseRootFromParent_Done,
      // Label 731: @26757
      GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(26802), // Rule ID 1312 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7217:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_PH_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1312,
        GIR_EraseRootFromParent_Done,
      // Label 732: @26802
      GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(26847), // Rule ID 1313 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7218:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_PH_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1313,
        GIR_EraseRootFromParent_Done,
      // Label 733: @26847
      GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(26892), // Rule ID 1314 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 7220:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_W_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1314,
        GIR_EraseRootFromParent_Done,
      // Label 734: @26892
      GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(26937), // Rule ID 1315 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 7219:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_W_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1315,
        GIR_EraseRootFromParent_Done,
      // Label 735: @26937
      GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(26982), // Rule ID 1318 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7238:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_QB_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1318,
        GIR_EraseRootFromParent_Done,
      // Label 736: @26982
      GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(27027), // Rule ID 1319 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_r_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7239:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_R_QB_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1319,
        GIR_EraseRootFromParent_Done,
      // Label 737: @27027
      GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(27072), // Rule ID 1325 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7766:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRAV_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_QB_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1325,
        GIR_EraseRootFromParent_Done,
      // Label 738: @27072
      GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(27117), // Rule ID 1326 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7768:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRAV_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_QB_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1326,
        GIR_EraseRootFromParent_Done,
      // Label 739: @27117
      GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(27162), // Rule ID 1331 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7770:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRLV_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_PH_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1331,
        GIR_EraseRootFromParent_Done,
      // Label 740: @27162
      GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(27207), // Rule ID 1332 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7837:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_PH_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1332,
        GIR_EraseRootFromParent_Done,
      // Label 741: @27207
      GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(27252), // Rule ID 1333 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7838:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_PH_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1333,
        GIR_EraseRootFromParent_Done,
      // Label 742: @27252
      GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(27297), // Rule ID 1334 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 7840:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_W_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1334,
        GIR_EraseRootFromParent_Done,
      // Label 743: @27297
      GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(27342), // Rule ID 1335 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 7839:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_W_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1335,
        GIR_EraseRootFromParent_Done,
      // Label 744: @27342
      GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(27387), // Rule ID 1338 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7861:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_QB_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1338,
        GIR_EraseRootFromParent_Done,
      // Label 745: @27387
      GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(27432), // Rule ID 1339 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_r_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7862:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_R_QB_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1339,
        GIR_EraseRootFromParent_Done,
      // Label 746: @27432
      GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(27472), // Rule ID 1916 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7214:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // a
        GIR_RootToRootCopy, /*OpIdx*/3, // b
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1916,
        GIR_EraseRootFromParent_Done,
      // Label 747: @27472
      GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(27512), // Rule ID 1918 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7834:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // a
        GIR_RootToRootCopy, /*OpIdx*/3, // b
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1918,
        GIR_EraseRootFromParent_Done,
      // Label 748: @27512
      GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(27552), // Rule ID 1922 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7235:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // a
        GIR_RootToRootCopy, /*OpIdx*/3, // b
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1922,
        GIR_EraseRootFromParent_Done,
      // Label 749: @27552
      GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(27592), // Rule ID 1924 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i8] } 7858:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // a
        GIR_RootToRootCopy, /*OpIdx*/3, // b
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1924,
        GIR_EraseRootFromParent_Done,
      // Label 750: @27592
      GIM_Reject,
    // Label 536: @27593
    GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(30107),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
      GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(27656), // Rule ID 477 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_ph_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // MIs[0] sa
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7738:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PRECR_SRA_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_PH_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_RootToRootCopy, /*OpIdx*/4, // sa
        GIR_RootToRootCopy, /*OpIdx*/2, // src
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 477,
        GIR_EraseRootFromParent_Done,
      // Label 752: @27656
      GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(27711), // Rule ID 478 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_r_ph_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // MIs[0] sa
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7739:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PRECR_SRA_R_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_R_PH_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_RootToRootCopy, /*OpIdx*/4, // sa
        GIR_RootToRootCopy, /*OpIdx*/2, // src
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 478,
        GIR_EraseRootFromParent_Done,
      // Label 753: @27711
      GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(27766), // Rule ID 483 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_append),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // MIs[0] sa
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
        // (intrinsic_wo_chain:{ *:[i32] } 7251:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (APPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::APPEND),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_RootToRootCopy, /*OpIdx*/4, // sa
        GIR_RootToRootCopy, /*OpIdx*/2, // src
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 483,
        GIR_EraseRootFromParent_Done,
      // Label 754: @27766
      GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(27821), // Rule ID 484 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_balign),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // MIs[0] sa
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt2),
        // (intrinsic_wo_chain:{ *:[i32] } 7276:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt2>>:$sa)  =>  (BALIGN:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BALIGN),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_RootToRootCopy, /*OpIdx*/4, // sa
        GIR_RootToRootCopy, /*OpIdx*/2, // src
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 484,
        GIR_EraseRootFromParent_Done,
      // Label 755: @27821
      GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(27876), // Rule ID 485 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_prepend),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // MIs[0] sa
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
        // (intrinsic_wo_chain:{ *:[i32] } 7744:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PREPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PREPEND),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_RootToRootCopy, /*OpIdx*/4, // sa
        GIR_RootToRootCopy, /*OpIdx*/2, // src
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 485,
        GIR_EraseRootFromParent_Done,
      // Label 756: @27876
      GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(27931), // Rule ID 953 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // MIs[0] n
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7776:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$n)  =>  (SLDI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$n)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // n
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 953,
        GIR_EraseRootFromParent_Done,
      // Label 757: @27931
      GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(27986), // Rule ID 954 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // MIs[0] n
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7778:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$n)  =>  (SLDI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$n)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // n
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 954,
        GIR_EraseRootFromParent_Done,
      // Label 758: @27986
      GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(28041), // Rule ID 955 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // MIs[0] n
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt2),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7779:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt2>>:$n)  =>  (SLDI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$n)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // n
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 955,
        GIR_EraseRootFromParent_Done,
      // Label 759: @28041
      GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(28096), // Rule ID 956 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // MIs[0] n
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt1),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7777:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt1>>:$n)  =>  (SLDI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$n)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // n
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 956,
        GIR_EraseRootFromParent_Done,
      // Label 760: @28096
      GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(28151), // Rule ID 1349 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_ph_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // MIs[0] sa
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7738:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PRECR_SRA_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_PH_W_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_RootToRootCopy, /*OpIdx*/4, // sa
        GIR_RootToRootCopy, /*OpIdx*/2, // src
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1349,
        GIR_EraseRootFromParent_Done,
      // Label 761: @28151
      GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(28206), // Rule ID 1350 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_r_ph_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // MIs[0] sa
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
        // (intrinsic_wo_chain:{ *:[v2i16] } 7739:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PRECR_SRA_R_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_R_PH_W_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_RootToRootCopy, /*OpIdx*/4, // sa
        GIR_RootToRootCopy, /*OpIdx*/2, // src
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1350,
        GIR_EraseRootFromParent_Done,
      // Label 762: @28206
      GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(28261), // Rule ID 1351 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_prepend),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // MIs[0] sa
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
        // (intrinsic_wo_chain:{ *:[i32] } 7744:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PREPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PREPEND_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_RootToRootCopy, /*OpIdx*/4, // sa
        GIR_RootToRootCopy, /*OpIdx*/2, // src
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1351,
        GIR_EraseRootFromParent_Done,
      // Label 763: @28261
      GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(28316), // Rule ID 1352 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_append),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // MIs[0] sa
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
        // (intrinsic_wo_chain:{ *:[i32] } 7251:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (APPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::APPEND_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_RootToRootCopy, /*OpIdx*/4, // sa
        GIR_RootToRootCopy, /*OpIdx*/2, // src
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1352,
        GIR_EraseRootFromParent_Done,
      // Label 764: @28316
      GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(28378), // Rule ID 1327 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_balign),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // MIs[0] bp
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (intrinsic_wo_chain:{ *:[i32] } 7276:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$bp)  =>  (BALIGN_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$bp, GPR32Opnd:{ *:[i32] }:$src)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BALIGN_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // bp
        GIR_RootToRootCopy, /*OpIdx*/2, // src
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1327,
        GIR_EraseRootFromParent_Done,
      // Label 765: @28378
      GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(28432), // Rule ID 552 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7285:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (BINSL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 552,
        GIR_EraseRootFromParent_Done,
      // Label 766: @28432
      GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(28486), // Rule ID 553 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7287:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (BINSL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 553,
        GIR_EraseRootFromParent_Done,
      // Label 767: @28486
      GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(28540), // Rule ID 554 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7288:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (BINSL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 554,
        GIR_EraseRootFromParent_Done,
      // Label 768: @28540
      GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(28594), // Rule ID 555 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7286:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (BINSL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 555,
        GIR_EraseRootFromParent_Done,
      // Label 769: @28594
      GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(28648), // Rule ID 560 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7293:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (BINSR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 560,
        GIR_EraseRootFromParent_Done,
      // Label 770: @28648
      GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(28702), // Rule ID 561 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7295:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (BINSR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 561,
        GIR_EraseRootFromParent_Done,
      // Label 771: @28702
      GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(28756), // Rule ID 562 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7296:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (BINSR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 562,
        GIR_EraseRootFromParent_Done,
      // Label 772: @28756
      GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(28810), // Rule ID 563 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7294:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (BINSR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 563,
        GIR_EraseRootFromParent_Done,
      // Label 773: @28810
      GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(28864), // Rule ID 658 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7414:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DPADD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 658,
        GIR_EraseRootFromParent_Done,
      // Label 774: @28864
      GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(28918), // Rule ID 659 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7415:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DPADD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 659,
        GIR_EraseRootFromParent_Done,
      // Label 775: @28918
      GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(28972), // Rule ID 660 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7413:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DPADD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 660,
        GIR_EraseRootFromParent_Done,
      // Label 776: @28972
      GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(29026), // Rule ID 661 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7417:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DPADD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 661,
        GIR_EraseRootFromParent_Done,
      // Label 777: @29026
      GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(29080), // Rule ID 662 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7418:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DPADD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 662,
        GIR_EraseRootFromParent_Done,
      // Label 778: @29080
      GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(29134), // Rule ID 663 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7416:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DPADD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 663,
        GIR_EraseRootFromParent_Done,
      // Label 779: @29134
      GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(29188), // Rule ID 664 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7434:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DPSUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 664,
        GIR_EraseRootFromParent_Done,
      // Label 780: @29188
      GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(29242), // Rule ID 665 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7435:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DPSUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 665,
        GIR_EraseRootFromParent_Done,
      // Label 781: @29242
      GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(29296), // Rule ID 666 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7433:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DPSUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 666,
        GIR_EraseRootFromParent_Done,
      // Label 782: @29296
      GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(29350), // Rule ID 667 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7437:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DPSUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 667,
        GIR_EraseRootFromParent_Done,
      // Label 783: @29350
      GIM_Try, /*On fail goto*//*Label 784*/ GIMT_Encode4(29404), // Rule ID 668 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7438:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DPSUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 668,
        GIR_EraseRootFromParent_Done,
      // Label 784: @29404
      GIM_Try, /*On fail goto*//*Label 785*/ GIMT_Encode4(29458), // Rule ID 669 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7436:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DPSUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 669,
        GIR_EraseRootFromParent_Done,
      // Label 785: @29458
      GIM_Try, /*On fail goto*//*Label 786*/ GIMT_Encode4(29512), // Rule ID 836 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_madd_q_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7604:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MADD_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_Q_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 836,
        GIR_EraseRootFromParent_Done,
      // Label 786: @29512
      GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(29566), // Rule ID 837 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_madd_q_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7605:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MADD_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_Q_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 837,
        GIR_EraseRootFromParent_Done,
      // Label 787: @29566
      GIM_Try, /*On fail goto*//*Label 788*/ GIMT_Encode4(29620), // Rule ID 838 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_maddr_q_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7606:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MADDR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDR_Q_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 838,
        GIR_EraseRootFromParent_Done,
      // Label 788: @29620
      GIM_Try, /*On fail goto*//*Label 789*/ GIMT_Encode4(29674), // Rule ID 839 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_maddr_q_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7607:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MADDR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDR_Q_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 839,
        GIR_EraseRootFromParent_Done,
      // Label 789: @29674
      GIM_Try, /*On fail goto*//*Label 790*/ GIMT_Encode4(29728), // Rule ID 892 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msub_q_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7668:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MSUB_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_Q_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 892,
        GIR_EraseRootFromParent_Done,
      // Label 790: @29728
      GIM_Try, /*On fail goto*//*Label 791*/ GIMT_Encode4(29782), // Rule ID 893 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msub_q_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7669:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MSUB_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_Q_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 893,
        GIR_EraseRootFromParent_Done,
      // Label 791: @29782
      GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(29836), // Rule ID 894 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msubr_q_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7670:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MSUBR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBR_Q_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 894,
        GIR_EraseRootFromParent_Done,
      // Label 792: @29836
      GIM_Try, /*On fail goto*//*Label 793*/ GIMT_Encode4(29890), // Rule ID 895 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msubr_q_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7671:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MSUBR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBR_Q_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // wt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 895,
        GIR_EraseRootFromParent_Done,
      // Label 793: @29890
      GIM_Try, /*On fail goto*//*Label 794*/ GIMT_Encode4(29944), // Rule ID 949 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_b),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v16i8] } 7772:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SLD_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_B),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 949,
        GIR_EraseRootFromParent_Done,
      // Label 794: @29944
      GIM_Try, /*On fail goto*//*Label 795*/ GIMT_Encode4(29998), // Rule ID 950 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_h),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v8i16] } 7774:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SLD_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_H),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 950,
        GIR_EraseRootFromParent_Done,
      // Label 795: @29998
      GIM_Try, /*On fail goto*//*Label 796*/ GIMT_Encode4(30052), // Rule ID 951 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 7775:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SLD_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 951,
        GIR_EraseRootFromParent_Done,
      // Label 796: @30052
      GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(30106), // Rule ID 952 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_d),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
        GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_wo_chain:{ *:[v2i64] } 7773:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SLD_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_D),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
        GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
        GIR_RootToRootCopy, /*OpIdx*/3, // ws
        GIR_RootToRootCopy, /*OpIdx*/4, // rt
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 952,
        GIR_EraseRootFromParent_Done,
      // Label 797: @30106
      GIM_Reject,
    // Label 751: @30107
    GIM_Reject,
    // Label 18: @30108
    GIM_Try, /*On fail goto*//*Label 798*/ GIMT_Encode4(30139), // Rule ID 354 //
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bposge32),
      GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
      GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
      // (intrinsic_w_chain:{ *:[i32] } 7319:{ *:[iPTR] })  =>  (BPOSGE32_PSEUDO:{ *:[i32] })
      GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BPOSGE32_PSEUDO),
      GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_RootConstrainSelectedInstOperands,
      // GIR_Coverage, 354,
      GIR_EraseRootFromParent_Done,
    // Label 798: @30139
    GIM_Try, /*On fail goto*//*Label 799*/ GIMT_Encode4(31076),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
      GIM_Try, /*On fail goto*//*Label 800*/ GIMT_Encode4(30188), // Rule ID 441 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_rddsp),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // MIs[0] mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt10),
        // (intrinsic_w_chain:{ *:[i32] } 7746:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timmZExt10>>:$mask)  =>  (RDDSP:{ *:[i32] } (timm:{ *:[i32] }):$mask)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RDDSP),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // mask
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 441,
        GIR_EraseRootFromParent_Done,
      // Label 800: @30188
      GIM_Try, /*On fail goto*//*Label 801*/ GIMT_Encode4(30224), // Rule ID 1287 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_rddsp),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // MIs[0] mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        // (intrinsic_w_chain:{ *:[i32] } 7746:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timmZExt7>>:$mask)  =>  (RDDSP_MM:{ *:[i32] } (timm:{ *:[i32] }):$mask)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RDDSP_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // mask
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1287,
        GIR_EraseRootFromParent_Done,
      // Label 801: @30224
      GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(30265), // Rule ID 442 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_NotInMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_wrdsp),
        GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // MIs[0] mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt10),
        // (intrinsic_void 7875:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt10>>:$mask)  =>  (WRDSP GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$mask)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::WRDSP),
        GIR_RootToRootCopy, /*OpIdx*/1, // rs
        GIR_RootToRootCopy, /*OpIdx*/2, // mask
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 442,
        GIR_EraseRootFromParent_Done,
      // Label 802: @30265
      GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(30301), // Rule ID 1298 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_wrdsp),
        GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // MIs[0] mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        // (intrinsic_void 7875:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] })<<P:Predicate_timmZExt7>>:$mask)  =>  (WRDSP_MM GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] }):$mask)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::WRDSP_MM),
        GIR_RootToRootCopy, /*OpIdx*/1, // rt
        GIR_RootToRootCopy, /*OpIdx*/2, // mask
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1298,
        GIR_EraseRootFromParent_Done,
      // Label 803: @30301
      GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(30344), // Rule ID 363 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7207:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ABSQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 363,
        GIR_EraseRootFromParent_Done,
      // Label 804: @30344
      GIM_Try, /*On fail goto*//*Label 805*/ GIMT_Encode4(30387), // Rule ID 364 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7209:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ABSQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 364,
        GIR_EraseRootFromParent_Done,
      // Label 805: @30387
      GIM_Try, /*On fail goto*//*Label 806*/ GIMT_Encode4(30430), // Rule ID 450 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v4i8] } 7208:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ABSQ_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 450,
        GIR_EraseRootFromParent_Done,
      // Label 806: @30430
      GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(30473), // Rule ID 1230 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7207:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs)  =>  (ABSQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_PH_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1230,
        GIR_EraseRootFromParent_Done,
      // Label 807: @30473
      GIM_Try, /*On fail goto*//*Label 808*/ GIMT_Encode4(30516), // Rule ID 1231 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7209:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs)  =>  (ABSQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_W_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1231,
        GIR_EraseRootFromParent_Done,
      // Label 808: @30516
      GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(30559), // Rule ID 1311 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v4i8] } 7208:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (ABSQ_S_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_QB_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1311,
        GIR_EraseRootFromParent_Done,
      // Label 809: @30559
      GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(30602), // Rule ID 417 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_eq_qb),
        GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_void 7385:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_EQ_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_EQ_QB),
        GIR_RootToRootCopy, /*OpIdx*/1, // rs
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 417,
        GIR_EraseRootFromParent_Done,
      // Label 810: @30602
      GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(30645), // Rule ID 418 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_lt_qb),
        GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_void 7387:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_LT_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LT_QB),
        GIR_RootToRootCopy, /*OpIdx*/1, // rs
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 418,
        GIR_EraseRootFromParent_Done,
      // Label 811: @30645
      GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(30688), // Rule ID 419 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_le_qb),
        GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_void 7386:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_LE_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LE_QB),
        GIR_RootToRootCopy, /*OpIdx*/1, // rs
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 419,
        GIR_EraseRootFromParent_Done,
      // Label 812: @30688
      GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(30731), // Rule ID 423 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_eq_ph),
        GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_void 7376:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_EQ_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_PH),
        GIR_RootToRootCopy, /*OpIdx*/1, // rs
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 423,
        GIR_EraseRootFromParent_Done,
      // Label 813: @30731
      GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(30774), // Rule ID 424 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_lt_ph),
        GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_void 7378:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_LT_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_PH),
        GIR_RootToRootCopy, /*OpIdx*/1, // rs
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 424,
        GIR_EraseRootFromParent_Done,
      // Label 814: @30774
      GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(30817), // Rule ID 425 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_le_ph),
        GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_void 7377:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_LE_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_PH),
        GIR_RootToRootCopy, /*OpIdx*/1, // rs
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 425,
        GIR_EraseRootFromParent_Done,
      // Label 815: @30817
      GIM_Try, /*On fail goto*//*Label 816*/ GIMT_Encode4(30860), // Rule ID 1302 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_eq_ph),
        GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_void 7376:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_EQ_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_PH_MM),
        GIR_RootToRootCopy, /*OpIdx*/1, // rs
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1302,
        GIR_EraseRootFromParent_Done,
      // Label 816: @30860
      GIM_Try, /*On fail goto*//*Label 817*/ GIMT_Encode4(30903), // Rule ID 1303 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_lt_ph),
        GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_void 7378:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_LT_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_PH_MM),
        GIR_RootToRootCopy, /*OpIdx*/1, // rs
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1303,
        GIR_EraseRootFromParent_Done,
      // Label 817: @30903
      GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(30946), // Rule ID 1304 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_le_ph),
        GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_void 7377:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_LE_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_PH_MM),
        GIR_RootToRootCopy, /*OpIdx*/1, // rs
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1304,
        GIR_EraseRootFromParent_Done,
      // Label 818: @30946
      GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(30989), // Rule ID 1308 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_eq_qb),
        GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_void 7385:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_EQ_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_EQ_QB_MM),
        GIR_RootToRootCopy, /*OpIdx*/1, // rs
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1308,
        GIR_EraseRootFromParent_Done,
      // Label 819: @30989
      GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(31032), // Rule ID 1309 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_lt_qb),
        GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_void 7387:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_LT_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LT_QB_MM),
        GIR_RootToRootCopy, /*OpIdx*/1, // rs
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1309,
        GIR_EraseRootFromParent_Done,
      // Label 820: @31032
      GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(31075), // Rule ID 1310 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_le_qb),
        GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_void 7386:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_LE_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LE_QB_MM),
        GIR_RootToRootCopy, /*OpIdx*/1, // rs
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1310,
        GIR_EraseRootFromParent_Done,
      // Label 821: @31075
      GIM_Reject,
    // Label 799: @31076
    GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(34765),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
      GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(31148), // Rule ID 382 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (intrinsic_w_chain:{ *:[v2i16] } 7763:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa)  =>  (SHLL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 382,
        GIR_EraseRootFromParent_Done,
      // Label 823: @31148
      GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(31212), // Rule ID 387 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (intrinsic_w_chain:{ *:[i32] } 7764:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa)  =>  (SHLL_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 387,
        GIR_EraseRootFromParent_Done,
      // Label 824: @31212
      GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(31276), // Rule ID 1239 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (intrinsic_w_chain:{ *:[v2i16] } 7763:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa)  =>  (SHLL_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_PH_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1239,
        GIR_EraseRootFromParent_Done,
      // Label 825: @31276
      GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(31340), // Rule ID 1244 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (intrinsic_w_chain:{ *:[i32] } 7764:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa)  =>  (SHLL_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_W_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1244,
        GIR_EraseRootFromParent_Done,
      // Label 826: @31340
      GIM_Try, /*On fail goto*//*Label 827*/ GIMT_Encode4(31395), // Rule ID 1933 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (intrinsic_w_chain:{ *:[v2i16] } 7761:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)  =>  (SHLL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // a
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1933,
        GIR_EraseRootFromParent_Done,
      // Label 827: @31395
      GIM_Try, /*On fail goto*//*Label 828*/ GIMT_Encode4(31450), // Rule ID 1939 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*NumInsns*/1,
        // (intrinsic_w_chain:{ *:[v4i8] } 7762:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)  =>  (SHLL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // a
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1939,
        GIR_EraseRootFromParent_Done,
      // Label 828: @31450
      GIM_Try, /*On fail goto*//*Label 829*/ GIMT_Encode4(31502), // Rule ID 359 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7216:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 359,
        GIR_EraseRootFromParent_Done,
      // Label 829: @31502
      GIM_Try, /*On fail goto*//*Label 830*/ GIMT_Encode4(31554), // Rule ID 360 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7836:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 360,
        GIR_EraseRootFromParent_Done,
      // Label 830: @31554
      GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(31606), // Rule ID 367 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_rs_ph_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7742:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (PRECRQ_RS_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_RS_PH_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 367,
        GIR_EraseRootFromParent_Done,
      // Label 831: @31606
      GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(31658), // Rule ID 368 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrqu_s_qb_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v4i8] } 7743:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECRQU_S_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQU_S_QB_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 368,
        GIR_EraseRootFromParent_Done,
      // Label 832: @31658
      GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(31710), // Rule ID 379 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_w_chain:{ *:[v4i8] } 7762:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHLLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 379,
        GIR_EraseRootFromParent_Done,
      // Label 833: @31710
      GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(31762), // Rule ID 381 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7761:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHLLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 381,
        GIR_EraseRootFromParent_Done,
      // Label 834: @31762
      GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(31814), // Rule ID 383 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7763:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHLLV_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 383,
        GIR_EraseRootFromParent_Done,
      // Label 835: @31814
      GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(31866), // Rule ID 388 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7764:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHLLV_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 388,
        GIR_EraseRootFromParent_Done,
      // Label 836: @31866
      GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(31918), // Rule ID 391 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbl),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7684:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEU_S_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBL),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 391,
        GIR_EraseRootFromParent_Done,
      // Label 837: @31918
      GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(31970), // Rule ID 392 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbr),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7685:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEU_S_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBR),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 392,
        GIR_EraseRootFromParent_Done,
      // Label 838: @31970
      GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(32022), // Rule ID 393 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phl),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7682:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEQ_S_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHL),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 393,
        GIR_EraseRootFromParent_Done,
      // Label 839: @32022
      GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(32074), // Rule ID 394 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phr),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7683:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEQ_S_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHR),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 394,
        GIR_EraseRootFromParent_Done,
      // Label 840: @32074
      GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(32126), // Rule ID 395 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7686:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULQ_RS_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 395,
        GIR_EraseRootFromParent_Done,
      // Label 841: @32126
      GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(32175), // Rule ID 420 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_eq_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7382:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_EQ_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 420,
        GIR_EraseRootFromParent_Done,
      // Label 842: @32175
      GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(32224), // Rule ID 421 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_lt_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7384:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LT_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 421,
        GIR_EraseRootFromParent_Done,
      // Label 843: @32224
      GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(32273), // Rule ID 422 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_le_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7383:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LE_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 422,
        GIR_EraseRootFromParent_Done,
      // Label 844: @32273
      GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(32322), // Rule ID 432 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v4i8] } 7726:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PICK_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 432,
        GIR_EraseRootFromParent_Done,
      // Label 845: @32322
      GIM_Try, /*On fail goto*//*Label 846*/ GIMT_Encode4(32371), // Rule ID 433 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7725:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PICK_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 433,
        GIR_EraseRootFromParent_Done,
      // Label 846: @32371
      GIM_Try, /*On fail goto*//*Label 847*/ GIMT_Encode4(32420), // Rule ID 437 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_insv),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7584:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)  =>  (INSV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSV),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // src
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 437,
        GIR_EraseRootFromParent_Done,
      // Label 847: @32420
      GIM_Try, /*On fail goto*//*Label 848*/ GIMT_Encode4(32472), // Rule ID 443 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7234:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 443,
        GIR_EraseRootFromParent_Done,
      // Label 848: @32472
      GIM_Try, /*On fail goto*//*Label 849*/ GIMT_Encode4(32524), // Rule ID 444 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7236:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 444,
        GIR_EraseRootFromParent_Done,
      // Label 849: @32524
      GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(32576), // Rule ID 445 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7857:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 445,
        GIR_EraseRootFromParent_Done,
      // Label 850: @32576
      GIM_Try, /*On fail goto*//*Label 851*/ GIMT_Encode4(32628), // Rule ID 446 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7859:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 446,
        GIR_EraseRootFromParent_Done,
      // Label 851: @32628
      GIM_Try, /*On fail goto*//*Label 852*/ GIMT_Encode4(32680), // Rule ID 447 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_eq_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7379:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_EQ_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 447,
        GIR_EraseRootFromParent_Done,
      // Label 852: @32680
      GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(32732), // Rule ID 448 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_lt_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7381:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LT_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 448,
        GIR_EraseRootFromParent_Done,
      // Label 853: @32732
      GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(32784), // Rule ID 449 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_le_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7380:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LE_QB),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 449,
        GIR_EraseRootFromParent_Done,
      // Label 854: @32784
      GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(32836), // Rule ID 463 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_s_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7681:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MUL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_S_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 463,
        GIR_EraseRootFromParent_Done,
      // Label 855: @32836
      GIM_Try, /*On fail goto*//*Label 856*/ GIMT_Encode4(32888), // Rule ID 464 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7689:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MULQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 464,
        GIR_EraseRootFromParent_Done,
      // Label 856: @32888
      GIM_Try, /*On fail goto*//*Label 857*/ GIMT_Encode4(32940), // Rule ID 465 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7687:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MULQ_RS_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_W),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 465,
        GIR_EraseRootFromParent_Done,
      // Label 857: @32940
      GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(32992), // Rule ID 466 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7688:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 466,
        GIR_EraseRootFromParent_Done,
      // Label 858: @32992
      GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(33041), // Rule ID 476 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_qb_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v4i8] } 7737:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECR_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_QB_PH),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 476,
        GIR_EraseRootFromParent_Done,
      // Label 859: @33041
      GIM_Try, /*On fail goto*//*Label 860*/ GIMT_Encode4(33093), // Rule ID 1224 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7216:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_W_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1224,
        GIR_EraseRootFromParent_Done,
      // Label 860: @33093
      GIM_Try, /*On fail goto*//*Label 861*/ GIMT_Encode4(33142), // Rule ID 1232 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_insv),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7584:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)  =>  (INSV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSV_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
        GIR_RootToRootCopy, /*OpIdx*/2, // src
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1232,
        GIR_EraseRootFromParent_Done,
      // Label 861: @33142
      GIM_Try, /*On fail goto*//*Label 862*/ GIMT_Encode4(33194), // Rule ID 1240 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7761:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHLLV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_PH_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1240,
        GIR_EraseRootFromParent_Done,
      // Label 862: @33194
      GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(33246), // Rule ID 1241 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7763:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHLLV_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_PH_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1241,
        GIR_EraseRootFromParent_Done,
      // Label 863: @33246
      GIM_Try, /*On fail goto*//*Label 864*/ GIMT_Encode4(33298), // Rule ID 1242 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_w_chain:{ *:[v4i8] } 7762:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHLLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_QB_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1242,
        GIR_EraseRootFromParent_Done,
      // Label 864: @33298
      GIM_Try, /*On fail goto*//*Label 865*/ GIMT_Encode4(33350), // Rule ID 1243 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7764:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHLLV_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_W_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rt
        GIR_RootToRootCopy, /*OpIdx*/3, // rs
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1243,
        GIR_EraseRootFromParent_Done,
      // Label 865: @33350
      GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(33402), // Rule ID 1262 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7836:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_W_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1262,
        GIR_EraseRootFromParent_Done,
      // Label 866: @33402
      GIM_Try, /*On fail goto*//*Label 867*/ GIMT_Encode4(33454), // Rule ID 1268 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phl),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7682:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEQ_S_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHL_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1268,
        GIR_EraseRootFromParent_Done,
      // Label 867: @33454
      GIM_Try, /*On fail goto*//*Label 868*/ GIMT_Encode4(33506), // Rule ID 1269 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phr),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7683:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEQ_S_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHR_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1269,
        GIR_EraseRootFromParent_Done,
      // Label 868: @33506
      GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(33558), // Rule ID 1270 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbl),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7684:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEU_S_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBL_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1270,
        GIR_EraseRootFromParent_Done,
      // Label 869: @33558
      GIM_Try, /*On fail goto*//*Label 870*/ GIMT_Encode4(33610), // Rule ID 1271 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbr),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7685:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEU_S_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBR_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1271,
        GIR_EraseRootFromParent_Done,
      // Label 870: @33610
      GIM_Try, /*On fail goto*//*Label 871*/ GIMT_Encode4(33662), // Rule ID 1272 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7686:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULQ_RS_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_PH_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1272,
        GIR_EraseRootFromParent_Done,
      // Label 871: @33662
      GIM_Try, /*On fail goto*//*Label 872*/ GIMT_Encode4(33714), // Rule ID 1275 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrqu_s_qb_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v4i8] } 7743:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECRQU_S_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQU_S_QB_PH_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1275,
        GIR_EraseRootFromParent_Done,
      // Label 872: @33714
      GIM_Try, /*On fail goto*//*Label 873*/ GIMT_Encode4(33766), // Rule ID 1276 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_rs_ph_w),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7742:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (PRECRQ_RS_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_RS_PH_W_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1276,
        GIR_EraseRootFromParent_Done,
      // Label 873: @33766
      GIM_Try, /*On fail goto*//*Label 874*/ GIMT_Encode4(33815), // Rule ID 1294 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7725:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PICK_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_PH_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1294,
        GIR_EraseRootFromParent_Done,
      // Label 874: @33815
      GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(33864), // Rule ID 1295 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v4i8] } 7726:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PICK_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_QB_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1295,
        GIR_EraseRootFromParent_Done,
      // Label 875: @33864
      GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(33913), // Rule ID 1305 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_eq_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7382:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_EQ_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_EQ_QB_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1305,
        GIR_EraseRootFromParent_Done,
      // Label 876: @33913
      GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(33962), // Rule ID 1306 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_lt_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7384:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_LT_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LT_QB_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1306,
        GIR_EraseRootFromParent_Done,
      // Label 877: @33962
      GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(34011), // Rule ID 1307 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_le_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7383:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_LE_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LE_QB_MM),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1307,
        GIR_EraseRootFromParent_Done,
      // Label 878: @34011
      GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(34063), // Rule ID 1316 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7234:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_PH_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1316,
        GIR_EraseRootFromParent_Done,
      // Label 879: @34063
      GIM_Try, /*On fail goto*//*Label 880*/ GIMT_Encode4(34115), // Rule ID 1317 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_ph),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[v2i16] } 7236:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_PH_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1317,
        GIR_EraseRootFromParent_Done,
      // Label 880: @34115
      GIM_Try, /*On fail goto*//*Label 881*/ GIMT_Encode4(34167), // Rule ID 1328 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_eq_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7379:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_EQ_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_EQ_QB_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1328,
        GIR_EraseRootFromParent_Done,
      // Label 881: @34167
      GIM_Try, /*On fail goto*//*Label 882*/ GIMT_Encode4(34219), // Rule ID 1329 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_lt_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7381:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_LT_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LT_QB_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1329,
        GIR_EraseRootFromParent_Done,
      // Label 882: @34219
      GIM_Try, /*On fail goto*//*Label 883*/ GIMT_Encode4(34271), // Rule ID 1330 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_le_qb),
        GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
        GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
        GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
        GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 7380:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_LE_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LE_QB_MMR2),
        GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
        GIR_RootToRootCopy, /*OpIdx*/2, // rs
        GIR_RootToRootCopy, /*OpIdx*/3, // rt
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_RootConstrainSelectedInstOperands,
        // GIR_Coverage, 1330,
        GIR_EraseRootFromParent_Done,
      // Label 883: @34271
      GIM_Try, /*On fail goto*//*Label 884*/ GIMT_Encode4(34323), // Rule ID 1336 //
        GIM_CheckFeatures, GIMT_Encode2<TRUNCATED>#undef GIMT_Encode2#undef GIMT_Encode4#undef GIMT_Encode8#endif // ifdef GET_GLOBALISEL_IMPL#ifdef GET_GLOBALISEL_PREDICATES_DECL#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL#ifdef GET_GLOBALISEL_PREDICATES_INIT#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT