llvm/lib/Target/MSP430/MSP430GenInstrInfo.inc

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Instruction Enum Values and Descriptors                             *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
namespace llvm {

namespace MSP430 {
  enum { … };

} // end namespace MSP430
} // end namespace llvm
#endif // GET_INSTRINFO_ENUM

#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM
namespace llvm {

namespace MSP430 {
namespace Sched {
  enum {
    NoInstrModel	= 0,
    SCHED_LIST_END = 1
  };
} // end namespace Sched
} // end namespace MSP430
} // end namespace llvm
#endif // GET_INSTRINFO_SCHED_ENUM

#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
namespace llvm {

struct MSP430InstrTable {
  MCInstrDesc Insts[644];
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
  MCOperandInfo OperandInfo[267];
  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
  MCPhysReg ImplicitOps[17];
};

} // end namespace llvm
#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)

#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC
namespace llvm {

static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
static constexpr unsigned MSP430ImpOpBase = sizeof MSP430InstrTable::OperandInfo / (sizeof(MCPhysReg));

extern const MSP430InstrTable MSP430Descs = {
  {
    { 643,	2,	1,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	249,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #643 = ZEXT16r
    { 642,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	208,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #642 = XOR8rr
    { 641,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	204,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #641 = XOR8rp
    { 640,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	201,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #640 = XOR8rn
    { 639,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	197,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #639 = XOR8rm
    { 638,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	194,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #638 = XOR8ri
    { 637,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #637 = XOR8rc
    { 636,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #636 = XOR8mr
    { 635,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #635 = XOR8mp
    { 634,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #634 = XOR8mn
    { 633,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #633 = XOR8mm
    { 632,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #632 = XOR8mi
    { 631,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #631 = XOR8mc
    { 630,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	185,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #630 = XOR16rr
    { 629,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	181,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #629 = XOR16rp
    { 628,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	178,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #628 = XOR16rn
    { 627,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	174,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #627 = XOR16rm
    { 626,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	171,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #626 = XOR16ri
    { 625,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	168,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #625 = XOR16rc
    { 624,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #624 = XOR16mr
    { 623,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #623 = XOR16mp
    { 622,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #622 = XOR16mn
    { 621,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #621 = XOR16mm
    { 620,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #620 = XOR16mi
    { 619,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #619 = XOR16mc
    { 618,	3,	1,	0,	0,	0,	1,	MSP430ImpOpBase + 0,	264,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #618 = Srl8
    { 617,	3,	1,	0,	0,	0,	1,	MSP430ImpOpBase + 0,	261,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #617 = Srl16
    { 616,	3,	1,	0,	0,	0,	1,	MSP430ImpOpBase + 0,	264,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #616 = Sra8
    { 615,	3,	1,	0,	0,	0,	1,	MSP430ImpOpBase + 0,	261,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #615 = Sra16
    { 614,	3,	1,	0,	0,	0,	1,	MSP430ImpOpBase + 0,	264,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #614 = Shl8
    { 613,	3,	1,	0,	0,	0,	1,	MSP430ImpOpBase + 0,	261,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #613 = Shl16
    { 612,	4,	1,	0,	0,	1,	0,	MSP430ImpOpBase + 0,	257,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #612 = Select8
    { 611,	4,	1,	0,	0,	1,	0,	MSP430ImpOpBase + 0,	253,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #611 = Select16
    { 610,	2,	1,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	249,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #610 = SWPB16r
    { 609,	1,	0,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #609 = SWPB16p
    { 608,	1,	0,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #608 = SWPB16n
    { 607,	2,	0,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	236,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #607 = SWPB16m
    { 606,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	208,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #606 = SUBC8rr
    { 605,	4,	2,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	204,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #605 = SUBC8rp
    { 604,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	201,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #604 = SUBC8rn
    { 603,	4,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	197,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #603 = SUBC8rm
    { 602,	3,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	194,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #602 = SUBC8ri
    { 601,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #601 = SUBC8rc
    { 600,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #600 = SUBC8mr
    { 599,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #599 = SUBC8mp
    { 598,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #598 = SUBC8mn
    { 597,	4,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #597 = SUBC8mm
    { 596,	3,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #596 = SUBC8mi
    { 595,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #595 = SUBC8mc
    { 594,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	185,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #594 = SUBC16rr
    { 593,	4,	2,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	181,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #593 = SUBC16rp
    { 592,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	178,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #592 = SUBC16rn
    { 591,	4,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	174,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #591 = SUBC16rm
    { 590,	3,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	171,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #590 = SUBC16ri
    { 589,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	168,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #589 = SUBC16rc
    { 588,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #588 = SUBC16mr
    { 587,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #587 = SUBC16mp
    { 586,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #586 = SUBC16mn
    { 585,	4,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #585 = SUBC16mm
    { 584,	3,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #584 = SUBC16mi
    { 583,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #583 = SUBC16mc
    { 582,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	208,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #582 = SUB8rr
    { 581,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	204,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #581 = SUB8rp
    { 580,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	201,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #580 = SUB8rn
    { 579,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	197,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #579 = SUB8rm
    { 578,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	194,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #578 = SUB8ri
    { 577,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #577 = SUB8rc
    { 576,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #576 = SUB8mr
    { 575,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #575 = SUB8mp
    { 574,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #574 = SUB8mn
    { 573,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #573 = SUB8mm
    { 572,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #572 = SUB8mi
    { 571,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #571 = SUB8mc
    { 570,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	185,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #570 = SUB16rr
    { 569,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	181,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #569 = SUB16rp
    { 568,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	178,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #568 = SUB16rn
    { 567,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	174,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #567 = SUB16rm
    { 566,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	171,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #566 = SUB16ri
    { 565,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	168,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #565 = SUB16rc
    { 564,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #564 = SUB16mr
    { 563,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #563 = SUB16mp
    { 562,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #562 = SUB16mn
    { 561,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #561 = SUB16mm
    { 560,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #560 = SUB16mi
    { 559,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #559 = SUB16mc
    { 558,	2,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	249,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #558 = SEXT16r
    { 557,	1,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #557 = SEXT16p
    { 556,	1,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #556 = SEXT16n
    { 555,	2,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	236,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #555 = SEXT16m
    { 554,	2,	1,	0,	0,	0,	1,	MSP430ImpOpBase + 0,	234,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #554 = Rrcl8
    { 553,	2,	1,	0,	0,	0,	1,	MSP430ImpOpBase + 0,	223,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #553 = Rrcl16
    { 552,	2,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	251,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #552 = RRC8r
    { 551,	1,	0,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #551 = RRC8p
    { 550,	1,	0,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #550 = RRC8n
    { 549,	2,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	236,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #549 = RRC8m
    { 548,	2,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	249,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #548 = RRC16r
    { 547,	1,	0,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #547 = RRC16p
    { 546,	1,	0,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #546 = RRC16n
    { 545,	2,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	236,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #545 = RRC16m
    { 544,	2,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	251,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #544 = RRA8r
    { 543,	1,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #543 = RRA8p
    { 542,	1,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #542 = RRA8n
    { 541,	2,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	236,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #541 = RRA8m
    { 540,	2,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	249,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #540 = RRA16r
    { 539,	1,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #539 = RRA16p
    { 538,	1,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #538 = RRA16n
    { 537,	2,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	236,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #537 = RRA16m
    { 536,	0,	0,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #536 = RETI
    { 535,	0,	0,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #535 = RET
    { 534,	1,	0,	2,	0,	1,	1,	MSP430ImpOpBase + 15,	248,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #534 = PUSH8r
    { 533,	1,	0,	2,	0,	1,	1,	MSP430ImpOpBase + 15,	238,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #533 = PUSH16r
    { 532,	1,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 15,	1,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #532 = PUSH16i
    { 531,	1,	0,	2,	0,	1,	1,	MSP430ImpOpBase + 15,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #531 = PUSH16c
    { 530,	1,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 15,	238,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #530 = POP16r
    { 529,	2,	1,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	246,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #529 = MOVZX16rr8
    { 528,	3,	1,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	218,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #528 = MOVZX16rm8
    { 527,	2,	1,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	234,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #527 = MOV8rr
    { 526,	3,	2,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	243,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #526 = MOV8rp
    { 525,	2,	1,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	232,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #525 = MOV8rn
    { 524,	3,	1,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	229,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #524 = MOV8rm
    { 523,	2,	1,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	227,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #523 = MOV8ri
    { 522,	2,	1,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	225,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #522 = MOV8rc
    { 521,	3,	0,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	188,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #521 = MOV8mr
    { 520,	3,	0,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #520 = MOV8mn
    { 519,	4,	0,	6,	0,	0,	0,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #519 = MOV8mm
    { 518,	3,	0,	6,	0,	0,	0,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #518 = MOV8mi
    { 517,	3,	0,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #517 = MOV8mc
    { 516,	2,	1,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	223,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #516 = MOV16rr
    { 515,	3,	2,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	240,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #515 = MOV16rp
    { 514,	2,	1,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	221,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #514 = MOV16rn
    { 513,	3,	1,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	218,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #513 = MOV16rm
    { 512,	2,	1,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	216,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #512 = MOV16ri
    { 511,	2,	1,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	214,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #511 = MOV16rc
    { 510,	3,	0,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	165,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #510 = MOV16mr
    { 509,	3,	0,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #509 = MOV16mn
    { 508,	4,	0,	6,	0,	0,	0,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #508 = MOV16mm
    { 507,	3,	0,	6,	0,	0,	0,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #507 = MOV16mi
    { 506,	3,	0,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #506 = MOV16mc
    { 505,	1,	0,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #505 = JMP
    { 504,	2,	0,	2,	0,	1,	0,	MSP430ImpOpBase + 0,	13,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #504 = JCC
    { 503,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	208,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #503 = DADD8rr
    { 502,	4,	2,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	204,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #502 = DADD8rp
    { 501,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	201,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #501 = DADD8rn
    { 500,	4,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	197,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #500 = DADD8rm
    { 499,	3,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	194,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #499 = DADD8ri
    { 498,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #498 = DADD8rc
    { 497,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #497 = DADD8mr
    { 496,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #496 = DADD8mp
    { 495,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #495 = DADD8mn
    { 494,	4,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #494 = DADD8mm
    { 493,	3,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #493 = DADD8mi
    { 492,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #492 = DADD8mc
    { 491,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	185,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #491 = DADD16rr
    { 490,	4,	2,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	181,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #490 = DADD16rp
    { 489,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	178,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #489 = DADD16rn
    { 488,	4,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	174,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #488 = DADD16rm
    { 487,	3,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	171,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #487 = DADD16ri
    { 486,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	168,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #486 = DADD16rc
    { 485,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #485 = DADD16mr
    { 484,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #484 = DADD16mp
    { 483,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #483 = DADD16mn
    { 482,	4,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #482 = DADD16mm
    { 481,	3,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #481 = DADD16mi
    { 480,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #480 = DADD16mc
    { 479,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	234,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #479 = CMP8rr
    { 478,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	232,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #478 = CMP8rp
    { 477,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	232,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #477 = CMP8rn
    { 476,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	229,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #476 = CMP8rm
    { 475,	2,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	227,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #475 = CMP8ri
    { 474,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	225,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #474 = CMP8rc
    { 473,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #473 = CMP8mr
    { 472,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #472 = CMP8mp
    { 471,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #471 = CMP8mn
    { 470,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #470 = CMP8mm
    { 469,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #469 = CMP8mi
    { 468,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #468 = CMP8mc
    { 467,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	223,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #467 = CMP16rr
    { 466,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #466 = CMP16rp
    { 465,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #465 = CMP16rn
    { 464,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	218,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #464 = CMP16rm
    { 463,	2,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	216,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #463 = CMP16ri
    { 462,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	214,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #462 = CMP16rc
    { 461,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #461 = CMP16mr
    { 460,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #460 = CMP16mp
    { 459,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #459 = CMP16mn
    { 458,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #458 = CMP16mm
    { 457,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #457 = CMP16mi
    { 456,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #456 = CMP16mc
    { 455,	1,	0,	2,	0,	1,	6,	MSP430ImpOpBase + 8,	238,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #455 = CALLr
    { 454,	1,	0,	2,	0,	1,	6,	MSP430ImpOpBase + 8,	239,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #454 = CALLp
    { 453,	1,	0,	2,	0,	1,	6,	MSP430ImpOpBase + 8,	239,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #453 = CALLn
    { 452,	2,	0,	4,	0,	1,	6,	MSP430ImpOpBase + 8,	236,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #452 = CALLm
    { 451,	1,	0,	4,	0,	1,	6,	MSP430ImpOpBase + 8,	1,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #451 = CALLi
    { 450,	1,	0,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	238,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #450 = Br
    { 449,	2,	0,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	236,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #449 = Bm
    { 448,	1,	0,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #448 = Bi
    { 447,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	234,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #447 = BIT8rr
    { 446,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	232,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #446 = BIT8rp
    { 445,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	232,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #445 = BIT8rn
    { 444,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	229,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #444 = BIT8rm
    { 443,	2,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	227,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #443 = BIT8ri
    { 442,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	225,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #442 = BIT8rc
    { 441,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #441 = BIT8mr
    { 440,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #440 = BIT8mp
    { 439,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #439 = BIT8mn
    { 438,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #438 = BIT8mm
    { 437,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #437 = BIT8mi
    { 436,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #436 = BIT8mc
    { 435,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	223,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #435 = BIT16rr
    { 434,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #434 = BIT16rp
    { 433,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #433 = BIT16rn
    { 432,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	218,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #432 = BIT16rm
    { 431,	2,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	216,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #431 = BIT16ri
    { 430,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	214,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #430 = BIT16rc
    { 429,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #429 = BIT16mr
    { 428,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #428 = BIT16mp
    { 427,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #427 = BIT16mn
    { 426,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #426 = BIT16mm
    { 425,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #425 = BIT16mi
    { 424,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #424 = BIT16mc
    { 423,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	208,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #423 = BIS8rr
    { 422,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	204,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #422 = BIS8rp
    { 421,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	201,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #421 = BIS8rn
    { 420,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	197,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #420 = BIS8rm
    { 419,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	194,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #419 = BIS8ri
    { 418,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #418 = BIS8rc
    { 417,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #417 = BIS8mr
    { 416,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #416 = BIS8mp
    { 415,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #415 = BIS8mn
    { 414,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #414 = BIS8mm
    { 413,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #413 = BIS8mi
    { 412,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #412 = BIS8mc
    { 411,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	185,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #411 = BIS16rr
    { 410,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	181,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #410 = BIS16rp
    { 409,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	178,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #409 = BIS16rn
    { 408,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	174,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #408 = BIS16rm
    { 407,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	171,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #407 = BIS16ri
    { 406,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	168,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #406 = BIS16rc
    { 405,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #405 = BIS16mr
    { 404,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #404 = BIS16mp
    { 403,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #403 = BIS16mn
    { 402,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #402 = BIS16mm
    { 401,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #401 = BIS16mi
    { 400,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #400 = BIS16mc
    { 399,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	208,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #399 = BIC8rr
    { 398,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	204,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #398 = BIC8rp
    { 397,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	201,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #397 = BIC8rn
    { 396,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	197,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #396 = BIC8rm
    { 395,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	194,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #395 = BIC8ri
    { 394,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #394 = BIC8rc
    { 393,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #393 = BIC8mr
    { 392,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #392 = BIC8mp
    { 391,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #391 = BIC8mn
    { 390,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #390 = BIC8mm
    { 389,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #389 = BIC8mi
    { 388,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #388 = BIC8mc
    { 387,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	185,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #387 = BIC16rr
    { 386,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	181,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #386 = BIC16rp
    { 385,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	178,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #385 = BIC16rn
    { 384,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	174,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #384 = BIC16rm
    { 383,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	171,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #383 = BIC16ri
    { 382,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	168,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #382 = BIC16rc
    { 381,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #381 = BIC16mr
    { 380,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #380 = BIC16mp
    { 379,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #379 = BIC16mn
    { 378,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #378 = BIC16mm
    { 377,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #377 = BIC16mi
    { 376,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #376 = BIC16mc
    { 375,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	208,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #375 = AND8rr
    { 374,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	204,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #374 = AND8rp
    { 373,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	201,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #373 = AND8rn
    { 372,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	197,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #372 = AND8rm
    { 371,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	194,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #371 = AND8ri
    { 370,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #370 = AND8rc
    { 369,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #369 = AND8mr
    { 368,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #368 = AND8mp
    { 367,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #367 = AND8mn
    { 366,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #366 = AND8mm
    { 365,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #365 = AND8mi
    { 364,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #364 = AND8mc
    { 363,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	185,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #363 = AND16rr
    { 362,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	181,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #362 = AND16rp
    { 361,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	178,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #361 = AND16rn
    { 360,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	174,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #360 = AND16rm
    { 359,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	171,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #359 = AND16ri
    { 358,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	168,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #358 = AND16rc
    { 357,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #357 = AND16mr
    { 356,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #356 = AND16mp
    { 355,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #355 = AND16mn
    { 354,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #354 = AND16mm
    { 353,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #353 = AND16mi
    { 352,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #352 = AND16mc
    { 351,	2,	0,	0,	0,	1,	2,	MSP430ImpOpBase + 5,	21,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #351 = ADJCALLSTACKUP
    { 350,	2,	0,	0,	0,	1,	2,	MSP430ImpOpBase + 5,	21,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #350 = ADJCALLSTACKDOWN
    { 349,	3,	1,	0,	0,	1,	1,	MSP430ImpOpBase + 3,	211,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #349 = ADDframe
    { 348,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	208,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #348 = ADDC8rr
    { 347,	4,	2,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	204,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #347 = ADDC8rp
    { 346,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	201,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #346 = ADDC8rn
    { 345,	4,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	197,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #345 = ADDC8rm
    { 344,	3,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	194,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #344 = ADDC8ri
    { 343,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #343 = ADDC8rc
    { 342,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #342 = ADDC8mr
    { 341,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #341 = ADDC8mp
    { 340,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #340 = ADDC8mn
    { 339,	4,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #339 = ADDC8mm
    { 338,	3,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #338 = ADDC8mi
    { 337,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #337 = ADDC8mc
    { 336,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	185,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #336 = ADDC16rr
    { 335,	4,	2,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	181,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #335 = ADDC16rp
    { 334,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	178,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #334 = ADDC16rn
    { 333,	4,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	174,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #333 = ADDC16rm
    { 332,	3,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	171,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #332 = ADDC16ri
    { 331,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	168,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #331 = ADDC16rc
    { 330,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #330 = ADDC16mr
    { 329,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #329 = ADDC16mp
    { 328,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #328 = ADDC16mn
    { 327,	4,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #327 = ADDC16mm
    { 326,	3,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #326 = ADDC16mi
    { 325,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #325 = ADDC16mc
    { 324,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	208,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #324 = ADD8rr
    { 323,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	204,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #323 = ADD8rp
    { 322,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	201,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #322 = ADD8rn
    { 321,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	197,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #321 = ADD8rm
    { 320,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	194,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #320 = ADD8ri
    { 319,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #319 = ADD8rc
    { 318,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #318 = ADD8mr
    { 317,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #317 = ADD8mp
    { 316,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #316 = ADD8mn
    { 315,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #315 = ADD8mm
    { 314,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #314 = ADD8mi
    { 313,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #313 = ADD8mc
    { 312,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	185,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #312 = ADD16rr
    { 311,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	181,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #311 = ADD16rp
    { 310,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	178,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #310 = ADD16rn
    { 309,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	174,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #309 = ADD16rm
    { 308,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	171,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #308 = ADD16ri
    { 307,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	168,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #307 = ADD16rc
    { 306,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #306 = ADD16mr
    { 305,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #305 = ADD16mp
    { 304,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #304 = ADD16mn
    { 303,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #303 = ADD16mm
    { 302,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #302 = ADD16mi
    { 301,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #301 = ADD16mc
    { 300,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #300 = G_UBFX
    { 299,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #299 = G_SBFX
    { 298,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #298 = G_VECREDUCE_UMIN
    { 297,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #297 = G_VECREDUCE_UMAX
    { 296,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #296 = G_VECREDUCE_SMIN
    { 295,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #295 = G_VECREDUCE_SMAX
    { 294,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #294 = G_VECREDUCE_XOR
    { 293,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #293 = G_VECREDUCE_OR
    { 292,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #292 = G_VECREDUCE_AND
    { 291,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #291 = G_VECREDUCE_MUL
    { 290,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #290 = G_VECREDUCE_ADD
    { 289,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #289 = G_VECREDUCE_FMINIMUM
    { 288,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #288 = G_VECREDUCE_FMAXIMUM
    { 287,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #287 = G_VECREDUCE_FMIN
    { 286,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #286 = G_VECREDUCE_FMAX
    { 285,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #285 = G_VECREDUCE_FMUL
    { 284,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #284 = G_VECREDUCE_FADD
    { 283,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #283 = G_VECREDUCE_SEQ_FMUL
    { 282,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #282 = G_VECREDUCE_SEQ_FADD
    { 281,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #281 = G_UBSANTRAP
    { 280,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #280 = G_DEBUGTRAP
    { 279,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #279 = G_TRAP
    { 278,	3,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #278 = G_BZERO
    { 277,	4,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #277 = G_MEMSET
    { 276,	4,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #276 = G_MEMMOVE
    { 275,	3,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #275 = G_MEMCPY_INLINE
    { 274,	4,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #274 = G_MEMCPY
    { 273,	2,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	142,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #273 = G_WRITE_REGISTER
    { 272,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #272 = G_READ_REGISTER
    { 271,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #271 = G_STRICT_FLDEXP
    { 270,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #270 = G_STRICT_FSQRT
    { 269,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #269 = G_STRICT_FMA
    { 268,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #268 = G_STRICT_FREM
    { 267,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #267 = G_STRICT_FDIV
    { 266,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #266 = G_STRICT_FMUL
    { 265,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #265 = G_STRICT_FSUB
    { 264,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #264 = G_STRICT_FADD
    { 263,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #263 = G_STACKRESTORE
    { 262,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #262 = G_STACKSAVE
    { 261,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #261 = G_DYN_STACKALLOC
    { 260,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #260 = G_JUMP_TABLE
    { 259,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #259 = G_BLOCK_ADDR
    { 258,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #258 = G_ADDRSPACE_CAST
    { 257,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #257 = G_FNEARBYINT
    { 256,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #256 = G_FRINT
    { 255,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #255 = G_FFLOOR
    { 254,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #254 = G_FSQRT
    { 253,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #253 = G_FTANH
    { 252,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #252 = G_FSINH
    { 251,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #251 = G_FCOSH
    { 250,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #250 = G_FATAN
    { 249,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #249 = G_FASIN
    { 248,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #248 = G_FACOS
    { 247,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #247 = G_FTAN
    { 246,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #246 = G_FSIN
    { 245,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #245 = G_FCOS
    { 244,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #244 = G_FCEIL
    { 243,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #243 = G_BITREVERSE
    { 242,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #242 = G_BSWAP
    { 241,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #241 = G_CTPOP
    { 240,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #240 = G_CTLZ_ZERO_UNDEF
    { 239,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #239 = G_CTLZ
    { 238,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #238 = G_CTTZ_ZERO_UNDEF
    { 237,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #237 = G_CTTZ
    { 236,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	138,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #236 = G_VECTOR_COMPRESS
    { 235,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #235 = G_SPLAT_VECTOR
    { 234,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	134,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #234 = G_SHUFFLE_VECTOR
    { 233,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #233 = G_EXTRACT_VECTOR_ELT
    { 232,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	127,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #232 = G_INSERT_VECTOR_ELT
    { 231,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #231 = G_EXTRACT_SUBVECTOR
    { 230,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #230 = G_INSERT_SUBVECTOR
    { 229,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #229 = G_VSCALE
    { 228,	3,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	124,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #228 = G_BRJT
    { 227,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #227 = G_BR
    { 226,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #226 = G_LLROUND
    { 225,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #225 = G_LROUND
    { 224,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #224 = G_ABS
    { 223,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #223 = G_UMAX
    { 222,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #222 = G_UMIN
    { 221,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #221 = G_SMAX
    { 220,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #220 = G_SMIN
    { 219,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #219 = G_PTRMASK
    { 218,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #218 = G_PTR_ADD
    { 217,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #217 = G_RESET_FPMODE
    { 216,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #216 = G_SET_FPMODE
    { 215,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #215 = G_GET_FPMODE
    { 214,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #214 = G_RESET_FPENV
    { 213,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #213 = G_SET_FPENV
    { 212,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #212 = G_GET_FPENV
    { 211,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #211 = G_FMAXIMUM
    { 210,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #210 = G_FMINIMUM
    { 209,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #209 = G_FMAXNUM_IEEE
    { 208,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #208 = G_FMINNUM_IEEE
    { 207,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #207 = G_FMAXNUM
    { 206,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #206 = G_FMINNUM
    { 205,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #205 = G_FCANONICALIZE
    { 204,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #204 = G_IS_FPCLASS
    { 203,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #203 = G_FCOPYSIGN
    { 202,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #202 = G_FABS
    { 201,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #201 = G_FPTOUI_SAT
    { 200,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #200 = G_FPTOSI_SAT
    { 199,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #199 = G_UITOFP
    { 198,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #198 = G_SITOFP
    { 197,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #197 = G_FPTOUI
    { 196,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #196 = G_FPTOSI
    { 195,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #195 = G_FPTRUNC
    { 194,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #194 = G_FPEXT
    { 193,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #193 = G_FNEG
    { 192,	3,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #192 = G_FFREXP
    { 191,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #191 = G_FLDEXP
    { 190,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #190 = G_FLOG10
    { 189,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #189 = G_FLOG2
    { 188,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #188 = G_FLOG
    { 187,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #187 = G_FEXP10
    { 186,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #186 = G_FEXP2
    { 185,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #185 = G_FEXP
    { 184,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #184 = G_FPOWI
    { 183,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #183 = G_FPOW
    { 182,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #182 = G_FREM
    { 181,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #181 = G_FDIV
    { 180,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #180 = G_FMAD
    { 179,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #179 = G_FMA
    { 178,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #178 = G_FMUL
    { 177,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #177 = G_FSUB
    { 176,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #176 = G_FADD
    { 175,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #175 = G_UDIVFIXSAT
    { 174,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #174 = G_SDIVFIXSAT
    { 173,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #173 = G_UDIVFIX
    { 172,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #172 = G_SDIVFIX
    { 171,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #171 = G_UMULFIXSAT
    { 170,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #170 = G_SMULFIXSAT
    { 169,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #169 = G_UMULFIX
    { 168,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #168 = G_SMULFIX
    { 167,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #167 = G_SSHLSAT
    { 166,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #166 = G_USHLSAT
    { 165,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #165 = G_SSUBSAT
    { 164,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #164 = G_USUBSAT
    { 163,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #163 = G_SADDSAT
    { 162,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #162 = G_UADDSAT
    { 161,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #161 = G_SMULH
    { 160,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #160 = G_UMULH
    { 159,	4,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #159 = G_SMULO
    { 158,	4,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #158 = G_UMULO
    { 157,	5,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #157 = G_SSUBE
    { 156,	4,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #156 = G_SSUBO
    { 155,	5,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #155 = G_SADDE
    { 154,	4,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #154 = G_SADDO
    { 153,	5,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #153 = G_USUBE
    { 152,	4,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #152 = G_USUBO
    { 151,	5,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #151 = G_UADDE
    { 150,	4,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #150 = G_UADDO
    { 149,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #149 = G_SELECT
    { 148,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #148 = G_UCMP
    { 147,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #147 = G_SCMP
    { 146,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #146 = G_FCMP
    { 145,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #145 = G_ICMP
    { 144,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #144 = G_ROTL
    { 143,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #143 = G_ROTR
    { 142,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #142 = G_FSHR
    { 141,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #141 = G_FSHL
    { 140,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #140 = G_ASHR
    { 139,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #139 = G_LSHR
    { 138,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #138 = G_SHL
    { 137,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #137 = G_ZEXT
    { 136,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #136 = G_SEXT_INREG
    { 135,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #135 = G_SEXT
    { 134,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #134 = G_VAARG
    { 133,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #133 = G_VASTART
    { 132,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #132 = G_FCONSTANT
    { 131,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #131 = G_CONSTANT
    { 130,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #130 = G_TRUNC
    { 129,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #129 = G_ANYEXT
    { 128,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #128 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
    { 127,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #127 = G_INTRINSIC_CONVERGENT
    { 126,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #126 = G_INTRINSIC_W_SIDE_EFFECTS
    { 125,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #125 = G_INTRINSIC
    { 124,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #124 = G_INVOKE_REGION_START
    { 123,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #123 = G_BRINDIRECT
    { 122,	2,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #122 = G_BRCOND
    { 121,	4,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	94,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #121 = G_PREFETCH
    { 120,	2,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	21,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #120 = G_FENCE
    { 119,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #119 = G_ATOMICRMW_USUB_SAT
    { 118,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #118 = G_ATOMICRMW_USUB_COND
    { 117,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #117 = G_ATOMICRMW_UDEC_WRAP
    { 116,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #116 = G_ATOMICRMW_UINC_WRAP
    { 115,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #115 = G_ATOMICRMW_FMIN
    { 114,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #114 = G_ATOMICRMW_FMAX
    { 113,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #113 = G_ATOMICRMW_FSUB
    { 112,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #112 = G_ATOMICRMW_FADD
    { 111,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #111 = G_ATOMICRMW_UMIN
    { 110,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #110 = G_ATOMICRMW_UMAX
    { 109,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #109 = G_ATOMICRMW_MIN
    { 108,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #108 = G_ATOMICRMW_MAX
    { 107,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #107 = G_ATOMICRMW_XOR
    { 106,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #106 = G_ATOMICRMW_OR
    { 105,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #105 = G_ATOMICRMW_NAND
    { 104,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #104 = G_ATOMICRMW_AND
    { 103,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #103 = G_ATOMICRMW_SUB
    { 102,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #102 = G_ATOMICRMW_ADD
    { 101,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #101 = G_ATOMICRMW_XCHG
    { 100,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #100 = G_ATOMIC_CMPXCHG
    { 99,	5,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	82,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #99 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
    { 98,	5,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	77,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #98 = G_INDEXED_STORE
    { 97,	2,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #97 = G_STORE
    { 96,	5,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #96 = G_INDEXED_ZEXTLOAD
    { 95,	5,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #95 = G_INDEXED_SEXTLOAD
    { 94,	5,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #94 = G_INDEXED_LOAD
    { 93,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #93 = G_ZEXTLOAD
    { 92,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #92 = G_SEXTLOAD
    { 91,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #91 = G_LOAD
    { 90,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #90 = G_READSTEADYCOUNTER
    { 89,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #89 = G_READCYCLECOUNTER
    { 88,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #88 = G_INTRINSIC_ROUNDEVEN
    { 87,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #87 = G_INTRINSIC_LLRINT
    { 86,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #86 = G_INTRINSIC_LRINT
    { 85,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #85 = G_INTRINSIC_ROUND
    { 84,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #84 = G_INTRINSIC_TRUNC
    { 83,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #83 = G_INTRINSIC_FPTRUNC_ROUND
    { 82,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #82 = G_CONSTANT_FOLD_BARRIER
    { 81,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #81 = G_FREEZE
    { 80,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #80 = G_BITCAST
    { 79,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #79 = G_INTTOPTR
    { 78,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #78 = G_PTRTOINT
    { 77,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #77 = G_CONCAT_VECTORS
    { 76,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #76 = G_BUILD_VECTOR_TRUNC
    { 75,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #75 = G_BUILD_VECTOR
    { 74,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #74 = G_MERGE_VALUES
    { 73,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #73 = G_INSERT
    { 72,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #72 = G_UNMERGE_VALUES
    { 71,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #71 = G_EXTRACT
    { 70,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #70 = G_CONSTANT_POOL
    { 69,	5,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	53,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #69 = G_PTRAUTH_GLOBAL_VALUE
    { 68,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #68 = G_GLOBAL_VALUE
    { 67,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #67 = G_FRAME_INDEX
    { 66,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #66 = G_PHI
    { 65,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #65 = G_IMPLICIT_DEF
    { 64,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #64 = G_XOR
    { 63,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #63 = G_OR
    { 62,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #62 = G_AND
    { 61,	4,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #61 = G_UDIVREM
    { 60,	4,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #60 = G_SDIVREM
    { 59,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #59 = G_UREM
    { 58,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #58 = G_SREM
    { 57,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #57 = G_UDIV
    { 56,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #56 = G_SDIV
    { 55,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #55 = G_MUL
    { 54,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #54 = G_SUB
    { 53,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #53 = G_ADD
    { 52,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #52 = G_ASSERT_ALIGN
    { 51,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #51 = G_ASSERT_ZEXT
    { 50,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #50 = G_ASSERT_SEXT
    { 49,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #49 = CONVERGENCECTRL_GLUE
    { 48,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #48 = CONVERGENCECTRL_LOOP
    { 47,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #47 = CONVERGENCECTRL_ANCHOR
    { 46,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #46 = CONVERGENCECTRL_ENTRY
    { 45,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #45 = JUMP_TABLE_DEBUG_INFO
    { 44,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #44 = MEMBARRIER
    { 43,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #43 = FAKE_USE
    { 42,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #42 = ICALL_BRANCH_FUNNEL
    { 41,	3,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	37,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #41 = PATCHABLE_TYPED_EVENT_CALL
    { 40,	2,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	35,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #40 = PATCHABLE_EVENT_CALL
    { 39,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #39 = PATCHABLE_TAIL_CALL
    { 38,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #38 = PATCHABLE_FUNCTION_EXIT
    { 37,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #37 = PATCHABLE_RET
    { 36,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #36 = PATCHABLE_FUNCTION_ENTER
    { 35,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #35 = PATCHABLE_OP
    { 34,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #34 = FAULTING_OP
    { 33,	2,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	33,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #33 = LOCAL_ESCAPE
    { 32,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #32 = STATEPOINT
    { 31,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	30,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #31 = PREALLOCATED_ARG
    { 30,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #30 = PREALLOCATED_SETUP
    { 29,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	29,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #29 = LOAD_STACK_GUARD
    { 28,	6,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	23,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #28 = PATCHPOINT
    { 27,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #27 = FENTRY_CALL
    { 26,	2,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #26 = STACKMAP
    { 25,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	19,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #25 = ARITH_FENCE
    { 24,	4,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	15,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #24 = PSEUDO_PROBE
    { 23,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #23 = LIFETIME_END
    { 22,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #22 = LIFETIME_START
    { 21,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #21 = BUNDLE
    { 20,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #20 = COPY
    { 19,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #19 = REG_SEQUENCE
    { 18,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #18 = DBG_LABEL
    { 17,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #17 = DBG_PHI
    { 16,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #16 = DBG_INSTR_REF
    { 15,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #15 = DBG_VALUE_LIST
    { 14,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #14 = DBG_VALUE
    { 13,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #13 = COPY_TO_REGCLASS
    { 12,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #12 = SUBREG_TO_REG
    { 11,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #11 = INIT_UNDEF
    { 10,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #10 = IMPLICIT_DEF
    { 9,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	5,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #9 = INSERT_SUBREG
    { 8,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #8 = EXTRACT_SUBREG
    { 7,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #7 = KILL
    { 6,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #6 = ANNOTATION_LABEL
    { 5,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #5 = GC_LABEL
    { 4,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #4 = EH_LABEL
    { 3,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #3 = CFI_INSTRUCTION
    { 2,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #2 = INLINEASM_BR
    { 1,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1 = INLINEASM
    { 0,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #0 = PHI
  }, {
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 1 */
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
    /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
    /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 152 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 155 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 158 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 162 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 165 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 168 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 171 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 174 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 178 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 181 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
    /* 185 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 188 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 191 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 194 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 197 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 201 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 204 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
    /* 208 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 211 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 214 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 216 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 218 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 221 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 223 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 225 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 227 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 229 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 232 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 234 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 236 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 238 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 239 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 240 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
    /* 243 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
    /* 246 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 248 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 249 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
    /* 251 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
    /* 253 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 257 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 261 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 264 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
  }, {
    /* 0 */
    /* 0 */ MSP430::SR,
    /* 1 */ MSP430::SR, MSP430::SR,
    /* 3 */ MSP430::SP, MSP430::SR,
    /* 5 */ MSP430::SP, MSP430::SP, MSP430::SR,
    /* 8 */ MSP430::SP, MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::SR,
    /* 15 */ MSP430::SP, MSP430::SP,
  }
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char MSP430InstrNameData[] = {
  /* 0 */ "G_FLOG10\0"
  /* 9 */ "G_FEXP10\0"
  /* 18 */ "G_FLOG2\0"
  /* 26 */ "G_FEXP2\0"
  /* 34 */ "Sra16\0"
  /* 40 */ "Rrcl16\0"
  /* 47 */ "Shl16\0"
  /* 53 */ "Srl16\0"
  /* 59 */ "Select16\0"
  /* 68 */ "Sra8\0"
  /* 73 */ "Rrcl8\0"
  /* 79 */ "Shl8\0"
  /* 84 */ "Srl8\0"
  /* 89 */ "MOVZX16rm8\0"
  /* 100 */ "MOVZX16rr8\0"
  /* 111 */ "Select8\0"
  /* 119 */ "G_FMA\0"
  /* 125 */ "G_STRICT_FMA\0"
  /* 138 */ "G_FSUB\0"
  /* 145 */ "G_STRICT_FSUB\0"
  /* 159 */ "G_ATOMICRMW_FSUB\0"
  /* 176 */ "G_SUB\0"
  /* 182 */ "G_ATOMICRMW_SUB\0"
  /* 198 */ "JCC\0"
  /* 202 */ "G_INTRINSIC\0"
  /* 214 */ "G_FPTRUNC\0"
  /* 224 */ "G_INTRINSIC_TRUNC\0"
  /* 242 */ "G_TRUNC\0"
  /* 250 */ "G_BUILD_VECTOR_TRUNC\0"
  /* 271 */ "G_DYN_STACKALLOC\0"
  /* 288 */ "G_FMAD\0"
  /* 295 */ "G_INDEXED_SEXTLOAD\0"
  /* 314 */ "G_SEXTLOAD\0"
  /* 325 */ "G_INDEXED_ZEXTLOAD\0"
  /* 344 */ "G_ZEXTLOAD\0"
  /* 355 */ "G_INDEXED_LOAD\0"
  /* 370 */ "G_LOAD\0"
  /* 377 */ "G_VECREDUCE_FADD\0"
  /* 394 */ "G_FADD\0"
  /* 401 */ "G_VECREDUCE_SEQ_FADD\0"
  /* 422 */ "G_STRICT_FADD\0"
  /* 436 */ "G_ATOMICRMW_FADD\0"
  /* 453 */ "G_VECREDUCE_ADD\0"
  /* 469 */ "G_ADD\0"
  /* 475 */ "G_PTR_ADD\0"
  /* 485 */ "G_ATOMICRMW_ADD\0"
  /* 501 */ "G_ATOMICRMW_NAND\0"
  /* 518 */ "G_VECREDUCE_AND\0"
  /* 534 */ "G_AND\0"
  /* 540 */ "G_ATOMICRMW_AND\0"
  /* 556 */ "LIFETIME_END\0"
  /* 569 */ "G_BRCOND\0"
  /* 578 */ "G_ATOMICRMW_USUB_COND\0"
  /* 600 */ "G_LLROUND\0"
  /* 610 */ "G_LROUND\0"
  /* 619 */ "G_INTRINSIC_ROUND\0"
  /* 637 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
  /* 663 */ "LOAD_STACK_GUARD\0"
  /* 680 */ "PSEUDO_PROBE\0"
  /* 693 */ "G_SSUBE\0"
  /* 701 */ "G_USUBE\0"
  /* 709 */ "G_FENCE\0"
  /* 717 */ "ARITH_FENCE\0"
  /* 729 */ "REG_SEQUENCE\0"
  /* 742 */ "G_SADDE\0"
  /* 750 */ "G_UADDE\0"
  /* 758 */ "G_GET_FPMODE\0"
  /* 771 */ "G_RESET_FPMODE\0"
  /* 786 */ "G_SET_FPMODE\0"
  /* 799 */ "G_FMINNUM_IEEE\0"
  /* 814 */ "G_FMAXNUM_IEEE\0"
  /* 829 */ "G_VSCALE\0"
  /* 838 */ "G_JUMP_TABLE\0"
  /* 851 */ "BUNDLE\0"
  /* 858 */ "G_MEMCPY_INLINE\0"
  /* 874 */ "LOCAL_ESCAPE\0"
  /* 887 */ "G_STACKRESTORE\0"
  /* 902 */ "G_INDEXED_STORE\0"
  /* 918 */ "G_STORE\0"
  /* 926 */ "G_BITREVERSE\0"
  /* 939 */ "FAKE_USE\0"
  /* 948 */ "DBG_VALUE\0"
  /* 958 */ "G_GLOBAL_VALUE\0"
  /* 973 */ "G_PTRAUTH_GLOBAL_VALUE\0"
  /* 996 */ "CONVERGENCECTRL_GLUE\0"
  /* 1017 */ "G_STACKSAVE\0"
  /* 1029 */ "G_MEMMOVE\0"
  /* 1039 */ "G_FREEZE\0"
  /* 1048 */ "G_FCANONICALIZE\0"
  /* 1064 */ "G_CTLZ_ZERO_UNDEF\0"
  /* 1082 */ "G_CTTZ_ZERO_UNDEF\0"
  /* 1100 */ "INIT_UNDEF\0"
  /* 1111 */ "G_IMPLICIT_DEF\0"
  /* 1126 */ "DBG_INSTR_REF\0"
  /* 1140 */ "G_FNEG\0"
  /* 1147 */ "EXTRACT_SUBREG\0"
  /* 1162 */ "INSERT_SUBREG\0"
  /* 1176 */ "G_SEXT_INREG\0"
  /* 1189 */ "SUBREG_TO_REG\0"
  /* 1203 */ "G_ATOMIC_CMPXCHG\0"
  /* 1220 */ "G_ATOMICRMW_XCHG\0"
  /* 1237 */ "G_FLOG\0"
  /* 1244 */ "G_VAARG\0"
  /* 1252 */ "PREALLOCATED_ARG\0"
  /* 1269 */ "G_PREFETCH\0"
  /* 1280 */ "G_SMULH\0"
  /* 1288 */ "G_UMULH\0"
  /* 1296 */ "G_FTANH\0"
  /* 1304 */ "G_FSINH\0"
  /* 1312 */ "G_FCOSH\0"
  /* 1320 */ "DBG_PHI\0"
  /* 1328 */ "G_FPTOSI\0"
  /* 1337 */ "RETI\0"
  /* 1342 */ "G_FPTOUI\0"
  /* 1351 */ "G_FPOWI\0"
  /* 1359 */ "G_PTRMASK\0"
  /* 1369 */ "GC_LABEL\0"
  /* 1378 */ "DBG_LABEL\0"
  /* 1388 */ "EH_LABEL\0"
  /* 1397 */ "ANNOTATION_LABEL\0"
  /* 1414 */ "ICALL_BRANCH_FUNNEL\0"
  /* 1434 */ "G_FSHL\0"
  /* 1441 */ "G_SHL\0"
  /* 1447 */ "G_FCEIL\0"
  /* 1455 */ "PATCHABLE_TAIL_CALL\0"
  /* 1475 */ "PATCHABLE_TYPED_EVENT_CALL\0"
  /* 1502 */ "PATCHABLE_EVENT_CALL\0"
  /* 1523 */ "FENTRY_CALL\0"
  /* 1535 */ "KILL\0"
  /* 1540 */ "G_CONSTANT_POOL\0"
  /* 1556 */ "G_ROTL\0"
  /* 1563 */ "G_VECREDUCE_FMUL\0"
  /* 1580 */ "G_FMUL\0"
  /* 1587 */ "G_VECREDUCE_SEQ_FMUL\0"
  /* 1608 */ "G_STRICT_FMUL\0"
  /* 1622 */ "G_VECREDUCE_MUL\0"
  /* 1638 */ "G_MUL\0"
  /* 1644 */ "G_FREM\0"
  /* 1651 */ "G_STRICT_FREM\0"
  /* 1665 */ "G_SREM\0"
  /* 1672 */ "G_UREM\0"
  /* 1679 */ "G_SDIVREM\0"
  /* 1689 */ "G_UDIVREM\0"
  /* 1699 */ "INLINEASM\0"
  /* 1709 */ "G_VECREDUCE_FMINIMUM\0"
  /* 1730 */ "G_FMINIMUM\0"
  /* 1741 */ "G_VECREDUCE_FMAXIMUM\0"
  /* 1762 */ "G_FMAXIMUM\0"
  /* 1773 */ "G_FMINNUM\0"
  /* 1783 */ "G_FMAXNUM\0"
  /* 1793 */ "G_FATAN\0"
  /* 1801 */ "G_FTAN\0"
  /* 1808 */ "G_INTRINSIC_ROUNDEVEN\0"
  /* 1830 */ "G_ASSERT_ALIGN\0"
  /* 1845 */ "G_FCOPYSIGN\0"
  /* 1857 */ "G_VECREDUCE_FMIN\0"
  /* 1874 */ "G_ATOMICRMW_FMIN\0"
  /* 1891 */ "G_VECREDUCE_SMIN\0"
  /* 1908 */ "G_SMIN\0"
  /* 1915 */ "G_VECREDUCE_UMIN\0"
  /* 1932 */ "G_UMIN\0"
  /* 1939 */ "G_ATOMICRMW_UMIN\0"
  /* 1956 */ "G_ATOMICRMW_MIN\0"
  /* 1972 */ "G_FASIN\0"
  /* 1980 */ "G_FSIN\0"
  /* 1987 */ "CFI_INSTRUCTION\0"
  /* 2003 */ "ADJCALLSTACKDOWN\0"
  /* 2020 */ "G_SSUBO\0"
  /* 2028 */ "G_USUBO\0"
  /* 2036 */ "G_SADDO\0"
  /* 2044 */ "G_UADDO\0"
  /* 2052 */ "JUMP_TABLE_DEBUG_INFO\0"
  /* 2074 */ "G_SMULO\0"
  /* 2082 */ "G_UMULO\0"
  /* 2090 */ "G_BZERO\0"
  /* 2098 */ "STACKMAP\0"
  /* 2107 */ "G_DEBUGTRAP\0"
  /* 2119 */ "G_UBSANTRAP\0"
  /* 2131 */ "G_TRAP\0"
  /* 2138 */ "G_ATOMICRMW_UDEC_WRAP\0"
  /* 2160 */ "G_ATOMICRMW_UINC_WRAP\0"
  /* 2182 */ "G_BSWAP\0"
  /* 2190 */ "G_SITOFP\0"
  /* 2199 */ "G_UITOFP\0"
  /* 2208 */ "G_FCMP\0"
  /* 2215 */ "G_ICMP\0"
  /* 2222 */ "G_SCMP\0"
  /* 2229 */ "G_UCMP\0"
  /* 2236 */ "JMP\0"
  /* 2240 */ "CONVERGENCECTRL_LOOP\0"
  /* 2261 */ "G_CTPOP\0"
  /* 2269 */ "PATCHABLE_OP\0"
  /* 2282 */ "FAULTING_OP\0"
  /* 2294 */ "ADJCALLSTACKUP\0"
  /* 2309 */ "PREALLOCATED_SETUP\0"
  /* 2328 */ "G_FLDEXP\0"
  /* 2337 */ "G_STRICT_FLDEXP\0"
  /* 2353 */ "G_FEXP\0"
  /* 2360 */ "G_FFREXP\0"
  /* 2369 */ "G_BR\0"
  /* 2374 */ "INLINEASM_BR\0"
  /* 2387 */ "G_BLOCK_ADDR\0"
  /* 2400 */ "MEMBARRIER\0"
  /* 2411 */ "G_CONSTANT_FOLD_BARRIER\0"
  /* 2435 */ "PATCHABLE_FUNCTION_ENTER\0"
  /* 2460 */ "G_READCYCLECOUNTER\0"
  /* 2479 */ "G_READSTEADYCOUNTER\0"
  /* 2499 */ "G_READ_REGISTER\0"
  /* 2515 */ "G_WRITE_REGISTER\0"
  /* 2532 */ "G_ASHR\0"
  /* 2539 */ "G_FSHR\0"
  /* 2546 */ "G_LSHR\0"
  /* 2553 */ "CONVERGENCECTRL_ANCHOR\0"
  /* 2576 */ "G_FFLOOR\0"
  /* 2585 */ "G_EXTRACT_SUBVECTOR\0"
  /* 2605 */ "G_INSERT_SUBVECTOR\0"
  /* 2624 */ "G_BUILD_VECTOR\0"
  /* 2639 */ "G_SHUFFLE_VECTOR\0"
  /* 2656 */ "G_SPLAT_VECTOR\0"
  /* 2671 */ "G_VECREDUCE_XOR\0"
  /* 2687 */ "G_XOR\0"
  /* 2693 */ "G_ATOMICRMW_XOR\0"
  /* 2709 */ "G_VECREDUCE_OR\0"
  /* 2724 */ "G_OR\0"
  /* 2729 */ "G_ATOMICRMW_OR\0"
  /* 2744 */ "G_ROTR\0"
  /* 2751 */ "G_INTTOPTR\0"
  /* 2762 */ "G_FABS\0"
  /* 2769 */ "G_ABS\0"
  /* 2775 */ "G_UNMERGE_VALUES\0"
  /* 2792 */ "G_MERGE_VALUES\0"
  /* 2807 */ "G_FACOS\0"
  /* 2815 */ "G_FCOS\0"
  /* 2822 */ "G_CONCAT_VECTORS\0"
  /* 2839 */ "COPY_TO_REGCLASS\0"
  /* 2856 */ "G_IS_FPCLASS\0"
  /* 2869 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
  /* 2899 */ "G_VECTOR_COMPRESS\0"
  /* 2917 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
  /* 2944 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
  /* 2982 */ "G_SSUBSAT\0"
  /* 2992 */ "G_USUBSAT\0"
  /* 3002 */ "G_SADDSAT\0"
  /* 3012 */ "G_UADDSAT\0"
  /* 3022 */ "G_SSHLSAT\0"
  /* 3032 */ "G_USHLSAT\0"
  /* 3042 */ "G_SMULFIXSAT\0"
  /* 3055 */ "G_UMULFIXSAT\0"
  /* 3068 */ "G_SDIVFIXSAT\0"
  /* 3081 */ "G_UDIVFIXSAT\0"
  /* 3094 */ "G_ATOMICRMW_USUB_SAT\0"
  /* 3115 */ "G_FPTOSI_SAT\0"
  /* 3128 */ "G_FPTOUI_SAT\0"
  /* 3141 */ "G_EXTRACT\0"
  /* 3151 */ "G_SELECT\0"
  /* 3160 */ "G_BRINDIRECT\0"
  /* 3173 */ "PATCHABLE_RET\0"
  /* 3187 */ "G_MEMSET\0"
  /* 3196 */ "PATCHABLE_FUNCTION_EXIT\0"
  /* 3220 */ "G_BRJT\0"
  /* 3227 */ "G_EXTRACT_VECTOR_ELT\0"
  /* 3248 */ "G_INSERT_VECTOR_ELT\0"
  /* 3268 */ "G_FCONSTANT\0"
  /* 3280 */ "G_CONSTANT\0"
  /* 3291 */ "G_INTRINSIC_CONVERGENT\0"
  /* 3314 */ "STATEPOINT\0"
  /* 3325 */ "PATCHPOINT\0"
  /* 3336 */ "G_PTRTOINT\0"
  /* 3347 */ "G_FRINT\0"
  /* 3355 */ "G_INTRINSIC_LLRINT\0"
  /* 3374 */ "G_INTRINSIC_LRINT\0"
  /* 3392 */ "G_FNEARBYINT\0"
  /* 3405 */ "G_VASTART\0"
  /* 3415 */ "LIFETIME_START\0"
  /* 3430 */ "G_INVOKE_REGION_START\0"
  /* 3452 */ "G_INSERT\0"
  /* 3461 */ "G_FSQRT\0"
  /* 3469 */ "G_STRICT_FSQRT\0"
  /* 3484 */ "G_BITCAST\0"
  /* 3494 */ "G_ADDRSPACE_CAST\0"
  /* 3511 */ "DBG_VALUE_LIST\0"
  /* 3526 */ "G_FPEXT\0"
  /* 3534 */ "G_SEXT\0"
  /* 3541 */ "G_ASSERT_SEXT\0"
  /* 3555 */ "G_ANYEXT\0"
  /* 3564 */ "G_ZEXT\0"
  /* 3571 */ "G_ASSERT_ZEXT\0"
  /* 3585 */ "G_FDIV\0"
  /* 3592 */ "G_STRICT_FDIV\0"
  /* 3606 */ "G_SDIV\0"
  /* 3613 */ "G_UDIV\0"
  /* 3620 */ "G_GET_FPENV\0"
  /* 3632 */ "G_RESET_FPENV\0"
  /* 3646 */ "G_SET_FPENV\0"
  /* 3658 */ "G_FPOW\0"
  /* 3665 */ "G_VECREDUCE_FMAX\0"
  /* 3682 */ "G_ATOMICRMW_FMAX\0"
  /* 3699 */ "G_VECREDUCE_SMAX\0"
  /* 3716 */ "G_SMAX\0"
  /* 3723 */ "G_VECREDUCE_UMAX\0"
  /* 3740 */ "G_UMAX\0"
  /* 3747 */ "G_ATOMICRMW_UMAX\0"
  /* 3764 */ "G_ATOMICRMW_MAX\0"
  /* 3780 */ "G_FRAME_INDEX\0"
  /* 3794 */ "G_SBFX\0"
  /* 3801 */ "G_UBFX\0"
  /* 3808 */ "G_SMULFIX\0"
  /* 3818 */ "G_UMULFIX\0"
  /* 3828 */ "G_SDIVFIX\0"
  /* 3838 */ "G_UDIVFIX\0"
  /* 3848 */ "G_MEMCPY\0"
  /* 3857 */ "COPY\0"
  /* 3862 */ "CONVERGENCECTRL_ENTRY\0"
  /* 3884 */ "G_CTLZ\0"
  /* 3891 */ "G_CTTZ\0"
  /* 3898 */ "PUSH16c\0"
  /* 3906 */ "SUB16mc\0"
  /* 3914 */ "SUBC16mc\0"
  /* 3923 */ "ADDC16mc\0"
  /* 3932 */ "BIC16mc\0"
  /* 3940 */ "DADD16mc\0"
  /* 3949 */ "AND16mc\0"
  /* 3957 */ "CMP16mc\0"
  /* 3965 */ "XOR16mc\0"
  /* 3973 */ "BIS16mc\0"
  /* 3981 */ "BIT16mc\0"
  /* 3989 */ "MOV16mc\0"
  /* 3997 */ "SUB8mc\0"
  /* 4004 */ "SUBC8mc\0"
  /* 4012 */ "ADDC8mc\0"
  /* 4020 */ "BIC8mc\0"
  /* 4027 */ "DADD8mc\0"
  /* 4035 */ "AND8mc\0"
  /* 4042 */ "CMP8mc\0"
  /* 4049 */ "XOR8mc\0"
  /* 4056 */ "BIS8mc\0"
  /* 4063 */ "BIT8mc\0"
  /* 4070 */ "MOV8mc\0"
  /* 4077 */ "SUB16rc\0"
  /* 4085 */ "SUBC16rc\0"
  /* 4094 */ "ADDC16rc\0"
  /* 4103 */ "BIC16rc\0"
  /* 4111 */ "DADD16rc\0"
  /* 4120 */ "AND16rc\0"
  /* 4128 */ "CMP16rc\0"
  /* 4136 */ "XOR16rc\0"
  /* 4144 */ "BIS16rc\0"
  /* 4152 */ "BIT16rc\0"
  /* 4160 */ "MOV16rc\0"
  /* 4168 */ "SUB8rc\0"
  /* 4175 */ "SUBC8rc\0"
  /* 4183 */ "ADDC8rc\0"
  /* 4191 */ "BIC8rc\0"
  /* 4198 */ "DADD8rc\0"
  /* 4206 */ "AND8rc\0"
  /* 4213 */ "CMP8rc\0"
  /* 4220 */ "XOR8rc\0"
  /* 4227 */ "BIS8rc\0"
  /* 4234 */ "BIT8rc\0"
  /* 4241 */ "MOV8rc\0"
  /* 4248 */ "ADDframe\0"
  /* 4257 */ "PUSH16i\0"
  /* 4265 */ "Bi\0"
  /* 4268 */ "CALLi\0"
  /* 4274 */ "SUB16mi\0"
  /* 4282 */ "SUBC16mi\0"
  /* 4291 */ "ADDC16mi\0"
  /* 4300 */ "BIC16mi\0"
  /* 4308 */ "DADD16mi\0"
  /* 4317 */ "AND16mi\0"
  /* 4325 */ "CMP16mi\0"
  /* 4333 */ "XOR16mi\0"
  /* 4341 */ "BIS16mi\0"
  /* 4349 */ "BIT16mi\0"
  /* 4357 */ "MOV16mi\0"
  /* 4365 */ "SUB8mi\0"
  /* 4372 */ "SUBC8mi\0"
  /* 4380 */ "ADDC8mi\0"
  /* 4388 */ "BIC8mi\0"
  /* 4395 */ "DADD8mi\0"
  /* 4403 */ "AND8mi\0"
  /* 4410 */ "CMP8mi\0"
  /* 4417 */ "XOR8mi\0"
  /* 4424 */ "BIS8mi\0"
  /* 4431 */ "BIT8mi\0"
  /* 4438 */ "MOV8mi\0"
  /* 4445 */ "SUB16ri\0"
  /* 4453 */ "SUBC16ri\0"
  /* 4462 */ "ADDC16ri\0"
  /* 4471 */ "BIC16ri\0"
  /* 4479 */ "DADD16ri\0"
  /* 4488 */ "AND16ri\0"
  /* 4496 */ "CMP16ri\0"
  /* 4504 */ "XOR16ri\0"
  /* 4512 */ "BIS16ri\0"
  /* 4520 */ "BIT16ri\0"
  /* 4528 */ "MOV16ri\0"
  /* 4536 */ "SUB8ri\0"
  /* 4543 */ "SUBC8ri\0"
  /* 4551 */ "ADDC8ri\0"
  /* 4559 */ "BIC8ri\0"
  /* 4566 */ "DADD8ri\0"
  /* 4574 */ "AND8ri\0"
  /* 4581 */ "CMP8ri\0"
  /* 4588 */ "XOR8ri\0"
  /* 4595 */ "BIS8ri\0"
  /* 4602 */ "BIT8ri\0"
  /* 4609 */ "MOV8ri\0"
  /* 4616 */ "RRA16m\0"
  /* 4623 */ "SWPB16m\0"
  /* 4631 */ "RRC16m\0"
  /* 4638 */ "SEXT16m\0"
  /* 4646 */ "RRA8m\0"
  /* 4652 */ "RRC8m\0"
  /* 4658 */ "Bm\0"
  /* 4661 */ "CALLm\0"
  /* 4667 */ "SUB16mm\0"
  /* 4675 */ "SUBC16mm\0"
  /* 4684 */ "ADDC16mm\0"
  /* 4693 */ "BIC16mm\0"
  /* 4701 */ "DADD16mm\0"
  /* 4710 */ "AND16mm\0"
  /* 4718 */ "CMP16mm\0"
  /* 4726 */ "XOR16mm\0"
  /* 4734 */ "BIS16mm\0"
  /* 4742 */ "BIT16mm\0"
  /* 4750 */ "MOV16mm\0"
  /* 4758 */ "SUB8mm\0"
  /* 4765 */ "SUBC8mm\0"
  /* 4773 */ "ADDC8mm\0"
  /* 4781 */ "BIC8mm\0"
  /* 4788 */ "DADD8mm\0"
  /* 4796 */ "AND8mm\0"
  /* 4803 */ "CMP8mm\0"
  /* 4810 */ "XOR8mm\0"
  /* 4817 */ "BIS8mm\0"
  /* 4824 */ "BIT8mm\0"
  /* 4831 */ "MOV8mm\0"
  /* 4838 */ "SUB16rm\0"
  /* 4846 */ "SUBC16rm\0"
  /* 4855 */ "ADDC16rm\0"
  /* 4864 */ "BIC16rm\0"
  /* 4872 */ "DADD16rm\0"
  /* 4881 */ "AND16rm\0"
  /* 4889 */ "CMP16rm\0"
  /* 4897 */ "XOR16rm\0"
  /* 4905 */ "BIS16rm\0"
  /* 4913 */ "BIT16rm\0"
  /* 4921 */ "MOV16rm\0"
  /* 4929 */ "SUB8rm\0"
  /* 4936 */ "SUBC8rm\0"
  /* 4944 */ "ADDC8rm\0"
  /* 4952 */ "BIC8rm\0"
  /* 4959 */ "DADD8rm\0"
  /* 4967 */ "AND8rm\0"
  /* 4974 */ "CMP8rm\0"
  /* 4981 */ "XOR8rm\0"
  /* 4988 */ "BIS8rm\0"
  /* 4995 */ "BIT8rm\0"
  /* 5002 */ "MOV8rm\0"
  /* 5009 */ "RRA16n\0"
  /* 5016 */ "SWPB16n\0"
  /* 5024 */ "RRC16n\0"
  /* 5031 */ "SEXT16n\0"
  /* 5039 */ "RRA8n\0"
  /* 5045 */ "RRC8n\0"
  /* 5051 */ "CALLn\0"
  /* 5057 */ "SUB16mn\0"
  /* 5065 */ "SUBC16mn\0"
  /* 5074 */ "ADDC16mn\0"
  /* 5083 */ "BIC16mn\0"
  /* 5091 */ "DADD16mn\0"
  /* 5100 */ "AND16mn\0"
  /* 5108 */ "CMP16mn\0"
  /* 5116 */ "XOR16mn\0"
  /* 5124 */ "BIS16mn\0"
  /* 5132 */ "BIT16mn\0"
  /* 5140 */ "MOV16mn\0"
  /* 5148 */ "SUB8mn\0"
  /* 5155 */ "SUBC8mn\0"
  /* 5163 */ "ADDC8mn\0"
  /* 5171 */ "BIC8mn\0"
  /* 5178 */ "DADD8mn\0"
  /* 5186 */ "AND8mn\0"
  /* 5193 */ "CMP8mn\0"
  /* 5200 */ "XOR8mn\0"
  /* 5207 */ "BIS8mn\0"
  /* 5214 */ "BIT8mn\0"
  /* 5221 */ "MOV8mn\0"
  /* 5228 */ "SUB16rn\0"
  /* 5236 */ "SUBC16rn\0"
  /* 5245 */ "ADDC16rn\0"
  /* 5254 */ "BIC16rn\0"
  /* 5262 */ "DADD16rn\0"
  /* 5271 */ "AND16rn\0"
  /* 5279 */ "CMP16rn\0"
  /* 5287 */ "XOR16rn\0"
  /* 5295 */ "BIS16rn\0"
  /* 5303 */ "BIT16rn\0"
  /* 5311 */ "MOV16rn\0"
  /* 5319 */ "SUB8rn\0"
  /* 5326 */ "SUBC8rn\0"
  /* 5334 */ "ADDC8rn\0"
  /* 5342 */ "BIC8rn\0"
  /* 5349 */ "DADD8rn\0"
  /* 5357 */ "AND8rn\0"
  /* 5364 */ "CMP8rn\0"
  /* 5371 */ "XOR8rn\0"
  /* 5378 */ "BIS8rn\0"
  /* 5385 */ "BIT8rn\0"
  /* 5392 */ "MOV8rn\0"
  /* 5399 */ "RRA16p\0"
  /* 5406 */ "SWPB16p\0"
  /* 5414 */ "RRC16p\0"
  /* 5421 */ "SEXT16p\0"
  /* 5429 */ "RRA8p\0"
  /* 5435 */ "RRC8p\0"
  /* 5441 */ "CALLp\0"
  /* 5447 */ "SUB16mp\0"
  /* 5455 */ "SUBC16mp\0"
  /* 5464 */ "ADDC16mp\0"
  /* 5473 */ "BIC16mp\0"
  /* 5481 */ "DADD16mp\0"
  /* 5490 */ "AND16mp\0"
  /* 5498 */ "CMP16mp\0"
  /* 5506 */ "XOR16mp\0"
  /* 5514 */ "BIS16mp\0"
  /* 5522 */ "BIT16mp\0"
  /* 5530 */ "SUB8mp\0"
  /* 5537 */ "SUBC8mp\0"
  /* 5545 */ "ADDC8mp\0"
  /* 5553 */ "BIC8mp\0"
  /* 5560 */ "DADD8mp\0"
  /* 5568 */ "AND8mp\0"
  /* 5575 */ "CMP8mp\0"
  /* 5582 */ "XOR8mp\0"
  /* 5589 */ "BIS8mp\0"
  /* 5596 */ "BIT8mp\0"
  /* 5603 */ "SUB16rp\0"
  /* 5611 */ "SUBC16rp\0"
  /* 5620 */ "ADDC16rp\0"
  /* 5629 */ "BIC16rp\0"
  /* 5637 */ "DADD16rp\0"
  /* 5646 */ "AND16rp\0"
  /* 5654 */ "CMP16rp\0"
  /* 5662 */ "XOR16rp\0"
  /* 5670 */ "BIS16rp\0"
  /* 5678 */ "BIT16rp\0"
  /* 5686 */ "MOV16rp\0"
  /* 5694 */ "SUB8rp\0"
  /* 5701 */ "SUBC8rp\0"
  /* 5709 */ "ADDC8rp\0"
  /* 5717 */ "BIC8rp\0"
  /* 5724 */ "DADD8rp\0"
  /* 5732 */ "AND8rp\0"
  /* 5739 */ "CMP8rp\0"
  /* 5746 */ "XOR8rp\0"
  /* 5753 */ "BIS8rp\0"
  /* 5760 */ "BIT8rp\0"
  /* 5767 */ "MOV8rp\0"
  /* 5774 */ "RRA16r\0"
  /* 5781 */ "SWPB16r\0"
  /* 5789 */ "RRC16r\0"
  /* 5796 */ "PUSH16r\0"
  /* 5804 */ "POP16r\0"
  /* 5811 */ "SEXT16r\0"
  /* 5819 */ "ZEXT16r\0"
  /* 5827 */ "RRA8r\0"
  /* 5833 */ "RRC8r\0"
  /* 5839 */ "PUSH8r\0"
  /* 5846 */ "Br\0"
  /* 5849 */ "CALLr\0"
  /* 5855 */ "SUB16mr\0"
  /* 5863 */ "SUBC16mr\0"
  /* 5872 */ "ADDC16mr\0"
  /* 5881 */ "BIC16mr\0"
  /* 5889 */ "DADD16mr\0"
  /* 5898 */ "AND16mr\0"
  /* 5906 */ "CMP16mr\0"
  /* 5914 */ "XOR16mr\0"
  /* 5922 */ "BIS16mr\0"
  /* 5930 */ "BIT16mr\0"
  /* 5938 */ "MOV16mr\0"
  /* 5946 */ "SUB8mr\0"
  /* 5953 */ "SUBC8mr\0"
  /* 5961 */ "ADDC8mr\0"
  /* 5969 */ "BIC8mr\0"
  /* 5976 */ "DADD8mr\0"
  /* 5984 */ "AND8mr\0"
  /* 5991 */ "CMP8mr\0"
  /* 5998 */ "XOR8mr\0"
  /* 6005 */ "BIS8mr\0"
  /* 6012 */ "BIT8mr\0"
  /* 6019 */ "MOV8mr\0"
  /* 6026 */ "SUB16rr\0"
  /* 6034 */ "SUBC16rr\0"
  /* 6043 */ "ADDC16rr\0"
  /* 6052 */ "BIC16rr\0"
  /* 6060 */ "DADD16rr\0"
  /* 6069 */ "AND16rr\0"
  /* 6077 */ "CMP16rr\0"
  /* 6085 */ "XOR16rr\0"
  /* 6093 */ "BIS16rr\0"
  /* 6101 */ "BIT16rr\0"
  /* 6109 */ "MOV16rr\0"
  /* 6117 */ "SUB8rr\0"
  /* 6124 */ "SUBC8rr\0"
  /* 6132 */ "ADDC8rr\0"
  /* 6140 */ "BIC8rr\0"
  /* 6147 */ "DADD8rr\0"
  /* 6155 */ "AND8rr\0"
  /* 6162 */ "CMP8rr\0"
  /* 6169 */ "XOR8rr\0"
  /* 6176 */ "BIS8rr\0"
  /* 6183 */ "BIT8rr\0"
  /* 6190 */ "MOV8rr\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const unsigned MSP430InstrNameIndices[] = {
    1324U, 1699U, 2374U, 1987U, 1388U, 1369U, 1397U, 1535U, 
    1147U, 1162U, 1113U, 1100U, 1189U, 2839U, 948U, 3511U, 
    1126U, 1320U, 1378U, 729U, 3857U, 851U, 3415U, 556U, 
    680U, 717U, 2098U, 1523U, 3325U, 663U, 2309U, 1252U, 
    3314U, 874U, 2282U, 2269U, 2435U, 3173U, 3196U, 1455U, 
    1502U, 1475U, 1414U, 939U, 2400U, 2052U, 3862U, 2553U, 
    2240U, 996U, 3541U, 3571U, 1830U, 469U, 176U, 1638U, 
    3606U, 3613U, 1665U, 1672U, 1679U, 1689U, 534U, 2724U, 
    2687U, 1111U, 1322U, 3780U, 958U, 973U, 1540U, 3141U, 
    2775U, 3452U, 2792U, 2624U, 250U, 2822U, 3336U, 2751U, 
    3484U, 1039U, 2411U, 637U, 224U, 619U, 3374U, 3355U, 
    1808U, 2460U, 2479U, 370U, 314U, 344U, 355U, 295U, 
    325U, 918U, 902U, 2869U, 1203U, 1220U, 485U, 182U, 
    540U, 501U, 2729U, 2693U, 3764U, 1956U, 3747U, 1939U, 
    436U, 159U, 3682U, 1874U, 2160U, 2138U, 578U, 3094U, 
    709U, 1269U, 569U, 3160U, 3430U, 202U, 2917U, 3291U, 
    2944U, 3555U, 242U, 3280U, 3268U, 3405U, 1244U, 3534U, 
    1176U, 3564U, 1441U, 2546U, 2532U, 1434U, 2539U, 2744U, 
    1556U, 2215U, 2208U, 2222U, 2229U, 3151U, 2044U, 750U, 
    2028U, 701U, 2036U, 742U, 2020U, 693U, 2082U, 2074U, 
    1288U, 1280U, 3012U, 3002U, 2992U, 2982U, 3032U, 3022U, 
    3808U, 3818U, 3042U, 3055U, 3828U, 3838U, 3068U, 3081U, 
    394U, 138U, 1580U, 119U, 288U, 3585U, 1644U, 3658U, 
    1351U, 2353U, 26U, 9U, 1237U, 18U, 0U, 2328U, 
    2360U, 1140U, 3526U, 214U, 1328U, 1342U, 2190U, 2199U, 
    3115U, 3128U, 2762U, 1845U, 2856U, 1048U, 1773U, 1783U, 
    799U, 814U, 1730U, 1762U, 3620U, 3646U, 3632U, 758U, 
    786U, 771U, 475U, 1359U, 1908U, 3716U, 1932U, 3740U, 
    2769U, 610U, 600U, 2369U, 3220U, 829U, 2605U, 2585U, 
    3248U, 3227U, 2639U, 2656U, 2899U, 3891U, 1082U, 3884U, 
    1064U, 2261U, 2182U, 926U, 1447U, 2815U, 1980U, 1801U, 
    2807U, 1972U, 1793U, 1312U, 1304U, 1296U, 3461U, 2576U, 
    3347U, 3392U, 3494U, 2387U, 838U, 271U, 1017U, 887U, 
    422U, 145U, 1608U, 3592U, 1651U, 125U, 3469U, 2337U, 
    2499U, 2515U, 3848U, 858U, 1029U, 3187U, 2090U, 2131U, 
    2107U, 2119U, 401U, 1587U, 377U, 1563U, 3665U, 1857U, 
    1741U, 1709U, 453U, 1622U, 518U, 2709U, 2671U, 3699U, 
    1891U, 3723U, 1915U, 3794U, 3801U, 3941U, 4309U, 4702U, 
    5092U, 5482U, 5890U, 4112U, 4480U, 4873U, 5263U, 5638U, 
    6061U, 4028U, 4396U, 4789U, 5179U, 5561U, 5977U, 4199U, 
    4567U, 4960U, 5350U, 5725U, 6148U, 3923U, 4291U, 4684U, 
    5074U, 5464U, 5872U, 4094U, 4462U, 4855U, 5245U, 5620U, 
    6043U, 4012U, 4380U, 4773U, 5163U, 5545U, 5961U, 4183U, 
    4551U, 4944U, 5334U, 5709U, 6132U, 4248U, 2003U, 2294U, 
    3949U, 4317U, 4710U, 5100U, 5490U, 5898U, 4120U, 4488U, 
    4881U, 5271U, 5646U, 6069U, 4035U, 4403U, 4796U, 5186U, 
    5568U, 5984U, 4206U, 4574U, 4967U, 5357U, 5732U, 6155U, 
    3932U, 4300U, 4693U, 5083U, 5473U, 5881U, 4103U, 4471U, 
    4864U, 5254U, 5629U, 6052U, 4020U, 4388U, 4781U, 5171U, 
    5553U, 5969U, 4191U, 4559U, 4952U, 5342U, 5717U, 6140U, 
    3973U, 4341U, 4734U, 5124U, 5514U, 5922U, 4144U, 4512U, 
    4905U, 5295U, 5670U, 6093U, 4056U, 4424U, 4817U, 5207U, 
    5589U, 6005U, 4227U, 4595U, 4988U, 5378U, 5753U, 6176U, 
    3981U, 4349U, 4742U, 5132U, 5522U, 5930U, 4152U, 4520U, 
    4913U, 5303U, 5678U, 6101U, 4063U, 4431U, 4824U, 5214U, 
    5596U, 6012U, 4234U, 4602U, 4995U, 5385U, 5760U, 6183U, 
    4265U, 4658U, 5846U, 4268U, 4661U, 5051U, 5441U, 5849U, 
    3957U, 4325U, 4718U, 5108U, 5498U, 5906U, 4128U, 4496U, 
    4889U, 5279U, 5654U, 6077U, 4042U, 4410U, 4803U, 5193U, 
    5575U, 5991U, 4213U, 4581U, 4974U, 5364U, 5739U, 6162U, 
    3940U, 4308U, 4701U, 5091U, 5481U, 5889U, 4111U, 4479U, 
    4872U, 5262U, 5637U, 6060U, 4027U, 4395U, 4788U, 5178U, 
    5560U, 5976U, 4198U, 4566U, 4959U, 5349U, 5724U, 6147U, 
    198U, 2236U, 3989U, 4357U, 4750U, 5140U, 5938U, 4160U, 
    4528U, 4921U, 5311U, 5686U, 6109U, 4070U, 4438U, 4831U, 
    5221U, 6019U, 4241U, 4609U, 5002U, 5392U, 5767U, 6190U, 
    89U, 100U, 5804U, 3898U, 4257U, 5796U, 5839U, 3183U, 
    1337U, 4616U, 5009U, 5399U, 5774U, 4646U, 5039U, 5429U, 
    5827U, 4631U, 5024U, 5414U, 5789U, 4652U, 5045U, 5435U, 
    5833U, 40U, 73U, 4638U, 5031U, 5421U, 5811U, 3906U, 
    4274U, 4667U, 5057U, 5447U, 5855U, 4077U, 4445U, 4838U, 
    5228U, 5603U, 6026U, 3997U, 4365U, 4758U, 5148U, 5530U, 
    5946U, 4168U, 4536U, 4929U, 5319U, 5694U, 6117U, 3914U, 
    4282U, 4675U, 5065U, 5455U, 5863U, 4085U, 4453U, 4846U, 
    5236U, 5611U, 6034U, 4004U, 4372U, 4765U, 5155U, 5537U, 
    5953U, 4175U, 4543U, 4936U, 5326U, 5701U, 6124U, 4623U, 
    5016U, 5406U, 5781U, 59U, 111U, 47U, 79U, 34U, 
    68U, 53U, 84U, 3965U, 4333U, 4726U, 5116U, 5506U, 
    5914U, 4136U, 4504U, 4897U, 5287U, 5662U, 6085U, 4049U, 
    4417U, 4810U, 5200U, 5582U, 5998U, 4220U, 4588U, 4981U, 
    5371U, 5746U, 6169U, 5819U, 
};

static inline void InitMSP430MCInstrInfo(MCInstrInfo *II) {
  II->InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 644);
}

} // end namespace llvm
#endif // GET_INSTRINFO_MC_DESC

#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER
namespace llvm {
struct MSP430GenInstrInfo : public TargetInstrInfo {
  explicit MSP430GenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
  ~MSP430GenInstrInfo() override = default;

};
} // end namespace llvm
#endif // GET_INSTRINFO_HEADER

#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS


#endif // GET_INSTRINFO_HELPER_DECLS

#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS

#endif // GET_INSTRINFO_HELPERS

#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR
namespace llvm {
extern const MSP430InstrTable MSP430Descs;
extern const unsigned MSP430InstrNameIndices[];
extern const char MSP430InstrNameData[];
MSP430GenInstrInfo::MSP430GenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
  InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 644);
}
} // end namespace llvm
#endif // GET_INSTRINFO_CTOR_DTOR

#ifdef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_OPERAND_ENUM
namespace llvm {
namespace MSP430 {
namespace OpName {
enum {
  OPERAND_LAST
};
} // end namespace OpName
} // end namespace MSP430
} // end namespace llvm
#endif //GET_INSTRINFO_OPERAND_ENUM

#ifdef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_NAMED_OPS
namespace llvm {
namespace MSP430 {
LLVM_READONLY
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
  return -1;
}
} // end namespace MSP430
} // end namespace llvm
#endif //GET_INSTRINFO_NAMED_OPS

#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
namespace llvm {
namespace MSP430 {
namespace OpTypes {
enum OperandType {
  cc = 0,
  cg8imm = 1,
  cg16imm = 2,
  f32imm = 3,
  f64imm = 4,
  i1imm = 5,
  i8imm = 6,
  i16imm = 7,
  i32imm = 8,
  i64imm = 9,
  indreg = 10,
  jmptarget = 11,
  memdst = 12,
  memsrc = 13,
  postreg = 14,
  ptype0 = 15,
  ptype1 = 16,
  ptype2 = 17,
  ptype3 = 18,
  ptype4 = 19,
  ptype5 = 20,
  type0 = 21,
  type1 = 22,
  type2 = 23,
  type3 = 24,
  type4 = 25,
  type5 = 26,
  untyped_imm_0 = 27,
  GR8 = 28,
  GR16 = 29,
  OPERAND_TYPE_LIST_END
};
} // end namespace OpTypes
} // end namespace MSP430
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM

#ifdef GET_INSTRINFO_OPERAND_TYPE
#undef GET_INSTRINFO_OPERAND_TYPE
namespace llvm {
namespace MSP430 {
LLVM_READONLY
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
  static const uint16_t Offsets[] = {
    /* PHI */
    0,
    /* INLINEASM */
    1,
    /* INLINEASM_BR */
    1,
    /* CFI_INSTRUCTION */
    1,
    /* EH_LABEL */
    2,
    /* GC_LABEL */
    3,
    /* ANNOTATION_LABEL */
    4,
    /* KILL */
    5,
    /* EXTRACT_SUBREG */
    5,
    /* INSERT_SUBREG */
    8,
    /* IMPLICIT_DEF */
    12,
    /* INIT_UNDEF */
    13,
    /* SUBREG_TO_REG */
    14,
    /* COPY_TO_REGCLASS */
    18,
    /* DBG_VALUE */
    21,
    /* DBG_VALUE_LIST */
    21,
    /* DBG_INSTR_REF */
    21,
    /* DBG_PHI */
    21,
    /* DBG_LABEL */
    21,
    /* REG_SEQUENCE */
    22,
    /* COPY */
    24,
    /* BUNDLE */
    26,
    /* LIFETIME_START */
    26,
    /* LIFETIME_END */
    27,
    /* PSEUDO_PROBE */
    28,
    /* ARITH_FENCE */
    32,
    /* STACKMAP */
    34,
    /* FENTRY_CALL */
    36,
    /* PATCHPOINT */
    36,
    /* LOAD_STACK_GUARD */
    42,
    /* PREALLOCATED_SETUP */
    43,
    /* PREALLOCATED_ARG */
    44,
    /* STATEPOINT */
    47,
    /* LOCAL_ESCAPE */
    47,
    /* FAULTING_OP */
    49,
    /* PATCHABLE_OP */
    50,
    /* PATCHABLE_FUNCTION_ENTER */
    50,
    /* PATCHABLE_RET */
    50,
    /* PATCHABLE_FUNCTION_EXIT */
    50,
    /* PATCHABLE_TAIL_CALL */
    50,
    /* PATCHABLE_EVENT_CALL */
    50,
    /* PATCHABLE_TYPED_EVENT_CALL */
    52,
    /* ICALL_BRANCH_FUNNEL */
    55,
    /* FAKE_USE */
    55,
    /* MEMBARRIER */
    55,
    /* JUMP_TABLE_DEBUG_INFO */
    55,
    /* CONVERGENCECTRL_ENTRY */
    56,
    /* CONVERGENCECTRL_ANCHOR */
    57,
    /* CONVERGENCECTRL_LOOP */
    58,
    /* CONVERGENCECTRL_GLUE */
    60,
    /* G_ASSERT_SEXT */
    61,
    /* G_ASSERT_ZEXT */
    64,
    /* G_ASSERT_ALIGN */
    67,
    /* G_ADD */
    70,
    /* G_SUB */
    73,
    /* G_MUL */
    76,
    /* G_SDIV */
    79,
    /* G_UDIV */
    82,
    /* G_SREM */
    85,
    /* G_UREM */
    88,
    /* G_SDIVREM */
    91,
    /* G_UDIVREM */
    95,
    /* G_AND */
    99,
    /* G_OR */
    102,
    /* G_XOR */
    105,
    /* G_IMPLICIT_DEF */
    108,
    /* G_PHI */
    109,
    /* G_FRAME_INDEX */
    110,
    /* G_GLOBAL_VALUE */
    112,
    /* G_PTRAUTH_GLOBAL_VALUE */
    114,
    /* G_CONSTANT_POOL */
    119,
    /* G_EXTRACT */
    121,
    /* G_UNMERGE_VALUES */
    124,
    /* G_INSERT */
    126,
    /* G_MERGE_VALUES */
    130,
    /* G_BUILD_VECTOR */
    132,
    /* G_BUILD_VECTOR_TRUNC */
    134,
    /* G_CONCAT_VECTORS */
    136,
    /* G_PTRTOINT */
    138,
    /* G_INTTOPTR */
    140,
    /* G_BITCAST */
    142,
    /* G_FREEZE */
    144,
    /* G_CONSTANT_FOLD_BARRIER */
    146,
    /* G_INTRINSIC_FPTRUNC_ROUND */
    148,
    /* G_INTRINSIC_TRUNC */
    151,
    /* G_INTRINSIC_ROUND */
    153,
    /* G_INTRINSIC_LRINT */
    155,
    /* G_INTRINSIC_LLRINT */
    157,
    /* G_INTRINSIC_ROUNDEVEN */
    159,
    /* G_READCYCLECOUNTER */
    161,
    /* G_READSTEADYCOUNTER */
    162,
    /* G_LOAD */
    163,
    /* G_SEXTLOAD */
    165,
    /* G_ZEXTLOAD */
    167,
    /* G_INDEXED_LOAD */
    169,
    /* G_INDEXED_SEXTLOAD */
    174,
    /* G_INDEXED_ZEXTLOAD */
    179,
    /* G_STORE */
    184,
    /* G_INDEXED_STORE */
    186,
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    191,
    /* G_ATOMIC_CMPXCHG */
    196,
    /* G_ATOMICRMW_XCHG */
    200,
    /* G_ATOMICRMW_ADD */
    203,
    /* G_ATOMICRMW_SUB */
    206,
    /* G_ATOMICRMW_AND */
    209,
    /* G_ATOMICRMW_NAND */
    212,
    /* G_ATOMICRMW_OR */
    215,
    /* G_ATOMICRMW_XOR */
    218,
    /* G_ATOMICRMW_MAX */
    221,
    /* G_ATOMICRMW_MIN */
    224,
    /* G_ATOMICRMW_UMAX */
    227,
    /* G_ATOMICRMW_UMIN */
    230,
    /* G_ATOMICRMW_FADD */
    233,
    /* G_ATOMICRMW_FSUB */
    236,
    /* G_ATOMICRMW_FMAX */
    239,
    /* G_ATOMICRMW_FMIN */
    242,
    /* G_ATOMICRMW_UINC_WRAP */
    245,
    /* G_ATOMICRMW_UDEC_WRAP */
    248,
    /* G_ATOMICRMW_USUB_COND */
    251,
    /* G_ATOMICRMW_USUB_SAT */
    254,
    /* G_FENCE */
    257,
    /* G_PREFETCH */
    259,
    /* G_BRCOND */
    263,
    /* G_BRINDIRECT */
    265,
    /* G_INVOKE_REGION_START */
    266,
    /* G_INTRINSIC */
    266,
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    267,
    /* G_INTRINSIC_CONVERGENT */
    268,
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    269,
    /* G_ANYEXT */
    270,
    /* G_TRUNC */
    272,
    /* G_CONSTANT */
    274,
    /* G_FCONSTANT */
    276,
    /* G_VASTART */
    278,
    /* G_VAARG */
    279,
    /* G_SEXT */
    282,
    /* G_SEXT_INREG */
    284,
    /* G_ZEXT */
    287,
    /* G_SHL */
    289,
    /* G_LSHR */
    292,
    /* G_ASHR */
    295,
    /* G_FSHL */
    298,
    /* G_FSHR */
    302,
    /* G_ROTR */
    306,
    /* G_ROTL */
    309,
    /* G_ICMP */
    312,
    /* G_FCMP */
    316,
    /* G_SCMP */
    320,
    /* G_UCMP */
    323,
    /* G_SELECT */
    326,
    /* G_UADDO */
    330,
    /* G_UADDE */
    334,
    /* G_USUBO */
    339,
    /* G_USUBE */
    343,
    /* G_SADDO */
    348,
    /* G_SADDE */
    352,
    /* G_SSUBO */
    357,
    /* G_SSUBE */
    361,
    /* G_UMULO */
    366,
    /* G_SMULO */
    370,
    /* G_UMULH */
    374,
    /* G_SMULH */
    377,
    /* G_UADDSAT */
    380,
    /* G_SADDSAT */
    383,
    /* G_USUBSAT */
    386,
    /* G_SSUBSAT */
    389,
    /* G_USHLSAT */
    392,
    /* G_SSHLSAT */
    395,
    /* G_SMULFIX */
    398,
    /* G_UMULFIX */
    402,
    /* G_SMULFIXSAT */
    406,
    /* G_UMULFIXSAT */
    410,
    /* G_SDIVFIX */
    414,
    /* G_UDIVFIX */
    418,
    /* G_SDIVFIXSAT */
    422,
    /* G_UDIVFIXSAT */
    426,
    /* G_FADD */
    430,
    /* G_FSUB */
    433,
    /* G_FMUL */
    436,
    /* G_FMA */
    439,
    /* G_FMAD */
    443,
    /* G_FDIV */
    447,
    /* G_FREM */
    450,
    /* G_FPOW */
    453,
    /* G_FPOWI */
    456,
    /* G_FEXP */
    459,
    /* G_FEXP2 */
    461,
    /* G_FEXP10 */
    463,
    /* G_FLOG */
    465,
    /* G_FLOG2 */
    467,
    /* G_FLOG10 */
    469,
    /* G_FLDEXP */
    471,
    /* G_FFREXP */
    474,
    /* G_FNEG */
    477,
    /* G_FPEXT */
    479,
    /* G_FPTRUNC */
    481,
    /* G_FPTOSI */
    483,
    /* G_FPTOUI */
    485,
    /* G_SITOFP */
    487,
    /* G_UITOFP */
    489,
    /* G_FPTOSI_SAT */
    491,
    /* G_FPTOUI_SAT */
    493,
    /* G_FABS */
    495,
    /* G_FCOPYSIGN */
    497,
    /* G_IS_FPCLASS */
    500,
    /* G_FCANONICALIZE */
    503,
    /* G_FMINNUM */
    505,
    /* G_FMAXNUM */
    508,
    /* G_FMINNUM_IEEE */
    511,
    /* G_FMAXNUM_IEEE */
    514,
    /* G_FMINIMUM */
    517,
    /* G_FMAXIMUM */
    520,
    /* G_GET_FPENV */
    523,
    /* G_SET_FPENV */
    524,
    /* G_RESET_FPENV */
    525,
    /* G_GET_FPMODE */
    525,
    /* G_SET_FPMODE */
    526,
    /* G_RESET_FPMODE */
    527,
    /* G_PTR_ADD */
    527,
    /* G_PTRMASK */
    530,
    /* G_SMIN */
    533,
    /* G_SMAX */
    536,
    /* G_UMIN */
    539,
    /* G_UMAX */
    542,
    /* G_ABS */
    545,
    /* G_LROUND */
    547,
    /* G_LLROUND */
    549,
    /* G_BR */
    551,
    /* G_BRJT */
    552,
    /* G_VSCALE */
    555,
    /* G_INSERT_SUBVECTOR */
    557,
    /* G_EXTRACT_SUBVECTOR */
    561,
    /* G_INSERT_VECTOR_ELT */
    564,
    /* G_EXTRACT_VECTOR_ELT */
    568,
    /* G_SHUFFLE_VECTOR */
    571,
    /* G_SPLAT_VECTOR */
    575,
    /* G_VECTOR_COMPRESS */
    577,
    /* G_CTTZ */
    581,
    /* G_CTTZ_ZERO_UNDEF */
    583,
    /* G_CTLZ */
    585,
    /* G_CTLZ_ZERO_UNDEF */
    587,
    /* G_CTPOP */
    589,
    /* G_BSWAP */
    591,
    /* G_BITREVERSE */
    593,
    /* G_FCEIL */
    595,
    /* G_FCOS */
    597,
    /* G_FSIN */
    599,
    /* G_FTAN */
    601,
    /* G_FACOS */
    603,
    /* G_FASIN */
    605,
    /* G_FATAN */
    607,
    /* G_FCOSH */
    609,
    /* G_FSINH */
    611,
    /* G_FTANH */
    613,
    /* G_FSQRT */
    615,
    /* G_FFLOOR */
    617,
    /* G_FRINT */
    619,
    /* G_FNEARBYINT */
    621,
    /* G_ADDRSPACE_CAST */
    623,
    /* G_BLOCK_ADDR */
    625,
    /* G_JUMP_TABLE */
    627,
    /* G_DYN_STACKALLOC */
    629,
    /* G_STACKSAVE */
    632,
    /* G_STACKRESTORE */
    633,
    /* G_STRICT_FADD */
    634,
    /* G_STRICT_FSUB */
    637,
    /* G_STRICT_FMUL */
    640,
    /* G_STRICT_FDIV */
    643,
    /* G_STRICT_FREM */
    646,
    /* G_STRICT_FMA */
    649,
    /* G_STRICT_FSQRT */
    653,
    /* G_STRICT_FLDEXP */
    655,
    /* G_READ_REGISTER */
    658,
    /* G_WRITE_REGISTER */
    660,
    /* G_MEMCPY */
    662,
    /* G_MEMCPY_INLINE */
    666,
    /* G_MEMMOVE */
    669,
    /* G_MEMSET */
    673,
    /* G_BZERO */
    677,
    /* G_TRAP */
    680,
    /* G_DEBUGTRAP */
    680,
    /* G_UBSANTRAP */
    680,
    /* G_VECREDUCE_SEQ_FADD */
    681,
    /* G_VECREDUCE_SEQ_FMUL */
    684,
    /* G_VECREDUCE_FADD */
    687,
    /* G_VECREDUCE_FMUL */
    689,
    /* G_VECREDUCE_FMAX */
    691,
    /* G_VECREDUCE_FMIN */
    693,
    /* G_VECREDUCE_FMAXIMUM */
    695,
    /* G_VECREDUCE_FMINIMUM */
    697,
    /* G_VECREDUCE_ADD */
    699,
    /* G_VECREDUCE_MUL */
    701,
    /* G_VECREDUCE_AND */
    703,
    /* G_VECREDUCE_OR */
    705,
    /* G_VECREDUCE_XOR */
    707,
    /* G_VECREDUCE_SMAX */
    709,
    /* G_VECREDUCE_SMIN */
    711,
    /* G_VECREDUCE_UMAX */
    713,
    /* G_VECREDUCE_UMIN */
    715,
    /* G_SBFX */
    717,
    /* G_UBFX */
    721,
    /* ADD16mc */
    725,
    /* ADD16mi */
    728,
    /* ADD16mm */
    731,
    /* ADD16mn */
    735,
    /* ADD16mp */
    738,
    /* ADD16mr */
    741,
    /* ADD16rc */
    744,
    /* ADD16ri */
    747,
    /* ADD16rm */
    750,
    /* ADD16rn */
    754,
    /* ADD16rp */
    757,
    /* ADD16rr */
    761,
    /* ADD8mc */
    764,
    /* ADD8mi */
    767,
    /* ADD8mm */
    770,
    /* ADD8mn */
    774,
    /* ADD8mp */
    777,
    /* ADD8mr */
    780,
    /* ADD8rc */
    783,
    /* ADD8ri */
    786,
    /* ADD8rm */
    789,
    /* ADD8rn */
    793,
    /* ADD8rp */
    796,
    /* ADD8rr */
    800,
    /* ADDC16mc */
    803,
    /* ADDC16mi */
    806,
    /* ADDC16mm */
    809,
    /* ADDC16mn */
    813,
    /* ADDC16mp */
    816,
    /* ADDC16mr */
    819,
    /* ADDC16rc */
    822,
    /* ADDC16ri */
    825,
    /* ADDC16rm */
    828,
    /* ADDC16rn */
    832,
    /* ADDC16rp */
    835,
    /* ADDC16rr */
    839,
    /* ADDC8mc */
    842,
    /* ADDC8mi */
    845,
    /* ADDC8mm */
    848,
    /* ADDC8mn */
    852,
    /* ADDC8mp */
    855,
    /* ADDC8mr */
    858,
    /* ADDC8rc */
    861,
    /* ADDC8ri */
    864,
    /* ADDC8rm */
    867,
    /* ADDC8rn */
    871,
    /* ADDC8rp */
    874,
    /* ADDC8rr */
    878,
    /* ADDframe */
    881,
    /* ADJCALLSTACKDOWN */
    884,
    /* ADJCALLSTACKUP */
    886,
    /* AND16mc */
    888,
    /* AND16mi */
    891,
    /* AND16mm */
    894,
    /* AND16mn */
    898,
    /* AND16mp */
    901,
    /* AND16mr */
    904,
    /* AND16rc */
    907,
    /* AND16ri */
    910,
    /* AND16rm */
    913,
    /* AND16rn */
    917,
    /* AND16rp */
    920,
    /* AND16rr */
    924,
    /* AND8mc */
    927,
    /* AND8mi */
    930,
    /* AND8mm */
    933,
    /* AND8mn */
    937,
    /* AND8mp */
    940,
    /* AND8mr */
    943,
    /* AND8rc */
    946,
    /* AND8ri */
    949,
    /* AND8rm */
    952,
    /* AND8rn */
    956,
    /* AND8rp */
    959,
    /* AND8rr */
    963,
    /* BIC16mc */
    966,
    /* BIC16mi */
    969,
    /* BIC16mm */
    972,
    /* BIC16mn */
    976,
    /* BIC16mp */
    979,
    /* BIC16mr */
    982,
    /* BIC16rc */
    985,
    /* BIC16ri */
    988,
    /* BIC16rm */
    991,
    /* BIC16rn */
    995,
    /* BIC16rp */
    998,
    /* BIC16rr */
    1002,
    /* BIC8mc */
    1005,
    /* BIC8mi */
    1008,
    /* BIC8mm */
    1011,
    /* BIC8mn */
    1015,
    /* BIC8mp */
    1018,
    /* BIC8mr */
    1021,
    /* BIC8rc */
    1024,
    /* BIC8ri */
    1027,
    /* BIC8rm */
    1030,
    /* BIC8rn */
    1034,
    /* BIC8rp */
    1037,
    /* BIC8rr */
    1041,
    /* BIS16mc */
    1044,
    /* BIS16mi */
    1047,
    /* BIS16mm */
    1050,
    /* BIS16mn */
    1054,
    /* BIS16mp */
    1057,
    /* BIS16mr */
    1060,
    /* BIS16rc */
    1063,
    /* BIS16ri */
    1066,
    /* BIS16rm */
    1069,
    /* BIS16rn */
    1073,
    /* BIS16rp */
    1076,
    /* BIS16rr */
    1080,
    /* BIS8mc */
    1083,
    /* BIS8mi */
    1086,
    /* BIS8mm */
    1089,
    /* BIS8mn */
    1093,
    /* BIS8mp */
    1096,
    /* BIS8mr */
    1099,
    /* BIS8rc */
    1102,
    /* BIS8ri */
    1105,
    /* BIS8rm */
    1108,
    /* BIS8rn */
    1112,
    /* BIS8rp */
    1115,
    /* BIS8rr */
    1119,
    /* BIT16mc */
    1122,
    /* BIT16mi */
    1125,
    /* BIT16mm */
    1128,
    /* BIT16mn */
    1132,
    /* BIT16mp */
    1135,
    /* BIT16mr */
    1138,
    /* BIT16rc */
    1141,
    /* BIT16ri */
    1143,
    /* BIT16rm */
    1145,
    /* BIT16rn */
    1148,
    /* BIT16rp */
    1150,
    /* BIT16rr */
    1152,
    /* BIT8mc */
    1154,
    /* BIT8mi */
    1157,
    /* BIT8mm */
    1160,
    /* BIT8mn */
    1164,
    /* BIT8mp */
    1167,
    /* BIT8mr */
    1170,
    /* BIT8rc */
    1173,
    /* BIT8ri */
    1175,
    /* BIT8rm */
    1177,
    /* BIT8rn */
    1180,
    /* BIT8rp */
    1182,
    /* BIT8rr */
    1184,
    /* Bi */
    1186,
    /* Bm */
    1187,
    /* Br */
    1189,
    /* CALLi */
    1190,
    /* CALLm */
    1191,
    /* CALLn */
    1193,
    /* CALLp */
    1194,
    /* CALLr */
    1195,
    /* CMP16mc */
    1196,
    /* CMP16mi */
    1199,
    /* CMP16mm */
    1202,
    /* CMP16mn */
    1206,
    /* CMP16mp */
    1209,
    /* CMP16mr */
    1212,
    /* CMP16rc */
    1215,
    /* CMP16ri */
    1217,
    /* CMP16rm */
    1219,
    /* CMP16rn */
    1222,
    /* CMP16rp */
    1224,
    /* CMP16rr */
    1226,
    /* CMP8mc */
    1228,
    /* CMP8mi */
    1231,
    /* CMP8mm */
    1234,
    /* CMP8mn */
    1238,
    /* CMP8mp */
    1241,
    /* CMP8mr */
    1244,
    /* CMP8rc */
    1247,
    /* CMP8ri */
    1249,
    /* CMP8rm */
    1251,
    /* CMP8rn */
    1254,
    /* CMP8rp */
    1256,
    /* CMP8rr */
    1258,
    /* DADD16mc */
    1260,
    /* DADD16mi */
    1263,
    /* DADD16mm */
    1266,
    /* DADD16mn */
    1270,
    /* DADD16mp */
    1273,
    /* DADD16mr */
    1276,
    /* DADD16rc */
    1279,
    /* DADD16ri */
    1282,
    /* DADD16rm */
    1285,
    /* DADD16rn */
    1289,
    /* DADD16rp */
    1292,
    /* DADD16rr */
    1296,
    /* DADD8mc */
    1299,
    /* DADD8mi */
    1302,
    /* DADD8mm */
    1305,
    /* DADD8mn */
    1309,
    /* DADD8mp */
    1312,
    /* DADD8mr */
    1315,
    /* DADD8rc */
    1318,
    /* DADD8ri */
    1321,
    /* DADD8rm */
    1324,
    /* DADD8rn */
    1328,
    /* DADD8rp */
    1331,
    /* DADD8rr */
    1335,
    /* JCC */
    1338,
    /* JMP */
    1340,
    /* MOV16mc */
    1341,
    /* MOV16mi */
    1344,
    /* MOV16mm */
    1347,
    /* MOV16mn */
    1351,
    /* MOV16mr */
    1354,
    /* MOV16rc */
    1357,
    /* MOV16ri */
    1359,
    /* MOV16rm */
    1361,
    /* MOV16rn */
    1364,
    /* MOV16rp */
    1366,
    /* MOV16rr */
    1369,
    /* MOV8mc */
    1371,
    /* MOV8mi */
    1374,
    /* MOV8mm */
    1377,
    /* MOV8mn */
    1381,
    /* MOV8mr */
    1384,
    /* MOV8rc */
    1387,
    /* MOV8ri */
    1389,
    /* MOV8rm */
    1391,
    /* MOV8rn */
    1394,
    /* MOV8rp */
    1396,
    /* MOV8rr */
    1399,
    /* MOVZX16rm8 */
    1401,
    /* MOVZX16rr8 */
    1404,
    /* POP16r */
    1406,
    /* PUSH16c */
    1407,
    /* PUSH16i */
    1408,
    /* PUSH16r */
    1409,
    /* PUSH8r */
    1410,
    /* RET */
    1411,
    /* RETI */
    1411,
    /* RRA16m */
    1411,
    /* RRA16n */
    1413,
    /* RRA16p */
    1414,
    /* RRA16r */
    1415,
    /* RRA8m */
    1417,
    /* RRA8n */
    1419,
    /* RRA8p */
    1420,
    /* RRA8r */
    1421,
    /* RRC16m */
    1423,
    /* RRC16n */
    1425,
    /* RRC16p */
    1426,
    /* RRC16r */
    1427,
    /* RRC8m */
    1429,
    /* RRC8n */
    1431,
    /* RRC8p */
    1432,
    /* RRC8r */
    1433,
    /* Rrcl16 */
    1435,
    /* Rrcl8 */
    1437,
    /* SEXT16m */
    1439,
    /* SEXT16n */
    1441,
    /* SEXT16p */
    1442,
    /* SEXT16r */
    1443,
    /* SUB16mc */
    1445,
    /* SUB16mi */
    1448,
    /* SUB16mm */
    1451,
    /* SUB16mn */
    1455,
    /* SUB16mp */
    1458,
    /* SUB16mr */
    1461,
    /* SUB16rc */
    1464,
    /* SUB16ri */
    1467,
    /* SUB16rm */
    1470,
    /* SUB16rn */
    1474,
    /* SUB16rp */
    1477,
    /* SUB16rr */
    1481,
    /* SUB8mc */
    1484,
    /* SUB8mi */
    1487,
    /* SUB8mm */
    1490,
    /* SUB8mn */
    1494,
    /* SUB8mp */
    1497,
    /* SUB8mr */
    1500,
    /* SUB8rc */
    1503,
    /* SUB8ri */
    1506,
    /* SUB8rm */
    1509,
    /* SUB8rn */
    1513,
    /* SUB8rp */
    1516,
    /* SUB8rr */
    1520,
    /* SUBC16mc */
    1523,
    /* SUBC16mi */
    1526,
    /* SUBC16mm */
    1529,
    /* SUBC16mn */
    1533,
    /* SUBC16mp */
    1536,
    /* SUBC16mr */
    1539,
    /* SUBC16rc */
    1542,
    /* SUBC16ri */
    1545,
    /* SUBC16rm */
    1548,
    /* SUBC16rn */
    1552,
    /* SUBC16rp */
    1555,
    /* SUBC16rr */
    1559,
    /* SUBC8mc */
    1562,
    /* SUBC8mi */
    1565,
    /* SUBC8mm */
    1568,
    /* SUBC8mn */
    1572,
    /* SUBC8mp */
    1575,
    /* SUBC8mr */
    1578,
    /* SUBC8rc */
    1581,
    /* SUBC8ri */
    1584,
    /* SUBC8rm */
    1587,
    /* SUBC8rn */
    1591,
    /* SUBC8rp */
    1594,
    /* SUBC8rr */
    1598,
    /* SWPB16m */
    1601,
    /* SWPB16n */
    1603,
    /* SWPB16p */
    1604,
    /* SWPB16r */
    1605,
    /* Select16 */
    1607,
    /* Select8 */
    1611,
    /* Shl16 */
    1615,
    /* Shl8 */
    1618,
    /* Sra16 */
    1621,
    /* Sra8 */
    1624,
    /* Srl16 */
    1627,
    /* Srl8 */
    1630,
    /* XOR16mc */
    1633,
    /* XOR16mi */
    1636,
    /* XOR16mm */
    1639,
    /* XOR16mn */
    1643,
    /* XOR16mp */
    1646,
    /* XOR16mr */
    1649,
    /* XOR16rc */
    1652,
    /* XOR16ri */
    1655,
    /* XOR16rm */
    1658,
    /* XOR16rn */
    1662,
    /* XOR16rp */
    1665,
    /* XOR16rr */
    1669,
    /* XOR8mc */
    1672,
    /* XOR8mi */
    1675,
    /* XOR8mm */
    1678,
    /* XOR8mn */
    1682,
    /* XOR8mp */
    1685,
    /* XOR8mr */
    1688,
    /* XOR8rc */
    1691,
    /* XOR8ri */
    1694,
    /* XOR8rm */
    1697,
    /* XOR8rn */
    1701,
    /* XOR8rp */
    1704,
    /* XOR8rr */
    1708,
    /* ZEXT16r */
    1711,
  };

  using namespace OpTypes;
  static const int8_t OpcodeOperandTypes[] = {
    
    /* PHI */
    -1, 
    /* INLINEASM */
    /* INLINEASM_BR */
    /* CFI_INSTRUCTION */
    i32imm, 
    /* EH_LABEL */
    i32imm, 
    /* GC_LABEL */
    i32imm, 
    /* ANNOTATION_LABEL */
    i32imm, 
    /* KILL */
    /* EXTRACT_SUBREG */
    -1, -1, i32imm, 
    /* INSERT_SUBREG */
    -1, -1, -1, i32imm, 
    /* IMPLICIT_DEF */
    -1, 
    /* INIT_UNDEF */
    -1, 
    /* SUBREG_TO_REG */
    -1, -1, -1, i32imm, 
    /* COPY_TO_REGCLASS */
    -1, -1, i32imm, 
    /* DBG_VALUE */
    /* DBG_VALUE_LIST */
    /* DBG_INSTR_REF */
    /* DBG_PHI */
    /* DBG_LABEL */
    -1, 
    /* REG_SEQUENCE */
    -1, -1, 
    /* COPY */
    -1, -1, 
    /* BUNDLE */
    /* LIFETIME_START */
    i32imm, 
    /* LIFETIME_END */
    i32imm, 
    /* PSEUDO_PROBE */
    i64imm, i64imm, i8imm, i32imm, 
    /* ARITH_FENCE */
    -1, -1, 
    /* STACKMAP */
    i64imm, i32imm, 
    /* FENTRY_CALL */
    /* PATCHPOINT */
    -1, i64imm, i32imm, -1, i32imm, i32imm, 
    /* LOAD_STACK_GUARD */
    -1, 
    /* PREALLOCATED_SETUP */
    i32imm, 
    /* PREALLOCATED_ARG */
    -1, i32imm, i32imm, 
    /* STATEPOINT */
    /* LOCAL_ESCAPE */
    -1, i32imm, 
    /* FAULTING_OP */
    -1, 
    /* PATCHABLE_OP */
    /* PATCHABLE_FUNCTION_ENTER */
    /* PATCHABLE_RET */
    /* PATCHABLE_FUNCTION_EXIT */
    /* PATCHABLE_TAIL_CALL */
    /* PATCHABLE_EVENT_CALL */
    -1, -1, 
    /* PATCHABLE_TYPED_EVENT_CALL */
    -1, -1, -1, 
    /* ICALL_BRANCH_FUNNEL */
    /* FAKE_USE */
    /* MEMBARRIER */
    /* JUMP_TABLE_DEBUG_INFO */
    i64imm, 
    /* CONVERGENCECTRL_ENTRY */
    -1, 
    /* CONVERGENCECTRL_ANCHOR */
    -1, 
    /* CONVERGENCECTRL_LOOP */
    -1, -1, 
    /* CONVERGENCECTRL_GLUE */
    -1, 
    /* G_ASSERT_SEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ZEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ALIGN */
    type0, type0, untyped_imm_0, 
    /* G_ADD */
    type0, type0, type0, 
    /* G_SUB */
    type0, type0, type0, 
    /* G_MUL */
    type0, type0, type0, 
    /* G_SDIV */
    type0, type0, type0, 
    /* G_UDIV */
    type0, type0, type0, 
    /* G_SREM */
    type0, type0, type0, 
    /* G_UREM */
    type0, type0, type0, 
    /* G_SDIVREM */
    type0, type0, type0, type0, 
    /* G_UDIVREM */
    type0, type0, type0, type0, 
    /* G_AND */
    type0, type0, type0, 
    /* G_OR */
    type0, type0, type0, 
    /* G_XOR */
    type0, type0, type0, 
    /* G_IMPLICIT_DEF */
    type0, 
    /* G_PHI */
    type0, 
    /* G_FRAME_INDEX */
    type0, -1, 
    /* G_GLOBAL_VALUE */
    type0, -1, 
    /* G_PTRAUTH_GLOBAL_VALUE */
    type0, -1, i32imm, type1, i64imm, 
    /* G_CONSTANT_POOL */
    type0, -1, 
    /* G_EXTRACT */
    type0, type1, untyped_imm_0, 
    /* G_UNMERGE_VALUES */
    type0, type1, 
    /* G_INSERT */
    type0, type0, type1, untyped_imm_0, 
    /* G_MERGE_VALUES */
    type0, type1, 
    /* G_BUILD_VECTOR */
    type0, type1, 
    /* G_BUILD_VECTOR_TRUNC */
    type0, type1, 
    /* G_CONCAT_VECTORS */
    type0, type1, 
    /* G_PTRTOINT */
    type0, type1, 
    /* G_INTTOPTR */
    type0, type1, 
    /* G_BITCAST */
    type0, type1, 
    /* G_FREEZE */
    type0, type0, 
    /* G_CONSTANT_FOLD_BARRIER */
    type0, type0, 
    /* G_INTRINSIC_FPTRUNC_ROUND */
    type0, type1, i32imm, 
    /* G_INTRINSIC_TRUNC */
    type0, type0, 
    /* G_INTRINSIC_ROUND */
    type0, type0, 
    /* G_INTRINSIC_LRINT */
    type0, type1, 
    /* G_INTRINSIC_LLRINT */
    type0, type1, 
    /* G_INTRINSIC_ROUNDEVEN */
    type0, type0, 
    /* G_READCYCLECOUNTER */
    type0, 
    /* G_READSTEADYCOUNTER */
    type0, 
    /* G_LOAD */
    type0, ptype1, 
    /* G_SEXTLOAD */
    type0, ptype1, 
    /* G_ZEXTLOAD */
    type0, ptype1, 
    /* G_INDEXED_LOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_SEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_ZEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_STORE */
    type0, ptype1, 
    /* G_INDEXED_STORE */
    ptype0, type1, ptype0, ptype2, -1, 
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    type0, type1, type2, type0, type0, 
    /* G_ATOMIC_CMPXCHG */
    type0, ptype1, type0, type0, 
    /* G_ATOMICRMW_XCHG */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_ADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_SUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_AND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_NAND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_OR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_XOR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FSUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UINC_WRAP */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UDEC_WRAP */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_USUB_COND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_USUB_SAT */
    type0, ptype1, type0, 
    /* G_FENCE */
    i32imm, i32imm, 
    /* G_PREFETCH */
    ptype0, i32imm, i32imm, i32imm, 
    /* G_BRCOND */
    type0, -1, 
    /* G_BRINDIRECT */
    type0, 
    /* G_INVOKE_REGION_START */
    /* G_INTRINSIC */
    -1, 
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    -1, 
    /* G_INTRINSIC_CONVERGENT */
    -1, 
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    -1, 
    /* G_ANYEXT */
    type0, type1, 
    /* G_TRUNC */
    type0, type1, 
    /* G_CONSTANT */
    type0, -1, 
    /* G_FCONSTANT */
    type0, -1, 
    /* G_VASTART */
    type0, 
    /* G_VAARG */
    type0, type1, -1, 
    /* G_SEXT */
    type0, type1, 
    /* G_SEXT_INREG */
    type0, type0, untyped_imm_0, 
    /* G_ZEXT */
    type0, type1, 
    /* G_SHL */
    type0, type0, type1, 
    /* G_LSHR */
    type0, type0, type1, 
    /* G_ASHR */
    type0, type0, type1, 
    /* G_FSHL */
    type0, type0, type0, type1, 
    /* G_FSHR */
    type0, type0, type0, type1, 
    /* G_ROTR */
    type0, type0, type1, 
    /* G_ROTL */
    type0, type0, type1, 
    /* G_ICMP */
    type0, -1, type1, type1, 
    /* G_FCMP */
    type0, -1, type1, type1, 
    /* G_SCMP */
    type0, type1, type1, 
    /* G_UCMP */
    type0, type1, type1, 
    /* G_SELECT */
    type0, type1, type0, type0, 
    /* G_UADDO */
    type0, type1, type0, type0, 
    /* G_UADDE */
    type0, type1, type0, type0, type1, 
    /* G_USUBO */
    type0, type1, type0, type0, 
    /* G_USUBE */
    type0, type1, type0, type0, type1, 
    /* G_SADDO */
    type0, type1, type0, type0, 
    /* G_SADDE */
    type0, type1, type0, type0, type1, 
    /* G_SSUBO */
    type0, type1, type0, type0, 
    /* G_SSUBE */
    type0, type1, type0, type0, type1, 
    /* G_UMULO */
    type0, type1, type0, type0, 
    /* G_SMULO */
    type0, type1, type0, type0, 
    /* G_UMULH */
    type0, type0, type0, 
    /* G_SMULH */
    type0, type0, type0, 
    /* G_UADDSAT */
    type0, type0, type0, 
    /* G_SADDSAT */
    type0, type0, type0, 
    /* G_USUBSAT */
    type0, type0, type0, 
    /* G_SSUBSAT */
    type0, type0, type0, 
    /* G_USHLSAT */
    type0, type0, type1, 
    /* G_SSHLSAT */
    type0, type0, type1, 
    /* G_SMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_FADD */
    type0, type0, type0, 
    /* G_FSUB */
    type0, type0, type0, 
    /* G_FMUL */
    type0, type0, type0, 
    /* G_FMA */
    type0, type0, type0, type0, 
    /* G_FMAD */
    type0, type0, type0, type0, 
    /* G_FDIV */
    type0, type0, type0, 
    /* G_FREM */
    type0, type0, type0, 
    /* G_FPOW */
    type0, type0, type0, 
    /* G_FPOWI */
    type0, type0, type1, 
    /* G_FEXP */
    type0, type0, 
    /* G_FEXP2 */
    type0, type0, 
    /* G_FEXP10 */
    type0, type0, 
    /* G_FLOG */
    type0, type0, 
    /* G_FLOG2 */
    type0, type0, 
    /* G_FLOG10 */
    type0, type0, 
    /* G_FLDEXP */
    type0, type0, type1, 
    /* G_FFREXP */
    type0, type1, type0, 
    /* G_FNEG */
    type0, type0, 
    /* G_FPEXT */
    type0, type1, 
    /* G_FPTRUNC */
    type0, type1, 
    /* G_FPTOSI */
    type0, type1, 
    /* G_FPTOUI */
    type0, type1, 
    /* G_SITOFP */
    type0, type1, 
    /* G_UITOFP */
    type0, type1, 
    /* G_FPTOSI_SAT */
    type0, type1, 
    /* G_FPTOUI_SAT */
    type0, type1, 
    /* G_FABS */
    type0, type0, 
    /* G_FCOPYSIGN */
    type0, type0, type1, 
    /* G_IS_FPCLASS */
    type0, type1, -1, 
    /* G_FCANONICALIZE */
    type0, type0, 
    /* G_FMINNUM */
    type0, type0, type0, 
    /* G_FMAXNUM */
    type0, type0, type0, 
    /* G_FMINNUM_IEEE */
    type0, type0, type0, 
    /* G_FMAXNUM_IEEE */
    type0, type0, type0, 
    /* G_FMINIMUM */
    type0, type0, type0, 
    /* G_FMAXIMUM */
    type0, type0, type0, 
    /* G_GET_FPENV */
    type0, 
    /* G_SET_FPENV */
    type0, 
    /* G_RESET_FPENV */
    /* G_GET_FPMODE */
    type0, 
    /* G_SET_FPMODE */
    type0, 
    /* G_RESET_FPMODE */
    /* G_PTR_ADD */
    ptype0, ptype0, type1, 
    /* G_PTRMASK */
    ptype0, ptype0, type1, 
    /* G_SMIN */
    type0, type0, type0, 
    /* G_SMAX */
    type0, type0, type0, 
    /* G_UMIN */
    type0, type0, type0, 
    /* G_UMAX */
    type0, type0, type0, 
    /* G_ABS */
    type0, type0, 
    /* G_LROUND */
    type0, type1, 
    /* G_LLROUND */
    type0, type1, 
    /* G_BR */
    -1, 
    /* G_BRJT */
    ptype0, -1, type1, 
    /* G_VSCALE */
    type0, -1, 
    /* G_INSERT_SUBVECTOR */
    type0, type0, type1, untyped_imm_0, 
    /* G_EXTRACT_SUBVECTOR */
    type0, type0, untyped_imm_0, 
    /* G_INSERT_VECTOR_ELT */
    type0, type0, type1, type2, 
    /* G_EXTRACT_VECTOR_ELT */
    type0, type1, type2, 
    /* G_SHUFFLE_VECTOR */
    type0, type1, type1, -1, 
    /* G_SPLAT_VECTOR */
    type0, type1, 
    /* G_VECTOR_COMPRESS */
    type0, type0, type1, type0, 
    /* G_CTTZ */
    type0, type1, 
    /* G_CTTZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTLZ */
    type0, type1, 
    /* G_CTLZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTPOP */
    type0, type1, 
    /* G_BSWAP */
    type0, type0, 
    /* G_BITREVERSE */
    type0, type0, 
    /* G_FCEIL */
    type0, type0, 
    /* G_FCOS */
    type0, type0, 
    /* G_FSIN */
    type0, type0, 
    /* G_FTAN */
    type0, type0, 
    /* G_FACOS */
    type0, type0, 
    /* G_FASIN */
    type0, type0, 
    /* G_FATAN */
    type0, type0, 
    /* G_FCOSH */
    type0, type0, 
    /* G_FSINH */
    type0, type0, 
    /* G_FTANH */
    type0, type0, 
    /* G_FSQRT */
    type0, type0, 
    /* G_FFLOOR */
    type0, type0, 
    /* G_FRINT */
    type0, type0, 
    /* G_FNEARBYINT */
    type0, type0, 
    /* G_ADDRSPACE_CAST */
    type0, type1, 
    /* G_BLOCK_ADDR */
    type0, -1, 
    /* G_JUMP_TABLE */
    type0, -1, 
    /* G_DYN_STACKALLOC */
    ptype0, type1, i32imm, 
    /* G_STACKSAVE */
    ptype0, 
    /* G_STACKRESTORE */
    ptype0, 
    /* G_STRICT_FADD */
    type0, type0, type0, 
    /* G_STRICT_FSUB */
    type0, type0, type0, 
    /* G_STRICT_FMUL */
    type0, type0, type0, 
    /* G_STRICT_FDIV */
    type0, type0, type0, 
    /* G_STRICT_FREM */
    type0, type0, type0, 
    /* G_STRICT_FMA */
    type0, type0, type0, type0, 
    /* G_STRICT_FSQRT */
    type0, type0, 
    /* G_STRICT_FLDEXP */
    type0, type0, type1, 
    /* G_READ_REGISTER */
    type0, -1, 
    /* G_WRITE_REGISTER */
    -1, type0, 
    /* G_MEMCPY */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMCPY_INLINE */
    ptype0, ptype1, type2, 
    /* G_MEMMOVE */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMSET */
    ptype0, type1, type2, untyped_imm_0, 
    /* G_BZERO */
    ptype0, type1, untyped_imm_0, 
    /* G_TRAP */
    /* G_DEBUGTRAP */
    /* G_UBSANTRAP */
    i8imm, 
    /* G_VECREDUCE_SEQ_FADD */
    type0, type1, type2, 
    /* G_VECREDUCE_SEQ_FMUL */
    type0, type1, type2, 
    /* G_VECREDUCE_FADD */
    type0, type1, 
    /* G_VECREDUCE_FMUL */
    type0, type1, 
    /* G_VECREDUCE_FMAX */
    type0, type1, 
    /* G_VECREDUCE_FMIN */
    type0, type1, 
    /* G_VECREDUCE_FMAXIMUM */
    type0, type1, 
    /* G_VECREDUCE_FMINIMUM */
    type0, type1, 
    /* G_VECREDUCE_ADD */
    type0, type1, 
    /* G_VECREDUCE_MUL */
    type0, type1, 
    /* G_VECREDUCE_AND */
    type0, type1, 
    /* G_VECREDUCE_OR */
    type0, type1, 
    /* G_VECREDUCE_XOR */
    type0, type1, 
    /* G_VECREDUCE_SMAX */
    type0, type1, 
    /* G_VECREDUCE_SMIN */
    type0, type1, 
    /* G_VECREDUCE_UMAX */
    type0, type1, 
    /* G_VECREDUCE_UMIN */
    type0, type1, 
    /* G_SBFX */
    type0, type0, type1, type1, 
    /* G_UBFX */
    type0, type0, type1, type1, 
    /* ADD16mc */
    GR16, i16imm, cg16imm, 
    /* ADD16mi */
    GR16, i16imm, i16imm, 
    /* ADD16mm */
    GR16, i16imm, GR16, i16imm, 
    /* ADD16mn */
    GR16, i16imm, GR16, 
    /* ADD16mp */
    GR16, i16imm, GR16, 
    /* ADD16mr */
    GR16, i16imm, GR16, 
    /* ADD16rc */
    GR16, GR16, cg16imm, 
    /* ADD16ri */
    GR16, GR16, i16imm, 
    /* ADD16rm */
    GR16, GR16, GR16, i16imm, 
    /* ADD16rn */
    GR16, GR16, GR16, 
    /* ADD16rp */
    GR16, GR16, GR16, GR16, 
    /* ADD16rr */
    GR16, GR16, GR16, 
    /* ADD8mc */
    GR16, i16imm, cg8imm, 
    /* ADD8mi */
    GR16, i16imm, i8imm, 
    /* ADD8mm */
    GR16, i16imm, GR16, i16imm, 
    /* ADD8mn */
    GR16, i16imm, GR16, 
    /* ADD8mp */
    GR16, i16imm, GR16, 
    /* ADD8mr */
    GR16, i16imm, GR8, 
    /* ADD8rc */
    GR8, GR8, cg8imm, 
    /* ADD8ri */
    GR8, GR8, i8imm, 
    /* ADD8rm */
    GR8, GR8, GR16, i16imm, 
    /* ADD8rn */
    GR8, GR8, GR16, 
    /* ADD8rp */
    GR8, GR16, GR8, GR16, 
    /* ADD8rr */
    GR8, GR8, GR8, 
    /* ADDC16mc */
    GR16, i16imm, cg16imm, 
    /* ADDC16mi */
    GR16, i16imm, i16imm, 
    /* ADDC16mm */
    GR16, i16imm, GR16, i16imm, 
    /* ADDC16mn */
    GR16, i16imm, GR16, 
    /* ADDC16mp */
    GR16, i16imm, GR16, 
    /* ADDC16mr */
    GR16, i16imm, GR16, 
    /* ADDC16rc */
    GR16, GR16, cg16imm, 
    /* ADDC16ri */
    GR16, GR16, i16imm, 
    /* ADDC16rm */
    GR16, GR16, GR16, i16imm, 
    /* ADDC16rn */
    GR16, GR16, GR16, 
    /* ADDC16rp */
    GR16, GR16, GR16, GR16, 
    /* ADDC16rr */
    GR16, GR16, GR16, 
    /* ADDC8mc */
    GR16, i16imm, cg8imm, 
    /* ADDC8mi */
    GR16, i16imm, i8imm, 
    /* ADDC8mm */
    GR16, i16imm, GR16, i16imm, 
    /* ADDC8mn */
    GR16, i16imm, GR16, 
    /* ADDC8mp */
    GR16, i16imm, GR16, 
    /* ADDC8mr */
    GR16, i16imm, GR8, 
    /* ADDC8rc */
    GR8, GR8, cg8imm, 
    /* ADDC8ri */
    GR8, GR8, i8imm, 
    /* ADDC8rm */
    GR8, GR8, GR16, i16imm, 
    /* ADDC8rn */
    GR8, GR8, GR16, 
    /* ADDC8rp */
    GR8, GR16, GR8, GR16, 
    /* ADDC8rr */
    GR8, GR8, GR8, 
    /* ADDframe */
    GR16, i16imm, i16imm, 
    /* ADJCALLSTACKDOWN */
    i16imm, i16imm, 
    /* ADJCALLSTACKUP */
    i16imm, i16imm, 
    /* AND16mc */
    GR16, i16imm, cg16imm, 
    /* AND16mi */
    GR16, i16imm, i16imm, 
    /* AND16mm */
    GR16, i16imm, GR16, i16imm, 
    /* AND16mn */
    GR16, i16imm, GR16, 
    /* AND16mp */
    GR16, i16imm, GR16, 
    /* AND16mr */
    GR16, i16imm, GR16, 
    /* AND16rc */
    GR16, GR16, cg16imm, 
    /* AND16ri */
    GR16, GR16, i16imm, 
    /* AND16rm */
    GR16, GR16, GR16, i16imm, 
    /* AND16rn */
    GR16, GR16, GR16, 
    /* AND16rp */
    GR16, GR16, GR16, GR16, 
    /* AND16rr */
    GR16, GR16, GR16, 
    /* AND8mc */
    GR16, i16imm, cg8imm, 
    /* AND8mi */
    GR16, i16imm, i8imm, 
    /* AND8mm */
    GR16, i16imm, GR16, i16imm, 
    /* AND8mn */
    GR16, i16imm, GR16, 
    /* AND8mp */
    GR16, i16imm, GR16, 
    /* AND8mr */
    GR16, i16imm, GR8, 
    /* AND8rc */
    GR8, GR8, cg8imm, 
    /* AND8ri */
    GR8, GR8, i8imm, 
    /* AND8rm */
    GR8, GR8, GR16, i16imm, 
    /* AND8rn */
    GR8, GR8, GR16, 
    /* AND8rp */
    GR8, GR16, GR8, GR16, 
    /* AND8rr */
    GR8, GR8, GR8, 
    /* BIC16mc */
    GR16, i16imm, cg16imm, 
    /* BIC16mi */
    GR16, i16imm, i16imm, 
    /* BIC16mm */
    GR16, i16imm, GR16, i16imm, 
    /* BIC16mn */
    GR16, i16imm, GR16, 
    /* BIC16mp */
    GR16, i16imm, GR16, 
    /* BIC16mr */
    GR16, i16imm, GR16, 
    /* BIC16rc */
    GR16, GR16, cg16imm, 
    /* BIC16ri */
    GR16, GR16, i16imm, 
    /* BIC16rm */
    GR16, GR16, GR16, i16imm, 
    /* BIC16rn */
    GR16, GR16, GR16, 
    /* BIC16rp */
    GR16, GR16, GR16, GR16, 
    /* BIC16rr */
    GR16, GR16, GR16, 
    /* BIC8mc */
    GR16, i16imm, cg8imm, 
    /* BIC8mi */
    GR16, i16imm, i8imm, 
    /* BIC8mm */
    GR16, i16imm, GR16, i16imm, 
    /* BIC8mn */
    GR16, i16imm, GR16, 
    /* BIC8mp */
    GR16, i16imm, GR16, 
    /* BIC8mr */
    GR16, i16imm, GR8, 
    /* BIC8rc */
    GR8, GR8, cg8imm, 
    /* BIC8ri */
    GR8, GR8, i8imm, 
    /* BIC8rm */
    GR8, GR8, GR16, i16imm, 
    /* BIC8rn */
    GR8, GR8, GR16, 
    /* BIC8rp */
    GR8, GR16, GR8, GR16, 
    /* BIC8rr */
    GR8, GR8, GR8, 
    /* BIS16mc */
    GR16, i16imm, cg16imm, 
    /* BIS16mi */
    GR16, i16imm, i16imm, 
    /* BIS16mm */
    GR16, i16imm, GR16, i16imm, 
    /* BIS16mn */
    GR16, i16imm, GR16, 
    /* BIS16mp */
    GR16, i16imm, GR16, 
    /* BIS16mr */
    GR16, i16imm, GR16, 
    /* BIS16rc */
    GR16, GR16, cg16imm, 
    /* BIS16ri */
    GR16, GR16, i16imm, 
    /* BIS16rm */
    GR16, GR16, GR16, i16imm, 
    /* BIS16rn */
    GR16, GR16, GR16, 
    /* BIS16rp */
    GR16, GR16, GR16, GR16, 
    /* BIS16rr */
    GR16, GR16, GR16, 
    /* BIS8mc */
    GR16, i16imm, cg8imm, 
    /* BIS8mi */
    GR16, i16imm, i8imm, 
    /* BIS8mm */
    GR16, i16imm, GR16, i16imm, 
    /* BIS8mn */
    GR16, i16imm, GR16, 
    /* BIS8mp */
    GR16, i16imm, GR16, 
    /* BIS8mr */
    GR16, i16imm, GR8, 
    /* BIS8rc */
    GR8, GR8, cg8imm, 
    /* BIS8ri */
    GR8, GR8, i8imm, 
    /* BIS8rm */
    GR8, GR8, GR16, i16imm, 
    /* BIS8rn */
    GR8, GR8, GR16, 
    /* BIS8rp */
    GR8, GR16, GR8, GR16, 
    /* BIS8rr */
    GR8, GR8, GR8, 
    /* BIT16mc */
    GR16, i16imm, cg16imm, 
    /* BIT16mi */
    GR16, i16imm, i16imm, 
    /* BIT16mm */
    GR16, i16imm, GR16, i16imm, 
    /* BIT16mn */
    GR16, i16imm, GR16, 
    /* BIT16mp */
    GR16, i16imm, GR16, 
    /* BIT16mr */
    GR16, i16imm, GR16, 
    /* BIT16rc */
    GR16, cg16imm, 
    /* BIT16ri */
    GR16, i16imm, 
    /* BIT16rm */
    GR16, GR16, i16imm, 
    /* BIT16rn */
    GR16, GR16, 
    /* BIT16rp */
    GR16, GR16, 
    /* BIT16rr */
    GR16, GR16, 
    /* BIT8mc */
    GR16, i16imm, cg8imm, 
    /* BIT8mi */
    GR16, i16imm, i8imm, 
    /* BIT8mm */
    GR16, i16imm, GR16, i16imm, 
    /* BIT8mn */
    GR16, i16imm, GR16, 
    /* BIT8mp */
    GR16, i16imm, GR16, 
    /* BIT8mr */
    GR16, i16imm, GR8, 
    /* BIT8rc */
    GR8, cg8imm, 
    /* BIT8ri */
    GR8, i8imm, 
    /* BIT8rm */
    GR8, GR16, i16imm, 
    /* BIT8rn */
    GR8, GR16, 
    /* BIT8rp */
    GR8, GR16, 
    /* BIT8rr */
    GR8, GR8, 
    /* Bi */
    i16imm, 
    /* Bm */
    GR16, i16imm, 
    /* Br */
    GR16, 
    /* CALLi */
    i16imm, 
    /* CALLm */
    GR16, i16imm, 
    /* CALLn */
    GR16, 
    /* CALLp */
    GR16, 
    /* CALLr */
    GR16, 
    /* CMP16mc */
    GR16, i16imm, cg16imm, 
    /* CMP16mi */
    GR16, i16imm, i16imm, 
    /* CMP16mm */
    GR16, i16imm, GR16, i16imm, 
    /* CMP16mn */
    GR16, i16imm, GR16, 
    /* CMP16mp */
    GR16, i16imm, GR16, 
    /* CMP16mr */
    GR16, i16imm, GR16, 
    /* CMP16rc */
    GR16, cg16imm, 
    /* CMP16ri */
    GR16, i16imm, 
    /* CMP16rm */
    GR16, GR16, i16imm, 
    /* CMP16rn */
    GR16, GR16, 
    /* CMP16rp */
    GR16, GR16, 
    /* CMP16rr */
    GR16, GR16, 
    /* CMP8mc */
    GR16, i16imm, cg8imm, 
    /* CMP8mi */
    GR16, i16imm, i8imm, 
    /* CMP8mm */
    GR16, i16imm, GR16, i16imm, 
    /* CMP8mn */
    GR16, i16imm, GR16, 
    /* CMP8mp */
    GR16, i16imm, GR16, 
    /* CMP8mr */
    GR16, i16imm, GR8, 
    /* CMP8rc */
    GR8, cg8imm, 
    /* CMP8ri */
    GR8, i8imm, 
    /* CMP8rm */
    GR8, GR16, i16imm, 
    /* CMP8rn */
    GR8, GR16, 
    /* CMP8rp */
    GR8, GR16, 
    /* CMP8rr */
    GR8, GR8, 
    /* DADD16mc */
    GR16, i16imm, cg16imm, 
    /* DADD16mi */
    GR16, i16imm, i16imm, 
    /* DADD16mm */
    GR16, i16imm, GR16, i16imm, 
    /* DADD16mn */
    GR16, i16imm, GR16, 
    /* DADD16mp */
    GR16, i16imm, GR16, 
    /* DADD16mr */
    GR16, i16imm, GR16, 
    /* DADD16rc */
    GR16, GR16, cg16imm, 
    /* DADD16ri */
    GR16, GR16, i16imm, 
    /* DADD16rm */
    GR16, GR16, GR16, i16imm, 
    /* DADD16rn */
    GR16, GR16, GR16, 
    /* DADD16rp */
    GR16, GR16, GR16, GR16, 
    /* DADD16rr */
    GR16, GR16, GR16, 
    /* DADD8mc */
    GR16, i16imm, cg8imm, 
    /* DADD8mi */
    GR16, i16imm, i8imm, 
    /* DADD8mm */
    GR16, i16imm, GR16, i16imm, 
    /* DADD8mn */
    GR16, i16imm, GR16, 
    /* DADD8mp */
    GR16, i16imm, GR16, 
    /* DADD8mr */
    GR16, i16imm, GR8, 
    /* DADD8rc */
    GR8, GR8, cg8imm, 
    /* DADD8ri */
    GR8, GR8, i8imm, 
    /* DADD8rm */
    GR8, GR8, GR16, i16imm, 
    /* DADD8rn */
    GR8, GR8, GR16, 
    /* DADD8rp */
    GR8, GR16, GR8, GR16, 
    /* DADD8rr */
    GR8, GR8, GR8, 
    /* JCC */
    jmptarget, cc, 
    /* JMP */
    jmptarget, 
    /* MOV16mc */
    GR16, i16imm, cg16imm, 
    /* MOV16mi */
    GR16, i16imm, i16imm, 
    /* MOV16mm */
    GR16, i16imm, GR16, i16imm, 
    /* MOV16mn */
    GR16, i16imm, GR16, 
    /* MOV16mr */
    GR16, i16imm, GR16, 
    /* MOV16rc */
    GR16, cg16imm, 
    /* MOV16ri */
    GR16, i16imm, 
    /* MOV16rm */
    GR16, GR16, i16imm, 
    /* MOV16rn */
    GR16, GR16, 
    /* MOV16rp */
    GR16, GR16, GR16, 
    /* MOV16rr */
    GR16, GR16, 
    /* MOV8mc */
    GR16, i16imm, cg8imm, 
    /* MOV8mi */
    GR16, i16imm, i8imm, 
    /* MOV8mm */
    GR16, i16imm, GR16, i16imm, 
    /* MOV8mn */
    GR16, i16imm, GR16, 
    /* MOV8mr */
    GR16, i16imm, GR8, 
    /* MOV8rc */
    GR8, cg8imm, 
    /* MOV8ri */
    GR8, i8imm, 
    /* MOV8rm */
    GR8, GR16, i16imm, 
    /* MOV8rn */
    GR8, GR16, 
    /* MOV8rp */
    GR8, GR16, GR16, 
    /* MOV8rr */
    GR8, GR8, 
    /* MOVZX16rm8 */
    GR16, GR16, i16imm, 
    /* MOVZX16rr8 */
    GR16, GR8, 
    /* POP16r */
    GR16, 
    /* PUSH16c */
    cg16imm, 
    /* PUSH16i */
    i16imm, 
    /* PUSH16r */
    GR16, 
    /* PUSH8r */
    GR8, 
    /* RET */
    /* RETI */
    /* RRA16m */
    GR16, i16imm, 
    /* RRA16n */
    GR16, 
    /* RRA16p */
    GR16, 
    /* RRA16r */
    GR16, GR16, 
    /* RRA8m */
    GR16, i16imm, 
    /* RRA8n */
    GR16, 
    /* RRA8p */
    GR16, 
    /* RRA8r */
    GR8, GR8, 
    /* RRC16m */
    GR16, i16imm, 
    /* RRC16n */
    GR16, 
    /* RRC16p */
    GR16, 
    /* RRC16r */
    GR16, GR16, 
    /* RRC8m */
    GR16, i16imm, 
    /* RRC8n */
    GR16, 
    /* RRC8p */
    GR16, 
    /* RRC8r */
    GR8, GR8, 
    /* Rrcl16 */
    GR16, GR16, 
    /* Rrcl8 */
    GR8, GR8, 
    /* SEXT16m */
    GR16, i16imm, 
    /* SEXT16n */
    GR16, 
    /* SEXT16p */
    GR16, 
    /* SEXT16r */
    GR16, GR16, 
    /* SUB16mc */
    GR16, i16imm, cg16imm, 
    /* SUB16mi */
    GR16, i16imm, i16imm, 
    /* SUB16mm */
    GR16, i16imm, GR16, i16imm, 
    /* SUB16mn */
    GR16, i16imm, GR16, 
    /* SUB16mp */
    GR16, i16imm, GR16, 
    /* SUB16mr */
    GR16, i16imm, GR16, 
    /* SUB16rc */
    GR16, GR16, cg16imm, 
    /* SUB16ri */
    GR16, GR16, i16imm, 
    /* SUB16rm */
    GR16, GR16, GR16, i16imm, 
    /* SUB16rn */
    GR16, GR16, GR16, 
    /* SUB16rp */
    GR16, GR16, GR16, GR16, 
    /* SUB16rr */
    GR16, GR16, GR16, 
    /* SUB8mc */
    GR16, i16imm, cg8imm, 
    /* SUB8mi */
    GR16, i16imm, i8imm, 
    /* SUB8mm */
    GR16, i16imm, GR16, i16imm, 
    /* SUB8mn */
    GR16, i16imm, GR16, 
    /* SUB8mp */
    GR16, i16imm, GR16, 
    /* SUB8mr */
    GR16, i16imm, GR8, 
    /* SUB8rc */
    GR8, GR8, cg8imm, 
    /* SUB8ri */
    GR8, GR8, i8imm, 
    /* SUB8rm */
    GR8, GR8, GR16, i16imm, 
    /* SUB8rn */
    GR8, GR8, GR16, 
    /* SUB8rp */
    GR8, GR16, GR8, GR16, 
    /* SUB8rr */
    GR8, GR8, GR8, 
    /* SUBC16mc */
    GR16, i16imm, cg16imm, 
    /* SUBC16mi */
    GR16, i16imm, i16imm, 
    /* SUBC16mm */
    GR16, i16imm, GR16, i16imm, 
    /* SUBC16mn */
    GR16, i16imm, GR16, 
    /* SUBC16mp */
    GR16, i16imm, GR16, 
    /* SUBC16mr */
    GR16, i16imm, GR16, 
    /* SUBC16rc */
    GR16, GR16, cg16imm, 
    /* SUBC16ri */
    GR16, GR16, i16imm, 
    /* SUBC16rm */
    GR16, GR16, GR16, i16imm, 
    /* SUBC16rn */
    GR16, GR16, GR16, 
    /* SUBC16rp */
    GR16, GR16, GR16, GR16, 
    /* SUBC16rr */
    GR16, GR16, GR16, 
    /* SUBC8mc */
    GR16, i16imm, cg8imm, 
    /* SUBC8mi */
    GR16, i16imm, i8imm, 
    /* SUBC8mm */
    GR16, i16imm, GR16, i16imm, 
    /* SUBC8mn */
    GR16, i16imm, GR16, 
    /* SUBC8mp */
    GR16, i16imm, GR16, 
    /* SUBC8mr */
    GR16, i16imm, GR8, 
    /* SUBC8rc */
    GR8, GR8, cg8imm, 
    /* SUBC8ri */
    GR8, GR8, i8imm, 
    /* SUBC8rm */
    GR8, GR8, GR16, i16imm, 
    /* SUBC8rn */
    GR8, GR8, GR16, 
    /* SUBC8rp */
    GR8, GR16, GR8, GR16, 
    /* SUBC8rr */
    GR8, GR8, GR8, 
    /* SWPB16m */
    GR16, i16imm, 
    /* SWPB16n */
    GR16, 
    /* SWPB16p */
    GR16, 
    /* SWPB16r */
    GR16, GR16, 
    /* Select16 */
    GR16, GR16, GR16, i8imm, 
    /* Select8 */
    GR8, GR8, GR8, i8imm, 
    /* Shl16 */
    GR16, GR16, GR8, 
    /* Shl8 */
    GR8, GR8, GR8, 
    /* Sra16 */
    GR16, GR16, GR8, 
    /* Sra8 */
    GR8, GR8, GR8, 
    /* Srl16 */
    GR16, GR16, GR8, 
    /* Srl8 */
    GR8, GR8, GR8, 
    /* XOR16mc */
    GR16, i16imm, cg16imm, 
    /* XOR16mi */
    GR16, i16imm, i16imm, 
    /* XOR16mm */
    GR16, i16imm, GR16, i16imm, 
    /* XOR16mn */
    GR16, i16imm, GR16, 
    /* XOR16mp */
    GR16, i16imm, GR16, 
    /* XOR16mr */
    GR16, i16imm, GR16, 
    /* XOR16rc */
    GR16, GR16, cg16imm, 
    /* XOR16ri */
    GR16, GR16, i16imm, 
    /* XOR16rm */
    GR16, GR16, GR16, i16imm, 
    /* XOR16rn */
    GR16, GR16, GR16, 
    /* XOR16rp */
    GR16, GR16, GR16, GR16, 
    /* XOR16rr */
    GR16, GR16, GR16, 
    /* XOR8mc */
    GR16, i16imm, cg8imm, 
    /* XOR8mi */
    GR16, i16imm, i8imm, 
    /* XOR8mm */
    GR16, i16imm, GR16, i16imm, 
    /* XOR8mn */
    GR16, i16imm, GR16, 
    /* XOR8mp */
    GR16, i16imm, GR16, 
    /* XOR8mr */
    GR16, i16imm, GR8, 
    /* XOR8rc */
    GR8, GR8, cg8imm, 
    /* XOR8ri */
    GR8, GR8, i8imm, 
    /* XOR8rm */
    GR8, GR8, GR16, i16imm, 
    /* XOR8rn */
    GR8, GR8, GR16, 
    /* XOR8rp */
    GR8, GR16, GR8, GR16, 
    /* XOR8rr */
    GR8, GR8, GR8, 
    /* ZEXT16r */
    GR16, GR16, 
  };
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
}
} // end namespace MSP430
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPE

#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
namespace llvm {
namespace MSP430 {
LLVM_READONLY
static int getMemOperandSize(int OpType) {
  switch (OpType) {
  default: return 0;
  }
}
} // end namespace MSP430
} // end namespace llvm
#endif // GET_INSTRINFO_MEM_OPERAND_SIZE

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
namespace llvm {
namespace MSP430 {
LLVM_READONLY static unsigned
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return LogicalOpIdx;
}
LLVM_READONLY static inline unsigned
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
  auto S = 0U;
  for (auto i = 0U; i < LogicalOpIdx; ++i)
    S += getLogicalOperandSize(Opcode, i);
  return S;
}
} // end namespace MSP430
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
namespace llvm {
namespace MSP430 {
LLVM_READONLY static int
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return -1;
}
} // end namespace MSP430
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP

#ifdef GET_INSTRINFO_MC_HELPER_DECLS
#undef GET_INSTRINFO_MC_HELPER_DECLS

namespace llvm {
class MCInst;
class FeatureBitset;

namespace MSP430_MC {

void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);

} // end namespace MSP430_MC
} // end namespace llvm

#endif // GET_INSTRINFO_MC_HELPER_DECLS

#ifdef GET_INSTRINFO_MC_HELPERS
#undef GET_INSTRINFO_MC_HELPERS

namespace llvm {
namespace MSP430_MC {

} // end namespace MSP430_MC
} // end namespace llvm

#endif // GET_GENISTRINFO_MC_HELPERS

#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
    defined(GET_AVAILABLE_OPCODE_CHECKER)
#define GET_COMPUTE_FEATURES
#endif
#ifdef GET_COMPUTE_FEATURES
#undef GET_COMPUTE_FEATURES
namespace llvm {
namespace MSP430_MC {

// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
};

inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
  FeatureBitset Features;
  return Features;
}

inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
  enum : uint8_t {
    CEFBS_None,
  };

  static constexpr FeatureBitset FeatureBitsets[] = {
    {}, // CEFBS_None
  };
  static constexpr uint8_t RequiredFeaturesRefs[] = {
    CEFBS_None, // PHI = 0
    CEFBS_None, // INLINEASM = 1
    CEFBS_None, // INLINEASM_BR = 2
    CEFBS_None, // CFI_INSTRUCTION = 3
    CEFBS_None, // EH_LABEL = 4
    CEFBS_None, // GC_LABEL = 5
    CEFBS_None, // ANNOTATION_LABEL = 6
    CEFBS_None, // KILL = 7
    CEFBS_None, // EXTRACT_SUBREG = 8
    CEFBS_None, // INSERT_SUBREG = 9
    CEFBS_None, // IMPLICIT_DEF = 10
    CEFBS_None, // INIT_UNDEF = 11
    CEFBS_None, // SUBREG_TO_REG = 12
    CEFBS_None, // COPY_TO_REGCLASS = 13
    CEFBS_None, // DBG_VALUE = 14
    CEFBS_None, // DBG_VALUE_LIST = 15
    CEFBS_None, // DBG_INSTR_REF = 16
    CEFBS_None, // DBG_PHI = 17
    CEFBS_None, // DBG_LABEL = 18
    CEFBS_None, // REG_SEQUENCE = 19
    CEFBS_None, // COPY = 20
    CEFBS_None, // BUNDLE = 21
    CEFBS_None, // LIFETIME_START = 22
    CEFBS_None, // LIFETIME_END = 23
    CEFBS_None, // PSEUDO_PROBE = 24
    CEFBS_None, // ARITH_FENCE = 25
    CEFBS_None, // STACKMAP = 26
    CEFBS_None, // FENTRY_CALL = 27
    CEFBS_None, // PATCHPOINT = 28
    CEFBS_None, // LOAD_STACK_GUARD = 29
    CEFBS_None, // PREALLOCATED_SETUP = 30
    CEFBS_None, // PREALLOCATED_ARG = 31
    CEFBS_None, // STATEPOINT = 32
    CEFBS_None, // LOCAL_ESCAPE = 33
    CEFBS_None, // FAULTING_OP = 34
    CEFBS_None, // PATCHABLE_OP = 35
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 36
    CEFBS_None, // PATCHABLE_RET = 37
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 38
    CEFBS_None, // PATCHABLE_TAIL_CALL = 39
    CEFBS_None, // PATCHABLE_EVENT_CALL = 40
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 41
    CEFBS_None, // ICALL_BRANCH_FUNNEL = 42
    CEFBS_None, // FAKE_USE = 43
    CEFBS_None, // MEMBARRIER = 44
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 45
    CEFBS_None, // CONVERGENCECTRL_ENTRY = 46
    CEFBS_None, // CONVERGENCECTRL_ANCHOR = 47
    CEFBS_None, // CONVERGENCECTRL_LOOP = 48
    CEFBS_None, // CONVERGENCECTRL_GLUE = 49
    CEFBS_None, // G_ASSERT_SEXT = 50
    CEFBS_None, // G_ASSERT_ZEXT = 51
    CEFBS_None, // G_ASSERT_ALIGN = 52
    CEFBS_None, // G_ADD = 53
    CEFBS_None, // G_SUB = 54
    CEFBS_None, // G_MUL = 55
    CEFBS_None, // G_SDIV = 56
    CEFBS_None, // G_UDIV = 57
    CEFBS_None, // G_SREM = 58
    CEFBS_None, // G_UREM = 59
    CEFBS_None, // G_SDIVREM = 60
    CEFBS_None, // G_UDIVREM = 61
    CEFBS_None, // G_AND = 62
    CEFBS_None, // G_OR = 63
    CEFBS_None, // G_XOR = 64
    CEFBS_None, // G_IMPLICIT_DEF = 65
    CEFBS_None, // G_PHI = 66
    CEFBS_None, // G_FRAME_INDEX = 67
    CEFBS_None, // G_GLOBAL_VALUE = 68
    CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 69
    CEFBS_None, // G_CONSTANT_POOL = 70
    CEFBS_None, // G_EXTRACT = 71
    CEFBS_None, // G_UNMERGE_VALUES = 72
    CEFBS_None, // G_INSERT = 73
    CEFBS_None, // G_MERGE_VALUES = 74
    CEFBS_None, // G_BUILD_VECTOR = 75
    CEFBS_None, // G_BUILD_VECTOR_TRUNC = 76
    CEFBS_None, // G_CONCAT_VECTORS = 77
    CEFBS_None, // G_PTRTOINT = 78
    CEFBS_None, // G_INTTOPTR = 79
    CEFBS_None, // G_BITCAST = 80
    CEFBS_None, // G_FREEZE = 81
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 82
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 83
    CEFBS_None, // G_INTRINSIC_TRUNC = 84
    CEFBS_None, // G_INTRINSIC_ROUND = 85
    CEFBS_None, // G_INTRINSIC_LRINT = 86
    CEFBS_None, // G_INTRINSIC_LLRINT = 87
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 88
    CEFBS_None, // G_READCYCLECOUNTER = 89
    CEFBS_None, // G_READSTEADYCOUNTER = 90
    CEFBS_None, // G_LOAD = 91
    CEFBS_None, // G_SEXTLOAD = 92
    CEFBS_None, // G_ZEXTLOAD = 93
    CEFBS_None, // G_INDEXED_LOAD = 94
    CEFBS_None, // G_INDEXED_SEXTLOAD = 95
    CEFBS_None, // G_INDEXED_ZEXTLOAD = 96
    CEFBS_None, // G_STORE = 97
    CEFBS_None, // G_INDEXED_STORE = 98
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 99
    CEFBS_None, // G_ATOMIC_CMPXCHG = 100
    CEFBS_None, // G_ATOMICRMW_XCHG = 101
    CEFBS_None, // G_ATOMICRMW_ADD = 102
    CEFBS_None, // G_ATOMICRMW_SUB = 103
    CEFBS_None, // G_ATOMICRMW_AND = 104
    CEFBS_None, // G_ATOMICRMW_NAND = 105
    CEFBS_None, // G_ATOMICRMW_OR = 106
    CEFBS_None, // G_ATOMICRMW_XOR = 107
    CEFBS_None, // G_ATOMICRMW_MAX = 108
    CEFBS_None, // G_ATOMICRMW_MIN = 109
    CEFBS_None, // G_ATOMICRMW_UMAX = 110
    CEFBS_None, // G_ATOMICRMW_UMIN = 111
    CEFBS_None, // G_ATOMICRMW_FADD = 112
    CEFBS_None, // G_ATOMICRMW_FSUB = 113
    CEFBS_None, // G_ATOMICRMW_FMAX = 114
    CEFBS_None, // G_ATOMICRMW_FMIN = 115
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 116
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 117
    CEFBS_None, // G_ATOMICRMW_USUB_COND = 118
    CEFBS_None, // G_ATOMICRMW_USUB_SAT = 119
    CEFBS_None, // G_FENCE = 120
    CEFBS_None, // G_PREFETCH = 121
    CEFBS_None, // G_BRCOND = 122
    CEFBS_None, // G_BRINDIRECT = 123
    CEFBS_None, // G_INVOKE_REGION_START = 124
    CEFBS_None, // G_INTRINSIC = 125
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 126
    CEFBS_None, // G_INTRINSIC_CONVERGENT = 127
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 128
    CEFBS_None, // G_ANYEXT = 129
    CEFBS_None, // G_TRUNC = 130
    CEFBS_None, // G_CONSTANT = 131
    CEFBS_None, // G_FCONSTANT = 132
    CEFBS_None, // G_VASTART = 133
    CEFBS_None, // G_VAARG = 134
    CEFBS_None, // G_SEXT = 135
    CEFBS_None, // G_SEXT_INREG = 136
    CEFBS_None, // G_ZEXT = 137
    CEFBS_None, // G_SHL = 138
    CEFBS_None, // G_LSHR = 139
    CEFBS_None, // G_ASHR = 140
    CEFBS_None, // G_FSHL = 141
    CEFBS_None, // G_FSHR = 142
    CEFBS_None, // G_ROTR = 143
    CEFBS_None, // G_ROTL = 144
    CEFBS_None, // G_ICMP = 145
    CEFBS_None, // G_FCMP = 146
    CEFBS_None, // G_SCMP = 147
    CEFBS_None, // G_UCMP = 148
    CEFBS_None, // G_SELECT = 149
    CEFBS_None, // G_UADDO = 150
    CEFBS_None, // G_UADDE = 151
    CEFBS_None, // G_USUBO = 152
    CEFBS_None, // G_USUBE = 153
    CEFBS_None, // G_SADDO = 154
    CEFBS_None, // G_SADDE = 155
    CEFBS_None, // G_SSUBO = 156
    CEFBS_None, // G_SSUBE = 157
    CEFBS_None, // G_UMULO = 158
    CEFBS_None, // G_SMULO = 159
    CEFBS_None, // G_UMULH = 160
    CEFBS_None, // G_SMULH = 161
    CEFBS_None, // G_UADDSAT = 162
    CEFBS_None, // G_SADDSAT = 163
    CEFBS_None, // G_USUBSAT = 164
    CEFBS_None, // G_SSUBSAT = 165
    CEFBS_None, // G_USHLSAT = 166
    CEFBS_None, // G_SSHLSAT = 167
    CEFBS_None, // G_SMULFIX = 168
    CEFBS_None, // G_UMULFIX = 169
    CEFBS_None, // G_SMULFIXSAT = 170
    CEFBS_None, // G_UMULFIXSAT = 171
    CEFBS_None, // G_SDIVFIX = 172
    CEFBS_None, // G_UDIVFIX = 173
    CEFBS_None, // G_SDIVFIXSAT = 174
    CEFBS_None, // G_UDIVFIXSAT = 175
    CEFBS_None, // G_FADD = 176
    CEFBS_None, // G_FSUB = 177
    CEFBS_None, // G_FMUL = 178
    CEFBS_None, // G_FMA = 179
    CEFBS_None, // G_FMAD = 180
    CEFBS_None, // G_FDIV = 181
    CEFBS_None, // G_FREM = 182
    CEFBS_None, // G_FPOW = 183
    CEFBS_None, // G_FPOWI = 184
    CEFBS_None, // G_FEXP = 185
    CEFBS_None, // G_FEXP2 = 186
    CEFBS_None, // G_FEXP10 = 187
    CEFBS_None, // G_FLOG = 188
    CEFBS_None, // G_FLOG2 = 189
    CEFBS_None, // G_FLOG10 = 190
    CEFBS_None, // G_FLDEXP = 191
    CEFBS_None, // G_FFREXP = 192
    CEFBS_None, // G_FNEG = 193
    CEFBS_None, // G_FPEXT = 194
    CEFBS_None, // G_FPTRUNC = 195
    CEFBS_None, // G_FPTOSI = 196
    CEFBS_None, // G_FPTOUI = 197
    CEFBS_None, // G_SITOFP = 198
    CEFBS_None, // G_UITOFP = 199
    CEFBS_None, // G_FPTOSI_SAT = 200
    CEFBS_None, // G_FPTOUI_SAT = 201
    CEFBS_None, // G_FABS = 202
    CEFBS_None, // G_FCOPYSIGN = 203
    CEFBS_None, // G_IS_FPCLASS = 204
    CEFBS_None, // G_FCANONICALIZE = 205
    CEFBS_None, // G_FMINNUM = 206
    CEFBS_None, // G_FMAXNUM = 207
    CEFBS_None, // G_FMINNUM_IEEE = 208
    CEFBS_None, // G_FMAXNUM_IEEE = 209
    CEFBS_None, // G_FMINIMUM = 210
    CEFBS_None, // G_FMAXIMUM = 211
    CEFBS_None, // G_GET_FPENV = 212
    CEFBS_None, // G_SET_FPENV = 213
    CEFBS_None, // G_RESET_FPENV = 214
    CEFBS_None, // G_GET_FPMODE = 215
    CEFBS_None, // G_SET_FPMODE = 216
    CEFBS_None, // G_RESET_FPMODE = 217
    CEFBS_None, // G_PTR_ADD = 218
    CEFBS_None, // G_PTRMASK = 219
    CEFBS_None, // G_SMIN = 220
    CEFBS_None, // G_SMAX = 221
    CEFBS_None, // G_UMIN = 222
    CEFBS_None, // G_UMAX = 223
    CEFBS_None, // G_ABS = 224
    CEFBS_None, // G_LROUND = 225
    CEFBS_None, // G_LLROUND = 226
    CEFBS_None, // G_BR = 227
    CEFBS_None, // G_BRJT = 228
    CEFBS_None, // G_VSCALE = 229
    CEFBS_None, // G_INSERT_SUBVECTOR = 230
    CEFBS_None, // G_EXTRACT_SUBVECTOR = 231
    CEFBS_None, // G_INSERT_VECTOR_ELT = 232
    CEFBS_None, // G_EXTRACT_VECTOR_ELT = 233
    CEFBS_None, // G_SHUFFLE_VECTOR = 234
    CEFBS_None, // G_SPLAT_VECTOR = 235
    CEFBS_None, // G_VECTOR_COMPRESS = 236
    CEFBS_None, // G_CTTZ = 237
    CEFBS_None, // G_CTTZ_ZERO_UNDEF = 238
    CEFBS_None, // G_CTLZ = 239
    CEFBS_None, // G_CTLZ_ZERO_UNDEF = 240
    CEFBS_None, // G_CTPOP = 241
    CEFBS_None, // G_BSWAP = 242
    CEFBS_None, // G_BITREVERSE = 243
    CEFBS_None, // G_FCEIL = 244
    CEFBS_None, // G_FCOS = 245
    CEFBS_None, // G_FSIN = 246
    CEFBS_None, // G_FTAN = 247
    CEFBS_None, // G_FACOS = 248
    CEFBS_None, // G_FASIN = 249
    CEFBS_None, // G_FATAN = 250
    CEFBS_None, // G_FCOSH = 251
    CEFBS_None, // G_FSINH = 252
    CEFBS_None, // G_FTANH = 253
    CEFBS_None, // G_FSQRT = 254
    CEFBS_None, // G_FFLOOR = 255
    CEFBS_None, // G_FRINT = 256
    CEFBS_None, // G_FNEARBYINT = 257
    CEFBS_None, // G_ADDRSPACE_CAST = 258
    CEFBS_None, // G_BLOCK_ADDR = 259
    CEFBS_None, // G_JUMP_TABLE = 260
    CEFBS_None, // G_DYN_STACKALLOC = 261
    CEFBS_None, // G_STACKSAVE = 262
    CEFBS_None, // G_STACKRESTORE = 263
    CEFBS_None, // G_STRICT_FADD = 264
    CEFBS_None, // G_STRICT_FSUB = 265
    CEFBS_None, // G_STRICT_FMUL = 266
    CEFBS_None, // G_STRICT_FDIV = 267
    CEFBS_None, // G_STRICT_FREM = 268
    CEFBS_None, // G_STRICT_FMA = 269
    CEFBS_None, // G_STRICT_FSQRT = 270
    CEFBS_None, // G_STRICT_FLDEXP = 271
    CEFBS_None, // G_READ_REGISTER = 272
    CEFBS_None, // G_WRITE_REGISTER = 273
    CEFBS_None, // G_MEMCPY = 274
    CEFBS_None, // G_MEMCPY_INLINE = 275
    CEFBS_None, // G_MEMMOVE = 276
    CEFBS_None, // G_MEMSET = 277
    CEFBS_None, // G_BZERO = 278
    CEFBS_None, // G_TRAP = 279
    CEFBS_None, // G_DEBUGTRAP = 280
    CEFBS_None, // G_UBSANTRAP = 281
    CEFBS_None, // G_VECREDUCE_SEQ_FADD = 282
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 283
    CEFBS_None, // G_VECREDUCE_FADD = 284
    CEFBS_None, // G_VECREDUCE_FMUL = 285
    CEFBS_None, // G_VECREDUCE_FMAX = 286
    CEFBS_None, // G_VECREDUCE_FMIN = 287
    CEFBS_None, // G_VECREDUCE_FMAXIMUM = 288
    CEFBS_None, // G_VECREDUCE_FMINIMUM = 289
    CEFBS_None, // G_VECREDUCE_ADD = 290
    CEFBS_None, // G_VECREDUCE_MUL = 291
    CEFBS_None, // G_VECREDUCE_AND = 292
    CEFBS_None, // G_VECREDUCE_OR = 293
    CEFBS_None, // G_VECREDUCE_XOR = 294
    CEFBS_None, // G_VECREDUCE_SMAX = 295
    CEFBS_None, // G_VECREDUCE_SMIN = 296
    CEFBS_None, // G_VECREDUCE_UMAX = 297
    CEFBS_None, // G_VECREDUCE_UMIN = 298
    CEFBS_None, // G_SBFX = 299
    CEFBS_None, // G_UBFX = 300
    CEFBS_None, // ADD16mc = 301
    CEFBS_None, // ADD16mi = 302
    CEFBS_None, // ADD16mm = 303
    CEFBS_None, // ADD16mn = 304
    CEFBS_None, // ADD16mp = 305
    CEFBS_None, // ADD16mr = 306
    CEFBS_None, // ADD16rc = 307
    CEFBS_None, // ADD16ri = 308
    CEFBS_None, // ADD16rm = 309
    CEFBS_None, // ADD16rn = 310
    CEFBS_None, // ADD16rp = 311
    CEFBS_None, // ADD16rr = 312
    CEFBS_None, // ADD8mc = 313
    CEFBS_None, // ADD8mi = 314
    CEFBS_None, // ADD8mm = 315
    CEFBS_None, // ADD8mn = 316
    CEFBS_None, // ADD8mp = 317
    CEFBS_None, // ADD8mr = 318
    CEFBS_None, // ADD8rc = 319
    CEFBS_None, // ADD8ri = 320
    CEFBS_None, // ADD8rm = 321
    CEFBS_None, // ADD8rn = 322
    CEFBS_None, // ADD8rp = 323
    CEFBS_None, // ADD8rr = 324
    CEFBS_None, // ADDC16mc = 325
    CEFBS_None, // ADDC16mi = 326
    CEFBS_None, // ADDC16mm = 327
    CEFBS_None, // ADDC16mn = 328
    CEFBS_None, // ADDC16mp = 329
    CEFBS_None, // ADDC16mr = 330
    CEFBS_None, // ADDC16rc = 331
    CEFBS_None, // ADDC16ri = 332
    CEFBS_None, // ADDC16rm = 333
    CEFBS_None, // ADDC16rn = 334
    CEFBS_None, // ADDC16rp = 335
    CEFBS_None, // ADDC16rr = 336
    CEFBS_None, // ADDC8mc = 337
    CEFBS_None, // ADDC8mi = 338
    CEFBS_None, // ADDC8mm = 339
    CEFBS_None, // ADDC8mn = 340
    CEFBS_None, // ADDC8mp = 341
    CEFBS_None, // ADDC8mr = 342
    CEFBS_None, // ADDC8rc = 343
    CEFBS_None, // ADDC8ri = 344
    CEFBS_None, // ADDC8rm = 345
    CEFBS_None, // ADDC8rn = 346
    CEFBS_None, // ADDC8rp = 347
    CEFBS_None, // ADDC8rr = 348
    CEFBS_None, // ADDframe = 349
    CEFBS_None, // ADJCALLSTACKDOWN = 350
    CEFBS_None, // ADJCALLSTACKUP = 351
    CEFBS_None, // AND16mc = 352
    CEFBS_None, // AND16mi = 353
    CEFBS_None, // AND16mm = 354
    CEFBS_None, // AND16mn = 355
    CEFBS_None, // AND16mp = 356
    CEFBS_None, // AND16mr = 357
    CEFBS_None, // AND16rc = 358
    CEFBS_None, // AND16ri = 359
    CEFBS_None, // AND16rm = 360
    CEFBS_None, // AND16rn = 361
    CEFBS_None, // AND16rp = 362
    CEFBS_None, // AND16rr = 363
    CEFBS_None, // AND8mc = 364
    CEFBS_None, // AND8mi = 365
    CEFBS_None, // AND8mm = 366
    CEFBS_None, // AND8mn = 367
    CEFBS_None, // AND8mp = 368
    CEFBS_None, // AND8mr = 369
    CEFBS_None, // AND8rc = 370
    CEFBS_None, // AND8ri = 371
    CEFBS_None, // AND8rm = 372
    CEFBS_None, // AND8rn = 373
    CEFBS_None, // AND8rp = 374
    CEFBS_None, // AND8rr = 375
    CEFBS_None, // BIC16mc = 376
    CEFBS_None, // BIC16mi = 377
    CEFBS_None, // BIC16mm = 378
    CEFBS_None, // BIC16mn = 379
    CEFBS_None, // BIC16mp = 380
    CEFBS_None, // BIC16mr = 381
    CEFBS_None, // BIC16rc = 382
    CEFBS_None, // BIC16ri = 383
    CEFBS_None, // BIC16rm = 384
    CEFBS_None, // BIC16rn = 385
    CEFBS_None, // BIC16rp = 386
    CEFBS_None, // BIC16rr = 387
    CEFBS_None, // BIC8mc = 388
    CEFBS_None, // BIC8mi = 389
    CEFBS_None, // BIC8mm = 390
    CEFBS_None, // BIC8mn = 391
    CEFBS_None, // BIC8mp = 392
    CEFBS_None, // BIC8mr = 393
    CEFBS_None, // BIC8rc = 394
    CEFBS_None, // BIC8ri = 395
    CEFBS_None, // BIC8rm = 396
    CEFBS_None, // BIC8rn = 397
    CEFBS_None, // BIC8rp = 398
    CEFBS_None, // BIC8rr = 399
    CEFBS_None, // BIS16mc = 400
    CEFBS_None, // BIS16mi = 401
    CEFBS_None, // BIS16mm = 402
    CEFBS_None, // BIS16mn = 403
    CEFBS_None, // BIS16mp = 404
    CEFBS_None, // BIS16mr = 405
    CEFBS_None, // BIS16rc = 406
    CEFBS_None, // BIS16ri = 407
    CEFBS_None, // BIS16rm = 408
    CEFBS_None, // BIS16rn = 409
    CEFBS_None, // BIS16rp = 410
    CEFBS_None, // BIS16rr = 411
    CEFBS_None, // BIS8mc = 412
    CEFBS_None, // BIS8mi = 413
    CEFBS_None, // BIS8mm = 414
    CEFBS_None, // BIS8mn = 415
    CEFBS_None, // BIS8mp = 416
    CEFBS_None, // BIS8mr = 417
    CEFBS_None, // BIS8rc = 418
    CEFBS_None, // BIS8ri = 419
    CEFBS_None, // BIS8rm = 420
    CEFBS_None, // BIS8rn = 421
    CEFBS_None, // BIS8rp = 422
    CEFBS_None, // BIS8rr = 423
    CEFBS_None, // BIT16mc = 424
    CEFBS_None, // BIT16mi = 425
    CEFBS_None, // BIT16mm = 426
    CEFBS_None, // BIT16mn = 427
    CEFBS_None, // BIT16mp = 428
    CEFBS_None, // BIT16mr = 429
    CEFBS_None, // BIT16rc = 430
    CEFBS_None, // BIT16ri = 431
    CEFBS_None, // BIT16rm = 432
    CEFBS_None, // BIT16rn = 433
    CEFBS_None, // BIT16rp = 434
    CEFBS_None, // BIT16rr = 435
    CEFBS_None, // BIT8mc = 436
    CEFBS_None, // BIT8mi = 437
    CEFBS_None, // BIT8mm = 438
    CEFBS_None, // BIT8mn = 439
    CEFBS_None, // BIT8mp = 440
    CEFBS_None, // BIT8mr = 441
    CEFBS_None, // BIT8rc = 442
    CEFBS_None, // BIT8ri = 443
    CEFBS_None, // BIT8rm = 444
    CEFBS_None, // BIT8rn = 445
    CEFBS_None, // BIT8rp = 446
    CEFBS_None, // BIT8rr = 447
    CEFBS_None, // Bi = 448
    CEFBS_None, // Bm = 449
    CEFBS_None, // Br = 450
    CEFBS_None, // CALLi = 451
    CEFBS_None, // CALLm = 452
    CEFBS_None, // CALLn = 453
    CEFBS_None, // CALLp = 454
    CEFBS_None, // CALLr = 455
    CEFBS_None, // CMP16mc = 456
    CEFBS_None, // CMP16mi = 457
    CEFBS_None, // CMP16mm = 458
    CEFBS_None, // CMP16mn = 459
    CEFBS_None, // CMP16mp = 460
    CEFBS_None, // CMP16mr = 461
    CEFBS_None, // CMP16rc = 462
    CEFBS_None, // CMP16ri = 463
    CEFBS_None, // CMP16rm = 464
    CEFBS_None, // CMP16rn = 465
    CEFBS_None, // CMP16rp = 466
    CEFBS_None, // CMP16rr = 467
    CEFBS_None, // CMP8mc = 468
    CEFBS_None, // CMP8mi = 469
    CEFBS_None, // CMP8mm = 470
    CEFBS_None, // CMP8mn = 471
    CEFBS_None, // CMP8mp = 472
    CEFBS_None, // CMP8mr = 473
    CEFBS_None, // CMP8rc = 474
    CEFBS_None, // CMP8ri = 475
    CEFBS_None, // CMP8rm = 476
    CEFBS_None, // CMP8rn = 477
    CEFBS_None, // CMP8rp = 478
    CEFBS_None, // CMP8rr = 479
    CEFBS_None, // DADD16mc = 480
    CEFBS_None, // DADD16mi = 481
    CEFBS_None, // DADD16mm = 482
    CEFBS_None, // DADD16mn = 483
    CEFBS_None, // DADD16mp = 484
    CEFBS_None, // DADD16mr = 485
    CEFBS_None, // DADD16rc = 486
    CEFBS_None, // DADD16ri = 487
    CEFBS_None, // DADD16rm = 488
    CEFBS_None, // DADD16rn = 489
    CEFBS_None, // DADD16rp = 490
    CEFBS_None, // DADD16rr = 491
    CEFBS_None, // DADD8mc = 492
    CEFBS_None, // DADD8mi = 493
    CEFBS_None, // DADD8mm = 494
    CEFBS_None, // DADD8mn = 495
    CEFBS_None, // DADD8mp = 496
    CEFBS_None, // DADD8mr = 497
    CEFBS_None, // DADD8rc = 498
    CEFBS_None, // DADD8ri = 499
    CEFBS_None, // DADD8rm = 500
    CEFBS_None, // DADD8rn = 501
    CEFBS_None, // DADD8rp = 502
    CEFBS_None, // DADD8rr = 503
    CEFBS_None, // JCC = 504
    CEFBS_None, // JMP = 505
    CEFBS_None, // MOV16mc = 506
    CEFBS_None, // MOV16mi = 507
    CEFBS_None, // MOV16mm = 508
    CEFBS_None, // MOV16mn = 509
    CEFBS_None, // MOV16mr = 510
    CEFBS_None, // MOV16rc = 511
    CEFBS_None, // MOV16ri = 512
    CEFBS_None, // MOV16rm = 513
    CEFBS_None, // MOV16rn = 514
    CEFBS_None, // MOV16rp = 515
    CEFBS_None, // MOV16rr = 516
    CEFBS_None, // MOV8mc = 517
    CEFBS_None, // MOV8mi = 518
    CEFBS_None, // MOV8mm = 519
    CEFBS_None, // MOV8mn = 520
    CEFBS_None, // MOV8mr = 521
    CEFBS_None, // MOV8rc = 522
    CEFBS_None, // MOV8ri = 523
    CEFBS_None, // MOV8rm = 524
    CEFBS_None, // MOV8rn = 525
    CEFBS_None, // MOV8rp = 526
    CEFBS_None, // MOV8rr = 527
    CEFBS_None, // MOVZX16rm8 = 528
    CEFBS_None, // MOVZX16rr8 = 529
    CEFBS_None, // POP16r = 530
    CEFBS_None, // PUSH16c = 531
    CEFBS_None, // PUSH16i = 532
    CEFBS_None, // PUSH16r = 533
    CEFBS_None, // PUSH8r = 534
    CEFBS_None, // RET = 535
    CEFBS_None, // RETI = 536
    CEFBS_None, // RRA16m = 537
    CEFBS_None, // RRA16n = 538
    CEFBS_None, // RRA16p = 539
    CEFBS_None, // RRA16r = 540
    CEFBS_None, // RRA8m = 541
    CEFBS_None, // RRA8n = 542
    CEFBS_None, // RRA8p = 543
    CEFBS_None, // RRA8r = 544
    CEFBS_None, // RRC16m = 545
    CEFBS_None, // RRC16n = 546
    CEFBS_None, // RRC16p = 547
    CEFBS_None, // RRC16r = 548
    CEFBS_None, // RRC8m = 549
    CEFBS_None, // RRC8n = 550
    CEFBS_None, // RRC8p = 551
    CEFBS_None, // RRC8r = 552
    CEFBS_None, // Rrcl16 = 553
    CEFBS_None, // Rrcl8 = 554
    CEFBS_None, // SEXT16m = 555
    CEFBS_None, // SEXT16n = 556
    CEFBS_None, // SEXT16p = 557
    CEFBS_None, // SEXT16r = 558
    CEFBS_None, // SUB16mc = 559
    CEFBS_None, // SUB16mi = 560
    CEFBS_None, // SUB16mm = 561
    CEFBS_None, // SUB16mn = 562
    CEFBS_None, // SUB16mp = 563
    CEFBS_None, // SUB16mr = 564
    CEFBS_None, // SUB16rc = 565
    CEFBS_None, // SUB16ri = 566
    CEFBS_None, // SUB16rm = 567
    CEFBS_None, // SUB16rn = 568
    CEFBS_None, // SUB16rp = 569
    CEFBS_None, // SUB16rr = 570
    CEFBS_None, // SUB8mc = 571
    CEFBS_None, // SUB8mi = 572
    CEFBS_None, // SUB8mm = 573
    CEFBS_None, // SUB8mn = 574
    CEFBS_None, // SUB8mp = 575
    CEFBS_None, // SUB8mr = 576
    CEFBS_None, // SUB8rc = 577
    CEFBS_None, // SUB8ri = 578
    CEFBS_None, // SUB8rm = 579
    CEFBS_None, // SUB8rn = 580
    CEFBS_None, // SUB8rp = 581
    CEFBS_None, // SUB8rr = 582
    CEFBS_None, // SUBC16mc = 583
    CEFBS_None, // SUBC16mi = 584
    CEFBS_None, // SUBC16mm = 585
    CEFBS_None, // SUBC16mn = 586
    CEFBS_None, // SUBC16mp = 587
    CEFBS_None, // SUBC16mr = 588
    CEFBS_None, // SUBC16rc = 589
    CEFBS_None, // SUBC16ri = 590
    CEFBS_None, // SUBC16rm = 591
    CEFBS_None, // SUBC16rn = 592
    CEFBS_None, // SUBC16rp = 593
    CEFBS_None, // SUBC16rr = 594
    CEFBS_None, // SUBC8mc = 595
    CEFBS_None, // SUBC8mi = 596
    CEFBS_None, // SUBC8mm = 597
    CEFBS_None, // SUBC8mn = 598
    CEFBS_None, // SUBC8mp = 599
    CEFBS_None, // SUBC8mr = 600
    CEFBS_None, // SUBC8rc = 601
    CEFBS_None, // SUBC8ri = 602
    CEFBS_None, // SUBC8rm = 603
    CEFBS_None, // SUBC8rn = 604
    CEFBS_None, // SUBC8rp = 605
    CEFBS_None, // SUBC8rr = 606
    CEFBS_None, // SWPB16m = 607
    CEFBS_None, // SWPB16n = 608
    CEFBS_None, // SWPB16p = 609
    CEFBS_None, // SWPB16r = 610
    CEFBS_None, // Select16 = 611
    CEFBS_None, // Select8 = 612
    CEFBS_None, // Shl16 = 613
    CEFBS_None, // Shl8 = 614
    CEFBS_None, // Sra16 = 615
    CEFBS_None, // Sra8 = 616
    CEFBS_None, // Srl16 = 617
    CEFBS_None, // Srl8 = 618
    CEFBS_None, // XOR16mc = 619
    CEFBS_None, // XOR16mi = 620
    CEFBS_None, // XOR16mm = 621
    CEFBS_None, // XOR16mn = 622
    CEFBS_None, // XOR16mp = 623
    CEFBS_None, // XOR16mr = 624
    CEFBS_None, // XOR16rc = 625
    CEFBS_None, // XOR16ri = 626
    CEFBS_None, // XOR16rm = 627
    CEFBS_None, // XOR16rn = 628
    CEFBS_None, // XOR16rp = 629
    CEFBS_None, // XOR16rr = 630
    CEFBS_None, // XOR8mc = 631
    CEFBS_None, // XOR8mi = 632
    CEFBS_None, // XOR8mm = 633
    CEFBS_None, // XOR8mn = 634
    CEFBS_None, // XOR8mp = 635
    CEFBS_None, // XOR8mr = 636
    CEFBS_None, // XOR8rc = 637
    CEFBS_None, // XOR8ri = 638
    CEFBS_None, // XOR8rm = 639
    CEFBS_None, // XOR8rn = 640
    CEFBS_None, // XOR8rp = 641
    CEFBS_None, // XOR8rr = 642
    CEFBS_None, // ZEXT16r = 643
  };

  assert(Opcode < 644);
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
}

} // end namespace MSP430_MC
} // end namespace llvm
#endif // GET_COMPUTE_FEATURES

#ifdef GET_AVAILABLE_OPCODE_CHECKER
#undef GET_AVAILABLE_OPCODE_CHECKER
namespace llvm {
namespace MSP430_MC {
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  return !MissingFeatures.any();
}
} // end namespace MSP430_MC
} // end namespace llvm
#endif // GET_AVAILABLE_OPCODE_CHECKER

#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
#undef ENABLE_INSTR_PREDICATE_VERIFIER
#include <sstream>

namespace llvm {
namespace MSP430_MC {

#ifndef NDEBUG
static const char *SubtargetFeatureNames[] = {
  nullptr
};

#endif // NDEBUG

void verifyInstructionPredicates(
    unsigned Opcode, const FeatureBitset &Features) {
#ifndef NDEBUG
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  if (MissingFeatures.any()) {
    std::ostringstream Msg;
    Msg << "Attempting to emit " << &MSP430InstrNameData[MSP430InstrNameIndices[Opcode]]
        << " instruction but the ";
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
      if (MissingFeatures.test(i))
        Msg << SubtargetFeatureNames[i] << " ";
    Msg << "predicate(s) are not met";
    report_fatal_error(Msg.str().c_str());
  }
#endif // NDEBUG
}
} // end namespace MSP430_MC
} // end namespace llvm
#endif // ENABLE_INSTR_PREDICATE_VERIFIER