llvm/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp

//===-- RISCVPostRAExpandPseudoInsts.cpp - Expand pseudo instrs ----===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains a pass that expands the pseudo instruction pseudolisimm32
// into target instructions. This pass should be run during the post-regalloc
// passes, before post RA scheduling.
//
//===----------------------------------------------------------------------===//

#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCV.h"
#include "RISCVInstrInfo.h"
#include "RISCVTargetMachine.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"

usingnamespacellvm;

#define RISCV_POST_RA_EXPAND_PSEUDO_NAME …

namespace {

class RISCVPostRAExpandPseudo : public MachineFunctionPass { … };

char RISCVPostRAExpandPseudo::ID = …;

bool RISCVPostRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) { … }

bool RISCVPostRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) { … }

bool RISCVPostRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
                                       MachineBasicBlock::iterator MBBI,
                                       MachineBasicBlock::iterator &NextMBBI) { … }

bool RISCVPostRAExpandPseudo::expandMovImm(MachineBasicBlock &MBB,
                                           MachineBasicBlock::iterator MBBI) { … }

bool RISCVPostRAExpandPseudo::expandMovAddr(MachineBasicBlock &MBB,
                                            MachineBasicBlock::iterator MBBI) { … }

} // end of anonymous namespace

INITIALIZE_PASS(…)
namespace llvm {

FunctionPass *createRISCVPostRAExpandPseudoPass() { … }

} // end of namespace llvm