/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Global Instruction Selector for the RISCV target *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_GLOBALISEL_PREDICATE_BITSET const unsigned MAX_SUBTARGET_PREDICATES = …; PredicateBitset; #endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET #ifdef GET_GLOBALISEL_TEMPORARIES_DECL mutable MatcherState State; typedef ComplexRendererFns(RISCVInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; typedef void(RISCVInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const; const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo; static RISCVInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; static RISCVInstructionSelector::CustomRendererFn CustomRenderers[]; bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; const uint8_t *getMatchTable() const override; bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override; bool testSimplePredicate(unsigned PredicateID) const override; bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override; #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL #ifdef GET_GLOBALISEL_TEMPORARIES_INIT , State(1), ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT #ifdef GET_GLOBALISEL_IMPL // LLT Objects. enum { GILLT_p0s32, GILLT_p0s64, GILLT_s16, GILLT_s32, GILLT_s64, GILLT_nxv1s1, GILLT_nxv1s8, GILLT_nxv1s16, GILLT_nxv1s32, GILLT_nxv1s64, GILLT_nxv2s1, GILLT_nxv2s8, GILLT_nxv2s16, GILLT_nxv2s32, GILLT_nxv2s64, GILLT_nxv4s1, GILLT_nxv4s8, GILLT_nxv4s16, GILLT_nxv4s32, GILLT_nxv4s64, GILLT_nxv8s1, GILLT_nxv8s8, GILLT_nxv8s16, GILLT_nxv8s32, GILLT_nxv8s64, GILLT_nxv16s1, GILLT_nxv16s8, GILLT_nxv16s16, GILLT_nxv16s32, GILLT_nxv32s1, GILLT_nxv32s8, GILLT_nxv32s16, GILLT_nxv64s1, GILLT_nxv64s8, }; const static size_t NumTypeObjects = 34; const static LLT TypeObjects[] = { LLT::pointer(0, 32), LLT::pointer(0, 64), LLT::scalar(16), LLT::scalar(32), LLT::scalar(64), LLT::vector(ElementCount::getScalable(1), 1), LLT::vector(ElementCount::getScalable(1), 8), LLT::vector(ElementCount::getScalable(1), 16), LLT::vector(ElementCount::getScalable(1), 32), LLT::vector(ElementCount::getScalable(1), 64), LLT::vector(ElementCount::getScalable(2), 1), LLT::vector(ElementCount::getScalable(2), 8), LLT::vector(ElementCount::getScalable(2), 16), LLT::vector(ElementCount::getScalable(2), 32), LLT::vector(ElementCount::getScalable(2), 64), LLT::vector(ElementCount::getScalable(4), 1), LLT::vector(ElementCount::getScalable(4), 8), LLT::vector(ElementCount::getScalable(4), 16), LLT::vector(ElementCount::getScalable(4), 32), LLT::vector(ElementCount::getScalable(4), 64), LLT::vector(ElementCount::getScalable(8), 1), LLT::vector(ElementCount::getScalable(8), 8), LLT::vector(ElementCount::getScalable(8), 16), LLT::vector(ElementCount::getScalable(8), 32), LLT::vector(ElementCount::getScalable(8), 64), LLT::vector(ElementCount::getScalable(16), 1), LLT::vector(ElementCount::getScalable(16), 8), LLT::vector(ElementCount::getScalable(16), 16), LLT::vector(ElementCount::getScalable(16), 32), LLT::vector(ElementCount::getScalable(32), 1), LLT::vector(ElementCount::getScalable(32), 8), LLT::vector(ElementCount::getScalable(32), 16), LLT::vector(ElementCount::getScalable(64), 1), LLT::vector(ElementCount::getScalable(64), 8), }; // Bits for subtarget features that participate in instruction matching. enum SubtargetFeatureBits : uint8_t { Feature_HasStdExtZicbopBit = 65, Feature_HasStdExtZicondBit = 66, Feature_HasStdExtZimopBit = 64, Feature_HasStdExtZicfilpBit = 2, Feature_NoStdExtZicfilpBit = 1, Feature_HasStdExtZmmulBit = 21, Feature_HasStdExtMBit = 22, Feature_HasStdExtABit = 24, Feature_HasStdExtZtsoBit = 26, Feature_NotHasStdExtZtsoBit = 25, Feature_HasStdExtZabhaBit = 29, Feature_HasStdExtZacasBit = 28, Feature_NoStdExtZacasBit = 27, Feature_HasStdExtFBit = 5, Feature_HasStdExtDBit = 7, Feature_HasStdExtZfhminBit = 11, Feature_HasStdExtZfhBit = 9, Feature_HasStdExtZfbfminBit = 30, Feature_HasStdExtZfaBit = 31, Feature_HasStdExtZfinxBit = 6, Feature_HasStdExtZdinxBit = 8, Feature_HasStdExtZhinxminBit = 12, Feature_HasStdExtZhinxBit = 10, Feature_HasStdExtCBit = 17, Feature_HasStdExtCOrZcaBit = 19, Feature_HasStdExtZbaBit = 37, Feature_NotHasStdExtZbaBit = 20, Feature_HasStdExtZbbBit = 34, Feature_NoStdExtZbbBit = 36, Feature_HasStdExtZbcBit = 39, Feature_HasStdExtZbsBit = 33, Feature_HasStdExtZbkbBit = 35, Feature_HasStdExtZbkxBit = 40, Feature_HasStdExtZbbOrZbkbBit = 32, Feature_HasStdExtZbcOrZbkcBit = 38, Feature_HasStdExtZkndBit = 41, Feature_HasStdExtZkneBit = 43, Feature_HasStdExtZkndOrZkneBit = 42, Feature_HasStdExtZknhBit = 44, Feature_HasStdExtZksedBit = 45, Feature_HasStdExtZkshBit = 46, Feature_HasStdExtZvfbfwmaBit = 54, Feature_HasStdExtZvkbBit = 56, Feature_HasStdExtZvbbBit = 55, Feature_HasStdExtZvbcBit = 60, Feature_HasStdExtZvkgBit = 57, Feature_HasStdExtZvknedBit = 58, Feature_HasStdExtZvknhaBit = 61, Feature_HasStdExtZvknhbBit = 62, Feature_HasStdExtZvksedBit = 63, Feature_HasStdExtZvkshBit = 59, Feature_HasVInstructionsBit = 13, Feature_HasVInstructionsI64Bit = 49, Feature_HasVInstructionsAnyFBit = 48, Feature_HasVInstructionsF16MinimalBit = 51, Feature_HasVInstructionsBF16MinimalBit = 53, Feature_HasVInstructionsF16Bit = 47, Feature_HasVInstructionsF64Bit = 52, Feature_HasVInstructionsFullMultiplyBit = 50, Feature_HasVendorXVentanaCondOpsBit = 67, Feature_HasVendorXTHeadBaBit = 68, Feature_HasVendorXTHeadBbBit = 69, Feature_HasVendorXTHeadBsBit = 70, Feature_HasVendorXTHeadCondMovBit = 71, Feature_HasVendorXTHeadFMemIdxBit = 76, Feature_HasVendorXTHeadMacBit = 72, Feature_HasVendorXTHeadMemIdxBit = 75, Feature_HasVendorXTHeadMemPairBit = 74, Feature_HasVendorXTHeadVdotBit = 73, Feature_HasVendorXSfvcpBit = 77, Feature_HasVendorXSfvqmaccdodBit = 78, Feature_HasVendorXSfvqmaccqoqBit = 79, Feature_HasVendorXSfvfwmaccqqqBit = 80, Feature_HasVendorXSfvfnrclipxfqfBit = 81, Feature_HasVendorXCVbitmanipBit = 83, Feature_HasVendorXCVmacBit = 86, Feature_HasVendorXCVmemBit = 82, Feature_HasVendorXCValuBit = 84, Feature_HasVendorXCVbiBit = 85, Feature_IsRV64Bit = 4, Feature_IsRV32Bit = 3, Feature_HasShortForwardBranchOptBit = 14, Feature_NoShortForwardBranchOptBit = 16, Feature_HasConditionalMoveFusionBit = 15, Feature_NoConditionalMoveFusionBit = 0, Feature_HasAtomicLdStBit = 23, Feature_OptForMinSizeBit = 18, Feature_HwMode1Bit = 88, Feature_HwMode0Bit = 87, }; PredicateBitset RISCVInstructionSelector:: computeAvailableModuleFeatures(const RISCVSubtarget *Subtarget) const { PredicateBitset Features{}; if (Subtarget->hasStdExtZicbop()) Features.set(Feature_HasStdExtZicbopBit); if (Subtarget->hasStdExtZicond()) Features.set(Feature_HasStdExtZicondBit); if (Subtarget->hasStdExtZimop()) Features.set(Feature_HasStdExtZimopBit); if (Subtarget->hasStdExtZicfilp()) Features.set(Feature_HasStdExtZicfilpBit); if (!Subtarget->hasStdExtZicfilp()) Features.set(Feature_NoStdExtZicfilpBit); if (Subtarget->hasStdExtZmmul()) Features.set(Feature_HasStdExtZmmulBit); if (Subtarget->hasStdExtM()) Features.set(Feature_HasStdExtMBit); if (Subtarget->hasStdExtA()) Features.set(Feature_HasStdExtABit); if (Subtarget->hasStdExtZtso()) Features.set(Feature_HasStdExtZtsoBit); if (!Subtarget->hasStdExtZtso()) Features.set(Feature_NotHasStdExtZtsoBit); if (Subtarget->hasStdExtZabha()) Features.set(Feature_HasStdExtZabhaBit); if (Subtarget->hasStdExtZacas()) Features.set(Feature_HasStdExtZacasBit); if (!Subtarget->hasStdExtZacas()) Features.set(Feature_NoStdExtZacasBit); if (Subtarget->hasStdExtF()) Features.set(Feature_HasStdExtFBit); if (Subtarget->hasStdExtD()) Features.set(Feature_HasStdExtDBit); if (Subtarget->hasStdExtZfhmin()) Features.set(Feature_HasStdExtZfhminBit); if (Subtarget->hasStdExtZfh()) Features.set(Feature_HasStdExtZfhBit); if (Subtarget->hasStdExtZfbfmin()) Features.set(Feature_HasStdExtZfbfminBit); if (Subtarget->hasStdExtZfa()) Features.set(Feature_HasStdExtZfaBit); if (Subtarget->hasStdExtZfinx()) Features.set(Feature_HasStdExtZfinxBit); if (Subtarget->hasStdExtZdinx()) Features.set(Feature_HasStdExtZdinxBit); if (Subtarget->hasStdExtZhinxmin()) Features.set(Feature_HasStdExtZhinxminBit); if (Subtarget->hasStdExtZhinx()) Features.set(Feature_HasStdExtZhinxBit); if (Subtarget->hasStdExtC()) Features.set(Feature_HasStdExtCBit); if (Subtarget->hasStdExtCOrZca()) Features.set(Feature_HasStdExtCOrZcaBit); if (Subtarget->hasStdExtZba()) Features.set(Feature_HasStdExtZbaBit); if (!Subtarget->hasStdExtZba()) Features.set(Feature_NotHasStdExtZbaBit); if (Subtarget->hasStdExtZbb()) Features.set(Feature_HasStdExtZbbBit); if (!Subtarget->hasStdExtZbb()) Features.set(Feature_NoStdExtZbbBit); if (Subtarget->hasStdExtZbc()) Features.set(Feature_HasStdExtZbcBit); if (Subtarget->hasStdExtZbs()) Features.set(Feature_HasStdExtZbsBit); if (Subtarget->hasStdExtZbkb()) Features.set(Feature_HasStdExtZbkbBit); if (Subtarget->hasStdExtZbkx()) Features.set(Feature_HasStdExtZbkxBit); if (Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()) Features.set(Feature_HasStdExtZbbOrZbkbBit); if (Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()) Features.set(Feature_HasStdExtZbcOrZbkcBit); if (Subtarget->hasStdExtZknd()) Features.set(Feature_HasStdExtZkndBit); if (Subtarget->hasStdExtZkne()) Features.set(Feature_HasStdExtZkneBit); if (Subtarget->hasStdExtZknd() || Subtarget->hasStdExtZkne()) Features.set(Feature_HasStdExtZkndOrZkneBit); if (Subtarget->hasStdExtZknh()) Features.set(Feature_HasStdExtZknhBit); if (Subtarget->hasStdExtZksed()) Features.set(Feature_HasStdExtZksedBit); if (Subtarget->hasStdExtZksh()) Features.set(Feature_HasStdExtZkshBit); if (Subtarget->hasStdExtZvfbfwma()) Features.set(Feature_HasStdExtZvfbfwmaBit); if (Subtarget->hasStdExtZvkb()) Features.set(Feature_HasStdExtZvkbBit); if (Subtarget->hasStdExtZvbb()) Features.set(Feature_HasStdExtZvbbBit); if (Subtarget->hasStdExtZvbc()) Features.set(Feature_HasStdExtZvbcBit); if (Subtarget->hasStdExtZvkg()) Features.set(Feature_HasStdExtZvkgBit); if (Subtarget->hasStdExtZvkned()) Features.set(Feature_HasStdExtZvknedBit); if (Subtarget->hasStdExtZvknha()) Features.set(Feature_HasStdExtZvknhaBit); if (Subtarget->hasStdExtZvknhb()) Features.set(Feature_HasStdExtZvknhbBit); if (Subtarget->hasStdExtZvksed()) Features.set(Feature_HasStdExtZvksedBit); if (Subtarget->hasStdExtZvksh()) Features.set(Feature_HasStdExtZvkshBit); if (Subtarget->hasVInstructions()) Features.set(Feature_HasVInstructionsBit); if (Subtarget->hasVInstructionsI64()) Features.set(Feature_HasVInstructionsI64Bit); if (Subtarget->hasVInstructionsAnyF()) Features.set(Feature_HasVInstructionsAnyFBit); if (Subtarget->hasVInstructionsF16Minimal()) Features.set(Feature_HasVInstructionsF16MinimalBit); if (Subtarget->hasVInstructionsBF16Minimal()) Features.set(Feature_HasVInstructionsBF16MinimalBit); if (Subtarget->hasVInstructionsF16()) Features.set(Feature_HasVInstructionsF16Bit); if (Subtarget->hasVInstructionsF64()) Features.set(Feature_HasVInstructionsF64Bit); if (Subtarget->hasVInstructionsFullMultiply()) Features.set(Feature_HasVInstructionsFullMultiplyBit); if (Subtarget->hasVendorXVentanaCondOps()) Features.set(Feature_HasVendorXVentanaCondOpsBit); if (Subtarget->hasVendorXTHeadBa()) Features.set(Feature_HasVendorXTHeadBaBit); if (Subtarget->hasVendorXTHeadBb()) Features.set(Feature_HasVendorXTHeadBbBit); if (Subtarget->hasVendorXTHeadBs()) Features.set(Feature_HasVendorXTHeadBsBit); if (Subtarget->hasVendorXTHeadCondMov()) Features.set(Feature_HasVendorXTHeadCondMovBit); if (Subtarget->hasVendorXTHeadFMemIdx()) Features.set(Feature_HasVendorXTHeadFMemIdxBit); if (Subtarget->hasVendorXTHeadMac()) Features.set(Feature_HasVendorXTHeadMacBit); if (Subtarget->hasVendorXTHeadMemIdx()) Features.set(Feature_HasVendorXTHeadMemIdxBit); if (Subtarget->hasVendorXTHeadMemPair()) Features.set(Feature_HasVendorXTHeadMemPairBit); if (Subtarget->hasVendorXTHeadVdot()) Features.set(Feature_HasVendorXTHeadVdotBit); if (Subtarget->hasVendorXSfvcp()) Features.set(Feature_HasVendorXSfvcpBit); if (Subtarget->hasVendorXSfvqmaccdod()) Features.set(Feature_HasVendorXSfvqmaccdodBit); if (Subtarget->hasVendorXSfvqmaccqoq()) Features.set(Feature_HasVendorXSfvqmaccqoqBit); if (Subtarget->hasVendorXSfvfwmaccqqq()) Features.set(Feature_HasVendorXSfvfwmaccqqqBit); if (Subtarget->hasVendorXSfvfnrclipxfqf()) Features.set(Feature_HasVendorXSfvfnrclipxfqfBit); if (Subtarget->hasVendorXCVbitmanip()) Features.set(Feature_HasVendorXCVbitmanipBit); if (Subtarget->hasVendorXCVmac()) Features.set(Feature_HasVendorXCVmacBit); if (Subtarget->hasVendorXCVmem()) Features.set(Feature_HasVendorXCVmemBit); if (Subtarget->hasVendorXCValu()) Features.set(Feature_HasVendorXCValuBit); if (Subtarget->hasVendorXCVbi()) Features.set(Feature_HasVendorXCVbiBit); if (Subtarget->is64Bit()) Features.set(Feature_IsRV64Bit); if (!Subtarget->is64Bit()) Features.set(Feature_IsRV32Bit); if (Subtarget->hasShortForwardBranchOpt()) Features.set(Feature_HasShortForwardBranchOptBit); if (!Subtarget->hasShortForwardBranchOpt()) Features.set(Feature_NoShortForwardBranchOptBit); if (Subtarget->hasConditionalMoveFusion()) Features.set(Feature_HasConditionalMoveFusionBit); if (!Subtarget->hasConditionalMoveFusion()) Features.set(Feature_NoConditionalMoveFusionBit); if (Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()) Features.set(Feature_HasAtomicLdStBit); if (MF ? MF->getFunction().hasMinSize() : false) Features.set(Feature_OptForMinSizeBit); if (!((Subtarget->is64Bit()))) Features.set(Feature_HwMode1Bit); if ((Subtarget->is64Bit())) Features.set(Feature_HwMode0Bit); return Features; } void RISCVInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) { AvailableFunctionFeatures = computeAvailableFunctionFeatures((const RISCVSubtarget *)&MF.getSubtarget(), &MF); } PredicateBitset RISCVInstructionSelector:: computeAvailableFunctionFeatures(const RISCVSubtarget *Subtarget, const MachineFunction *MF) const { PredicateBitset Features{}; return Features; } // Feature bitsets. enum { GIFBS_Invalid, GIFBS_HwMode0, GIFBS_HwMode1, GIFBS_HasAtomicLdSt_HwMode0, GIFBS_HasAtomicLdSt_HwMode1, GIFBS_HasShortForwardBranchOpt_HwMode0, GIFBS_HasShortForwardBranchOpt_HwMode1, GIFBS_HasStdExtA_HwMode1, GIFBS_HasStdExtD, GIFBS_HasStdExtD_HwMode0, GIFBS_HasStdExtD_HwMode1, GIFBS_HasStdExtF, GIFBS_HasStdExtF_HwMode0, GIFBS_HasStdExtF_HwMode1, GIFBS_HasStdExtM_HwMode0, GIFBS_HasStdExtM_HwMode1, GIFBS_HasStdExtZba_HwMode0, GIFBS_HasStdExtZba_HwMode1, GIFBS_HasStdExtZbb_HwMode0, GIFBS_HasStdExtZbb_HwMode1, GIFBS_HasStdExtZbbOrZbkb_HwMode0, GIFBS_HasStdExtZbbOrZbkb_HwMode1, GIFBS_HasStdExtZbkx_HwMode0, GIFBS_HasStdExtZbkx_HwMode1, GIFBS_HasStdExtZbs_HwMode0, GIFBS_HasStdExtZbs_HwMode1, GIFBS_HasStdExtZfa, GIFBS_HasStdExtZfa_HwMode0, GIFBS_HasStdExtZfa_HwMode1, GIFBS_HasStdExtZfbfmin_HwMode0, GIFBS_HasStdExtZfbfmin_HwMode1, GIFBS_HasStdExtZfh, GIFBS_HasStdExtZfh_HwMode0, GIFBS_HasStdExtZfh_HwMode1, GIFBS_HasStdExtZfhmin_HwMode0, GIFBS_HasStdExtZfhmin_HwMode1, GIFBS_HasStdExtZfinx, GIFBS_HasStdExtZfinx_HwMode0, GIFBS_HasStdExtZfinx_HwMode1, GIFBS_HasStdExtZhinx, GIFBS_HasStdExtZhinx_HwMode0, GIFBS_HasStdExtZhinx_HwMode1, GIFBS_HasStdExtZhinxmin_HwMode0, GIFBS_HasStdExtZhinxmin_HwMode1, GIFBS_HasStdExtZmmul_HwMode0, GIFBS_HasStdExtZmmul_HwMode1, GIFBS_HasVInstructions_HwMode0, GIFBS_HasVInstructions_HwMode1, GIFBS_HasVInstructionsAnyF_HwMode0, GIFBS_HasVInstructionsAnyF_HwMode1, GIFBS_HasVInstructionsBF16Minimal_HwMode0, GIFBS_HasVInstructionsBF16Minimal_HwMode1, GIFBS_HasVInstructionsF16_HwMode0, GIFBS_HasVInstructionsF16_HwMode1, GIFBS_HasVInstructionsF16Minimal_HwMode0, GIFBS_HasVInstructionsF16Minimal_HwMode1, GIFBS_HasVInstructionsF64_HwMode0, GIFBS_HasVInstructionsF64_HwMode1, GIFBS_HasVInstructionsFullMultiply_HwMode0, GIFBS_HasVInstructionsFullMultiply_HwMode1, GIFBS_HasVInstructionsI64_HwMode0, GIFBS_HasVInstructionsI64_HwMode1, GIFBS_HasVendorXCVmac_HwMode0, GIFBS_HasVendorXCVmac_HwMode1, GIFBS_HasVendorXTHeadBa_HwMode0, GIFBS_HasVendorXTHeadBa_HwMode1, GIFBS_HasVendorXTHeadBb_HwMode0, GIFBS_HasVendorXTHeadBb_HwMode1, GIFBS_HasVendorXTHeadBs_HwMode0, GIFBS_HasVendorXTHeadBs_HwMode1, GIFBS_HasVendorXTHeadCondMov_HwMode0, GIFBS_HasVendorXTHeadCondMov_HwMode1, GIFBS_HasVendorXTHeadMac_HwMode0, GIFBS_HasVendorXTHeadMac_HwMode1, GIFBS_IsRV32_HwMode0, GIFBS_IsRV32_HwMode1, GIFBS_IsRV64_HwMode0, GIFBS_IsRV64_HwMode1, GIFBS_HasAtomicLdSt_IsRV64_HwMode0, GIFBS_HasStdExtA_HasStdExtZtso_HwMode0, GIFBS_HasStdExtA_HasStdExtZtso_HwMode1, GIFBS_HasStdExtA_IsRV64_HwMode1, GIFBS_HasStdExtA_NoStdExtZacas_HwMode1, GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode0, GIFBS_HasStdExtA_NotHasStdExtZtso_HwMode1, GIFBS_HasStdExtD_HasStdExtZfa, GIFBS_HasStdExtD_HasStdExtZfa_HwMode0, GIFBS_HasStdExtD_HasStdExtZfa_HwMode1, GIFBS_HasStdExtD_HasStdExtZfbfmin_HwMode0, GIFBS_HasStdExtD_HasStdExtZfbfmin_HwMode1, GIFBS_HasStdExtD_HasStdExtZfhmin_HwMode0, GIFBS_HasStdExtD_HasStdExtZfhmin_HwMode1, GIFBS_HasStdExtD_IsRV64_HwMode0, GIFBS_HasStdExtF_IsRV64_HwMode0, GIFBS_HasStdExtM_IsRV64_HwMode0, GIFBS_HasStdExtM_IsRV64_HwMode1, GIFBS_HasStdExtZacas_HasStdExtZtso_HwMode0, GIFBS_HasStdExtZacas_HasStdExtZtso_HwMode1, GIFBS_HasStdExtZacas_NotHasStdExtZtso_HwMode0, GIFBS_HasStdExtZacas_NotHasStdExtZtso_HwMode1, GIFBS_HasStdExtZba_IsRV64_HwMode0, GIFBS_HasStdExtZba_IsRV64_HwMode1, GIFBS_HasStdExtZbb_IsRV32_HwMode0, GIFBS_HasStdExtZbb_IsRV32_HwMode1, GIFBS_HasStdExtZbb_IsRV64_HwMode0, GIFBS_HasStdExtZbb_IsRV64_HwMode1, GIFBS_HasStdExtZbbOrZbkb_IsRV32_HwMode0, GIFBS_HasStdExtZbbOrZbkb_IsRV32_HwMode1, GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode0, GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode1, GIFBS_HasStdExtZbs_IsRV64_HwMode0, GIFBS_HasStdExtZbs_IsRV64_HwMode1, GIFBS_HasStdExtZdinx_IsRV32, GIFBS_HasStdExtZdinx_IsRV32_HwMode0, GIFBS_HasStdExtZdinx_IsRV32_HwMode1, GIFBS_HasStdExtZdinx_IsRV64_HwMode0, GIFBS_HasStdExtZfa_HasStdExtZfh, GIFBS_HasStdExtZfa_HasStdExtZfh_HwMode0, GIFBS_HasStdExtZfa_HasStdExtZfh_HwMode1, GIFBS_HasStdExtZfh_IsRV64_HwMode0, GIFBS_HasStdExtZfinx_IsRV64_HwMode0, GIFBS_HasStdExtZhinx_IsRV64_HwMode0, GIFBS_HasStdExtZknd_IsRV32_HwMode1, GIFBS_HasStdExtZknd_IsRV64_HwMode0, GIFBS_HasStdExtZkndOrZkne_IsRV64_HwMode0, GIFBS_HasStdExtZkne_IsRV32_HwMode1, GIFBS_HasStdExtZkne_IsRV64_HwMode0, GIFBS_HasStdExtZknh_IsRV32_HwMode1, GIFBS_HasStdExtZknh_IsRV64_HwMode0, GIFBS_HasStdExtZmmul_IsRV64_HwMode0, GIFBS_HasStdExtZmmul_IsRV64_HwMode1, GIFBS_HasStdExtZvbb_HasVInstructions_HwMode0, GIFBS_HasStdExtZvbb_HasVInstructions_HwMode1, GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode0, GIFBS_HasStdExtZvbb_HasVInstructionsI64_HwMode1, GIFBS_HasStdExtZvkb_HasVInstructions_HwMode0, GIFBS_HasStdExtZvkb_HasVInstructions_HwMode1, GIFBS_HasStdExtZvkb_HasVInstructionsI64_HwMode0, GIFBS_HasStdExtZvkb_HasVInstructionsI64_HwMode1, GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode0, GIFBS_HasVInstructions_HasVInstructionsAnyF_HwMode1, GIFBS_HasVInstructions_HasVInstructionsF16_HwMode0, GIFBS_HasVInstructions_HasVInstructionsF16_HwMode1, GIFBS_HasVInstructions_HasVInstructionsF64_HwMode0, GIFBS_HasVInstructions_HasVInstructionsF64_HwMode1, GIFBS_HasVInstructions_HasVInstructionsI64_HwMode0, GIFBS_HasVInstructions_HasVInstructionsI64_HwMode1, GIFBS_HasVInstructionsAnyF_HasVInstructionsF64_HwMode0, GIFBS_HasVInstructionsAnyF_HasVInstructionsF64_HwMode1, GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode0, GIFBS_HasVInstructionsAnyF_HasVInstructionsI64_HwMode1, GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode0, GIFBS_HasVInstructionsF64_HasVInstructionsI64_HwMode1, GIFBS_HasVendorXCValu_IsRV32_HwMode0, GIFBS_HasVendorXCValu_IsRV32_HwMode1, GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode0, GIFBS_HasVendorXCVbitmanip_IsRV32_HwMode1, GIFBS_HasVendorXTHeadBb_IsRV64_HwMode0, GIFBS_HasVendorXTHeadCondMov_IsRV64_HwMode0, GIFBS_HasVendorXTHeadCondMov_IsRV64_HwMode1, GIFBS_HasVendorXTHeadMac_IsRV64_HwMode0, GIFBS_HasVendorXTHeadMac_IsRV64_HwMode1, GIFBS_IsRV64_NotHasStdExtZba_HwMode0, GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode0, GIFBS_HasStdExtA_HasStdExtZabha_HasStdExtZtso_HwMode1, GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode0, GIFBS_HasStdExtA_HasStdExtZabha_NotHasStdExtZtso_HwMode1, GIFBS_HasStdExtA_HasStdExtZtso_IsRV64_HwMode0, GIFBS_HasStdExtA_IsRV64_NotHasStdExtZtso_HwMode0, GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode0, GIFBS_HasStdExtZabha_HasStdExtZacas_HasStdExtZtso_HwMode1, GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode0, GIFBS_HasStdExtZabha_HasStdExtZacas_NotHasStdExtZtso_HwMode1, GIFBS_HasStdExtZacas_HasStdExtZtso_IsRV64_HwMode0, GIFBS_HasStdExtZacas_IsRV64_NotHasStdExtZtso_HwMode0, GIFBS_HasStdExtZbkb_IsRV32_NoStdExtZbb_HwMode0, GIFBS_HasStdExtZbkb_IsRV32_NoStdExtZbb_HwMode1, GIFBS_HasStdExtZbkb_IsRV64_NoStdExtZbb_HwMode0, GIFBS_HasStdExtZbkb_IsRV64_NoStdExtZbb_HwMode1, GIFBS_HasStdExtZdinx_HasStdExtZhinxmin_IsRV32_HwMode0, GIFBS_HasStdExtZdinx_HasStdExtZhinxmin_IsRV32_HwMode1, GIFBS_HasStdExtZdinx_HasStdExtZhinxmin_IsRV64_HwMode0, GIFBS_HasStdExtZmmul_IsRV64_NotHasStdExtZba_HwMode0, }; constexpr static PredicateBitset FeatureBitsets[] { {}, // GIFBS_Invalid {Feature_HwMode0Bit, }, {Feature_HwMode1Bit, }, {Feature_HasAtomicLdStBit, Feature_HwMode0Bit, }, {Feature_HasAtomicLdStBit, Feature_HwMode1Bit, }, {Feature_HasShortForwardBranchOptBit, Feature_HwMode0Bit, }, {Feature_HasShortForwardBranchOptBit, Feature_HwMode1Bit, }, {Feature_HasStdExtABit, Feature_HwMode1Bit, }, {Feature_HasStdExtDBit, }, {Feature_HasStdExtDBit, Feature_HwMode0Bit, }, {Feature_HasStdExtDBit, Feature_HwMode1Bit, }, {Feature_HasStdExtFBit, }, {Feature_HasStdExtFBit, Feature_HwMode0Bit, }, {Feature_HasStdExtFBit, Feature_HwMode1Bit, }, {Feature_HasStdExtMBit, Feature_HwMode0Bit, }, {Feature_HasStdExtMBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZbaBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZbaBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZbbBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZbbBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZbbOrZbkbBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZbbOrZbkbBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZbkxBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZbkxBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZbsBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZbsBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZfaBit, }, {Feature_HasStdExtZfaBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZfaBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZfbfminBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZfbfminBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZfhBit, }, {Feature_HasStdExtZfhBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZfhBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZfhminBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZfhminBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZfinxBit, }, {Feature_HasStdExtZfinxBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZfinxBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZhinxBit, }, {Feature_HasStdExtZhinxBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZhinxBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZhinxminBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZhinxminBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZmmulBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZmmulBit, Feature_HwMode1Bit, }, {Feature_HasVInstructionsBit, Feature_HwMode0Bit, }, {Feature_HasVInstructionsBit, Feature_HwMode1Bit, }, {Feature_HasVInstructionsAnyFBit, Feature_HwMode0Bit, }, {Feature_HasVInstructionsAnyFBit, Feature_HwMode1Bit, }, {Feature_HasVInstructionsBF16MinimalBit, Feature_HwMode0Bit, }, {Feature_HasVInstructionsBF16MinimalBit, Feature_HwMode1Bit, }, {Feature_HasVInstructionsF16Bit, Feature_HwMode0Bit, }, {Feature_HasVInstructionsF16Bit, Feature_HwMode1Bit, }, {Feature_HasVInstructionsF16MinimalBit, Feature_HwMode0Bit, }, {Feature_HasVInstructionsF16MinimalBit, Feature_HwMode1Bit, }, {Feature_HasVInstructionsF64Bit, Feature_HwMode0Bit, }, {Feature_HasVInstructionsF64Bit, Feature_HwMode1Bit, }, {Feature_HasVInstructionsFullMultiplyBit, Feature_HwMode0Bit, }, {Feature_HasVInstructionsFullMultiplyBit, Feature_HwMode1Bit, }, {Feature_HasVInstructionsI64Bit, Feature_HwMode0Bit, }, {Feature_HasVInstructionsI64Bit, Feature_HwMode1Bit, }, {Feature_HasVendorXCVmacBit, Feature_HwMode0Bit, }, {Feature_HasVendorXCVmacBit, Feature_HwMode1Bit, }, {Feature_HasVendorXTHeadBaBit, Feature_HwMode0Bit, }, {Feature_HasVendorXTHeadBaBit, Feature_HwMode1Bit, }, {Feature_HasVendorXTHeadBbBit, Feature_HwMode0Bit, }, {Feature_HasVendorXTHeadBbBit, Feature_HwMode1Bit, }, {Feature_HasVendorXTHeadBsBit, Feature_HwMode0Bit, }, {Feature_HasVendorXTHeadBsBit, Feature_HwMode1Bit, }, {Feature_HasVendorXTHeadCondMovBit, Feature_HwMode0Bit, }, {Feature_HasVendorXTHeadCondMovBit, Feature_HwMode1Bit, }, {Feature_HasVendorXTHeadMacBit, Feature_HwMode0Bit, }, {Feature_HasVendorXTHeadMacBit, Feature_HwMode1Bit, }, {Feature_IsRV32Bit, Feature_HwMode0Bit, }, {Feature_IsRV32Bit, Feature_HwMode1Bit, }, {Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_IsRV64Bit, Feature_HwMode1Bit, }, {Feature_HasAtomicLdStBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtABit, Feature_HasStdExtZtsoBit, Feature_HwMode0Bit, }, {Feature_HasStdExtABit, Feature_HasStdExtZtsoBit, Feature_HwMode1Bit, }, {Feature_HasStdExtABit, Feature_IsRV64Bit, Feature_HwMode1Bit, }, {Feature_HasStdExtABit, Feature_NoStdExtZacasBit, Feature_HwMode1Bit, }, {Feature_HasStdExtABit, Feature_NotHasStdExtZtsoBit, Feature_HwMode0Bit, }, {Feature_HasStdExtABit, Feature_NotHasStdExtZtsoBit, Feature_HwMode1Bit, }, {Feature_HasStdExtDBit, Feature_HasStdExtZfaBit, }, {Feature_HasStdExtDBit, Feature_HasStdExtZfaBit, Feature_HwMode0Bit, }, {Feature_HasStdExtDBit, Feature_HasStdExtZfaBit, Feature_HwMode1Bit, }, {Feature_HasStdExtDBit, Feature_HasStdExtZfbfminBit, Feature_HwMode0Bit, }, {Feature_HasStdExtDBit, Feature_HasStdExtZfbfminBit, Feature_HwMode1Bit, }, {Feature_HasStdExtDBit, Feature_HasStdExtZfhminBit, Feature_HwMode0Bit, }, {Feature_HasStdExtDBit, Feature_HasStdExtZfhminBit, Feature_HwMode1Bit, }, {Feature_HasStdExtDBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtFBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtMBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtMBit, Feature_IsRV64Bit, Feature_HwMode1Bit, }, {Feature_HasStdExtZacasBit, Feature_HasStdExtZtsoBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZacasBit, Feature_HasStdExtZtsoBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZacasBit, Feature_NotHasStdExtZtsoBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZacasBit, Feature_NotHasStdExtZtsoBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZbaBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtZbaBit, Feature_IsRV64Bit, Feature_HwMode1Bit, }, {Feature_HasStdExtZbbBit, Feature_IsRV32Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtZbbBit, Feature_IsRV32Bit, Feature_HwMode1Bit, }, {Feature_HasStdExtZbbBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtZbbBit, Feature_IsRV64Bit, Feature_HwMode1Bit, }, {Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV32Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV32Bit, Feature_HwMode1Bit, }, {Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV64Bit, Feature_HwMode1Bit, }, {Feature_HasStdExtZbsBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtZbsBit, Feature_IsRV64Bit, Feature_HwMode1Bit, }, {Feature_HasStdExtZdinxBit, Feature_IsRV32Bit, }, {Feature_HasStdExtZdinxBit, Feature_IsRV32Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtZdinxBit, Feature_IsRV32Bit, Feature_HwMode1Bit, }, {Feature_HasStdExtZdinxBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtZfaBit, Feature_HasStdExtZfhBit, }, {Feature_HasStdExtZfaBit, Feature_HasStdExtZfhBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZfaBit, Feature_HasStdExtZfhBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZfhBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtZfinxBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtZhinxBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtZkndBit, Feature_IsRV32Bit, Feature_HwMode1Bit, }, {Feature_HasStdExtZkndBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtZkndOrZkneBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtZkneBit, Feature_IsRV32Bit, Feature_HwMode1Bit, }, {Feature_HasStdExtZkneBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtZknhBit, Feature_IsRV32Bit, Feature_HwMode1Bit, }, {Feature_HasStdExtZknhBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtZmmulBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtZmmulBit, Feature_IsRV64Bit, Feature_HwMode1Bit, }, {Feature_HasStdExtZvbbBit, Feature_HasVInstructionsBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZvbbBit, Feature_HasVInstructionsBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZvbbBit, Feature_HasVInstructionsI64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtZvbbBit, Feature_HasVInstructionsI64Bit, Feature_HwMode1Bit, }, {Feature_HasStdExtZvkbBit, Feature_HasVInstructionsBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZvkbBit, Feature_HasVInstructionsBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZvkbBit, Feature_HasVInstructionsI64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtZvkbBit, Feature_HasVInstructionsI64Bit, Feature_HwMode1Bit, }, {Feature_HasVInstructionsBit, Feature_HasVInstructionsAnyFBit, Feature_HwMode0Bit, }, {Feature_HasVInstructionsBit, Feature_HasVInstructionsAnyFBit, Feature_HwMode1Bit, }, {Feature_HasVInstructionsBit, Feature_HasVInstructionsF16Bit, Feature_HwMode0Bit, }, {Feature_HasVInstructionsBit, Feature_HasVInstructionsF16Bit, Feature_HwMode1Bit, }, {Feature_HasVInstructionsBit, Feature_HasVInstructionsF64Bit, Feature_HwMode0Bit, }, {Feature_HasVInstructionsBit, Feature_HasVInstructionsF64Bit, Feature_HwMode1Bit, }, {Feature_HasVInstructionsBit, Feature_HasVInstructionsI64Bit, Feature_HwMode0Bit, }, {Feature_HasVInstructionsBit, Feature_HasVInstructionsI64Bit, Feature_HwMode1Bit, }, {Feature_HasVInstructionsAnyFBit, Feature_HasVInstructionsF64Bit, Feature_HwMode0Bit, }, {Feature_HasVInstructionsAnyFBit, Feature_HasVInstructionsF64Bit, Feature_HwMode1Bit, }, {Feature_HasVInstructionsAnyFBit, Feature_HasVInstructionsI64Bit, Feature_HwMode0Bit, }, {Feature_HasVInstructionsAnyFBit, Feature_HasVInstructionsI64Bit, Feature_HwMode1Bit, }, {Feature_HasVInstructionsF64Bit, Feature_HasVInstructionsI64Bit, Feature_HwMode0Bit, }, {Feature_HasVInstructionsF64Bit, Feature_HasVInstructionsI64Bit, Feature_HwMode1Bit, }, {Feature_HasVendorXCValuBit, Feature_IsRV32Bit, Feature_HwMode0Bit, }, {Feature_HasVendorXCValuBit, Feature_IsRV32Bit, Feature_HwMode1Bit, }, {Feature_HasVendorXCVbitmanipBit, Feature_IsRV32Bit, Feature_HwMode0Bit, }, {Feature_HasVendorXCVbitmanipBit, Feature_IsRV32Bit, Feature_HwMode1Bit, }, {Feature_HasVendorXTHeadBbBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasVendorXTHeadCondMovBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasVendorXTHeadCondMovBit, Feature_IsRV64Bit, Feature_HwMode1Bit, }, {Feature_HasVendorXTHeadMacBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasVendorXTHeadMacBit, Feature_IsRV64Bit, Feature_HwMode1Bit, }, {Feature_IsRV64Bit, Feature_NotHasStdExtZbaBit, Feature_HwMode0Bit, }, {Feature_HasStdExtABit, Feature_HasStdExtZabhaBit, Feature_HasStdExtZtsoBit, Feature_HwMode0Bit, }, {Feature_HasStdExtABit, Feature_HasStdExtZabhaBit, Feature_HasStdExtZtsoBit, Feature_HwMode1Bit, }, {Feature_HasStdExtABit, Feature_HasStdExtZabhaBit, Feature_NotHasStdExtZtsoBit, Feature_HwMode0Bit, }, {Feature_HasStdExtABit, Feature_HasStdExtZabhaBit, Feature_NotHasStdExtZtsoBit, Feature_HwMode1Bit, }, {Feature_HasStdExtABit, Feature_HasStdExtZtsoBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtABit, Feature_IsRV64Bit, Feature_NotHasStdExtZtsoBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZabhaBit, Feature_HasStdExtZacasBit, Feature_HasStdExtZtsoBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZabhaBit, Feature_HasStdExtZacasBit, Feature_HasStdExtZtsoBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZabhaBit, Feature_HasStdExtZacasBit, Feature_NotHasStdExtZtsoBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZabhaBit, Feature_HasStdExtZacasBit, Feature_NotHasStdExtZtsoBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZacasBit, Feature_HasStdExtZtsoBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtZacasBit, Feature_IsRV64Bit, Feature_NotHasStdExtZtsoBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZbkbBit, Feature_IsRV32Bit, Feature_NoStdExtZbbBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZbkbBit, Feature_IsRV32Bit, Feature_NoStdExtZbbBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZbkbBit, Feature_IsRV64Bit, Feature_NoStdExtZbbBit, Feature_HwMode0Bit, }, {Feature_HasStdExtZbkbBit, Feature_IsRV64Bit, Feature_NoStdExtZbbBit, Feature_HwMode1Bit, }, {Feature_HasStdExtZdinxBit, Feature_HasStdExtZhinxminBit, Feature_IsRV32Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtZdinxBit, Feature_HasStdExtZhinxminBit, Feature_IsRV32Bit, Feature_HwMode1Bit, }, {Feature_HasStdExtZdinxBit, Feature_HasStdExtZhinxminBit, Feature_IsRV64Bit, Feature_HwMode0Bit, }, {Feature_HasStdExtZmmulBit, Feature_IsRV64Bit, Feature_NotHasStdExtZbaBit, Feature_HwMode0Bit, }, }; // ComplexPattern predicates. enum { GICP_Invalid, GICP_GIAddrRegImm, GICP_GIShiftMask32, GICP_GIShiftMaskXLen, GICP_gi_sh1add_op, GICP_gi_sh1add_uw_op, GICP_gi_sh2add_op, GICP_gi_sh2add_uw_op, GICP_gi_sh3add_op, GICP_gi_sh3add_uw_op, }; // See constructor for table contents RISCVInstructionSelector::ComplexMatcherMemFn RISCVInstructionSelector::ComplexPredicateFns[] = { nullptr, // GICP_Invalid &RISCVInstructionSelector::selectAddrRegImm, // GIAddrRegImm &RISCVInstructionSelector::selectShiftMask, // GIShiftMask32 &RISCVInstructionSelector::selectShiftMask, // GIShiftMaskXLen &RISCVInstructionSelector::selectSHXADDOp<1>, // gi_sh1add_op &RISCVInstructionSelector::selectSHXADD_UWOp<1>, // gi_sh1add_uw_op &RISCVInstructionSelector::selectSHXADDOp<2>, // gi_sh2add_op &RISCVInstructionSelector::selectSHXADD_UWOp<2>, // gi_sh2add_uw_op &RISCVInstructionSelector::selectSHXADDOp<3>, // gi_sh3add_op &RISCVInstructionSelector::selectSHXADD_UWOp<3>, // gi_sh3add_uw_op }; // PatFrag predicates. enum { GICXXPred_MI_Predicate_add_like_non_imm12 = GICXXPred_Invalid + 1, GICXXPred_MI_Predicate_add_non_imm12, }; bool RISCVInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const { const MachineFunction &MF = *MI.getParent()->getParent(); const MachineRegisterInfo &MRI = MF.getRegInfo(); const auto &Operands = State.RecordedOperands; (void)Operands; (void)MRI; switch (PredicateID) { case GICXXPred_MI_Predicate_add_like_non_imm12: { const MachineOperand &ImmOp = *Operands[1]; const MachineFunction &MF = *MI.getParent()->getParent(); const MachineRegisterInfo &MRI = MF.getRegInfo(); if (ImmOp.isReg() && ImmOp.getReg()) if (auto Val = getIConstantVRegValWithLookThrough(ImmOp.getReg(), MRI)) { // We do NOT want immediates that fit in 12 bits. return !isInt<12>(Val->Value.getSExtValue()); } return true; llvm_unreachable("add_like_non_imm12 should have returned"); } case GICXXPred_MI_Predicate_add_non_imm12: { const MachineOperand &ImmOp = *Operands[1]; const MachineFunction &MF = *MI.getParent()->getParent(); const MachineRegisterInfo &MRI = MF.getRegInfo(); if (ImmOp.isReg() && ImmOp.getReg()) if (auto Val = getIConstantVRegValWithLookThrough(ImmOp.getReg(), MRI)) { // We do NOT want immediates that fit in 12 bits. return !isInt<12>(Val->Value.getSExtValue()); } return true; llvm_unreachable("add_non_imm12 should have returned"); } } llvm_unreachable("Unknown predicate"); return false; } // PatFrag predicates. enum { GICXXPred_I64_Predicate_BCLRMask = GICXXPred_Invalid + 1, GICXXPred_I64_Predicate_BCLRMaski32, GICXXPred_I64_Predicate_SingleBitSetMask, GICXXPred_I64_Predicate_SingleBitSetMaski32, GICXXPred_I64_Predicate_byteselect, GICXXPred_I64_Predicate_c_lui_imm, GICXXPred_I64_Predicate_csr_sysreg, GICXXPred_I64_Predicate_cv_tuimm2, GICXXPred_I64_Predicate_cv_tuimm5, GICXXPred_I64_Predicate_cv_uimm10, GICXXPred_I64_Predicate_immzero, GICXXPred_I64_Predicate_payload1, GICXXPred_I64_Predicate_payload2, GICXXPred_I64_Predicate_payload5, GICXXPred_I64_Predicate_powerOf2Minus1, GICXXPred_I64_Predicate_rnum, GICXXPred_I64_Predicate_simm5, GICXXPred_I64_Predicate_simm5_plus1, GICXXPred_I64_Predicate_simm5_plus1_nonzero, GICXXPred_I64_Predicate_simm6, GICXXPred_I64_Predicate_simm6nonzero, GICXXPred_I64_Predicate_simm9_lsb0, GICXXPred_I64_Predicate_simm10_lsb0000nonzero, GICXXPred_I64_Predicate_simm12, GICXXPred_I64_Predicate_simm12Minus1Nonzero, GICXXPred_I64_Predicate_simm12Minus1NonzeroNonNeg1, GICXXPred_I64_Predicate_simm12Plus1, GICXXPred_I64_Predicate_simm12Plus1i32, GICXXPred_I64_Predicate_simm12_lsb0, GICXXPred_I64_Predicate_simm12_lsb00000, GICXXPred_I64_Predicate_simm12_no6, GICXXPred_I64_Predicate_simm12i32, GICXXPred_I64_Predicate_tsimm5, GICXXPred_I64_Predicate_tuimm5, GICXXPred_I64_Predicate_u32simm12, GICXXPred_I64_Predicate_uimm1, GICXXPred_I64_Predicate_uimm2, GICXXPred_I64_Predicate_uimm2_3, GICXXPred_I64_Predicate_uimm2_4, GICXXPred_I64_Predicate_uimm2_lsb0, GICXXPred_I64_Predicate_uimm4_with_predicate, GICXXPred_I64_Predicate_uimm5, GICXXPred_I64_Predicate_uimm5_lsb0, GICXXPred_I64_Predicate_uimm5_with_predicate, GICXXPred_I64_Predicate_uimm6, GICXXPred_I64_Predicate_uimm6_lsb0, GICXXPred_I64_Predicate_uimm6gt32, GICXXPred_I64_Predicate_uimm7_lsb00, GICXXPred_I64_Predicate_uimm8_lsb00, GICXXPred_I64_Predicate_uimm8_lsb000, GICXXPred_I64_Predicate_uimm9_lsb000, GICXXPred_I64_Predicate_uimm10_lsb00nonzero, GICXXPred_I64_Predicate_uimmlog2xlen, GICXXPred_I64_Predicate_uimmlog2xlennonzero, }; bool RISCVInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { switch (PredicateID) { case GICXXPred_I64_Predicate_BCLRMask: { if (Subtarget->is64Bit()) return !isInt<12>(Imm) && isPowerOf2_64(~Imm); return !isInt<12>(Imm) && isPowerOf2_32(~Imm); llvm_unreachable("BCLRMask should have returned"); } case GICXXPred_I64_Predicate_BCLRMaski32: { return !isInt<12>(Imm) && isPowerOf2_32(~Imm); } case GICXXPred_I64_Predicate_SingleBitSetMask: { if (Subtarget->is64Bit()) return !isInt<12>(Imm) && isPowerOf2_64(Imm); return !isInt<12>(Imm) && isPowerOf2_32(Imm); llvm_unreachable("SingleBitSetMask should have returned"); } case GICXXPred_I64_Predicate_SingleBitSetMaski32: { return !isInt<12>(Imm) && isPowerOf2_32(Imm); } case GICXXPred_I64_Predicate_byteselect: { return isUInt<2>(Imm); } case GICXXPred_I64_Predicate_c_lui_imm: { return (Imm != 0) && (isUInt<5>(Imm) || (Imm >= 0xfffe0 && Imm <= 0xfffff)); } case GICXXPred_I64_Predicate_csr_sysreg: { return isUInt<12>(Imm); } case GICXXPred_I64_Predicate_cv_tuimm2: { return isUInt<2>(Imm); } case GICXXPred_I64_Predicate_cv_tuimm5: { return isUInt<5>(Imm); } case GICXXPred_I64_Predicate_cv_uimm10: { return isUInt<10>(Imm); } case GICXXPred_I64_Predicate_immzero: { return (Imm == 0); } case GICXXPred_I64_Predicate_payload1: { return isUInt<1>(Imm); } case GICXXPred_I64_Predicate_payload2: { return isUInt<2>(Imm); } case GICXXPred_I64_Predicate_payload5: { return isUInt<5>(Imm); } case GICXXPred_I64_Predicate_powerOf2Minus1: { return isPowerOf2_32(Imm+1); } case GICXXPred_I64_Predicate_rnum: { return (Imm >= 0 && Imm <= 10); } case GICXXPred_I64_Predicate_simm5: { return isInt<5>(Imm); } case GICXXPred_I64_Predicate_simm5_plus1: { return (isInt<5>(Imm) && Imm != -16) || Imm == 16; } case GICXXPred_I64_Predicate_simm5_plus1_nonzero: { return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16); } case GICXXPred_I64_Predicate_simm6: { return isInt<6>(Imm); } case GICXXPred_I64_Predicate_simm6nonzero: { return (Imm != 0) && isInt<6>(Imm); } case GICXXPred_I64_Predicate_simm9_lsb0: { return isShiftedInt<8, 1>(Imm); } case GICXXPred_I64_Predicate_simm10_lsb0000nonzero: { return (Imm != 0) && isShiftedInt<6, 4>(Imm); } case GICXXPred_I64_Predicate_simm12: { return isInt<12>(Imm); } case GICXXPred_I64_Predicate_simm12Minus1Nonzero: { return (Imm >= -2049 && Imm < 0) || (Imm > 0 && Imm <= 2046); } case GICXXPred_I64_Predicate_simm12Minus1NonzeroNonNeg1: { return (Imm >= -2049 && Imm < -1) || (Imm > 0 && Imm <= 2046); } case GICXXPred_I64_Predicate_simm12Plus1: { return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048; } case GICXXPred_I64_Predicate_simm12Plus1i32: { return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048; } case GICXXPred_I64_Predicate_simm12_lsb0: { return isShiftedInt<11, 1>(Imm); } case GICXXPred_I64_Predicate_simm12_lsb00000: { return isShiftedInt<7, 5>(Imm); } case GICXXPred_I64_Predicate_simm12_no6: { return isInt<12>(Imm) && !isInt<6>(Imm) && isInt<12>(-Imm); } case GICXXPred_I64_Predicate_simm12i32: { return isInt<12>(Imm); } case GICXXPred_I64_Predicate_tsimm5: { return isInt<5>(Imm); } case GICXXPred_I64_Predicate_tuimm5: { return isUInt<5>(Imm); } case GICXXPred_I64_Predicate_u32simm12: { return isUInt<32>(Imm) && isInt<12>(SignExtend64<32>(Imm)); } case GICXXPred_I64_Predicate_uimm1: { return isUInt<1>(Imm); } case GICXXPred_I64_Predicate_uimm2: { return isUInt<2>(Imm); } case GICXXPred_I64_Predicate_uimm2_3: { return isShiftedUInt<2, 3>(Imm); } case GICXXPred_I64_Predicate_uimm2_4: { return isShiftedUInt<2, 4>(Imm); } case GICXXPred_I64_Predicate_uimm2_lsb0: { return isShiftedUInt<1, 1>(Imm); } case GICXXPred_I64_Predicate_uimm4_with_predicate: { return isUInt<4>(Imm); } case GICXXPred_I64_Predicate_uimm5: { return isUInt<5>(Imm); } case GICXXPred_I64_Predicate_uimm5_lsb0: { return isShiftedUInt<4, 1>(Imm); } case GICXXPred_I64_Predicate_uimm5_with_predicate: { return isUInt<5>(Imm); } case GICXXPred_I64_Predicate_uimm6: { return isUInt<6>(Imm); } case GICXXPred_I64_Predicate_uimm6_lsb0: { return isShiftedUInt<5, 1>(Imm); } case GICXXPred_I64_Predicate_uimm6gt32: { return isUInt<6>(Imm) && Imm > 32; } case GICXXPred_I64_Predicate_uimm7_lsb00: { return isShiftedUInt<5, 2>(Imm); } case GICXXPred_I64_Predicate_uimm8_lsb00: { return isShiftedUInt<6, 2>(Imm); } case GICXXPred_I64_Predicate_uimm8_lsb000: { return isShiftedUInt<5, 3>(Imm); } case GICXXPred_I64_Predicate_uimm9_lsb000: { return isShiftedUInt<6, 3>(Imm); } case GICXXPred_I64_Predicate_uimm10_lsb00nonzero: { return isShiftedUInt<8, 2>(Imm) && (Imm != 0); } case GICXXPred_I64_Predicate_uimmlog2xlen: { if (Subtarget->is64Bit()) return isUInt<6>(Imm); return isUInt<5>(Imm); llvm_unreachable("uimmlog2xlen should have returned"); } case GICXXPred_I64_Predicate_uimmlog2xlennonzero: { if (Subtarget->is64Bit()) return isUInt<6>(Imm) && (Imm != 0); return isUInt<5>(Imm) && (Imm != 0); llvm_unreachable("uimmlog2xlennonzero should have returned"); } } llvm_unreachable("Unknown predicate"); return false; } // PatFrag predicates. bool RISCVInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { llvm_unreachable("Unknown predicate"); return false; } // PatFrag predicates. enum { GICXXPred_APInt_Predicate_Shifted32OnesMask = GICXXPred_Invalid + 1, }; bool RISCVInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { switch (PredicateID) { case GICXXPred_APInt_Predicate_Shifted32OnesMask: { if (!Imm.isShiftedMask()) return false; unsigned TrailingZeros = Imm.countr_zero(); return TrailingZeros > 0 && TrailingZeros < 32 && Imm == UINT64_C(0xFFFFFFFF) << TrailingZeros; llvm_unreachable("Shifted32OnesMask should have returned"); } } llvm_unreachable("Unknown predicate"); return false; } bool RISCVInstructionSelector::testSimplePredicate(unsigned) const { llvm_unreachable("RISCVInstructionSelector does not support simple predicates!"); return false; } // Custom renderers. enum { GICR_Invalid, GICR_renderImm, GICR_renderImmPlus1, GICR_renderImmSubFrom32, GICR_renderImmSubFromXLen, GICR_renderNegImm, GICR_renderTrailingZeros, }; RISCVInstructionSelector::CustomRendererFn RISCVInstructionSelector::CustomRenderers[] = { nullptr, // GICR_Invalid &RISCVInstructionSelector::renderImm, &RISCVInstructionSelector::renderImmPlus1, &RISCVInstructionSelector::renderImmSubFrom32, &RISCVInstructionSelector::renderImmSubFromXLen, &RISCVInstructionSelector::renderNegImm, &RISCVInstructionSelector::renderTrailingZeros, }; bool RISCVInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { const PredicateBitset AvailableFeatures = getAvailableFeatures(); MachineIRBuilder B(I); State.MIs.clear(); State.MIs.push_back(&I); if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) { return true; } return false; } bool RISCVInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const { llvm_unreachable("RISCVInstructionSelector does not support custom C++ actions!"); } #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ #define GIMT_Encode2 … #define GIMT_Encode4 … #define GIMT_Encode8 … #else #define GIMT_Encode2 … #define GIMT_Encode4 … #define GIMT_Encode8 … #endif const uint8_t *RISCVInstructionSelector::getMatchTable() const { constexpr static uint8_t MatchTable0[] = { GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(53), GIMT_Encode2(306), /*)*//*default:*//*Label 99*/ GIMT_Encode4(319025), /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(1022), /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(10364), /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(13468), /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(16373), /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(19143), /*TargetOpcode::G_SREM*//*Label 5*/ GIMT_Encode4(21913), /*TargetOpcode::G_UREM*//*Label 6*/ GIMT_Encode4(24683), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_AND*//*Label 7*/ GIMT_Encode4(27453), /*TargetOpcode::G_OR*//*Label 8*/ GIMT_Encode4(36999), /*TargetOpcode::G_XOR*//*Label 9*/ GIMT_Encode4(44930), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_BITCAST*//*Label 10*/ GIMT_Encode4(60318), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 11*/ GIMT_Encode4(60631), /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 12*/ GIMT_Encode4(60829), /*TargetOpcode::G_INTRINSIC_LRINT*//*Label 13*/ GIMT_Encode4(61027), /*TargetOpcode::G_INTRINSIC_LLRINT*//*Label 14*/ GIMT_Encode4(61607), /*TargetOpcode::G_INTRINSIC_ROUNDEVEN*//*Label 15*/ GIMT_Encode4(61817), /*TargetOpcode::G_READCYCLECOUNTER*//*Label 16*/ GIMT_Encode4(61957), /*TargetOpcode::G_READSTEADYCOUNTER*//*Label 17*/ GIMT_Encode4(61996), /*TargetOpcode::G_LOAD*//*Label 18*/ GIMT_Encode4(62035), /*TargetOpcode::G_SEXTLOAD*//*Label 19*/ GIMT_Encode4(67489), /*TargetOpcode::G_ZEXTLOAD*//*Label 20*/ GIMT_Encode4(67997), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_STORE*//*Label 21*/ GIMT_Encode4(68505), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 22*/ GIMT_Encode4(72835), /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 23*/ GIMT_Encode4(77391), /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 24*/ GIMT_Encode4(81121), GIMT_Encode4(0), /*TargetOpcode::G_ATOMICRMW_AND*//*Label 25*/ GIMT_Encode4(84851), /*TargetOpcode::G_ATOMICRMW_NAND*//*Label 26*/ GIMT_Encode4(88581), /*TargetOpcode::G_ATOMICRMW_OR*//*Label 27*/ GIMT_Encode4(88866), /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 28*/ GIMT_Encode4(92596), /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 29*/ GIMT_Encode4(96326), /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 30*/ GIMT_Encode4(100056), /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 31*/ GIMT_Encode4(103786), /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 32*/ GIMT_Encode4(107516), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_FENCE*//*Label 33*/ GIMT_Encode4(111246), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_INTRINSIC*//*Label 34*/ GIMT_Encode4(111464), /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 35*/ GIMT_Encode4(115644), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_ANYEXT*//*Label 36*/ GIMT_Encode4(116370), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_SEXT*//*Label 37*/ GIMT_Encode4(119491), GIMT_Encode4(0), /*TargetOpcode::G_ZEXT*//*Label 38*/ GIMT_Encode4(122656), /*TargetOpcode::G_SHL*//*Label 39*/ GIMT_Encode4(125872), /*TargetOpcode::G_LSHR*//*Label 40*/ GIMT_Encode4(129317), /*TargetOpcode::G_ASHR*//*Label 41*/ GIMT_Encode4(132424), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_ROTR*//*Label 42*/ GIMT_Encode4(135500), /*TargetOpcode::G_ROTL*//*Label 43*/ GIMT_Encode4(138603), /*TargetOpcode::G_ICMP*//*Label 44*/ GIMT_Encode4(141669), /*TargetOpcode::G_FCMP*//*Label 45*/ GIMT_Encode4(168332), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_SELECT*//*Label 46*/ GIMT_Encode4(175794), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_UMULH*//*Label 47*/ GIMT_Encode4(182524), /*TargetOpcode::G_SMULH*//*Label 48*/ GIMT_Encode4(185258), /*TargetOpcode::G_UADDSAT*//*Label 49*/ GIMT_Encode4(187992), /*TargetOpcode::G_SADDSAT*//*Label 50*/ GIMT_Encode4(190778), /*TargetOpcode::G_USUBSAT*//*Label 51*/ GIMT_Encode4(193564), /*TargetOpcode::G_SSUBSAT*//*Label 52*/ GIMT_Encode4(196350), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_FADD*//*Label 53*/ GIMT_Encode4(199136), /*TargetOpcode::G_FSUB*//*Label 54*/ GIMT_Encode4(201564), /*TargetOpcode::G_FMUL*//*Label 55*/ GIMT_Encode4(203992), /*TargetOpcode::G_FMA*//*Label 56*/ GIMT_Encode4(206420), GIMT_Encode4(0), /*TargetOpcode::G_FDIV*//*Label 57*/ GIMT_Encode4(223065), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_FNEG*//*Label 58*/ GIMT_Encode4(225493), /*TargetOpcode::G_FPEXT*//*Label 59*/ GIMT_Encode4(227464), /*TargetOpcode::G_FPTRUNC*//*Label 60*/ GIMT_Encode4(228079), /*TargetOpcode::G_FPTOSI*//*Label 61*/ GIMT_Encode4(230243), /*TargetOpcode::G_FPTOUI*//*Label 62*/ GIMT_Encode4(235129), /*TargetOpcode::G_SITOFP*//*Label 63*/ GIMT_Encode4(240015), /*TargetOpcode::G_UITOFP*//*Label 64*/ GIMT_Encode4(245079), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_FABS*//*Label 65*/ GIMT_Encode4(250143), /*TargetOpcode::G_FCOPYSIGN*//*Label 66*/ GIMT_Encode4(252114), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_FMINNUM*//*Label 67*/ GIMT_Encode4(257763), /*TargetOpcode::G_FMAXNUM*//*Label 68*/ GIMT_Encode4(259848), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_FMINIMUM*//*Label 69*/ GIMT_Encode4(261933), /*TargetOpcode::G_FMAXIMUM*//*Label 70*/ GIMT_Encode4(262059), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_SMIN*//*Label 71*/ GIMT_Encode4(262185), /*TargetOpcode::G_SMAX*//*Label 72*/ GIMT_Encode4(264961), /*TargetOpcode::G_UMIN*//*Label 73*/ GIMT_Encode4(267737), /*TargetOpcode::G_UMAX*//*Label 74*/ GIMT_Encode4(270513), /*TargetOpcode::G_ABS*//*Label 75*/ GIMT_Encode4(273289), /*TargetOpcode::G_LROUND*//*Label 76*/ GIMT_Encode4(273447), /*TargetOpcode::G_LLROUND*//*Label 77*/ GIMT_Encode4(274027), /*TargetOpcode::G_BR*//*Label 78*/ GIMT_Encode4(274237), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_CTTZ*//*Label 79*/ GIMT_Encode4(274253), GIMT_Encode4(0), /*TargetOpcode::G_CTLZ*//*Label 80*/ GIMT_Encode4(276803), GIMT_Encode4(0), /*TargetOpcode::G_CTPOP*//*Label 81*/ GIMT_Encode4(279499), /*TargetOpcode::G_BSWAP*//*Label 82*/ GIMT_Encode4(282049), /*TargetOpcode::G_BITREVERSE*//*Label 83*/ GIMT_Encode4(284584), /*TargetOpcode::G_FCEIL*//*Label 84*/ GIMT_Encode4(287078), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_FSQRT*//*Label 85*/ GIMT_Encode4(287276), /*TargetOpcode::G_FFLOOR*//*Label 86*/ GIMT_Encode4(289452), /*TargetOpcode::G_FRINT*//*Label 87*/ GIMT_Encode4(289650), /*TargetOpcode::G_FNEARBYINT*//*Label 88*/ GIMT_Encode4(289848), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_STRICT_FADD*//*Label 89*/ GIMT_Encode4(290046), /*TargetOpcode::G_STRICT_FSUB*//*Label 90*/ GIMT_Encode4(292474), /*TargetOpcode::G_STRICT_FMUL*//*Label 91*/ GIMT_Encode4(294902), /*TargetOpcode::G_STRICT_FDIV*//*Label 92*/ GIMT_Encode4(297330), GIMT_Encode4(0), /*TargetOpcode::G_STRICT_FMA*//*Label 93*/ GIMT_Encode4(299758), /*TargetOpcode::G_STRICT_FSQRT*//*Label 94*/ GIMT_Encode4(316403), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*TargetOpcode::G_TRAP*//*Label 95*/ GIMT_Encode4(318579), /*TargetOpcode::G_DEBUGTRAP*//*Label 96*/ GIMT_Encode4(318592), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), /*RISCV::G_FCLASS*//*Label 97*/ GIMT_Encode4(318605), /*RISCV::G_READ_VLENB*//*Label 98*/ GIMT_Encode4(318965), // Label 0: @1022 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 124*/ GIMT_Encode4(10363), /*GILLT_s32*//*Label 100*/ GIMT_Encode4(1157), /*GILLT_s64*//*Label 101*/ GIMT_Encode4(3655), GIMT_Encode4(0), /*GILLT_nxv1s8*//*Label 102*/ GIMT_Encode4(7833), /*GILLT_nxv1s16*//*Label 103*/ GIMT_Encode4(7948), /*GILLT_nxv1s32*//*Label 104*/ GIMT_Encode4(8063), /*GILLT_nxv1s64*//*Label 105*/ GIMT_Encode4(8178), GIMT_Encode4(0), /*GILLT_nxv2s8*//*Label 106*/ GIMT_Encode4(8293), /*GILLT_nxv2s16*//*Label 107*/ GIMT_Encode4(8408), /*GILLT_nxv2s32*//*Label 108*/ GIMT_Encode4(8523), /*GILLT_nxv2s64*//*Label 109*/ GIMT_Encode4(8638), GIMT_Encode4(0), /*GILLT_nxv4s8*//*Label 110*/ GIMT_Encode4(8753), /*GILLT_nxv4s16*//*Label 111*/ GIMT_Encode4(8868), /*GILLT_nxv4s32*//*Label 112*/ GIMT_Encode4(8983), /*GILLT_nxv4s64*//*Label 113*/ GIMT_Encode4(9098), GIMT_Encode4(0), /*GILLT_nxv8s8*//*Label 114*/ GIMT_Encode4(9213), /*GILLT_nxv8s16*//*Label 115*/ GIMT_Encode4(9328), /*GILLT_nxv8s32*//*Label 116*/ GIMT_Encode4(9443), /*GILLT_nxv8s64*//*Label 117*/ GIMT_Encode4(9558), GIMT_Encode4(0), /*GILLT_nxv16s8*//*Label 118*/ GIMT_Encode4(9673), /*GILLT_nxv16s16*//*Label 119*/ GIMT_Encode4(9788), /*GILLT_nxv16s32*//*Label 120*/ GIMT_Encode4(9903), GIMT_Encode4(0), /*GILLT_nxv32s8*//*Label 121*/ GIMT_Encode4(10018), /*GILLT_nxv32s16*//*Label 122*/ GIMT_Encode4(10133), GIMT_Encode4(0), /*GILLT_nxv64s8*//*Label 123*/ GIMT_Encode4(10248), // Label 100: @1157 GIM_Try, /*On fail goto*//*Label 125*/ GIMT_Encode4(3654), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 126*/ GIMT_Encode4(1216), // Rule ID 2384 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:2:x GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:2:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh1add_op), // (add:{ *:[i32] } sh1add_op:{ *:[i32] }:$rs1:$pred:2:x, GPR:{ *:[i32] }:$rs2:$pred:2:y)<<P:2:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i32] } sh1add_op:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2384, GIR_EraseRootFromParent_Done, // Label 126: @1216 GIM_Try, /*On fail goto*//*Label 127*/ GIMT_Encode4(1264), // Rule ID 2394 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:4:x GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:4:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh2add_op), // (add:{ *:[i32] } sh2add_op:{ *:[i32] }:$rs1:$pred:4:x, GPR:{ *:[i32] }:$rs2:$pred:4:y)<<P:4:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i32] } sh2add_op:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2394, GIR_EraseRootFromParent_Done, // Label 127: @1264 GIM_Try, /*On fail goto*//*Label 128*/ GIMT_Encode4(1312), // Rule ID 2404 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:6:x GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:6:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh3add_op), // (add:{ *:[i32] } sh3add_op:{ *:[i32] }:$rs1:$pred:6:x, GPR:{ *:[i32] }:$rs2:$pred:6:y)<<P:6:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i32] } sh3add_op:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2404, GIR_EraseRootFromParent_Done, // Label 128: @1312 GIM_Try, /*On fail goto*//*Label 129*/ GIMT_Encode4(1363), // Rule ID 62599 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:23:x GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:23:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh1add_op), // (add:{ *:[i32] } sh1add_op:{ *:[i32] }:$rs1:$pred:23:x, GPR:{ *:[i32] }:$rs2:$pred:23:y)<<P:23:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i32] } GPR:{ *:[i32] }:$rs2, sh1add_op:{ *:[i32] }:$rs1, 1:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_AddImm8, /*InsnID*/0, /*Imm*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 62599, GIR_EraseRootFromParent_Done, // Label 129: @1363 GIM_Try, /*On fail goto*//*Label 130*/ GIMT_Encode4(1414), // Rule ID 62601 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:24:x GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:24:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh2add_op), // (add:{ *:[i32] } sh2add_op:{ *:[i32] }:$rs1:$pred:24:x, GPR:{ *:[i32] }:$rs2:$pred:24:y)<<P:24:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i32] } GPR:{ *:[i32] }:$rs2, sh2add_op:{ *:[i32] }:$rs1, 2:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_AddImm8, /*InsnID*/0, /*Imm*/2, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 62601, GIR_EraseRootFromParent_Done, // Label 130: @1414 GIM_Try, /*On fail goto*//*Label 131*/ GIMT_Encode4(1465), // Rule ID 62603 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:25:x GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:25:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh3add_op), // (add:{ *:[i32] } sh3add_op:{ *:[i32] }:$rs1:$pred:25:x, GPR:{ *:[i32] }:$rs2:$pred:25:y)<<P:25:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i32] } GPR:{ *:[i32] }:$rs2, sh3add_op:{ *:[i32] }:$rs1, 3:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 62603, GIR_EraseRootFromParent_Done, // Label 131: @1465 GIM_Try, /*On fail goto*//*Label 132*/ GIMT_Encode4(1513), // Rule ID 65149 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:2:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:2:x GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh1add_op), // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:2:y, sh1add_op:{ *:[i32] }:$rs1:$pred:2:x)<<P:2:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i32] } sh1add_op:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65149, GIR_EraseRootFromParent_Done, // Label 132: @1513 GIM_Try, /*On fail goto*//*Label 133*/ GIMT_Encode4(1561), // Rule ID 65157 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:4:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:4:x GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh2add_op), // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:4:y, sh2add_op:{ *:[i32] }:$rs1:$pred:4:x)<<P:4:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i32] } sh2add_op:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65157, GIR_EraseRootFromParent_Done, // Label 133: @1561 GIM_Try, /*On fail goto*//*Label 134*/ GIMT_Encode4(1609), // Rule ID 65165 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:6:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:6:x GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh3add_op), // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:6:y, sh3add_op:{ *:[i32] }:$rs1:$pred:6:x)<<P:6:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i32] } sh3add_op:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65165, GIR_EraseRootFromParent_Done, // Label 134: @1609 GIM_Try, /*On fail goto*//*Label 135*/ GIMT_Encode4(1660), // Rule ID 73671 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:23:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:23:x GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh1add_op), // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:23:y, sh1add_op:{ *:[i32] }:$rs1:$pred:23:x)<<P:23:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i32] } GPR:{ *:[i32] }:$rs2, sh1add_op:{ *:[i32] }:$rs1, 1:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_AddImm8, /*InsnID*/0, /*Imm*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73671, GIR_EraseRootFromParent_Done, // Label 135: @1660 GIM_Try, /*On fail goto*//*Label 136*/ GIMT_Encode4(1711), // Rule ID 73673 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:24:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:24:x GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh2add_op), // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:24:y, sh2add_op:{ *:[i32] }:$rs1:$pred:24:x)<<P:24:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i32] } GPR:{ *:[i32] }:$rs2, sh2add_op:{ *:[i32] }:$rs1, 2:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_AddImm8, /*InsnID*/0, /*Imm*/2, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73673, GIR_EraseRootFromParent_Done, // Label 136: @1711 GIM_Try, /*On fail goto*//*Label 137*/ GIMT_Encode4(1762), // Rule ID 73675 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:25:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:25:x GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh3add_op), // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:25:y, sh3add_op:{ *:[i32] }:$rs1:$pred:25:x)<<P:25:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i32] } GPR:{ *:[i32] }:$rs2, sh3add_op:{ *:[i32] }:$rs1, 3:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73675, GIR_EraseRootFromParent_Done, // Label 137: @1762 GIM_Try, /*On fail goto*//*Label 138*/ GIMT_Encode4(1830), // Rule ID 2378 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:1:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:1:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 1:{ *:[i32] }):$pred:1:x, GPR:{ *:[i32] }:$rs2:$pred:1:y)<<P:1:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2378, GIR_EraseRootFromParent_Done, // Label 138: @1830 GIM_Try, /*On fail goto*//*Label 139*/ GIMT_Encode4(1898), // Rule ID 2388 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:3:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:3:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 2:{ *:[i32] }):$pred:3:x, GPR:{ *:[i32] }:$rs2:$pred:3:y)<<P:3:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2388, GIR_EraseRootFromParent_Done, // Label 139: @1898 GIM_Try, /*On fail goto*//*Label 140*/ GIMT_Encode4(1966), // Rule ID 2398 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:5:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:5:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 3:{ *:[i32] }):$pred:5:x, GPR:{ *:[i32] }:$rs2:$pred:5:y)<<P:5:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2398, GIR_EraseRootFromParent_Done, // Label 140: @1966 GIM_Try, /*On fail goto*//*Label 141*/ GIMT_Encode4(2034), // Rule ID 64992 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:27:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:27:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 1:{ *:[i64] }):$pred:27:x, GPR:{ *:[i32] }:$rs2:$pred:27:y)<<P:27:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64992, GIR_EraseRootFromParent_Done, // Label 141: @2034 GIM_Try, /*On fail goto*//*Label 142*/ GIMT_Encode4(2102), // Rule ID 64993 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:27:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:27:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 1:{ *:[i64] }):$pred:27:x, GPR:{ *:[i32] }:$rs2:$pred:27:y)<<P:27:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64993, GIR_EraseRootFromParent_Done, // Label 142: @2102 GIM_Try, /*On fail goto*//*Label 143*/ GIMT_Encode4(2170), // Rule ID 64998 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:28:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:28:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 2:{ *:[i64] }):$pred:28:x, GPR:{ *:[i32] }:$rs2:$pred:28:y)<<P:28:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64998, GIR_EraseRootFromParent_Done, // Label 143: @2170 GIM_Try, /*On fail goto*//*Label 144*/ GIMT_Encode4(2238), // Rule ID 64999 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:28:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:28:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 2:{ *:[i64] }):$pred:28:x, GPR:{ *:[i32] }:$rs2:$pred:28:y)<<P:28:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64999, GIR_EraseRootFromParent_Done, // Label 144: @2238 GIM_Try, /*On fail goto*//*Label 145*/ GIMT_Encode4(2306), // Rule ID 65004 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:29:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:29:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 3:{ *:[i64] }):$pred:29:x, GPR:{ *:[i32] }:$rs2:$pred:29:y)<<P:29:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65004, GIR_EraseRootFromParent_Done, // Label 145: @2306 GIM_Try, /*On fail goto*//*Label 146*/ GIMT_Encode4(2374), // Rule ID 65005 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:29:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:29:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 3:{ *:[i64] }):$pred:29:x, GPR:{ *:[i32] }:$rs2:$pred:29:y)<<P:29:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65005, GIR_EraseRootFromParent_Done, // Label 146: @2374 GIM_Try, /*On fail goto*//*Label 147*/ GIMT_Encode4(2442), // Rule ID 65145 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:1:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:1:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:1:y, (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 1:{ *:[i32] }):$pred:1:x)<<P:1:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65145, GIR_EraseRootFromParent_Done, // Label 147: @2442 GIM_Try, /*On fail goto*//*Label 148*/ GIMT_Encode4(2510), // Rule ID 65153 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:3:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:3:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:3:y, (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 2:{ *:[i32] }):$pred:3:x)<<P:3:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65153, GIR_EraseRootFromParent_Done, // Label 148: @2510 GIM_Try, /*On fail goto*//*Label 149*/ GIMT_Encode4(2578), // Rule ID 65161 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:5:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:5:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:5:y, (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 3:{ *:[i32] }):$pred:5:x)<<P:5:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65161, GIR_EraseRootFromParent_Done, // Label 149: @2578 GIM_Try, /*On fail goto*//*Label 150*/ GIMT_Encode4(2646), // Rule ID 73700 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:27:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:27:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:27:y, (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 1:{ *:[i64] }):$pred:27:x)<<P:27:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73700, GIR_EraseRootFromParent_Done, // Label 150: @2646 GIM_Try, /*On fail goto*//*Label 151*/ GIMT_Encode4(2714), // Rule ID 73701 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:27:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:27:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:27:y, (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 1:{ *:[i64] }):$pred:27:x)<<P:27:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73701, GIR_EraseRootFromParent_Done, // Label 151: @2714 GIM_Try, /*On fail goto*//*Label 152*/ GIMT_Encode4(2782), // Rule ID 73704 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:28:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:28:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:28:y, (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 2:{ *:[i64] }):$pred:28:x)<<P:28:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73704, GIR_EraseRootFromParent_Done, // Label 152: @2782 GIM_Try, /*On fail goto*//*Label 153*/ GIMT_Encode4(2850), // Rule ID 73705 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:28:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:28:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:28:y, (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 2:{ *:[i64] }):$pred:28:x)<<P:28:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73705, GIR_EraseRootFromParent_Done, // Label 153: @2850 GIM_Try, /*On fail goto*//*Label 154*/ GIMT_Encode4(2918), // Rule ID 73708 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:29:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:29:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:29:y, (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 3:{ *:[i64] }):$pred:29:x)<<P:29:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73708, GIR_EraseRootFromParent_Done, // Label 154: @2918 GIM_Try, /*On fail goto*//*Label 155*/ GIMT_Encode4(2986), // Rule ID 73709 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:29:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:29:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs2:$pred:29:y, (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 3:{ *:[i64] }):$pred:29:x)<<P:29:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73709, GIR_EraseRootFromParent_Done, // Label 155: @2986 GIM_Try, /*On fail goto*//*Label 156*/ GIMT_Encode4(3053), // Rule ID 73669 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm2), // MIs[2] Operand 1 // No operand predicates GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm2>>:$uimm2), GPR:{ *:[i32] }:$rs1) => (TH_ADDSL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm2>>:$uimm2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // uimm2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73669, GIR_EraseRootFromParent_Done, // Label 156: @3053 GIM_Try, /*On fail goto*//*Label 157*/ GIMT_Encode4(3120), // Rule ID 62595 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm2), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm2>>:$uimm2)) => (TH_ADDSL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_uimm2>>:$uimm2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // uimm2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 62595, GIR_EraseRootFromParent_Done, // Label 157: @3120 GIM_Try, /*On fail goto*//*Label 158*/ GIMT_Encode4(3162), // Rule ID 69 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm) => (ADDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADDI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 69, GIR_EraseRootFromParent_Done, // Label 158: @3162 GIM_Try, /*On fail goto*//*Label 159*/ GIMT_Encode4(3206), // Rule ID 64727 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12i32), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12i32>>:$imm) => (ADDIW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (as_i64imm:{ *:[i64] } ?:{ *:[i32] }:$imm)) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADDIW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImm), // imm GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64727, GIR_EraseRootFromParent_Done, // Label 159: @3206 GIM_Try, /*On fail goto*//*Label 160*/ GIMT_Encode4(3267), // Rule ID 73677 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), GPR:{ *:[i32] }:$rd) => (TH_MULA:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULA), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] GIR_RootToRootCopy, /*OpIdx*/2, // rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73677, GIR_EraseRootFromParent_Done, // Label 160: @3267 GIM_Try, /*On fail goto*//*Label 161*/ GIMT_Encode4(3328), // Rule ID 73714 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), GPR:{ *:[i32] }:$rd) => (TH_MULAW:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULAW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] GIR_RootToRootCopy, /*OpIdx*/2, // rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73714, GIR_EraseRootFromParent_Done, // Label 161: @3328 GIM_Try, /*On fail goto*//*Label 162*/ GIMT_Encode4(3389), // Rule ID 73715 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_IsRV64_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), GPR:{ *:[i32] }:$rd) => (TH_MULAW:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULAW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] GIR_RootToRootCopy, /*OpIdx*/2, // rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73715, GIR_EraseRootFromParent_Done, // Label 162: @3389 GIM_Try, /*On fail goto*//*Label 163*/ GIMT_Encode4(3450), // Rule ID 62655 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$rd, (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)) => (TH_MULA:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULA), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] GIR_RootToRootCopy, /*OpIdx*/1, // rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 62655, GIR_EraseRootFromParent_Done, // Label 163: @3450 GIM_Try, /*On fail goto*//*Label 164*/ GIMT_Encode4(3511), // Rule ID 65054 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$rd, (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)) => (TH_MULAW:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULAW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] GIR_RootToRootCopy, /*OpIdx*/1, // rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65054, GIR_EraseRootFromParent_Done, // Label 164: @3511 GIM_Try, /*On fail goto*//*Label 165*/ GIMT_Encode4(3572), // Rule ID 65055 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_IsRV64_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$rd, (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)) => (TH_MULAW:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULAW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] GIR_RootToRootCopy, /*OpIdx*/1, // rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65055, GIR_EraseRootFromParent_Done, // Label 165: @3572 GIM_Try, /*On fail goto*//*Label 166*/ GIMT_Encode4(3599), // Rule ID 67 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::ADD), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 67, GIR_Done, // Label 166: @3599 GIM_Try, /*On fail goto*//*Label 167*/ GIMT_Encode4(3626), // Rule ID 64714 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (ADDW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::ADDW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64714, GIR_Done, // Label 167: @3626 GIM_Try, /*On fail goto*//*Label 168*/ GIMT_Encode4(3653), // Rule ID 64715 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (ADDW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::ADDW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64715, GIR_Done, // Label 168: @3653 GIM_Reject, // Label 125: @3654 GIM_Reject, // Label 101: @3655 GIM_Try, /*On fail goto*//*Label 169*/ GIMT_Encode4(7832), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_Try, /*On fail goto*//*Label 170*/ GIMT_Encode4(3761), // Rule ID 2428 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:11:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8589934591), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:11:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[i64] } (and:{ *:[i64] } (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] }), 8589934591:{ *:[i64] }):$pred:11:x, GPR:{ *:[i64] }:$rs2:$pred:11:y)<<P:11:Predicate_add_like_non_imm12>> => (SH1ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2428, GIR_EraseRootFromParent_Done, // Label 170: @3761 GIM_Try, /*On fail goto*//*Label 171*/ GIMT_Encode4(3856), // Rule ID 2430 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:12:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 2, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(17179869183), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:12:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[i64] } (and:{ *:[i64] } (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 2:{ *:[i64] }), 17179869183:{ *:[i64] }):$pred:12:x, GPR:{ *:[i64] }:$rs2:$pred:12:y)<<P:12:Predicate_add_like_non_imm12>> => (SH2ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2430, GIR_EraseRootFromParent_Done, // Label 171: @3856 GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(3951), // Rule ID 2432 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:13:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 3, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(34359738367), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:13:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[i64] } (and:{ *:[i64] } (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 3:{ *:[i64] }), 34359738367:{ *:[i64] }):$pred:13:x, GPR:{ *:[i64] }:$rs2:$pred:13:y)<<P:13:Predicate_add_like_non_imm12>> => (SH3ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2432, GIR_EraseRootFromParent_Done, // Label 172: @3951 GIM_Try, /*On fail goto*//*Label 173*/ GIMT_Encode4(4046), // Rule ID 2419 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:8:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294967295), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:8:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[i64] } (shl:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), 1:{ *:[i64] }):$pred:8:x, GPR:{ *:[i64] }:$rs2:$pred:8:y)<<P:8:Predicate_add_like_non_imm12>> => (SH1ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2419, GIR_EraseRootFromParent_Done, // Label 173: @4046 GIM_Try, /*On fail goto*//*Label 174*/ GIMT_Encode4(4141), // Rule ID 2422 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:9:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294967295), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:9:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[i64] } (shl:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), 2:{ *:[i64] }):$pred:9:x, GPR:{ *:[i64] }:$rs2:$pred:9:y)<<P:9:Predicate_add_like_non_imm12>> => (SH2ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2422, GIR_EraseRootFromParent_Done, // Label 174: @4141 GIM_Try, /*On fail goto*//*Label 175*/ GIMT_Encode4(4236), // Rule ID 2425 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:10:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294967295), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:10:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[i64] } (shl:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), 3:{ *:[i64] }):$pred:10:x, GPR:{ *:[i64] }:$rs2:$pred:10:y)<<P:10:Predicate_add_like_non_imm12>> => (SH3ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2425, GIR_EraseRootFromParent_Done, // Label 175: @4236 GIM_Try, /*On fail goto*//*Label 176*/ GIMT_Encode4(4331), // Rule ID 65175 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:11:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:11:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8589934591), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:11:y, (and:{ *:[i64] } (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] }), 8589934591:{ *:[i64] }):$pred:11:x)<<P:11:Predicate_add_like_non_imm12>> => (SH1ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65175, GIR_EraseRootFromParent_Done, // Label 176: @4331 GIM_Try, /*On fail goto*//*Label 177*/ GIMT_Encode4(4426), // Rule ID 65177 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:12:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:12:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 2, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(17179869183), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:12:y, (and:{ *:[i64] } (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 2:{ *:[i64] }), 17179869183:{ *:[i64] }):$pred:12:x)<<P:12:Predicate_add_like_non_imm12>> => (SH2ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65177, GIR_EraseRootFromParent_Done, // Label 177: @4426 GIM_Try, /*On fail goto*//*Label 178*/ GIMT_Encode4(4521), // Rule ID 65179 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:13:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:13:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 3, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(34359738367), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:13:y, (and:{ *:[i64] } (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 3:{ *:[i64] }), 34359738367:{ *:[i64] }):$pred:13:x)<<P:13:Predicate_add_like_non_imm12>> => (SH3ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65179, GIR_EraseRootFromParent_Done, // Label 178: @4521 GIM_Try, /*On fail goto*//*Label 179*/ GIMT_Encode4(4616), // Rule ID 65169 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:8:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:8:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294967295), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:8:y, (shl:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), 1:{ *:[i64] }):$pred:8:x)<<P:8:Predicate_add_like_non_imm12>> => (SH1ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65169, GIR_EraseRootFromParent_Done, // Label 179: @4616 GIM_Try, /*On fail goto*//*Label 180*/ GIMT_Encode4(4711), // Rule ID 65171 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:9:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:9:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294967295), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:9:y, (shl:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), 2:{ *:[i64] }):$pred:9:x)<<P:9:Predicate_add_like_non_imm12>> => (SH2ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65171, GIR_EraseRootFromParent_Done, // Label 180: @4711 GIM_Try, /*On fail goto*//*Label 181*/ GIMT_Encode4(4806), // Rule ID 65173 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:10:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:10:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294967295), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:10:y, (shl:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), 3:{ *:[i64] }):$pred:10:x)<<P:10:Predicate_add_like_non_imm12>> => (SH3ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65173, GIR_EraseRootFromParent_Done, // Label 181: @4806 GIM_Try, /*On fail goto*//*Label 182*/ GIMT_Encode4(4854), // Rule ID 2383 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:2:x GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:2:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh1add_op), // (add:{ *:[i64] } sh1add_op:{ *:[i64] }:$rs1:$pred:2:x, GPR:{ *:[i64] }:$rs2:$pred:2:y)<<P:2:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i64] } sh1add_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2383, GIR_EraseRootFromParent_Done, // Label 182: @4854 GIM_Try, /*On fail goto*//*Label 183*/ GIMT_Encode4(4902), // Rule ID 2393 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:4:x GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:4:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh2add_op), // (add:{ *:[i64] } sh2add_op:{ *:[i64] }:$rs1:$pred:4:x, GPR:{ *:[i64] }:$rs2:$pred:4:y)<<P:4:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i64] } sh2add_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2393, GIR_EraseRootFromParent_Done, // Label 183: @4902 GIM_Try, /*On fail goto*//*Label 184*/ GIMT_Encode4(4950), // Rule ID 2403 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:6:x GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:6:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh3add_op), // (add:{ *:[i64] } sh3add_op:{ *:[i64] }:$rs1:$pred:6:x, GPR:{ *:[i64] }:$rs2:$pred:6:y)<<P:6:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i64] } sh3add_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2403, GIR_EraseRootFromParent_Done, // Label 184: @4950 GIM_Try, /*On fail goto*//*Label 185*/ GIMT_Encode4(4998), // Rule ID 2434 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:14:x GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:14:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh1add_uw_op), // (add:{ *:[i64] } sh1add_uw_op:{ *:[i64] }:$rs1:$pred:14:x, GPR:{ *:[i64] }:$rs2:$pred:14:y)<<P:14:Predicate_add_like_non_imm12>> => (SH1ADD_UW:{ *:[i64] } sh1add_uw_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2434, GIR_EraseRootFromParent_Done, // Label 185: @4998 GIM_Try, /*On fail goto*//*Label 186*/ GIMT_Encode4(5046), // Rule ID 2436 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:15:x GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:15:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh2add_uw_op), // (add:{ *:[i64] } sh2add_uw_op:{ *:[i64] }:$rs1:$pred:15:x, GPR:{ *:[i64] }:$rs2:$pred:15:y)<<P:15:Predicate_add_like_non_imm12>> => (SH2ADD_UW:{ *:[i64] } sh2add_uw_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2436, GIR_EraseRootFromParent_Done, // Label 186: @5046 GIM_Try, /*On fail goto*//*Label 187*/ GIMT_Encode4(5094), // Rule ID 2438 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:16:x GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:16:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh3add_uw_op), // (add:{ *:[i64] } sh3add_uw_op:{ *:[i64] }:$rs1:$pred:16:x, GPR:{ *:[i64] }:$rs2:$pred:16:y)<<P:16:Predicate_add_like_non_imm12>> => (SH3ADD_UW:{ *:[i64] } sh3add_uw_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2438, GIR_EraseRootFromParent_Done, // Label 187: @5094 GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(5145), // Rule ID 62598 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:23:x GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:23:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh1add_op), // (add:{ *:[i64] } sh1add_op:{ *:[i64] }:$rs1:$pred:23:x, GPR:{ *:[i64] }:$rs2:$pred:23:y)<<P:23:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i64] } GPR:{ *:[i64] }:$rs2, sh1add_op:{ *:[i64] }:$rs1, 1:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_AddImm8, /*InsnID*/0, /*Imm*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 62598, GIR_EraseRootFromParent_Done, // Label 188: @5145 GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(5196), // Rule ID 62600 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:24:x GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:24:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh2add_op), // (add:{ *:[i64] } sh2add_op:{ *:[i64] }:$rs1:$pred:24:x, GPR:{ *:[i64] }:$rs2:$pred:24:y)<<P:24:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i64] } GPR:{ *:[i64] }:$rs2, sh2add_op:{ *:[i64] }:$rs1, 2:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_AddImm8, /*InsnID*/0, /*Imm*/2, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 62600, GIR_EraseRootFromParent_Done, // Label 189: @5196 GIM_Try, /*On fail goto*//*Label 190*/ GIMT_Encode4(5247), // Rule ID 62602 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:25:x GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:25:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh3add_op), // (add:{ *:[i64] } sh3add_op:{ *:[i64] }:$rs1:$pred:25:x, GPR:{ *:[i64] }:$rs2:$pred:25:y)<<P:25:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i64] } GPR:{ *:[i64] }:$rs2, sh3add_op:{ *:[i64] }:$rs1, 3:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 62602, GIR_EraseRootFromParent_Done, // Label 190: @5247 GIM_Try, /*On fail goto*//*Label 191*/ GIMT_Encode4(5295), // Rule ID 65148 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:2:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:2:x GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh1add_op), // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:2:y, sh1add_op:{ *:[i64] }:$rs1:$pred:2:x)<<P:2:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i64] } sh1add_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65148, GIR_EraseRootFromParent_Done, // Label 191: @5295 GIM_Try, /*On fail goto*//*Label 192*/ GIMT_Encode4(5343), // Rule ID 65156 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:4:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:4:x GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh2add_op), // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:4:y, sh2add_op:{ *:[i64] }:$rs1:$pred:4:x)<<P:4:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i64] } sh2add_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65156, GIR_EraseRootFromParent_Done, // Label 192: @5343 GIM_Try, /*On fail goto*//*Label 193*/ GIMT_Encode4(5391), // Rule ID 65164 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:6:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:6:x GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh3add_op), // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:6:y, sh3add_op:{ *:[i64] }:$rs1:$pred:6:x)<<P:6:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i64] } sh3add_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65164, GIR_EraseRootFromParent_Done, // Label 193: @5391 GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(5439), // Rule ID 65181 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:14:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:14:x GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh1add_uw_op), // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:14:y, sh1add_uw_op:{ *:[i64] }:$rs1:$pred:14:x)<<P:14:Predicate_add_like_non_imm12>> => (SH1ADD_UW:{ *:[i64] } sh1add_uw_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65181, GIR_EraseRootFromParent_Done, // Label 194: @5439 GIM_Try, /*On fail goto*//*Label 195*/ GIMT_Encode4(5487), // Rule ID 65183 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:15:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:15:x GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh2add_uw_op), // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:15:y, sh2add_uw_op:{ *:[i64] }:$rs1:$pred:15:x)<<P:15:Predicate_add_like_non_imm12>> => (SH2ADD_UW:{ *:[i64] } sh2add_uw_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65183, GIR_EraseRootFromParent_Done, // Label 195: @5487 GIM_Try, /*On fail goto*//*Label 196*/ GIMT_Encode4(5535), // Rule ID 65185 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:16:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:16:x GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh3add_uw_op), // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:16:y, sh3add_uw_op:{ *:[i64] }:$rs1:$pred:16:x)<<P:16:Predicate_add_like_non_imm12>> => (SH3ADD_UW:{ *:[i64] } sh3add_uw_op:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65185, GIR_EraseRootFromParent_Done, // Label 196: @5535 GIM_Try, /*On fail goto*//*Label 197*/ GIMT_Encode4(5586), // Rule ID 73670 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:23:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:23:x GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh1add_op), // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:23:y, sh1add_op:{ *:[i64] }:$rs1:$pred:23:x)<<P:23:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i64] } GPR:{ *:[i64] }:$rs2, sh1add_op:{ *:[i64] }:$rs1, 1:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_AddImm8, /*InsnID*/0, /*Imm*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73670, GIR_EraseRootFromParent_Done, // Label 197: @5586 GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(5637), // Rule ID 73672 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:24:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:24:x GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh2add_op), // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:24:y, sh2add_op:{ *:[i64] }:$rs1:$pred:24:x)<<P:24:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i64] } GPR:{ *:[i64] }:$rs2, sh2add_op:{ *:[i64] }:$rs1, 2:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_AddImm8, /*InsnID*/0, /*Imm*/2, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73672, GIR_EraseRootFromParent_Done, // Label 198: @5637 GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(5688), // Rule ID 73674 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:25:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:25:x GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_non_imm12), GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_sh3add_op), // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:25:y, sh3add_op:{ *:[i64] }:$rs1:$pred:25:x)<<P:25:Predicate_add_non_imm12>> => (TH_ADDSL:{ *:[i64] } GPR:{ *:[i64] }:$rs2, sh3add_op:{ *:[i64] }:$rs1, 3:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // rs1 GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73674, GIR_EraseRootFromParent_Done, // Label 199: @5688 GIM_Try, /*On fail goto*//*Label 200*/ GIMT_Encode4(5763), // Rule ID 2416 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:7:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967295), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:7:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }):$pred:7:x, GPR:{ *:[i64] }:$rs2:$pred:7:y)<<P:7:Predicate_add_like_non_imm12>> => (ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2416, GIR_EraseRootFromParent_Done, // Label 200: @5763 GIM_Try, /*On fail goto*//*Label 201*/ GIMT_Encode4(5858), // Rule ID 2440 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:17:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967294), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:17:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967294:{ *:[i64] }):$pred:17:x, GPR:{ *:[i64] }:$rs2:$pred:17:y)<<P:17:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i64] } (SRLIW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLIW), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_AddImm8, /*InsnID*/1, /*Imm*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2440, GIR_EraseRootFromParent_Done, // Label 201: @5858 GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(5953), // Rule ID 2442 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:18:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967292), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:18:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967292:{ *:[i64] }):$pred:18:x, GPR:{ *:[i64] }:$rs2:$pred:18:y)<<P:18:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i64] } (SRLIW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 2:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLIW), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_AddImm8, /*InsnID*/1, /*Imm*/2, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2442, GIR_EraseRootFromParent_Done, // Label 202: @5953 GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(6048), // Rule ID 2444 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:19:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967288), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:19:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967288:{ *:[i64] }):$pred:19:x, GPR:{ *:[i64] }:$rs2:$pred:19:y)<<P:19:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i64] } (SRLIW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 3:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLIW), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_AddImm8, /*InsnID*/1, /*Imm*/3, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2444, GIR_EraseRootFromParent_Done, // Label 203: @6048 GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(6143), // Rule ID 2446 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:20:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8589934590), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:20:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 8589934590:{ *:[i64] }):$pred:20:x, GPR:{ *:[i64] }:$rs2:$pred:20:y)<<P:20:Predicate_add_like_non_imm12>> => (SH1ADD_UW:{ *:[i64] } (SRLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLI), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_AddImm8, /*InsnID*/1, /*Imm*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2446, GIR_EraseRootFromParent_Done, // Label 204: @6143 GIM_Try, /*On fail goto*//*Label 205*/ GIMT_Encode4(6238), // Rule ID 2448 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:21:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(17179869180), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:21:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 17179869180:{ *:[i64] }):$pred:21:x, GPR:{ *:[i64] }:$rs2:$pred:21:y)<<P:21:Predicate_add_like_non_imm12>> => (SH2ADD_UW:{ *:[i64] } (SRLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 2:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLI), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_AddImm8, /*InsnID*/1, /*Imm*/2, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2448, GIR_EraseRootFromParent_Done, // Label 205: @6238 GIM_Try, /*On fail goto*//*Label 206*/ GIMT_Encode4(6333), // Rule ID 2450 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:22:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(34359738360), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:22:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 34359738360:{ *:[i64] }):$pred:22:x, GPR:{ *:[i64] }:$rs2:$pred:22:y)<<P:22:Predicate_add_like_non_imm12>> => (SH3ADD_UW:{ *:[i64] } (SRLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 3:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLI), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_AddImm8, /*InsnID*/1, /*Imm*/3, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2450, GIR_EraseRootFromParent_Done, // Label 206: @6333 GIM_Try, /*On fail goto*//*Label 207*/ GIMT_Encode4(6401), // Rule ID 2377 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:1:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:1:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] }):$pred:1:x, GPR:{ *:[i64] }:$rs2:$pred:1:y)<<P:1:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2377, GIR_EraseRootFromParent_Done, // Label 207: @6401 GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(6469), // Rule ID 2387 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:3:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:3:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 2:{ *:[i64] }):$pred:3:x, GPR:{ *:[i64] }:$rs2:$pred:3:y)<<P:3:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2387, GIR_EraseRootFromParent_Done, // Label 208: @6469 GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(6537), // Rule ID 2397 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:5:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:5:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 3:{ *:[i64] }):$pred:5:x, GPR:{ *:[i64] }:$rs2:$pred:5:y)<<P:5:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2397, GIR_EraseRootFromParent_Done, // Label 209: @6537 GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(6612), // Rule ID 65167 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:7:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:7:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967295), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:7:y, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }):$pred:7:x)<<P:7:Predicate_add_like_non_imm12>> => (ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65167, GIR_EraseRootFromParent_Done, // Label 210: @6612 GIM_Try, /*On fail goto*//*Label 211*/ GIMT_Encode4(6707), // Rule ID 65187 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:17:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:17:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967294), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:17:y, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967294:{ *:[i64] }):$pred:17:x)<<P:17:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i64] } (SRLIW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLIW), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_AddImm8, /*InsnID*/1, /*Imm*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65187, GIR_EraseRootFromParent_Done, // Label 211: @6707 GIM_Try, /*On fail goto*//*Label 212*/ GIMT_Encode4(6802), // Rule ID 65189 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:18:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:18:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967292), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:18:y, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967292:{ *:[i64] }):$pred:18:x)<<P:18:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i64] } (SRLIW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 2:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLIW), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_AddImm8, /*InsnID*/1, /*Imm*/2, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65189, GIR_EraseRootFromParent_Done, // Label 212: @6802 GIM_Try, /*On fail goto*//*Label 213*/ GIMT_Encode4(6897), // Rule ID 65191 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:19:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:19:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967288), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:19:y, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967288:{ *:[i64] }):$pred:19:x)<<P:19:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i64] } (SRLIW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 3:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLIW), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_AddImm8, /*InsnID*/1, /*Imm*/3, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65191, GIR_EraseRootFromParent_Done, // Label 213: @6897 GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(6992), // Rule ID 65193 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:20:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:20:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8589934590), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:20:y, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 8589934590:{ *:[i64] }):$pred:20:x)<<P:20:Predicate_add_like_non_imm12>> => (SH1ADD_UW:{ *:[i64] } (SRLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLI), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_AddImm8, /*InsnID*/1, /*Imm*/1, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65193, GIR_EraseRootFromParent_Done, // Label 214: @6992 GIM_Try, /*On fail goto*//*Label 215*/ GIMT_Encode4(7087), // Rule ID 65195 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:21:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:21:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(17179869180), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:21:y, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 17179869180:{ *:[i64] }):$pred:21:x)<<P:21:Predicate_add_like_non_imm12>> => (SH2ADD_UW:{ *:[i64] } (SRLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 2:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLI), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_AddImm8, /*InsnID*/1, /*Imm*/2, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65195, GIR_EraseRootFromParent_Done, // Label 215: @7087 GIM_Try, /*On fail goto*//*Label 216*/ GIMT_Encode4(7182), // Rule ID 65197 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:22:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:22:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(34359738360), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:22:y, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 34359738360:{ *:[i64] }):$pred:22:x)<<P:22:Predicate_add_like_non_imm12>> => (SH3ADD_UW:{ *:[i64] } (SRLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 3:{ *:[i64] }), GPR:{ *:[i64] }:$rs2) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLI), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_AddImm8, /*InsnID*/1, /*Imm*/3, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65197, GIR_EraseRootFromParent_Done, // Label 216: @7182 GIM_Try, /*On fail goto*//*Label 217*/ GIMT_Encode4(7250), // Rule ID 65144 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:1:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:1:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:1:y, (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] }):$pred:1:x)<<P:1:Predicate_add_like_non_imm12>> => (SH1ADD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH1ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65144, GIR_EraseRootFromParent_Done, // Label 217: @7250 GIM_Try, /*On fail goto*//*Label 218*/ GIMT_Encode4(7318), // Rule ID 65152 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:3:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:3:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:3:y, (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 2:{ *:[i64] }):$pred:3:x)<<P:3:Predicate_add_like_non_imm12>> => (SH2ADD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH2ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65152, GIR_EraseRootFromParent_Done, // Label 218: @7318 GIM_Try, /*On fail goto*//*Label 219*/ GIMT_Encode4(7386), // Rule ID 65160 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:5:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:5:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:5:y, (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 3:{ *:[i64] }):$pred:5:x)<<P:5:Predicate_add_like_non_imm12>> => (SH3ADD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SH3ADD), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65160, GIR_EraseRootFromParent_Done, // Label 219: @7386 GIM_Try, /*On fail goto*//*Label 220*/ GIMT_Encode4(7453), // Rule ID 73668 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm2), // MIs[2] Operand 1 // No operand predicates GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[i64] } (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs2, (imm:{ *:[i64] })<<P:Predicate_uimm2>>:$uimm2), GPR:{ *:[i64] }:$rs1) => (TH_ADDSL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, (imm:{ *:[i64] })<<P:Predicate_uimm2>>:$uimm2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // uimm2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73668, GIR_EraseRootFromParent_Done, // Label 220: @7453 GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(7520), // Rule ID 62594 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBa_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm2), // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/2, // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs2, (imm:{ *:[i64] })<<P:Predicate_uimm2>>:$uimm2)) => (TH_ADDSL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, (imm:{ *:[i64] })<<P:Predicate_uimm2>>:$uimm2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_ADDSL), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // uimm2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 62594, GIR_EraseRootFromParent_Done, // Label 221: @7520 GIM_Try, /*On fail goto*//*Label 222*/ GIMT_Encode4(7580), // Rule ID 64988 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:26:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:26:y GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } (zext:{ *:[i64] } GPR:{ *:[i32] }:$rs1):$pred:26:x, GPR:{ *:[i64] }:$rs2:$pred:26:y)<<P:26:Predicate_add_like_non_imm12>> => (ADD_UW:{ *:[i64] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64988, GIR_EraseRootFromParent_Done, // Label 222: @7580 GIM_Try, /*On fail goto*//*Label 223*/ GIMT_Encode4(7640), // Rule ID 73697 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:26:y GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:26:x GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_like_non_imm12), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs2:$pred:26:y, (zext:{ *:[i64] } GPR:{ *:[i32] }:$rs1):$pred:26:x)<<P:26:Predicate_add_like_non_imm12>> => (ADD_UW:{ *:[i64] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73697, GIR_EraseRootFromParent_Done, // Label 223: @7640 GIM_Try, /*On fail goto*//*Label 224*/ GIMT_Encode4(7682), // Rule ID 68 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm) => (ADDI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADDI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 68, GIR_EraseRootFromParent_Done, // Label 224: @7682 GIM_Try, /*On fail goto*//*Label 225*/ GIMT_Encode4(7743), // Rule ID 73676 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } (mul:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), GPR:{ *:[i64] }:$rd) => (TH_MULA:{ *:[i64] } GPR:{ *:[i64] }:$rd, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULA), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] GIR_RootToRootCopy, /*OpIdx*/2, // rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73676, GIR_EraseRootFromParent_Done, // Label 225: @7743 GIM_Try, /*On fail goto*//*Label 226*/ GIMT_Encode4(7804), // Rule ID 62654 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (add:{ *:[i64] } GPR:{ *:[i64] }:$rd, (mul:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)) => (TH_MULA:{ *:[i64] } GPR:{ *:[i64] }:$rd, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULA), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] GIR_RootToRootCopy, /*OpIdx*/1, // rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 62654, GIR_EraseRootFromParent_Done, // Label 226: @7804 GIM_Try, /*On fail goto*//*Label 227*/ GIMT_Encode4(7831), // Rule ID 66 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (ADD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::ADD), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 66, GIR_Done, // Label 227: @7831 GIM_Reject, // Label 169: @7832 GIM_Reject, // Label 102: @7833 GIM_Try, /*On fail goto*//*Label 228*/ GIMT_Encode4(7947), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 229*/ GIMT_Encode4(7901), // Rule ID 46132 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (add:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVADD_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46132, GIR_EraseRootFromParent_Done, // Label 229: @7901 GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(7946), // Rule ID 46133 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (add:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVADD_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46133, GIR_EraseRootFromParent_Done, // Label 230: @7946 GIM_Reject, // Label 228: @7947 GIM_Reject, // Label 103: @7948 GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(8062), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(8016), // Rule ID 46516 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (add:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVADD_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46516, GIR_EraseRootFromParent_Done, // Label 232: @8016 GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(8061), // Rule ID 46517 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (add:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVADD_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46517, GIR_EraseRootFromParent_Done, // Label 233: @8061 GIM_Reject, // Label 231: @8062 GIM_Reject, // Label 104: @8063 GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(8177), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(8131), // Rule ID 46524 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (add:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVADD_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46524, GIR_EraseRootFromParent_Done, // Label 235: @8131 GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(8176), // Rule ID 46525 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (add:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVADD_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46525, GIR_EraseRootFromParent_Done, // Label 236: @8176 GIM_Reject, // Label 234: @8177 GIM_Reject, // Label 105: @8178 GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(8292), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(8246), // Rule ID 46540 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (add:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVADD_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46540, GIR_EraseRootFromParent_Done, // Label 238: @8246 GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(8291), // Rule ID 46541 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (add:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVADD_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46541, GIR_EraseRootFromParent_Done, // Label 239: @8291 GIM_Reject, // Label 237: @8292 GIM_Reject, // Label 106: @8293 GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(8407), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 241*/ GIMT_Encode4(8361), // Rule ID 46508 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (add:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVADD_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46508, GIR_EraseRootFromParent_Done, // Label 241: @8361 GIM_Try, /*On fail goto*//*Label 242*/ GIMT_Encode4(8406), // Rule ID 46509 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (add:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVADD_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46509, GIR_EraseRootFromParent_Done, // Label 242: @8406 GIM_Reject, // Label 240: @8407 GIM_Reject, // Label 107: @8408 GIM_Try, /*On fail goto*//*Label 243*/ GIMT_Encode4(8522), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 244*/ GIMT_Encode4(8476), // Rule ID 46520 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (add:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVADD_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46520, GIR_EraseRootFromParent_Done, // Label 244: @8476 GIM_Try, /*On fail goto*//*Label 245*/ GIMT_Encode4(8521), // Rule ID 46521 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (add:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVADD_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46521, GIR_EraseRootFromParent_Done, // Label 245: @8521 GIM_Reject, // Label 243: @8522 GIM_Reject, // Label 108: @8523 GIM_Try, /*On fail goto*//*Label 246*/ GIMT_Encode4(8637), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 247*/ GIMT_Encode4(8591), // Rule ID 46536 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (add:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVADD_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46536, GIR_EraseRootFromParent_Done, // Label 247: @8591 GIM_Try, /*On fail goto*//*Label 248*/ GIMT_Encode4(8636), // Rule ID 46537 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (add:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVADD_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46537, GIR_EraseRootFromParent_Done, // Label 248: @8636 GIM_Reject, // Label 246: @8637 GIM_Reject, // Label 109: @8638 GIM_Try, /*On fail goto*//*Label 249*/ GIMT_Encode4(8752), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(8706), // Rule ID 46580 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (add:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVADD_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46580, GIR_EraseRootFromParent_Done, // Label 250: @8706 GIM_Try, /*On fail goto*//*Label 251*/ GIMT_Encode4(8751), // Rule ID 46581 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (add:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVADD_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46581, GIR_EraseRootFromParent_Done, // Label 251: @8751 GIM_Reject, // Label 249: @8752 GIM_Reject, // Label 110: @8753 GIM_Try, /*On fail goto*//*Label 252*/ GIMT_Encode4(8867), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 253*/ GIMT_Encode4(8821), // Rule ID 46512 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (add:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVADD_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46512, GIR_EraseRootFromParent_Done, // Label 253: @8821 GIM_Try, /*On fail goto*//*Label 254*/ GIMT_Encode4(8866), // Rule ID 46513 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (add:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVADD_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46513, GIR_EraseRootFromParent_Done, // Label 254: @8866 GIM_Reject, // Label 252: @8867 GIM_Reject, // Label 111: @8868 GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(8982), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(8936), // Rule ID 46532 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (add:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVADD_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46532, GIR_EraseRootFromParent_Done, // Label 256: @8936 GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(8981), // Rule ID 46533 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (add:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVADD_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46533, GIR_EraseRootFromParent_Done, // Label 257: @8981 GIM_Reject, // Label 255: @8982 GIM_Reject, // Label 112: @8983 GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(9097), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(9051), // Rule ID 46568 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (add:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVADD_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46568, GIR_EraseRootFromParent_Done, // Label 259: @9051 GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(9096), // Rule ID 46569 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (add:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVADD_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46569, GIR_EraseRootFromParent_Done, // Label 260: @9096 GIM_Reject, // Label 258: @9097 GIM_Reject, // Label 113: @9098 GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(9212), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(9166), // Rule ID 46584 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (add:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVADD_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46584, GIR_EraseRootFromParent_Done, // Label 262: @9166 GIM_Try, /*On fail goto*//*Label 263*/ GIMT_Encode4(9211), // Rule ID 46585 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (add:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVADD_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46585, GIR_EraseRootFromParent_Done, // Label 263: @9211 GIM_Reject, // Label 261: @9212 GIM_Reject, // Label 114: @9213 GIM_Try, /*On fail goto*//*Label 264*/ GIMT_Encode4(9327), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 265*/ GIMT_Encode4(9281), // Rule ID 46528 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (add:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVADD_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46528, GIR_EraseRootFromParent_Done, // Label 265: @9281 GIM_Try, /*On fail goto*//*Label 266*/ GIMT_Encode4(9326), // Rule ID 46529 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (add:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVADD_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46529, GIR_EraseRootFromParent_Done, // Label 266: @9326 GIM_Reject, // Label 264: @9327 GIM_Reject, // Label 115: @9328 GIM_Try, /*On fail goto*//*Label 267*/ GIMT_Encode4(9442), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 268*/ GIMT_Encode4(9396), // Rule ID 46556 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (add:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVADD_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46556, GIR_EraseRootFromParent_Done, // Label 268: @9396 GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(9441), // Rule ID 46557 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (add:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVADD_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46557, GIR_EraseRootFromParent_Done, // Label 269: @9441 GIM_Reject, // Label 267: @9442 GIM_Reject, // Label 116: @9443 GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(9557), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(9511), // Rule ID 46572 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (add:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVADD_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46572, GIR_EraseRootFromParent_Done, // Label 271: @9511 GIM_Try, /*On fail goto*//*Label 272*/ GIMT_Encode4(9556), // Rule ID 46573 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (add:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVADD_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46573, GIR_EraseRootFromParent_Done, // Label 272: @9556 GIM_Reject, // Label 270: @9557 GIM_Reject, // Label 117: @9558 GIM_Try, /*On fail goto*//*Label 273*/ GIMT_Encode4(9672), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(9626), // Rule ID 46588 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (add:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVADD_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46588, GIR_EraseRootFromParent_Done, // Label 274: @9626 GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(9671), // Rule ID 46589 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (add:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVADD_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46589, GIR_EraseRootFromParent_Done, // Label 275: @9671 GIM_Reject, // Label 273: @9672 GIM_Reject, // Label 118: @9673 GIM_Try, /*On fail goto*//*Label 276*/ GIMT_Encode4(9787), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 277*/ GIMT_Encode4(9741), // Rule ID 46544 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (add:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVADD_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46544, GIR_EraseRootFromParent_Done, // Label 277: @9741 GIM_Try, /*On fail goto*//*Label 278*/ GIMT_Encode4(9786), // Rule ID 46545 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (add:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVADD_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46545, GIR_EraseRootFromParent_Done, // Label 278: @9786 GIM_Reject, // Label 276: @9787 GIM_Reject, // Label 119: @9788 GIM_Try, /*On fail goto*//*Label 279*/ GIMT_Encode4(9902), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 280*/ GIMT_Encode4(9856), // Rule ID 46560 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (add:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVADD_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46560, GIR_EraseRootFromParent_Done, // Label 280: @9856 GIM_Try, /*On fail goto*//*Label 281*/ GIMT_Encode4(9901), // Rule ID 46561 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (add:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVADD_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46561, GIR_EraseRootFromParent_Done, // Label 281: @9901 GIM_Reject, // Label 279: @9902 GIM_Reject, // Label 120: @9903 GIM_Try, /*On fail goto*//*Label 282*/ GIMT_Encode4(10017), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 283*/ GIMT_Encode4(9971), // Rule ID 46576 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (add:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVADD_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46576, GIR_EraseRootFromParent_Done, // Label 283: @9971 GIM_Try, /*On fail goto*//*Label 284*/ GIMT_Encode4(10016), // Rule ID 46577 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (add:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVADD_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46577, GIR_EraseRootFromParent_Done, // Label 284: @10016 GIM_Reject, // Label 282: @10017 GIM_Reject, // Label 121: @10018 GIM_Try, /*On fail goto*//*Label 285*/ GIMT_Encode4(10132), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 286*/ GIMT_Encode4(10086), // Rule ID 46548 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (add:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVADD_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46548, GIR_EraseRootFromParent_Done, // Label 286: @10086 GIM_Try, /*On fail goto*//*Label 287*/ GIMT_Encode4(10131), // Rule ID 46549 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (add:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVADD_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46549, GIR_EraseRootFromParent_Done, // Label 287: @10131 GIM_Reject, // Label 285: @10132 GIM_Reject, // Label 122: @10133 GIM_Try, /*On fail goto*//*Label 288*/ GIMT_Encode4(10247), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(10201), // Rule ID 46564 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (add:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVADD_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46564, GIR_EraseRootFromParent_Done, // Label 289: @10201 GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(10246), // Rule ID 46565 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (add:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVADD_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46565, GIR_EraseRootFromParent_Done, // Label 290: @10246 GIM_Reject, // Label 288: @10247 GIM_Reject, // Label 123: @10248 GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(10362), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(10316), // Rule ID 46552 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (add:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVADD_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46552, GIR_EraseRootFromParent_Done, // Label 292: @10316 GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(10361), // Rule ID 46553 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (add:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVADD_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVADD_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46553, GIR_EraseRootFromParent_Done, // Label 293: @10361 GIM_Reject, // Label 291: @10362 GIM_Reject, // Label 124: @10363 GIM_Reject, // Label 1: @10364 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 318*/ GIMT_Encode4(13467), /*GILLT_s32*//*Label 294*/ GIMT_Encode4(10499), /*GILLT_s64*//*Label 295*/ GIMT_Encode4(10808), GIMT_Encode4(0), /*GILLT_nxv1s8*//*Label 296*/ GIMT_Encode4(10937), /*GILLT_nxv1s16*//*Label 297*/ GIMT_Encode4(11052), /*GILLT_nxv1s32*//*Label 298*/ GIMT_Encode4(11167), /*GILLT_nxv1s64*//*Label 299*/ GIMT_Encode4(11282), GIMT_Encode4(0), /*GILLT_nxv2s8*//*Label 300*/ GIMT_Encode4(11397), /*GILLT_nxv2s16*//*Label 301*/ GIMT_Encode4(11512), /*GILLT_nxv2s32*//*Label 302*/ GIMT_Encode4(11627), /*GILLT_nxv2s64*//*Label 303*/ GIMT_Encode4(11742), GIMT_Encode4(0), /*GILLT_nxv4s8*//*Label 304*/ GIMT_Encode4(11857), /*GILLT_nxv4s16*//*Label 305*/ GIMT_Encode4(11972), /*GILLT_nxv4s32*//*Label 306*/ GIMT_Encode4(12087), /*GILLT_nxv4s64*//*Label 307*/ GIMT_Encode4(12202), GIMT_Encode4(0), /*GILLT_nxv8s8*//*Label 308*/ GIMT_Encode4(12317), /*GILLT_nxv8s16*//*Label 309*/ GIMT_Encode4(12432), /*GILLT_nxv8s32*//*Label 310*/ GIMT_Encode4(12547), /*GILLT_nxv8s64*//*Label 311*/ GIMT_Encode4(12662), GIMT_Encode4(0), /*GILLT_nxv16s8*//*Label 312*/ GIMT_Encode4(12777), /*GILLT_nxv16s16*//*Label 313*/ GIMT_Encode4(12892), /*GILLT_nxv16s32*//*Label 314*/ GIMT_Encode4(13007), GIMT_Encode4(0), /*GILLT_nxv32s8*//*Label 315*/ GIMT_Encode4(13122), /*GILLT_nxv32s16*//*Label 316*/ GIMT_Encode4(13237), GIMT_Encode4(0), /*GILLT_nxv64s8*//*Label 317*/ GIMT_Encode4(13352), // Label 294: @10499 GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(10807), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(10554), // Rule ID 64598 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Plus1), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12Plus1>>:$imm) => (ADDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (NegImm:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_simm12Plus1>>:$imm)) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADDI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegImm), // imm GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64598, GIR_EraseRootFromParent_Done, // Label 320: @10554 GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(10590), // Rule ID 64599 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Plus1i32), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12Plus1i32>>:$imm) => (ADDIW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (NegImm:{ *:[i64] } ?:{ *:[i32] }:$imm)) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADDIW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegImm), // imm GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64599, GIR_EraseRootFromParent_Done, // Label 321: @10590 GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(10643), // Rule ID 62657 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_HwMode1), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[i32] } GPR:{ *:[i32] }:$rd, (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)) => (TH_MULS:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] GIR_RootToRootCopy, /*OpIdx*/1, // rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 62657, GIR_EraseRootFromParent_Done, // Label 322: @10643 GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(10696), // Rule ID 65056 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_IsRV64_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[i32] } GPR:{ *:[i32] }:$rd, (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)) => (TH_MULSW:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULSW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] GIR_RootToRootCopy, /*OpIdx*/1, // rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65056, GIR_EraseRootFromParent_Done, // Label 323: @10696 GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(10749), // Rule ID 65057 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_IsRV64_HwMode1), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[i32] } GPR:{ *:[i32] }:$rd, (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)) => (TH_MULSW:{ *:[i32] } GPR:{ *:[i32] }:$rd, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULSW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] GIR_RootToRootCopy, /*OpIdx*/1, // rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65057, GIR_EraseRootFromParent_Done, // Label 324: @10749 GIM_Try, /*On fail goto*//*Label 325*/ GIMT_Encode4(10768), // Rule ID 71 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), // (sub:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SUB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::SUB), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71, GIR_Done, // Label 325: @10768 GIM_Try, /*On fail goto*//*Label 326*/ GIMT_Encode4(10787), // Rule ID 64716 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), // (sub:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SUBW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::SUBW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64716, GIR_Done, // Label 326: @10787 GIM_Try, /*On fail goto*//*Label 327*/ GIMT_Encode4(10806), // Rule ID 64717 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), // (sub:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SUBW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::SUBW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64717, GIR_Done, // Label 327: @10806 GIM_Reject, // Label 319: @10807 GIM_Reject, // Label 295: @10808 GIM_Try, /*On fail goto*//*Label 328*/ GIMT_Encode4(10936), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(10863), // Rule ID 64597 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12Plus1), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12Plus1>>:$imm) => (ADDI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (NegImm:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_simm12Plus1>>:$imm)) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADDI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegImm), // imm GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64597, GIR_EraseRootFromParent_Done, // Label 329: @10863 GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(10916), // Rule ID 62656 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadMac_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (sub:{ *:[i64] } GPR:{ *:[i64] }:$rd, (mul:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)) => (TH_MULS:{ *:[i64] } GPR:{ *:[i64] }:$rd, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_MULS), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_wb] GIR_RootToRootCopy, /*OpIdx*/1, // rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 62656, GIR_EraseRootFromParent_Done, // Label 330: @10916 GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(10935), // Rule ID 70 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), // (sub:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (SUB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::SUB), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 70, GIR_Done, // Label 331: @10935 GIM_Reject, // Label 328: @10936 GIM_Reject, // Label 296: @10937 GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(11051), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 333*/ GIMT_Encode4(11005), // Rule ID 46634 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sub:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSUB_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46634, GIR_EraseRootFromParent_Done, // Label 333: @11005 GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(11050), // Rule ID 46635 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sub:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVSUB_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46635, GIR_EraseRootFromParent_Done, // Label 334: @11050 GIM_Reject, // Label 332: @11051 GIM_Reject, // Label 297: @11052 GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(11166), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(11120), // Rule ID 46646 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sub:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSUB_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46646, GIR_EraseRootFromParent_Done, // Label 336: @11120 GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(11165), // Rule ID 46647 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sub:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVSUB_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46647, GIR_EraseRootFromParent_Done, // Label 337: @11165 GIM_Reject, // Label 335: @11166 GIM_Reject, // Label 298: @11167 GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(11281), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(11235), // Rule ID 46654 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sub:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVSUB_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46654, GIR_EraseRootFromParent_Done, // Label 339: @11235 GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(11280), // Rule ID 46655 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sub:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVSUB_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46655, GIR_EraseRootFromParent_Done, // Label 340: @11280 GIM_Reject, // Label 338: @11281 GIM_Reject, // Label 299: @11282 GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(11396), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 342*/ GIMT_Encode4(11350), // Rule ID 46670 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (sub:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVSUB_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46670, GIR_EraseRootFromParent_Done, // Label 342: @11350 GIM_Try, /*On fail goto*//*Label 343*/ GIMT_Encode4(11395), // Rule ID 46671 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (sub:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVSUB_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46671, GIR_EraseRootFromParent_Done, // Label 343: @11395 GIM_Reject, // Label 341: @11396 GIM_Reject, // Label 300: @11397 GIM_Try, /*On fail goto*//*Label 344*/ GIMT_Encode4(11511), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 345*/ GIMT_Encode4(11465), // Rule ID 46638 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sub:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSUB_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46638, GIR_EraseRootFromParent_Done, // Label 345: @11465 GIM_Try, /*On fail goto*//*Label 346*/ GIMT_Encode4(11510), // Rule ID 46639 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sub:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVSUB_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46639, GIR_EraseRootFromParent_Done, // Label 346: @11510 GIM_Reject, // Label 344: @11511 GIM_Reject, // Label 301: @11512 GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(11626), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 348*/ GIMT_Encode4(11580), // Rule ID 46650 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sub:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSUB_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46650, GIR_EraseRootFromParent_Done, // Label 348: @11580 GIM_Try, /*On fail goto*//*Label 349*/ GIMT_Encode4(11625), // Rule ID 46651 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sub:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVSUB_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46651, GIR_EraseRootFromParent_Done, // Label 349: @11625 GIM_Reject, // Label 347: @11626 GIM_Reject, // Label 302: @11627 GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(11741), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(11695), // Rule ID 46666 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sub:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVSUB_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46666, GIR_EraseRootFromParent_Done, // Label 351: @11695 GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(11740), // Rule ID 46667 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sub:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVSUB_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46667, GIR_EraseRootFromParent_Done, // Label 352: @11740 GIM_Reject, // Label 350: @11741 GIM_Reject, // Label 303: @11742 GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(11856), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(11810), // Rule ID 46710 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (sub:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVSUB_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46710, GIR_EraseRootFromParent_Done, // Label 354: @11810 GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(11855), // Rule ID 46711 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (sub:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVSUB_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46711, GIR_EraseRootFromParent_Done, // Label 355: @11855 GIM_Reject, // Label 353: @11856 GIM_Reject, // Label 304: @11857 GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(11971), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(11925), // Rule ID 46642 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sub:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSUB_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46642, GIR_EraseRootFromParent_Done, // Label 357: @11925 GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(11970), // Rule ID 46643 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sub:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVSUB_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46643, GIR_EraseRootFromParent_Done, // Label 358: @11970 GIM_Reject, // Label 356: @11971 GIM_Reject, // Label 305: @11972 GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(12086), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(12040), // Rule ID 46662 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sub:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSUB_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46662, GIR_EraseRootFromParent_Done, // Label 360: @12040 GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(12085), // Rule ID 46663 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sub:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVSUB_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46663, GIR_EraseRootFromParent_Done, // Label 361: @12085 GIM_Reject, // Label 359: @12086 GIM_Reject, // Label 306: @12087 GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(12201), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(12155), // Rule ID 46698 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sub:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVSUB_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46698, GIR_EraseRootFromParent_Done, // Label 363: @12155 GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(12200), // Rule ID 46699 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sub:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVSUB_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46699, GIR_EraseRootFromParent_Done, // Label 364: @12200 GIM_Reject, // Label 362: @12201 GIM_Reject, // Label 307: @12202 GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(12316), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(12270), // Rule ID 46714 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (sub:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVSUB_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46714, GIR_EraseRootFromParent_Done, // Label 366: @12270 GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(12315), // Rule ID 46715 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (sub:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVSUB_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46715, GIR_EraseRootFromParent_Done, // Label 367: @12315 GIM_Reject, // Label 365: @12316 GIM_Reject, // Label 308: @12317 GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(12431), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(12385), // Rule ID 46658 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sub:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSUB_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46658, GIR_EraseRootFromParent_Done, // Label 369: @12385 GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(12430), // Rule ID 46659 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sub:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVSUB_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46659, GIR_EraseRootFromParent_Done, // Label 370: @12430 GIM_Reject, // Label 368: @12431 GIM_Reject, // Label 309: @12432 GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(12546), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(12500), // Rule ID 46686 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sub:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSUB_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46686, GIR_EraseRootFromParent_Done, // Label 372: @12500 GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(12545), // Rule ID 46687 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sub:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVSUB_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46687, GIR_EraseRootFromParent_Done, // Label 373: @12545 GIM_Reject, // Label 371: @12546 GIM_Reject, // Label 310: @12547 GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(12661), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(12615), // Rule ID 46702 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sub:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVSUB_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46702, GIR_EraseRootFromParent_Done, // Label 375: @12615 GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(12660), // Rule ID 46703 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sub:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVSUB_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46703, GIR_EraseRootFromParent_Done, // Label 376: @12660 GIM_Reject, // Label 374: @12661 GIM_Reject, // Label 311: @12662 GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(12776), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(12730), // Rule ID 46718 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (sub:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVSUB_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46718, GIR_EraseRootFromParent_Done, // Label 378: @12730 GIM_Try, /*On fail goto*//*Label 379*/ GIMT_Encode4(12775), // Rule ID 46719 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (sub:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVSUB_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46719, GIR_EraseRootFromParent_Done, // Label 379: @12775 GIM_Reject, // Label 377: @12776 GIM_Reject, // Label 312: @12777 GIM_Try, /*On fail goto*//*Label 380*/ GIMT_Encode4(12891), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 381*/ GIMT_Encode4(12845), // Rule ID 46674 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sub:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSUB_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46674, GIR_EraseRootFromParent_Done, // Label 381: @12845 GIM_Try, /*On fail goto*//*Label 382*/ GIMT_Encode4(12890), // Rule ID 46675 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sub:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVSUB_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46675, GIR_EraseRootFromParent_Done, // Label 382: @12890 GIM_Reject, // Label 380: @12891 GIM_Reject, // Label 313: @12892 GIM_Try, /*On fail goto*//*Label 383*/ GIMT_Encode4(13006), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 384*/ GIMT_Encode4(12960), // Rule ID 46690 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sub:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVSUB_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46690, GIR_EraseRootFromParent_Done, // Label 384: @12960 GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(13005), // Rule ID 46691 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sub:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVSUB_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46691, GIR_EraseRootFromParent_Done, // Label 385: @13005 GIM_Reject, // Label 383: @13006 GIM_Reject, // Label 314: @13007 GIM_Try, /*On fail goto*//*Label 386*/ GIMT_Encode4(13121), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 387*/ GIMT_Encode4(13075), // Rule ID 46706 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sub:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVSUB_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46706, GIR_EraseRootFromParent_Done, // Label 387: @13075 GIM_Try, /*On fail goto*//*Label 388*/ GIMT_Encode4(13120), // Rule ID 46707 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sub:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVSUB_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46707, GIR_EraseRootFromParent_Done, // Label 388: @13120 GIM_Reject, // Label 386: @13121 GIM_Reject, // Label 315: @13122 GIM_Try, /*On fail goto*//*Label 389*/ GIMT_Encode4(13236), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 390*/ GIMT_Encode4(13190), // Rule ID 46678 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sub:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVSUB_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46678, GIR_EraseRootFromParent_Done, // Label 390: @13190 GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(13235), // Rule ID 46679 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sub:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVSUB_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46679, GIR_EraseRootFromParent_Done, // Label 391: @13235 GIM_Reject, // Label 389: @13236 GIM_Reject, // Label 316: @13237 GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(13351), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 393*/ GIMT_Encode4(13305), // Rule ID 46694 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sub:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVSUB_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46694, GIR_EraseRootFromParent_Done, // Label 393: @13305 GIM_Try, /*On fail goto*//*Label 394*/ GIMT_Encode4(13350), // Rule ID 46695 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sub:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVSUB_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46695, GIR_EraseRootFromParent_Done, // Label 394: @13350 GIM_Reject, // Label 392: @13351 GIM_Reject, // Label 317: @13352 GIM_Try, /*On fail goto*//*Label 395*/ GIMT_Encode4(13466), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 396*/ GIMT_Encode4(13420), // Rule ID 46682 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sub:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVSUB_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46682, GIR_EraseRootFromParent_Done, // Label 396: @13420 GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(13465), // Rule ID 46683 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sub:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVSUB_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVSUB_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 46683, GIR_EraseRootFromParent_Done, // Label 397: @13465 GIM_Reject, // Label 395: @13466 GIM_Reject, // Label 318: @13467 GIM_Reject, // Label 2: @13468 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 422*/ GIMT_Encode4(16372), /*GILLT_s32*//*Label 398*/ GIMT_Encode4(13603), /*GILLT_s64*//*Label 399*/ GIMT_Encode4(13673), GIMT_Encode4(0), /*GILLT_nxv1s8*//*Label 400*/ GIMT_Encode4(13842), /*GILLT_nxv1s16*//*Label 401*/ GIMT_Encode4(13957), /*GILLT_nxv1s32*//*Label 402*/ GIMT_Encode4(14072), /*GILLT_nxv1s64*//*Label 403*/ GIMT_Encode4(14187), GIMT_Encode4(0), /*GILLT_nxv2s8*//*Label 404*/ GIMT_Encode4(14302), /*GILLT_nxv2s16*//*Label 405*/ GIMT_Encode4(14417), /*GILLT_nxv2s32*//*Label 406*/ GIMT_Encode4(14532), /*GILLT_nxv2s64*//*Label 407*/ GIMT_Encode4(14647), GIMT_Encode4(0), /*GILLT_nxv4s8*//*Label 408*/ GIMT_Encode4(14762), /*GILLT_nxv4s16*//*Label 409*/ GIMT_Encode4(14877), /*GILLT_nxv4s32*//*Label 410*/ GIMT_Encode4(14992), /*GILLT_nxv4s64*//*Label 411*/ GIMT_Encode4(15107), GIMT_Encode4(0), /*GILLT_nxv8s8*//*Label 412*/ GIMT_Encode4(15222), /*GILLT_nxv8s16*//*Label 413*/ GIMT_Encode4(15337), /*GILLT_nxv8s32*//*Label 414*/ GIMT_Encode4(15452), /*GILLT_nxv8s64*//*Label 415*/ GIMT_Encode4(15567), GIMT_Encode4(0), /*GILLT_nxv16s8*//*Label 416*/ GIMT_Encode4(15682), /*GILLT_nxv16s16*//*Label 417*/ GIMT_Encode4(15797), /*GILLT_nxv16s32*//*Label 418*/ GIMT_Encode4(15912), GIMT_Encode4(0), /*GILLT_nxv32s8*//*Label 419*/ GIMT_Encode4(16027), /*GILLT_nxv32s16*//*Label 420*/ GIMT_Encode4(16142), GIMT_Encode4(0), /*GILLT_nxv64s8*//*Label 421*/ GIMT_Encode4(16257), // Label 398: @13603 GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(13672), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_Try, /*On fail goto*//*Label 424*/ GIMT_Encode4(13641), // Rule ID 276 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZmmul_HwMode1), // (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MUL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::MUL), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 276, GIR_Done, // Label 424: @13641 GIM_Try, /*On fail goto*//*Label 425*/ GIMT_Encode4(13656), // Rule ID 64741 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZmmul_IsRV64_HwMode0), // (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MULW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::MULW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64741, GIR_Done, // Label 425: @13656 GIM_Try, /*On fail goto*//*Label 426*/ GIMT_Encode4(13671), // Rule ID 64742 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZmmul_IsRV64_HwMode1), // (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MULW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::MULW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64742, GIR_Done, // Label 426: @13671 GIM_Reject, // Label 423: @13672 GIM_Reject, // Label 399: @13673 GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(13841), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(13817), // Rule ID 298 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZmmul_IsRV64_NotHasStdExtZba_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967295), GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294967295), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (mul:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), (and:{ *:[i64] } GPR:{ *:[i64] }:$rs2, 4294967295:{ *:[i64] })) => (MULHU:{ *:[i64] } (SLLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 32:{ *:[i64] }), (SLLI:{ *:[i64] } GPR:{ *:[i64] }:$rs2, 32:{ *:[i64] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(RISCV::SLLI), GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // rs2 GIR_AddImm8, /*InsnID*/2, /*Imm*/32, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLLI), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_AddImm8, /*InsnID*/1, /*Imm*/32, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::MULHU), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 298, GIR_EraseRootFromParent_Done, // Label 428: @13817 GIM_Try, /*On fail goto*//*Label 429*/ GIMT_Encode4(13840), // Rule ID 275 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZmmul_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), // (mul:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (MUL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::MUL), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 275, GIR_Done, // Label 429: @13840 GIM_Reject, // Label 427: @13841 GIM_Reject, // Label 400: @13842 GIM_Try, /*On fail goto*//*Label 430*/ GIMT_Encode4(13956), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 431*/ GIMT_Encode4(13910), // Rule ID 51038 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (mul:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVMUL_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51038, GIR_EraseRootFromParent_Done, // Label 431: @13910 GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(13955), // Rule ID 51039 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (mul:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVMUL_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51039, GIR_EraseRootFromParent_Done, // Label 432: @13955 GIM_Reject, // Label 430: @13956 GIM_Reject, // Label 401: @13957 GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(14071), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 434*/ GIMT_Encode4(14025), // Rule ID 51050 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (mul:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVMUL_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51050, GIR_EraseRootFromParent_Done, // Label 434: @14025 GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(14070), // Rule ID 51051 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (mul:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVMUL_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51051, GIR_EraseRootFromParent_Done, // Label 435: @14070 GIM_Reject, // Label 433: @14071 GIM_Reject, // Label 402: @14072 GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(14186), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 437*/ GIMT_Encode4(14140), // Rule ID 51058 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (mul:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVMUL_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51058, GIR_EraseRootFromParent_Done, // Label 437: @14140 GIM_Try, /*On fail goto*//*Label 438*/ GIMT_Encode4(14185), // Rule ID 51059 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (mul:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVMUL_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51059, GIR_EraseRootFromParent_Done, // Label 438: @14185 GIM_Reject, // Label 436: @14186 GIM_Reject, // Label 403: @14187 GIM_Try, /*On fail goto*//*Label 439*/ GIMT_Encode4(14301), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(14255), // Rule ID 51074 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (mul:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVMUL_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51074, GIR_EraseRootFromParent_Done, // Label 440: @14255 GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(14300), // Rule ID 51075 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (mul:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVMUL_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51075, GIR_EraseRootFromParent_Done, // Label 441: @14300 GIM_Reject, // Label 439: @14301 GIM_Reject, // Label 404: @14302 GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(14416), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(14370), // Rule ID 51042 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (mul:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVMUL_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51042, GIR_EraseRootFromParent_Done, // Label 443: @14370 GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(14415), // Rule ID 51043 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (mul:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVMUL_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51043, GIR_EraseRootFromParent_Done, // Label 444: @14415 GIM_Reject, // Label 442: @14416 GIM_Reject, // Label 405: @14417 GIM_Try, /*On fail goto*//*Label 445*/ GIMT_Encode4(14531), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(14485), // Rule ID 51054 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (mul:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVMUL_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51054, GIR_EraseRootFromParent_Done, // Label 446: @14485 GIM_Try, /*On fail goto*//*Label 447*/ GIMT_Encode4(14530), // Rule ID 51055 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (mul:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVMUL_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51055, GIR_EraseRootFromParent_Done, // Label 447: @14530 GIM_Reject, // Label 445: @14531 GIM_Reject, // Label 406: @14532 GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(14646), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(14600), // Rule ID 51070 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (mul:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVMUL_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51070, GIR_EraseRootFromParent_Done, // Label 449: @14600 GIM_Try, /*On fail goto*//*Label 450*/ GIMT_Encode4(14645), // Rule ID 51071 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (mul:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVMUL_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51071, GIR_EraseRootFromParent_Done, // Label 450: @14645 GIM_Reject, // Label 448: @14646 GIM_Reject, // Label 407: @14647 GIM_Try, /*On fail goto*//*Label 451*/ GIMT_Encode4(14761), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(14715), // Rule ID 51114 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (mul:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVMUL_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51114, GIR_EraseRootFromParent_Done, // Label 452: @14715 GIM_Try, /*On fail goto*//*Label 453*/ GIMT_Encode4(14760), // Rule ID 51115 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (mul:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVMUL_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51115, GIR_EraseRootFromParent_Done, // Label 453: @14760 GIM_Reject, // Label 451: @14761 GIM_Reject, // Label 408: @14762 GIM_Try, /*On fail goto*//*Label 454*/ GIMT_Encode4(14876), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 455*/ GIMT_Encode4(14830), // Rule ID 51046 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (mul:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVMUL_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51046, GIR_EraseRootFromParent_Done, // Label 455: @14830 GIM_Try, /*On fail goto*//*Label 456*/ GIMT_Encode4(14875), // Rule ID 51047 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (mul:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVMUL_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51047, GIR_EraseRootFromParent_Done, // Label 456: @14875 GIM_Reject, // Label 454: @14876 GIM_Reject, // Label 409: @14877 GIM_Try, /*On fail goto*//*Label 457*/ GIMT_Encode4(14991), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 458*/ GIMT_Encode4(14945), // Rule ID 51066 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (mul:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVMUL_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51066, GIR_EraseRootFromParent_Done, // Label 458: @14945 GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(14990), // Rule ID 51067 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (mul:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVMUL_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51067, GIR_EraseRootFromParent_Done, // Label 459: @14990 GIM_Reject, // Label 457: @14991 GIM_Reject, // Label 410: @14992 GIM_Try, /*On fail goto*//*Label 460*/ GIMT_Encode4(15106), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 461*/ GIMT_Encode4(15060), // Rule ID 51102 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (mul:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVMUL_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51102, GIR_EraseRootFromParent_Done, // Label 461: @15060 GIM_Try, /*On fail goto*//*Label 462*/ GIMT_Encode4(15105), // Rule ID 51103 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (mul:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVMUL_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51103, GIR_EraseRootFromParent_Done, // Label 462: @15105 GIM_Reject, // Label 460: @15106 GIM_Reject, // Label 411: @15107 GIM_Try, /*On fail goto*//*Label 463*/ GIMT_Encode4(15221), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 464*/ GIMT_Encode4(15175), // Rule ID 51118 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (mul:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVMUL_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51118, GIR_EraseRootFromParent_Done, // Label 464: @15175 GIM_Try, /*On fail goto*//*Label 465*/ GIMT_Encode4(15220), // Rule ID 51119 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (mul:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVMUL_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51119, GIR_EraseRootFromParent_Done, // Label 465: @15220 GIM_Reject, // Label 463: @15221 GIM_Reject, // Label 412: @15222 GIM_Try, /*On fail goto*//*Label 466*/ GIMT_Encode4(15336), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 467*/ GIMT_Encode4(15290), // Rule ID 51062 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (mul:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVMUL_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51062, GIR_EraseRootFromParent_Done, // Label 467: @15290 GIM_Try, /*On fail goto*//*Label 468*/ GIMT_Encode4(15335), // Rule ID 51063 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (mul:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVMUL_VV_M1:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51063, GIR_EraseRootFromParent_Done, // Label 468: @15335 GIM_Reject, // Label 466: @15336 GIM_Reject, // Label 413: @15337 GIM_Try, /*On fail goto*//*Label 469*/ GIMT_Encode4(15451), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 470*/ GIMT_Encode4(15405), // Rule ID 51090 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (mul:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVMUL_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51090, GIR_EraseRootFromParent_Done, // Label 470: @15405 GIM_Try, /*On fail goto*//*Label 471*/ GIMT_Encode4(15450), // Rule ID 51091 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (mul:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVMUL_VV_M2:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51091, GIR_EraseRootFromParent_Done, // Label 471: @15450 GIM_Reject, // Label 469: @15451 GIM_Reject, // Label 414: @15452 GIM_Try, /*On fail goto*//*Label 472*/ GIMT_Encode4(15566), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 473*/ GIMT_Encode4(15520), // Rule ID 51106 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (mul:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVMUL_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51106, GIR_EraseRootFromParent_Done, // Label 473: @15520 GIM_Try, /*On fail goto*//*Label 474*/ GIMT_Encode4(15565), // Rule ID 51107 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (mul:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVMUL_VV_M4:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51107, GIR_EraseRootFromParent_Done, // Label 474: @15565 GIM_Reject, // Label 472: @15566 GIM_Reject, // Label 415: @15567 GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(15681), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(15635), // Rule ID 51122 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (mul:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVMUL_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51122, GIR_EraseRootFromParent_Done, // Label 476: @15635 GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(15680), // Rule ID 51123 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (mul:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVMUL_VV_M8:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51123, GIR_EraseRootFromParent_Done, // Label 477: @15680 GIM_Reject, // Label 475: @15681 GIM_Reject, // Label 416: @15682 GIM_Try, /*On fail goto*//*Label 478*/ GIMT_Encode4(15796), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 479*/ GIMT_Encode4(15750), // Rule ID 51078 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (mul:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVMUL_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51078, GIR_EraseRootFromParent_Done, // Label 479: @15750 GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(15795), // Rule ID 51079 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (mul:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVMUL_VV_M2:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51079, GIR_EraseRootFromParent_Done, // Label 480: @15795 GIM_Reject, // Label 478: @15796 GIM_Reject, // Label 417: @15797 GIM_Try, /*On fail goto*//*Label 481*/ GIMT_Encode4(15911), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 482*/ GIMT_Encode4(15865), // Rule ID 51094 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (mul:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVMUL_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51094, GIR_EraseRootFromParent_Done, // Label 482: @15865 GIM_Try, /*On fail goto*//*Label 483*/ GIMT_Encode4(15910), // Rule ID 51095 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (mul:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVMUL_VV_M4:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51095, GIR_EraseRootFromParent_Done, // Label 483: @15910 GIM_Reject, // Label 481: @15911 GIM_Reject, // Label 418: @15912 GIM_Try, /*On fail goto*//*Label 484*/ GIMT_Encode4(16026), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 485*/ GIMT_Encode4(15980), // Rule ID 51110 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (mul:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVMUL_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51110, GIR_EraseRootFromParent_Done, // Label 485: @15980 GIM_Try, /*On fail goto*//*Label 486*/ GIMT_Encode4(16025), // Rule ID 51111 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (mul:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVMUL_VV_M8:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51111, GIR_EraseRootFromParent_Done, // Label 486: @16025 GIM_Reject, // Label 484: @16026 GIM_Reject, // Label 419: @16027 GIM_Try, /*On fail goto*//*Label 487*/ GIMT_Encode4(16141), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 488*/ GIMT_Encode4(16095), // Rule ID 51082 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (mul:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVMUL_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51082, GIR_EraseRootFromParent_Done, // Label 488: @16095 GIM_Try, /*On fail goto*//*Label 489*/ GIMT_Encode4(16140), // Rule ID 51083 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (mul:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVMUL_VV_M4:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51083, GIR_EraseRootFromParent_Done, // Label 489: @16140 GIM_Reject, // Label 487: @16141 GIM_Reject, // Label 420: @16142 GIM_Try, /*On fail goto*//*Label 490*/ GIMT_Encode4(16256), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(16210), // Rule ID 51098 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (mul:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVMUL_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51098, GIR_EraseRootFromParent_Done, // Label 491: @16210 GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(16255), // Rule ID 51099 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (mul:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVMUL_VV_M8:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51099, GIR_EraseRootFromParent_Done, // Label 492: @16255 GIM_Reject, // Label 490: @16256 GIM_Reject, // Label 421: @16257 GIM_Try, /*On fail goto*//*Label 493*/ GIMT_Encode4(16371), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 494*/ GIMT_Encode4(16325), // Rule ID 51086 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (mul:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVMUL_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51086, GIR_EraseRootFromParent_Done, // Label 494: @16325 GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(16370), // Rule ID 51087 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (mul:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVMUL_VV_M8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMUL_VV_M8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51087, GIR_EraseRootFromParent_Done, // Label 495: @16370 GIM_Reject, // Label 493: @16371 GIM_Reject, // Label 422: @16372 GIM_Reject, // Label 3: @16373 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 520*/ GIMT_Encode4(19142), /*GILLT_s32*//*Label 496*/ GIMT_Encode4(16508), /*GILLT_s64*//*Label 497*/ GIMT_Encode4(16578), GIMT_Encode4(0), /*GILLT_nxv1s8*//*Label 498*/ GIMT_Encode4(16612), /*GILLT_nxv1s16*//*Label 499*/ GIMT_Encode4(16727), /*GILLT_nxv1s32*//*Label 500*/ GIMT_Encode4(16842), /*GILLT_nxv1s64*//*Label 501*/ GIMT_Encode4(16957), GIMT_Encode4(0), /*GILLT_nxv2s8*//*Label 502*/ GIMT_Encode4(17072), /*GILLT_nxv2s16*//*Label 503*/ GIMT_Encode4(17187), /*GILLT_nxv2s32*//*Label 504*/ GIMT_Encode4(17302), /*GILLT_nxv2s64*//*Label 505*/ GIMT_Encode4(17417), GIMT_Encode4(0), /*GILLT_nxv4s8*//*Label 506*/ GIMT_Encode4(17532), /*GILLT_nxv4s16*//*Label 507*/ GIMT_Encode4(17647), /*GILLT_nxv4s32*//*Label 508*/ GIMT_Encode4(17762), /*GILLT_nxv4s64*//*Label 509*/ GIMT_Encode4(17877), GIMT_Encode4(0), /*GILLT_nxv8s8*//*Label 510*/ GIMT_Encode4(17992), /*GILLT_nxv8s16*//*Label 511*/ GIMT_Encode4(18107), /*GILLT_nxv8s32*//*Label 512*/ GIMT_Encode4(18222), /*GILLT_nxv8s64*//*Label 513*/ GIMT_Encode4(18337), GIMT_Encode4(0), /*GILLT_nxv16s8*//*Label 514*/ GIMT_Encode4(18452), /*GILLT_nxv16s16*//*Label 515*/ GIMT_Encode4(18567), /*GILLT_nxv16s32*//*Label 516*/ GIMT_Encode4(18682), GIMT_Encode4(0), /*GILLT_nxv32s8*//*Label 517*/ GIMT_Encode4(18797), /*GILLT_nxv32s16*//*Label 518*/ GIMT_Encode4(18912), GIMT_Encode4(0), /*GILLT_nxv64s8*//*Label 519*/ GIMT_Encode4(19027), // Label 496: @16508 GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(16577), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(16546), // Rule ID 284 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_HwMode1), // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (DIV:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::DIV), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 284, GIR_Done, // Label 522: @16546 GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(16561), // Rule ID 64743 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_IsRV64_HwMode0), // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (DIVW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::DIVW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64743, GIR_Done, // Label 523: @16561 GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(16576), // Rule ID 64744 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_IsRV64_HwMode1), // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (DIVW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::DIVW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64744, GIR_Done, // Label 524: @16576 GIM_Reject, // Label 521: @16577 GIM_Reject, // Label 497: @16578 GIM_Try, /*On fail goto*//*Label 525*/ GIMT_Encode4(16611), // Rule ID 283 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_HwMode0), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), // (sdiv:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (DIV:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::DIV), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 283, GIR_Done, // Label 525: @16611 GIM_Reject, // Label 498: @16612 GIM_Try, /*On fail goto*//*Label 526*/ GIMT_Encode4(16726), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 527*/ GIMT_Encode4(16680), // Rule ID 51390 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sdiv:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVDIV_VV_MF8_E8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF8_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51390, GIR_EraseRootFromParent_Done, // Label 527: @16680 GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(16725), // Rule ID 51391 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sdiv:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVDIV_VV_MF8_E8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF8_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51391, GIR_EraseRootFromParent_Done, // Label 528: @16725 GIM_Reject, // Label 526: @16726 GIM_Reject, // Label 499: @16727 GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(16841), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 530*/ GIMT_Encode4(16795), // Rule ID 51402 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sdiv:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVDIV_VV_MF4_E16:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF4_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51402, GIR_EraseRootFromParent_Done, // Label 530: @16795 GIM_Try, /*On fail goto*//*Label 531*/ GIMT_Encode4(16840), // Rule ID 51403 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sdiv:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVDIV_VV_MF4_E16:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF4_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51403, GIR_EraseRootFromParent_Done, // Label 531: @16840 GIM_Reject, // Label 529: @16841 GIM_Reject, // Label 500: @16842 GIM_Try, /*On fail goto*//*Label 532*/ GIMT_Encode4(16956), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 533*/ GIMT_Encode4(16910), // Rule ID 51410 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sdiv:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVDIV_VV_MF2_E32:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF2_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51410, GIR_EraseRootFromParent_Done, // Label 533: @16910 GIM_Try, /*On fail goto*//*Label 534*/ GIMT_Encode4(16955), // Rule ID 51411 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sdiv:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVDIV_VV_MF2_E32:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF2_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51411, GIR_EraseRootFromParent_Done, // Label 534: @16955 GIM_Reject, // Label 532: @16956 GIM_Reject, // Label 501: @16957 GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(17071), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 536*/ GIMT_Encode4(17025), // Rule ID 51426 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (sdiv:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVDIV_VV_M1_E64:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M1_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51426, GIR_EraseRootFromParent_Done, // Label 536: @17025 GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(17070), // Rule ID 51427 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (sdiv:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVDIV_VV_M1_E64:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M1_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51427, GIR_EraseRootFromParent_Done, // Label 537: @17070 GIM_Reject, // Label 535: @17071 GIM_Reject, // Label 502: @17072 GIM_Try, /*On fail goto*//*Label 538*/ GIMT_Encode4(17186), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 539*/ GIMT_Encode4(17140), // Rule ID 51394 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sdiv:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVDIV_VV_MF4_E8:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF4_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51394, GIR_EraseRootFromParent_Done, // Label 539: @17140 GIM_Try, /*On fail goto*//*Label 540*/ GIMT_Encode4(17185), // Rule ID 51395 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sdiv:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVDIV_VV_MF4_E8:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF4_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51395, GIR_EraseRootFromParent_Done, // Label 540: @17185 GIM_Reject, // Label 538: @17186 GIM_Reject, // Label 503: @17187 GIM_Try, /*On fail goto*//*Label 541*/ GIMT_Encode4(17301), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 542*/ GIMT_Encode4(17255), // Rule ID 51406 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sdiv:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVDIV_VV_MF2_E16:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF2_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51406, GIR_EraseRootFromParent_Done, // Label 542: @17255 GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(17300), // Rule ID 51407 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sdiv:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVDIV_VV_MF2_E16:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF2_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51407, GIR_EraseRootFromParent_Done, // Label 543: @17300 GIM_Reject, // Label 541: @17301 GIM_Reject, // Label 504: @17302 GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(17416), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(17370), // Rule ID 51422 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sdiv:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVDIV_VV_M1_E32:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M1_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51422, GIR_EraseRootFromParent_Done, // Label 545: @17370 GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(17415), // Rule ID 51423 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sdiv:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVDIV_VV_M1_E32:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M1_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51423, GIR_EraseRootFromParent_Done, // Label 546: @17415 GIM_Reject, // Label 544: @17416 GIM_Reject, // Label 505: @17417 GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(17531), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(17485), // Rule ID 51466 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (sdiv:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVDIV_VV_M2_E64:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M2_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51466, GIR_EraseRootFromParent_Done, // Label 548: @17485 GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(17530), // Rule ID 51467 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (sdiv:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVDIV_VV_M2_E64:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M2_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51467, GIR_EraseRootFromParent_Done, // Label 549: @17530 GIM_Reject, // Label 547: @17531 GIM_Reject, // Label 506: @17532 GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(17646), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(17600), // Rule ID 51398 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sdiv:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVDIV_VV_MF2_E8:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF2_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51398, GIR_EraseRootFromParent_Done, // Label 551: @17600 GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(17645), // Rule ID 51399 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sdiv:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVDIV_VV_MF2_E8:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_MF2_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51399, GIR_EraseRootFromParent_Done, // Label 552: @17645 GIM_Reject, // Label 550: @17646 GIM_Reject, // Label 507: @17647 GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(17761), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(17715), // Rule ID 51418 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sdiv:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVDIV_VV_M1_E16:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M1_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51418, GIR_EraseRootFromParent_Done, // Label 554: @17715 GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(17760), // Rule ID 51419 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sdiv:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVDIV_VV_M1_E16:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M1_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51419, GIR_EraseRootFromParent_Done, // Label 555: @17760 GIM_Reject, // Label 553: @17761 GIM_Reject, // Label 508: @17762 GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(17876), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(17830), // Rule ID 51454 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sdiv:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVDIV_VV_M2_E32:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M2_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51454, GIR_EraseRootFromParent_Done, // Label 557: @17830 GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(17875), // Rule ID 51455 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sdiv:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVDIV_VV_M2_E32:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M2_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51455, GIR_EraseRootFromParent_Done, // Label 558: @17875 GIM_Reject, // Label 556: @17876 GIM_Reject, // Label 509: @17877 GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(17991), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(17945), // Rule ID 51470 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (sdiv:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVDIV_VV_M4_E64:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M4_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51470, GIR_EraseRootFromParent_Done, // Label 560: @17945 GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(17990), // Rule ID 51471 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (sdiv:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVDIV_VV_M4_E64:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M4_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51471, GIR_EraseRootFromParent_Done, // Label 561: @17990 GIM_Reject, // Label 559: @17991 GIM_Reject, // Label 510: @17992 GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(18106), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(18060), // Rule ID 51414 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sdiv:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVDIV_VV_M1_E8:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M1_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51414, GIR_EraseRootFromParent_Done, // Label 563: @18060 GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(18105), // Rule ID 51415 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sdiv:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVDIV_VV_M1_E8:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M1_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51415, GIR_EraseRootFromParent_Done, // Label 564: @18105 GIM_Reject, // Label 562: @18106 GIM_Reject, // Label 511: @18107 GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(18221), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(18175), // Rule ID 51442 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sdiv:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVDIV_VV_M2_E16:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M2_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51442, GIR_EraseRootFromParent_Done, // Label 566: @18175 GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(18220), // Rule ID 51443 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sdiv:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVDIV_VV_M2_E16:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M2_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51443, GIR_EraseRootFromParent_Done, // Label 567: @18220 GIM_Reject, // Label 565: @18221 GIM_Reject, // Label 512: @18222 GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(18336), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(18290), // Rule ID 51458 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sdiv:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVDIV_VV_M4_E32:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M4_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51458, GIR_EraseRootFromParent_Done, // Label 569: @18290 GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(18335), // Rule ID 51459 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sdiv:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVDIV_VV_M4_E32:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M4_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51459, GIR_EraseRootFromParent_Done, // Label 570: @18335 GIM_Reject, // Label 568: @18336 GIM_Reject, // Label 513: @18337 GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(18451), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(18405), // Rule ID 51474 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (sdiv:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVDIV_VV_M8_E64:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M8_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51474, GIR_EraseRootFromParent_Done, // Label 572: @18405 GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(18450), // Rule ID 51475 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (sdiv:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVDIV_VV_M8_E64:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M8_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51475, GIR_EraseRootFromParent_Done, // Label 573: @18450 GIM_Reject, // Label 571: @18451 GIM_Reject, // Label 514: @18452 GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(18566), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(18520), // Rule ID 51430 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sdiv:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVDIV_VV_M2_E8:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M2_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51430, GIR_EraseRootFromParent_Done, // Label 575: @18520 GIM_Try, /*On fail goto*//*Label 576*/ GIMT_Encode4(18565), // Rule ID 51431 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sdiv:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVDIV_VV_M2_E8:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M2_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51431, GIR_EraseRootFromParent_Done, // Label 576: @18565 GIM_Reject, // Label 574: @18566 GIM_Reject, // Label 515: @18567 GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(18681), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(18635), // Rule ID 51446 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sdiv:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVDIV_VV_M4_E16:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M4_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51446, GIR_EraseRootFromParent_Done, // Label 578: @18635 GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(18680), // Rule ID 51447 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sdiv:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVDIV_VV_M4_E16:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M4_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51447, GIR_EraseRootFromParent_Done, // Label 579: @18680 GIM_Reject, // Label 577: @18681 GIM_Reject, // Label 516: @18682 GIM_Try, /*On fail goto*//*Label 580*/ GIMT_Encode4(18796), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(18750), // Rule ID 51462 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sdiv:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVDIV_VV_M8_E32:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M8_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51462, GIR_EraseRootFromParent_Done, // Label 581: @18750 GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(18795), // Rule ID 51463 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sdiv:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVDIV_VV_M8_E32:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M8_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51463, GIR_EraseRootFromParent_Done, // Label 582: @18795 GIM_Reject, // Label 580: @18796 GIM_Reject, // Label 517: @18797 GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(18911), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(18865), // Rule ID 51434 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sdiv:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVDIV_VV_M4_E8:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M4_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51434, GIR_EraseRootFromParent_Done, // Label 584: @18865 GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(18910), // Rule ID 51435 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sdiv:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVDIV_VV_M4_E8:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M4_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51435, GIR_EraseRootFromParent_Done, // Label 585: @18910 GIM_Reject, // Label 583: @18911 GIM_Reject, // Label 518: @18912 GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(19026), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(18980), // Rule ID 51450 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sdiv:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVDIV_VV_M8_E16:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M8_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51450, GIR_EraseRootFromParent_Done, // Label 587: @18980 GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(19025), // Rule ID 51451 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sdiv:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVDIV_VV_M8_E16:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M8_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51451, GIR_EraseRootFromParent_Done, // Label 588: @19025 GIM_Reject, // Label 586: @19026 GIM_Reject, // Label 519: @19027 GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(19141), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(19095), // Rule ID 51438 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (sdiv:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVDIV_VV_M8_E8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M8_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51438, GIR_EraseRootFromParent_Done, // Label 590: @19095 GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(19140), // Rule ID 51439 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (sdiv:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVDIV_VV_M8_E8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIV_VV_M8_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51439, GIR_EraseRootFromParent_Done, // Label 591: @19140 GIM_Reject, // Label 589: @19141 GIM_Reject, // Label 520: @19142 GIM_Reject, // Label 4: @19143 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 616*/ GIMT_Encode4(21912), /*GILLT_s32*//*Label 592*/ GIMT_Encode4(19278), /*GILLT_s64*//*Label 593*/ GIMT_Encode4(19348), GIMT_Encode4(0), /*GILLT_nxv1s8*//*Label 594*/ GIMT_Encode4(19382), /*GILLT_nxv1s16*//*Label 595*/ GIMT_Encode4(19497), /*GILLT_nxv1s32*//*Label 596*/ GIMT_Encode4(19612), /*GILLT_nxv1s64*//*Label 597*/ GIMT_Encode4(19727), GIMT_Encode4(0), /*GILLT_nxv2s8*//*Label 598*/ GIMT_Encode4(19842), /*GILLT_nxv2s16*//*Label 599*/ GIMT_Encode4(19957), /*GILLT_nxv2s32*//*Label 600*/ GIMT_Encode4(20072), /*GILLT_nxv2s64*//*Label 601*/ GIMT_Encode4(20187), GIMT_Encode4(0), /*GILLT_nxv4s8*//*Label 602*/ GIMT_Encode4(20302), /*GILLT_nxv4s16*//*Label 603*/ GIMT_Encode4(20417), /*GILLT_nxv4s32*//*Label 604*/ GIMT_Encode4(20532), /*GILLT_nxv4s64*//*Label 605*/ GIMT_Encode4(20647), GIMT_Encode4(0), /*GILLT_nxv8s8*//*Label 606*/ GIMT_Encode4(20762), /*GILLT_nxv8s16*//*Label 607*/ GIMT_Encode4(20877), /*GILLT_nxv8s32*//*Label 608*/ GIMT_Encode4(20992), /*GILLT_nxv8s64*//*Label 609*/ GIMT_Encode4(21107), GIMT_Encode4(0), /*GILLT_nxv16s8*//*Label 610*/ GIMT_Encode4(21222), /*GILLT_nxv16s16*//*Label 611*/ GIMT_Encode4(21337), /*GILLT_nxv16s32*//*Label 612*/ GIMT_Encode4(21452), GIMT_Encode4(0), /*GILLT_nxv32s8*//*Label 613*/ GIMT_Encode4(21567), /*GILLT_nxv32s16*//*Label 614*/ GIMT_Encode4(21682), GIMT_Encode4(0), /*GILLT_nxv64s8*//*Label 615*/ GIMT_Encode4(21797), // Label 592: @19278 GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(19347), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(19316), // Rule ID 286 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_HwMode1), // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::DIVU), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 286, GIR_Done, // Label 618: @19316 GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(19331), // Rule ID 64745 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_IsRV64_HwMode0), // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (DIVUW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::DIVUW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64745, GIR_Done, // Label 619: @19331 GIM_Try, /*On fail goto*//*Label 620*/ GIMT_Encode4(19346), // Rule ID 64746 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_IsRV64_HwMode1), // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (DIVUW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::DIVUW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64746, GIR_Done, // Label 620: @19346 GIM_Reject, // Label 617: @19347 GIM_Reject, // Label 593: @19348 GIM_Try, /*On fail goto*//*Label 621*/ GIMT_Encode4(19381), // Rule ID 285 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_HwMode0), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), // (udiv:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (DIVU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::DIVU), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 285, GIR_Done, // Label 621: @19381 GIM_Reject, // Label 594: @19382 GIM_Try, /*On fail goto*//*Label 622*/ GIMT_Encode4(19496), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(19450), // Rule ID 51302 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (udiv:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVDIVU_VV_MF8_E8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF8_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51302, GIR_EraseRootFromParent_Done, // Label 623: @19450 GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(19495), // Rule ID 51303 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (udiv:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVDIVU_VV_MF8_E8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF8_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51303, GIR_EraseRootFromParent_Done, // Label 624: @19495 GIM_Reject, // Label 622: @19496 GIM_Reject, // Label 595: @19497 GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(19611), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(19565), // Rule ID 51314 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (udiv:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVDIVU_VV_MF4_E16:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF4_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51314, GIR_EraseRootFromParent_Done, // Label 626: @19565 GIM_Try, /*On fail goto*//*Label 627*/ GIMT_Encode4(19610), // Rule ID 51315 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (udiv:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVDIVU_VV_MF4_E16:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF4_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51315, GIR_EraseRootFromParent_Done, // Label 627: @19610 GIM_Reject, // Label 625: @19611 GIM_Reject, // Label 596: @19612 GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(19726), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(19680), // Rule ID 51322 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (udiv:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVDIVU_VV_MF2_E32:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF2_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51322, GIR_EraseRootFromParent_Done, // Label 629: @19680 GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(19725), // Rule ID 51323 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (udiv:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVDIVU_VV_MF2_E32:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF2_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51323, GIR_EraseRootFromParent_Done, // Label 630: @19725 GIM_Reject, // Label 628: @19726 GIM_Reject, // Label 597: @19727 GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(19841), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(19795), // Rule ID 51338 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (udiv:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVDIVU_VV_M1_E64:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M1_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51338, GIR_EraseRootFromParent_Done, // Label 632: @19795 GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(19840), // Rule ID 51339 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (udiv:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVDIVU_VV_M1_E64:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M1_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51339, GIR_EraseRootFromParent_Done, // Label 633: @19840 GIM_Reject, // Label 631: @19841 GIM_Reject, // Label 598: @19842 GIM_Try, /*On fail goto*//*Label 634*/ GIMT_Encode4(19956), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(19910), // Rule ID 51306 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (udiv:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVDIVU_VV_MF4_E8:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF4_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51306, GIR_EraseRootFromParent_Done, // Label 635: @19910 GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(19955), // Rule ID 51307 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (udiv:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVDIVU_VV_MF4_E8:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF4_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51307, GIR_EraseRootFromParent_Done, // Label 636: @19955 GIM_Reject, // Label 634: @19956 GIM_Reject, // Label 599: @19957 GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(20071), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(20025), // Rule ID 51318 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (udiv:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVDIVU_VV_MF2_E16:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF2_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51318, GIR_EraseRootFromParent_Done, // Label 638: @20025 GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(20070), // Rule ID 51319 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (udiv:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVDIVU_VV_MF2_E16:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF2_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51319, GIR_EraseRootFromParent_Done, // Label 639: @20070 GIM_Reject, // Label 637: @20071 GIM_Reject, // Label 600: @20072 GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(20186), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(20140), // Rule ID 51334 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (udiv:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVDIVU_VV_M1_E32:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M1_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51334, GIR_EraseRootFromParent_Done, // Label 641: @20140 GIM_Try, /*On fail goto*//*Label 642*/ GIMT_Encode4(20185), // Rule ID 51335 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (udiv:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVDIVU_VV_M1_E32:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M1_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51335, GIR_EraseRootFromParent_Done, // Label 642: @20185 GIM_Reject, // Label 640: @20186 GIM_Reject, // Label 601: @20187 GIM_Try, /*On fail goto*//*Label 643*/ GIMT_Encode4(20301), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 644*/ GIMT_Encode4(20255), // Rule ID 51378 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (udiv:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVDIVU_VV_M2_E64:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M2_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51378, GIR_EraseRootFromParent_Done, // Label 644: @20255 GIM_Try, /*On fail goto*//*Label 645*/ GIMT_Encode4(20300), // Rule ID 51379 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (udiv:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVDIVU_VV_M2_E64:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M2_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51379, GIR_EraseRootFromParent_Done, // Label 645: @20300 GIM_Reject, // Label 643: @20301 GIM_Reject, // Label 602: @20302 GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(20416), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(20370), // Rule ID 51310 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (udiv:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVDIVU_VV_MF2_E8:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF2_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51310, GIR_EraseRootFromParent_Done, // Label 647: @20370 GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(20415), // Rule ID 51311 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (udiv:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVDIVU_VV_MF2_E8:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_MF2_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51311, GIR_EraseRootFromParent_Done, // Label 648: @20415 GIM_Reject, // Label 646: @20416 GIM_Reject, // Label 603: @20417 GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(20531), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(20485), // Rule ID 51330 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (udiv:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVDIVU_VV_M1_E16:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M1_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51330, GIR_EraseRootFromParent_Done, // Label 650: @20485 GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(20530), // Rule ID 51331 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (udiv:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVDIVU_VV_M1_E16:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M1_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51331, GIR_EraseRootFromParent_Done, // Label 651: @20530 GIM_Reject, // Label 649: @20531 GIM_Reject, // Label 604: @20532 GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(20646), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(20600), // Rule ID 51366 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (udiv:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVDIVU_VV_M2_E32:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M2_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51366, GIR_EraseRootFromParent_Done, // Label 653: @20600 GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(20645), // Rule ID 51367 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (udiv:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVDIVU_VV_M2_E32:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M2_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51367, GIR_EraseRootFromParent_Done, // Label 654: @20645 GIM_Reject, // Label 652: @20646 GIM_Reject, // Label 605: @20647 GIM_Try, /*On fail goto*//*Label 655*/ GIMT_Encode4(20761), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 656*/ GIMT_Encode4(20715), // Rule ID 51382 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (udiv:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVDIVU_VV_M4_E64:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M4_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51382, GIR_EraseRootFromParent_Done, // Label 656: @20715 GIM_Try, /*On fail goto*//*Label 657*/ GIMT_Encode4(20760), // Rule ID 51383 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (udiv:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVDIVU_VV_M4_E64:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M4_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51383, GIR_EraseRootFromParent_Done, // Label 657: @20760 GIM_Reject, // Label 655: @20761 GIM_Reject, // Label 606: @20762 GIM_Try, /*On fail goto*//*Label 658*/ GIMT_Encode4(20876), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 659*/ GIMT_Encode4(20830), // Rule ID 51326 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (udiv:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVDIVU_VV_M1_E8:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M1_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51326, GIR_EraseRootFromParent_Done, // Label 659: @20830 GIM_Try, /*On fail goto*//*Label 660*/ GIMT_Encode4(20875), // Rule ID 51327 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (udiv:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVDIVU_VV_M1_E8:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M1_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51327, GIR_EraseRootFromParent_Done, // Label 660: @20875 GIM_Reject, // Label 658: @20876 GIM_Reject, // Label 607: @20877 GIM_Try, /*On fail goto*//*Label 661*/ GIMT_Encode4(20991), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 662*/ GIMT_Encode4(20945), // Rule ID 51354 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (udiv:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVDIVU_VV_M2_E16:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M2_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51354, GIR_EraseRootFromParent_Done, // Label 662: @20945 GIM_Try, /*On fail goto*//*Label 663*/ GIMT_Encode4(20990), // Rule ID 51355 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (udiv:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVDIVU_VV_M2_E16:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M2_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51355, GIR_EraseRootFromParent_Done, // Label 663: @20990 GIM_Reject, // Label 661: @20991 GIM_Reject, // Label 608: @20992 GIM_Try, /*On fail goto*//*Label 664*/ GIMT_Encode4(21106), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(21060), // Rule ID 51370 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (udiv:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVDIVU_VV_M4_E32:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M4_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51370, GIR_EraseRootFromParent_Done, // Label 665: @21060 GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(21105), // Rule ID 51371 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (udiv:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVDIVU_VV_M4_E32:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M4_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51371, GIR_EraseRootFromParent_Done, // Label 666: @21105 GIM_Reject, // Label 664: @21106 GIM_Reject, // Label 609: @21107 GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(21221), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(21175), // Rule ID 51386 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (udiv:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVDIVU_VV_M8_E64:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M8_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51386, GIR_EraseRootFromParent_Done, // Label 668: @21175 GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(21220), // Rule ID 51387 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (udiv:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVDIVU_VV_M8_E64:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M8_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51387, GIR_EraseRootFromParent_Done, // Label 669: @21220 GIM_Reject, // Label 667: @21221 GIM_Reject, // Label 610: @21222 GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(21336), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(21290), // Rule ID 51342 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (udiv:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVDIVU_VV_M2_E8:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M2_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51342, GIR_EraseRootFromParent_Done, // Label 671: @21290 GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(21335), // Rule ID 51343 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (udiv:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVDIVU_VV_M2_E8:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M2_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51343, GIR_EraseRootFromParent_Done, // Label 672: @21335 GIM_Reject, // Label 670: @21336 GIM_Reject, // Label 611: @21337 GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(21451), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(21405), // Rule ID 51358 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (udiv:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVDIVU_VV_M4_E16:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M4_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51358, GIR_EraseRootFromParent_Done, // Label 674: @21405 GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(21450), // Rule ID 51359 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (udiv:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVDIVU_VV_M4_E16:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M4_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51359, GIR_EraseRootFromParent_Done, // Label 675: @21450 GIM_Reject, // Label 673: @21451 GIM_Reject, // Label 612: @21452 GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(21566), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(21520), // Rule ID 51374 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (udiv:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVDIVU_VV_M8_E32:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M8_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51374, GIR_EraseRootFromParent_Done, // Label 677: @21520 GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(21565), // Rule ID 51375 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (udiv:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVDIVU_VV_M8_E32:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M8_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51375, GIR_EraseRootFromParent_Done, // Label 678: @21565 GIM_Reject, // Label 676: @21566 GIM_Reject, // Label 613: @21567 GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(21681), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(21635), // Rule ID 51346 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (udiv:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVDIVU_VV_M4_E8:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M4_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51346, GIR_EraseRootFromParent_Done, // Label 680: @21635 GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(21680), // Rule ID 51347 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (udiv:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVDIVU_VV_M4_E8:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M4_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51347, GIR_EraseRootFromParent_Done, // Label 681: @21680 GIM_Reject, // Label 679: @21681 GIM_Reject, // Label 614: @21682 GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(21796), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(21750), // Rule ID 51362 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (udiv:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVDIVU_VV_M8_E16:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M8_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51362, GIR_EraseRootFromParent_Done, // Label 683: @21750 GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(21795), // Rule ID 51363 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (udiv:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVDIVU_VV_M8_E16:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M8_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51363, GIR_EraseRootFromParent_Done, // Label 684: @21795 GIM_Reject, // Label 682: @21796 GIM_Reject, // Label 615: @21797 GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(21911), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(21865), // Rule ID 51350 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (udiv:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVDIVU_VV_M8_E8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M8_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51350, GIR_EraseRootFromParent_Done, // Label 686: @21865 GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(21910), // Rule ID 51351 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (udiv:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVDIVU_VV_M8_E8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVDIVU_VV_M8_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51351, GIR_EraseRootFromParent_Done, // Label 687: @21910 GIM_Reject, // Label 685: @21911 GIM_Reject, // Label 616: @21912 GIM_Reject, // Label 5: @21913 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 712*/ GIMT_Encode4(24682), /*GILLT_s32*//*Label 688*/ GIMT_Encode4(22048), /*GILLT_s64*//*Label 689*/ GIMT_Encode4(22118), GIMT_Encode4(0), /*GILLT_nxv1s8*//*Label 690*/ GIMT_Encode4(22152), /*GILLT_nxv1s16*//*Label 691*/ GIMT_Encode4(22267), /*GILLT_nxv1s32*//*Label 692*/ GIMT_Encode4(22382), /*GILLT_nxv1s64*//*Label 693*/ GIMT_Encode4(22497), GIMT_Encode4(0), /*GILLT_nxv2s8*//*Label 694*/ GIMT_Encode4(22612), /*GILLT_nxv2s16*//*Label 695*/ GIMT_Encode4(22727), /*GILLT_nxv2s32*//*Label 696*/ GIMT_Encode4(22842), /*GILLT_nxv2s64*//*Label 697*/ GIMT_Encode4(22957), GIMT_Encode4(0), /*GILLT_nxv4s8*//*Label 698*/ GIMT_Encode4(23072), /*GILLT_nxv4s16*//*Label 699*/ GIMT_Encode4(23187), /*GILLT_nxv4s32*//*Label 700*/ GIMT_Encode4(23302), /*GILLT_nxv4s64*//*Label 701*/ GIMT_Encode4(23417), GIMT_Encode4(0), /*GILLT_nxv8s8*//*Label 702*/ GIMT_Encode4(23532), /*GILLT_nxv8s16*//*Label 703*/ GIMT_Encode4(23647), /*GILLT_nxv8s32*//*Label 704*/ GIMT_Encode4(23762), /*GILLT_nxv8s64*//*Label 705*/ GIMT_Encode4(23877), GIMT_Encode4(0), /*GILLT_nxv16s8*//*Label 706*/ GIMT_Encode4(23992), /*GILLT_nxv16s16*//*Label 707*/ GIMT_Encode4(24107), /*GILLT_nxv16s32*//*Label 708*/ GIMT_Encode4(24222), GIMT_Encode4(0), /*GILLT_nxv32s8*//*Label 709*/ GIMT_Encode4(24337), /*GILLT_nxv32s16*//*Label 710*/ GIMT_Encode4(24452), GIMT_Encode4(0), /*GILLT_nxv64s8*//*Label 711*/ GIMT_Encode4(24567), // Label 688: @22048 GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(22117), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(22086), // Rule ID 288 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_HwMode1), // (srem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (REM:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::REM), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 288, GIR_Done, // Label 714: @22086 GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(22101), // Rule ID 64747 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_IsRV64_HwMode0), // (srem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (REMW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::REMW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64747, GIR_Done, // Label 715: @22101 GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(22116), // Rule ID 64748 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_IsRV64_HwMode1), // (srem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (REMW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::REMW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64748, GIR_Done, // Label 716: @22116 GIM_Reject, // Label 713: @22117 GIM_Reject, // Label 689: @22118 GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(22151), // Rule ID 287 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_HwMode0), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), // (srem:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (REM:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::REM), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 287, GIR_Done, // Label 717: @22151 GIM_Reject, // Label 690: @22152 GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(22266), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(22220), // Rule ID 51566 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (srem:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVREM_VV_MF8_E8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF8_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51566, GIR_EraseRootFromParent_Done, // Label 719: @22220 GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(22265), // Rule ID 51567 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (srem:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVREM_VV_MF8_E8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF8_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51567, GIR_EraseRootFromParent_Done, // Label 720: @22265 GIM_Reject, // Label 718: @22266 GIM_Reject, // Label 691: @22267 GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(22381), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(22335), // Rule ID 51578 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (srem:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVREM_VV_MF4_E16:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF4_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51578, GIR_EraseRootFromParent_Done, // Label 722: @22335 GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(22380), // Rule ID 51579 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (srem:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVREM_VV_MF4_E16:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF4_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51579, GIR_EraseRootFromParent_Done, // Label 723: @22380 GIM_Reject, // Label 721: @22381 GIM_Reject, // Label 692: @22382 GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(22496), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(22450), // Rule ID 51586 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (srem:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVREM_VV_MF2_E32:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF2_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51586, GIR_EraseRootFromParent_Done, // Label 725: @22450 GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(22495), // Rule ID 51587 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (srem:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVREM_VV_MF2_E32:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF2_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51587, GIR_EraseRootFromParent_Done, // Label 726: @22495 GIM_Reject, // Label 724: @22496 GIM_Reject, // Label 693: @22497 GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(22611), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(22565), // Rule ID 51602 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (srem:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVREM_VV_M1_E64:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M1_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51602, GIR_EraseRootFromParent_Done, // Label 728: @22565 GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(22610), // Rule ID 51603 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (srem:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVREM_VV_M1_E64:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M1_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51603, GIR_EraseRootFromParent_Done, // Label 729: @22610 GIM_Reject, // Label 727: @22611 GIM_Reject, // Label 694: @22612 GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(22726), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(22680), // Rule ID 51570 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (srem:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVREM_VV_MF4_E8:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF4_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51570, GIR_EraseRootFromParent_Done, // Label 731: @22680 GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(22725), // Rule ID 51571 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (srem:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVREM_VV_MF4_E8:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF4_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51571, GIR_EraseRootFromParent_Done, // Label 732: @22725 GIM_Reject, // Label 730: @22726 GIM_Reject, // Label 695: @22727 GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(22841), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(22795), // Rule ID 51582 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (srem:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVREM_VV_MF2_E16:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF2_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51582, GIR_EraseRootFromParent_Done, // Label 734: @22795 GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(22840), // Rule ID 51583 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (srem:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVREM_VV_MF2_E16:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF2_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51583, GIR_EraseRootFromParent_Done, // Label 735: @22840 GIM_Reject, // Label 733: @22841 GIM_Reject, // Label 696: @22842 GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(22956), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(22910), // Rule ID 51598 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (srem:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVREM_VV_M1_E32:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M1_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51598, GIR_EraseRootFromParent_Done, // Label 737: @22910 GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(22955), // Rule ID 51599 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (srem:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVREM_VV_M1_E32:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M1_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51599, GIR_EraseRootFromParent_Done, // Label 738: @22955 GIM_Reject, // Label 736: @22956 GIM_Reject, // Label 697: @22957 GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(23071), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(23025), // Rule ID 51642 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (srem:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVREM_VV_M2_E64:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M2_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51642, GIR_EraseRootFromParent_Done, // Label 740: @23025 GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(23070), // Rule ID 51643 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (srem:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVREM_VV_M2_E64:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M2_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51643, GIR_EraseRootFromParent_Done, // Label 741: @23070 GIM_Reject, // Label 739: @23071 GIM_Reject, // Label 698: @23072 GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(23186), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(23140), // Rule ID 51574 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (srem:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVREM_VV_MF2_E8:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF2_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51574, GIR_EraseRootFromParent_Done, // Label 743: @23140 GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(23185), // Rule ID 51575 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (srem:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVREM_VV_MF2_E8:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_MF2_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51575, GIR_EraseRootFromParent_Done, // Label 744: @23185 GIM_Reject, // Label 742: @23186 GIM_Reject, // Label 699: @23187 GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(23301), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(23255), // Rule ID 51594 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (srem:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVREM_VV_M1_E16:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M1_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51594, GIR_EraseRootFromParent_Done, // Label 746: @23255 GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(23300), // Rule ID 51595 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (srem:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVREM_VV_M1_E16:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M1_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51595, GIR_EraseRootFromParent_Done, // Label 747: @23300 GIM_Reject, // Label 745: @23301 GIM_Reject, // Label 700: @23302 GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(23416), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(23370), // Rule ID 51630 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (srem:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVREM_VV_M2_E32:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M2_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51630, GIR_EraseRootFromParent_Done, // Label 749: @23370 GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(23415), // Rule ID 51631 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (srem:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVREM_VV_M2_E32:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M2_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51631, GIR_EraseRootFromParent_Done, // Label 750: @23415 GIM_Reject, // Label 748: @23416 GIM_Reject, // Label 701: @23417 GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(23531), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(23485), // Rule ID 51646 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (srem:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVREM_VV_M4_E64:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M4_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51646, GIR_EraseRootFromParent_Done, // Label 752: @23485 GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(23530), // Rule ID 51647 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (srem:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVREM_VV_M4_E64:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M4_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51647, GIR_EraseRootFromParent_Done, // Label 753: @23530 GIM_Reject, // Label 751: @23531 GIM_Reject, // Label 702: @23532 GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(23646), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(23600), // Rule ID 51590 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (srem:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVREM_VV_M1_E8:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M1_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51590, GIR_EraseRootFromParent_Done, // Label 755: @23600 GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(23645), // Rule ID 51591 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (srem:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVREM_VV_M1_E8:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M1_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51591, GIR_EraseRootFromParent_Done, // Label 756: @23645 GIM_Reject, // Label 754: @23646 GIM_Reject, // Label 703: @23647 GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(23761), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(23715), // Rule ID 51618 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (srem:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVREM_VV_M2_E16:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M2_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51618, GIR_EraseRootFromParent_Done, // Label 758: @23715 GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(23760), // Rule ID 51619 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (srem:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVREM_VV_M2_E16:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M2_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51619, GIR_EraseRootFromParent_Done, // Label 759: @23760 GIM_Reject, // Label 757: @23761 GIM_Reject, // Label 704: @23762 GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(23876), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(23830), // Rule ID 51634 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (srem:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVREM_VV_M4_E32:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M4_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51634, GIR_EraseRootFromParent_Done, // Label 761: @23830 GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(23875), // Rule ID 51635 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (srem:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVREM_VV_M4_E32:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M4_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51635, GIR_EraseRootFromParent_Done, // Label 762: @23875 GIM_Reject, // Label 760: @23876 GIM_Reject, // Label 705: @23877 GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(23991), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(23945), // Rule ID 51650 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (srem:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVREM_VV_M8_E64:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M8_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51650, GIR_EraseRootFromParent_Done, // Label 764: @23945 GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(23990), // Rule ID 51651 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (srem:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVREM_VV_M8_E64:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M8_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51651, GIR_EraseRootFromParent_Done, // Label 765: @23990 GIM_Reject, // Label 763: @23991 GIM_Reject, // Label 706: @23992 GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(24106), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(24060), // Rule ID 51606 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (srem:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVREM_VV_M2_E8:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M2_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51606, GIR_EraseRootFromParent_Done, // Label 767: @24060 GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(24105), // Rule ID 51607 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (srem:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVREM_VV_M2_E8:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M2_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51607, GIR_EraseRootFromParent_Done, // Label 768: @24105 GIM_Reject, // Label 766: @24106 GIM_Reject, // Label 707: @24107 GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(24221), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(24175), // Rule ID 51622 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (srem:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVREM_VV_M4_E16:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M4_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51622, GIR_EraseRootFromParent_Done, // Label 770: @24175 GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(24220), // Rule ID 51623 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (srem:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVREM_VV_M4_E16:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M4_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51623, GIR_EraseRootFromParent_Done, // Label 771: @24220 GIM_Reject, // Label 769: @24221 GIM_Reject, // Label 708: @24222 GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(24336), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(24290), // Rule ID 51638 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (srem:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVREM_VV_M8_E32:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M8_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51638, GIR_EraseRootFromParent_Done, // Label 773: @24290 GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(24335), // Rule ID 51639 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (srem:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVREM_VV_M8_E32:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M8_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51639, GIR_EraseRootFromParent_Done, // Label 774: @24335 GIM_Reject, // Label 772: @24336 GIM_Reject, // Label 709: @24337 GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(24451), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(24405), // Rule ID 51610 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (srem:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVREM_VV_M4_E8:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M4_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51610, GIR_EraseRootFromParent_Done, // Label 776: @24405 GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(24450), // Rule ID 51611 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (srem:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVREM_VV_M4_E8:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M4_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51611, GIR_EraseRootFromParent_Done, // Label 777: @24450 GIM_Reject, // Label 775: @24451 GIM_Reject, // Label 710: @24452 GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(24566), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(24520), // Rule ID 51626 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (srem:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVREM_VV_M8_E16:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M8_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51626, GIR_EraseRootFromParent_Done, // Label 779: @24520 GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(24565), // Rule ID 51627 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (srem:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVREM_VV_M8_E16:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M8_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51627, GIR_EraseRootFromParent_Done, // Label 780: @24565 GIM_Reject, // Label 778: @24566 GIM_Reject, // Label 711: @24567 GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(24681), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(24635), // Rule ID 51614 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (srem:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVREM_VV_M8_E8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M8_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51614, GIR_EraseRootFromParent_Done, // Label 782: @24635 GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(24680), // Rule ID 51615 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (srem:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVREM_VV_M8_E8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREM_VV_M8_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51615, GIR_EraseRootFromParent_Done, // Label 783: @24680 GIM_Reject, // Label 781: @24681 GIM_Reject, // Label 712: @24682 GIM_Reject, // Label 6: @24683 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 808*/ GIMT_Encode4(27452), /*GILLT_s32*//*Label 784*/ GIMT_Encode4(24818), /*GILLT_s64*//*Label 785*/ GIMT_Encode4(24888), GIMT_Encode4(0), /*GILLT_nxv1s8*//*Label 786*/ GIMT_Encode4(24922), /*GILLT_nxv1s16*//*Label 787*/ GIMT_Encode4(25037), /*GILLT_nxv1s32*//*Label 788*/ GIMT_Encode4(25152), /*GILLT_nxv1s64*//*Label 789*/ GIMT_Encode4(25267), GIMT_Encode4(0), /*GILLT_nxv2s8*//*Label 790*/ GIMT_Encode4(25382), /*GILLT_nxv2s16*//*Label 791*/ GIMT_Encode4(25497), /*GILLT_nxv2s32*//*Label 792*/ GIMT_Encode4(25612), /*GILLT_nxv2s64*//*Label 793*/ GIMT_Encode4(25727), GIMT_Encode4(0), /*GILLT_nxv4s8*//*Label 794*/ GIMT_Encode4(25842), /*GILLT_nxv4s16*//*Label 795*/ GIMT_Encode4(25957), /*GILLT_nxv4s32*//*Label 796*/ GIMT_Encode4(26072), /*GILLT_nxv4s64*//*Label 797*/ GIMT_Encode4(26187), GIMT_Encode4(0), /*GILLT_nxv8s8*//*Label 798*/ GIMT_Encode4(26302), /*GILLT_nxv8s16*//*Label 799*/ GIMT_Encode4(26417), /*GILLT_nxv8s32*//*Label 800*/ GIMT_Encode4(26532), /*GILLT_nxv8s64*//*Label 801*/ GIMT_Encode4(26647), GIMT_Encode4(0), /*GILLT_nxv16s8*//*Label 802*/ GIMT_Encode4(26762), /*GILLT_nxv16s16*//*Label 803*/ GIMT_Encode4(26877), /*GILLT_nxv16s32*//*Label 804*/ GIMT_Encode4(26992), GIMT_Encode4(0), /*GILLT_nxv32s8*//*Label 805*/ GIMT_Encode4(27107), /*GILLT_nxv32s16*//*Label 806*/ GIMT_Encode4(27222), GIMT_Encode4(0), /*GILLT_nxv64s8*//*Label 807*/ GIMT_Encode4(27337), // Label 784: @24818 GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(24887), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(24856), // Rule ID 290 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_HwMode1), // (urem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::REMU), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 290, GIR_Done, // Label 810: @24856 GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(24871), // Rule ID 64749 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_IsRV64_HwMode0), // (urem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (REMUW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::REMUW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64749, GIR_Done, // Label 811: @24871 GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(24886), // Rule ID 64750 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_IsRV64_HwMode1), // (urem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (REMUW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::REMUW), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64750, GIR_Done, // Label 812: @24886 GIM_Reject, // Label 809: @24887 GIM_Reject, // Label 785: @24888 GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(24921), // Rule ID 289 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtM_HwMode0), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), // (urem:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (REMU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::REMU), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 289, GIR_Done, // Label 813: @24921 GIM_Reject, // Label 786: @24922 GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(25036), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(24990), // Rule ID 51478 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (urem:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVREMU_VV_MF8_E8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF8_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51478, GIR_EraseRootFromParent_Done, // Label 815: @24990 GIM_Try, /*On fail goto*//*Label 816*/ GIMT_Encode4(25035), // Rule ID 51479 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (urem:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVREMU_VV_MF8_E8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF8_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51479, GIR_EraseRootFromParent_Done, // Label 816: @25035 GIM_Reject, // Label 814: @25036 GIM_Reject, // Label 787: @25037 GIM_Try, /*On fail goto*//*Label 817*/ GIMT_Encode4(25151), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(25105), // Rule ID 51490 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (urem:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVREMU_VV_MF4_E16:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF4_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51490, GIR_EraseRootFromParent_Done, // Label 818: @25105 GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(25150), // Rule ID 51491 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (urem:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVREMU_VV_MF4_E16:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF4_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51491, GIR_EraseRootFromParent_Done, // Label 819: @25150 GIM_Reject, // Label 817: @25151 GIM_Reject, // Label 788: @25152 GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(25266), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(25220), // Rule ID 51498 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (urem:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVREMU_VV_MF2_E32:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF2_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51498, GIR_EraseRootFromParent_Done, // Label 821: @25220 GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(25265), // Rule ID 51499 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (urem:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVREMU_VV_MF2_E32:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF2_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51499, GIR_EraseRootFromParent_Done, // Label 822: @25265 GIM_Reject, // Label 820: @25266 GIM_Reject, // Label 789: @25267 GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(25381), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(25335), // Rule ID 51514 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (urem:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVREMU_VV_M1_E64:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M1_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51514, GIR_EraseRootFromParent_Done, // Label 824: @25335 GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(25380), // Rule ID 51515 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (urem:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVREMU_VV_M1_E64:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M1_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51515, GIR_EraseRootFromParent_Done, // Label 825: @25380 GIM_Reject, // Label 823: @25381 GIM_Reject, // Label 790: @25382 GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(25496), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 827*/ GIMT_Encode4(25450), // Rule ID 51482 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (urem:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVREMU_VV_MF4_E8:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF4_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51482, GIR_EraseRootFromParent_Done, // Label 827: @25450 GIM_Try, /*On fail goto*//*Label 828*/ GIMT_Encode4(25495), // Rule ID 51483 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (urem:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVREMU_VV_MF4_E8:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF4_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51483, GIR_EraseRootFromParent_Done, // Label 828: @25495 GIM_Reject, // Label 826: @25496 GIM_Reject, // Label 791: @25497 GIM_Try, /*On fail goto*//*Label 829*/ GIMT_Encode4(25611), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 830*/ GIMT_Encode4(25565), // Rule ID 51494 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (urem:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVREMU_VV_MF2_E16:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF2_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51494, GIR_EraseRootFromParent_Done, // Label 830: @25565 GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(25610), // Rule ID 51495 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (urem:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVREMU_VV_MF2_E16:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF2_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51495, GIR_EraseRootFromParent_Done, // Label 831: @25610 GIM_Reject, // Label 829: @25611 GIM_Reject, // Label 792: @25612 GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(25726), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(25680), // Rule ID 51510 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (urem:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVREMU_VV_M1_E32:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M1_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51510, GIR_EraseRootFromParent_Done, // Label 833: @25680 GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(25725), // Rule ID 51511 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (urem:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVREMU_VV_M1_E32:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M1_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51511, GIR_EraseRootFromParent_Done, // Label 834: @25725 GIM_Reject, // Label 832: @25726 GIM_Reject, // Label 793: @25727 GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(25841), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(25795), // Rule ID 51554 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (urem:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVREMU_VV_M2_E64:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M2_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51554, GIR_EraseRootFromParent_Done, // Label 836: @25795 GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(25840), // Rule ID 51555 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (urem:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVREMU_VV_M2_E64:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M2_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51555, GIR_EraseRootFromParent_Done, // Label 837: @25840 GIM_Reject, // Label 835: @25841 GIM_Reject, // Label 794: @25842 GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(25956), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(25910), // Rule ID 51486 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (urem:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVREMU_VV_MF2_E8:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF2_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51486, GIR_EraseRootFromParent_Done, // Label 839: @25910 GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(25955), // Rule ID 51487 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (urem:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVREMU_VV_MF2_E8:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_MF2_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51487, GIR_EraseRootFromParent_Done, // Label 840: @25955 GIM_Reject, // Label 838: @25956 GIM_Reject, // Label 795: @25957 GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(26071), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(26025), // Rule ID 51506 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (urem:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVREMU_VV_M1_E16:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M1_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51506, GIR_EraseRootFromParent_Done, // Label 842: @26025 GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(26070), // Rule ID 51507 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (urem:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVREMU_VV_M1_E16:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M1_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51507, GIR_EraseRootFromParent_Done, // Label 843: @26070 GIM_Reject, // Label 841: @26071 GIM_Reject, // Label 796: @26072 GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(26186), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(26140), // Rule ID 51542 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (urem:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVREMU_VV_M2_E32:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M2_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51542, GIR_EraseRootFromParent_Done, // Label 845: @26140 GIM_Try, /*On fail goto*//*Label 846*/ GIMT_Encode4(26185), // Rule ID 51543 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (urem:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVREMU_VV_M2_E32:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M2_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51543, GIR_EraseRootFromParent_Done, // Label 846: @26185 GIM_Reject, // Label 844: @26186 GIM_Reject, // Label 797: @26187 GIM_Try, /*On fail goto*//*Label 847*/ GIMT_Encode4(26301), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 848*/ GIMT_Encode4(26255), // Rule ID 51558 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (urem:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVREMU_VV_M4_E64:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M4_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51558, GIR_EraseRootFromParent_Done, // Label 848: @26255 GIM_Try, /*On fail goto*//*Label 849*/ GIMT_Encode4(26300), // Rule ID 51559 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (urem:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVREMU_VV_M4_E64:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M4_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51559, GIR_EraseRootFromParent_Done, // Label 849: @26300 GIM_Reject, // Label 847: @26301 GIM_Reject, // Label 798: @26302 GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(26416), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 851*/ GIMT_Encode4(26370), // Rule ID 51502 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (urem:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVREMU_VV_M1_E8:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M1_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51502, GIR_EraseRootFromParent_Done, // Label 851: @26370 GIM_Try, /*On fail goto*//*Label 852*/ GIMT_Encode4(26415), // Rule ID 51503 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (urem:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2) => (PseudoVREMU_VV_M1_E8:{ *:[nxv8i8] } (IMPLICIT_DEF:{ *:[nxv8i8] }), VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M1_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51503, GIR_EraseRootFromParent_Done, // Label 852: @26415 GIM_Reject, // Label 850: @26416 GIM_Reject, // Label 799: @26417 GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(26531), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(26485), // Rule ID 51530 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (urem:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVREMU_VV_M2_E16:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M2_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51530, GIR_EraseRootFromParent_Done, // Label 854: @26485 GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(26530), // Rule ID 51531 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (urem:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2) => (PseudoVREMU_VV_M2_E16:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv8i16] }), VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M2_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51531, GIR_EraseRootFromParent_Done, // Label 855: @26530 GIM_Reject, // Label 853: @26531 GIM_Reject, // Label 800: @26532 GIM_Try, /*On fail goto*//*Label 856*/ GIMT_Encode4(26646), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 857*/ GIMT_Encode4(26600), // Rule ID 51546 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (urem:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVREMU_VV_M4_E32:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M4_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51546, GIR_EraseRootFromParent_Done, // Label 857: @26600 GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(26645), // Rule ID 51547 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (urem:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2) => (PseudoVREMU_VV_M4_E32:{ *:[nxv8i32] } (IMPLICIT_DEF:{ *:[nxv8i32] }), VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M4_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51547, GIR_EraseRootFromParent_Done, // Label 858: @26645 GIM_Reject, // Label 856: @26646 GIM_Reject, // Label 801: @26647 GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(26761), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 860*/ GIMT_Encode4(26715), // Rule ID 51562 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (urem:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVREMU_VV_M8_E64:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M8_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51562, GIR_EraseRootFromParent_Done, // Label 860: @26715 GIM_Try, /*On fail goto*//*Label 861*/ GIMT_Encode4(26760), // Rule ID 51563 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (urem:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2) => (PseudoVREMU_VV_M8_E64:{ *:[nxv8i64] } (IMPLICIT_DEF:{ *:[nxv8i64] }), VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv8s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M8_E64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51563, GIR_EraseRootFromParent_Done, // Label 861: @26760 GIM_Reject, // Label 859: @26761 GIM_Reject, // Label 802: @26762 GIM_Try, /*On fail goto*//*Label 862*/ GIMT_Encode4(26876), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(26830), // Rule ID 51518 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (urem:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVREMU_VV_M2_E8:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M2_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51518, GIR_EraseRootFromParent_Done, // Label 863: @26830 GIM_Try, /*On fail goto*//*Label 864*/ GIMT_Encode4(26875), // Rule ID 51519 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (urem:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2) => (PseudoVREMU_VV_M2_E8:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M2_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51519, GIR_EraseRootFromParent_Done, // Label 864: @26875 GIM_Reject, // Label 862: @26876 GIM_Reject, // Label 803: @26877 GIM_Try, /*On fail goto*//*Label 865*/ GIMT_Encode4(26991), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(26945), // Rule ID 51534 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (urem:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVREMU_VV_M4_E16:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M4_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51534, GIR_EraseRootFromParent_Done, // Label 866: @26945 GIM_Try, /*On fail goto*//*Label 867*/ GIMT_Encode4(26990), // Rule ID 51535 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (urem:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2) => (PseudoVREMU_VV_M4_E16:{ *:[nxv16i16] } (IMPLICIT_DEF:{ *:[nxv16i16] }), VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M4_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51535, GIR_EraseRootFromParent_Done, // Label 867: @26990 GIM_Reject, // Label 865: @26991 GIM_Reject, // Label 804: @26992 GIM_Try, /*On fail goto*//*Label 868*/ GIMT_Encode4(27106), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(27060), // Rule ID 51550 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (urem:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVREMU_VV_M8_E32:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M8_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51550, GIR_EraseRootFromParent_Done, // Label 869: @27060 GIM_Try, /*On fail goto*//*Label 870*/ GIMT_Encode4(27105), // Rule ID 51551 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (urem:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2) => (PseudoVREMU_VV_M8_E32:{ *:[nxv16i32] } (IMPLICIT_DEF:{ *:[nxv16i32] }), VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M8_E32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51551, GIR_EraseRootFromParent_Done, // Label 870: @27105 GIM_Reject, // Label 868: @27106 GIM_Reject, // Label 805: @27107 GIM_Try, /*On fail goto*//*Label 871*/ GIMT_Encode4(27221), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 872*/ GIMT_Encode4(27175), // Rule ID 51522 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (urem:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVREMU_VV_M4_E8:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M4_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51522, GIR_EraseRootFromParent_Done, // Label 872: @27175 GIM_Try, /*On fail goto*//*Label 873*/ GIMT_Encode4(27220), // Rule ID 51523 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (urem:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2) => (PseudoVREMU_VV_M4_E8:{ *:[nxv32i8] } (IMPLICIT_DEF:{ *:[nxv32i8] }), VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M4_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51523, GIR_EraseRootFromParent_Done, // Label 873: @27220 GIM_Reject, // Label 871: @27221 GIM_Reject, // Label 806: @27222 GIM_Try, /*On fail goto*//*Label 874*/ GIMT_Encode4(27336), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv32s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv32s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(27290), // Rule ID 51538 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (urem:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVREMU_VV_M8_E16:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M8_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51538, GIR_EraseRootFromParent_Done, // Label 875: @27290 GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(27335), // Rule ID 51539 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (urem:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2) => (PseudoVREMU_VV_M8_E16:{ *:[nxv32i16] } (IMPLICIT_DEF:{ *:[nxv32i16] }), VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv32s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M8_E16), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51539, GIR_EraseRootFromParent_Done, // Label 876: @27335 GIM_Reject, // Label 874: @27336 GIM_Reject, // Label 807: @27337 GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(27451), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv64s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv64s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM8RegClassID), GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(27405), // Rule ID 51526 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (urem:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVREMU_VV_M8_E8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M8_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51526, GIR_EraseRootFromParent_Done, // Label 878: @27405 GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(27450), // Rule ID 51527 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (urem:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2) => (PseudoVREMU_VV_M8_E8:{ *:[nxv64i8] } (IMPLICIT_DEF:{ *:[nxv64i8] }), VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv64s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVREMU_VV_M8_E8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 51527, GIR_EraseRootFromParent_Done, // Label 879: @27450 GIM_Reject, // Label 877: @27451 GIM_Reject, // Label 808: @27452 GIM_Reject, // Label 7: @27453 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(34), /*)*//*default:*//*Label 911*/ GIMT_Encode4(36998), /*GILLT_s32*//*Label 880*/ GIMT_Encode4(27588), /*GILLT_s64*//*Label 881*/ GIMT_Encode4(29244), /*GILLT_nxv1s1*//*Label 882*/ GIMT_Encode4(30191), /*GILLT_nxv1s8*//*Label 883*/ GIMT_Encode4(30802), /*GILLT_nxv1s16*//*Label 884*/ GIMT_Encode4(30917), /*GILLT_nxv1s32*//*Label 885*/ GIMT_Encode4(31032), /*GILLT_nxv1s64*//*Label 886*/ GIMT_Encode4(31147), /*GILLT_nxv2s1*//*Label 887*/ GIMT_Encode4(31262), /*GILLT_nxv2s8*//*Label 888*/ GIMT_Encode4(31873), /*GILLT_nxv2s16*//*Label 889*/ GIMT_Encode4(31988), /*GILLT_nxv2s32*//*Label 890*/ GIMT_Encode4(32103), /*GILLT_nxv2s64*//*Label 891*/ GIMT_Encode4(32218), /*GILLT_nxv4s1*//*Label 892*/ GIMT_Encode4(32333), /*GILLT_nxv4s8*//*Label 893*/ GIMT_Encode4(32944), /*GILLT_nxv4s16*//*Label 894*/ GIMT_Encode4(33059), /*GILLT_nxv4s32*//*Label 895*/ GIMT_Encode4(33174), /*GILLT_nxv4s64*//*Label 896*/ GIMT_Encode4(33289), /*GILLT_nxv8s1*//*Label 897*/ GIMT_Encode4(33404), /*GILLT_nxv8s8*//*Label 898*/ GIMT_Encode4(34015), /*GILLT_nxv8s16*//*Label 899*/ GIMT_Encode4(34130), /*GILLT_nxv8s32*//*Label 900*/ GIMT_Encode4(34245), /*GILLT_nxv8s64*//*Label 901*/ GIMT_Encode4(34360), /*GILLT_nxv16s1*//*Label 902*/ GIMT_Encode4(34475), /*GILLT_nxv16s8*//*Label 903*/ GIMT_Encode4(35086), /*GILLT_nxv16s16*//*Label 904*/ GIMT_Encode4(35201), /*GILLT_nxv16s32*//*Label 905*/ GIMT_Encode4(35316), /*GILLT_nxv32s1*//*Label 906*/ GIMT_Encode4(35431), /*GILLT_nxv32s8*//*Label 907*/ GIMT_Encode4(36042), /*GILLT_nxv32s16*//*Label 908*/ GIMT_Encode4(36157), /*GILLT_nxv64s1*//*Label 909*/ GIMT_Encode4(36272), /*GILLT_nxv64s8*//*Label 910*/ GIMT_Encode4(36883), // Label 880: @27588 GIM_Try, /*On fail goto*//*Label 912*/ GIMT_Encode4(29243), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_Try, /*On fail goto*//*Label 913*/ GIMT_Encode4(27678), // Rule ID 2289 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode1), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 1, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), // (and:{ *:[i32] } (xor:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, (shiftMaskXLen:{ *:[i32] } GPR:{ *:[i32] }:$rs2)), -1:{ *:[i32] }), GPR:{ *:[i32] }:$rs1) => (BCLR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2289, GIR_EraseRootFromParent_Done, // Label 913: @27678 GIM_Try, /*On fail goto*//*Label 914*/ GIMT_Encode4(27753), // Rule ID 65008 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 1, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), // (and:{ *:[i32] } (xor:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)), -1:{ *:[i32] }), GPR:{ *:[i32] }:$rs1) => (BCLR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65008, GIR_EraseRootFromParent_Done, // Label 914: @27753 GIM_Try, /*On fail goto*//*Label 915*/ GIMT_Encode4(27828), // Rule ID 65123 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 1, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/2, GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (xor:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, (shiftMaskXLen:{ *:[i32] } GPR:{ *:[i32] }:$rs2)), -1:{ *:[i32] })) => (BCLR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65123, GIR_EraseRootFromParent_Done, // Label 915: @27828 GIM_Try, /*On fail goto*//*Label 916*/ GIMT_Encode4(27903), // Rule ID 73710 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 1, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/2, GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (xor:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)), -1:{ *:[i32] })) => (BCLR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73710, GIR_EraseRootFromParent_Done, // Label 916: @27903 GIM_Try, /*On fail goto*//*Label 917*/ GIMT_Encode4(27964), // Rule ID 2309 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode1), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt), 1:{ *:[i32] }) => (BEXTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BEXTI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shamt GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2309, GIR_EraseRootFromParent_Done, // Label 917: @27964 GIM_Try, /*On fail goto*//*Label 918*/ GIMT_Encode4(28025), // Rule ID 62633 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBs_HwMode1), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt), 1:{ *:[i32] }) => (TH_TST:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_TST), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shamt GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 62633, GIR_EraseRootFromParent_Done, // Label 918: @28025 GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(28086), // Rule ID 65016 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt), 1:{ *:[i32] }) => (BEXTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BEXTI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shamt GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65016, GIR_EraseRootFromParent_Done, // Label 919: @28086 GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(28147), // Rule ID 65017 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode1), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm5), // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$shamt), 1:{ *:[i32] }) => (BEXTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimm5>>:$shamt) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BEXTI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shamt GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65017, GIR_EraseRootFromParent_Done, // Label 920: @28147 GIM_Try, /*On fail goto*//*Label 921*/ GIMT_Encode4(28205), // Rule ID 2297 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode1), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*NumInsns*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shiftMaskXLen:{ *:[i32] } GPR:{ *:[i32] }:$rs2)), 1:{ *:[i32] }) => (BEXT:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BEXT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2297, GIR_EraseRootFromParent_Done, // Label 921: @28205 GIM_Try, /*On fail goto*//*Label 922*/ GIMT_Encode4(28263), // Rule ID 65012 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*NumInsns*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)), 1:{ *:[i32] }) => (BEXT:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BEXT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65012, GIR_EraseRootFromParent_Done, // Label 922: @28263 GIM_Try, /*On fail goto*//*Label 923*/ GIMT_Encode4(28315), // Rule ID 2291 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode1), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ROTL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-2), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } (rotl:{ *:[i32] } -2:{ *:[i32] }, GPR:{ *:[i32] }:$rs2), GPR:{ *:[i32] }:$rs1) => (BCLR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2291, GIR_EraseRootFromParent_Done, // Label 923: @28315 GIM_Try, /*On fail goto*//*Label 924*/ GIMT_Encode4(28367), // Rule ID 65009 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ROTL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-2), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } (rotl:{ *:[i32] } -2:{ *:[i32] }, GPR:{ *:[i64] }:$rs2), GPR:{ *:[i32] }:$rs1) => (BCLR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65009, GIR_EraseRootFromParent_Done, // Label 924: @28367 GIM_Try, /*On fail goto*//*Label 925*/ GIMT_Encode4(28419), // Rule ID 65115 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode1), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] }), GPR:{ *:[i32] }:$rs1) => (ANDN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65115, GIR_EraseRootFromParent_Done, // Label 925: @28419 GIM_Try, /*On fail goto*//*Label 926*/ GIMT_Encode4(28471), // Rule ID 73681 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] }), GPR:{ *:[i32] }:$rs1) => (ANDN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73681, GIR_EraseRootFromParent_Done, // Label 926: @28471 GIM_Try, /*On fail goto*//*Label 927*/ GIMT_Encode4(28523), // Rule ID 73682 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode1), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] }), GPR:{ *:[i32] }:$rs1) => (ANDN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73682, GIR_EraseRootFromParent_Done, // Label 927: @28523 GIM_Try, /*On fail goto*//*Label 928*/ GIMT_Encode4(28575), // Rule ID 65125 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ROTL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-2), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (rotl:{ *:[i32] } -2:{ *:[i32] }, GPR:{ *:[i32] }:$rs2)) => (BCLR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65125, GIR_EraseRootFromParent_Done, // Label 928: @28575 GIM_Try, /*On fail goto*//*Label 929*/ GIMT_Encode4(28627), // Rule ID 73711 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ROTL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-2), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (rotl:{ *:[i32] } -2:{ *:[i32] }, GPR:{ *:[i64] }:$rs2)) => (BCLR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 73711, GIR_EraseRootFromParent_Done, // Label 929: @28627 GIM_Try, /*On fail goto*//*Label 930*/ GIMT_Encode4(28679), // Rule ID 2271 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] })) => (ANDN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2271, GIR_EraseRootFromParent_Done, // Label 930: @28679 GIM_Try, /*On fail goto*//*Label 931*/ GIMT_Encode4(28731), // Rule ID 64967 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] })) => (ANDN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64967, GIR_EraseRootFromParent_Done, // Label 931: @28731 GIM_Try, /*On fail goto*//*Label 932*/ GIMT_Encode4(28783), // Rule ID 64968 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_IsRV64_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] })) => (ANDN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64968, GIR_EraseRootFromParent_Done, // Label 932: @28783 GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(28815), // Rule ID 64547 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 65535:{ *:[i32] }) => (CV_EXTHZ:{ *:[i32] } GPR:{ *:[i32] }:$rs1) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_EXTHZ), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64547, GIR_EraseRootFromParent_Done, // Label 933: @28815 GIM_Try, /*On fail goto*//*Label 934*/ GIMT_Encode4(28847), // Rule ID 2369 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_IsRV32_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs, 65535:{ *:[i32] }) => (ZEXT_H_RV32:{ *:[i32] } GPR:{ *:[i32] }:$rs) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ZEXT_H_RV32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2369, GIR_EraseRootFromParent_Done, // Label 934: @28847 GIM_Try, /*On fail goto*//*Label 935*/ GIMT_Encode4(28879), // Rule ID 2370 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_IsRV32_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs, 65535:{ *:[i32] }) => (ZEXT_H_RV32:{ *:[i32] } GPR:{ *:[i32] }:$rs) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ZEXT_H_RV32), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2370, GIR_EraseRootFromParent_Done, // Label 935: @28879 GIM_Try, /*On fail goto*//*Label 936*/ GIMT_Encode4(28917), // Rule ID 2372 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbkb_IsRV32_NoStdExtZbb_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs, 65535:{ *:[i32] }) => (PACK:{ *:[i32] } GPR:{ *:[i32] }:$rs, X0:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PACK), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2372, GIR_EraseRootFromParent_Done, // Label 936: @28917 GIM_Try, /*On fail goto*//*Label 937*/ GIMT_Encode4(28955), // Rule ID 2373 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbkb_IsRV32_NoStdExtZbb_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs, 65535:{ *:[i32] }) => (PACK:{ *:[i32] } GPR:{ *:[i32] }:$rs, X0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PACK), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2373, GIR_EraseRootFromParent_Done, // Label 937: @28955 GIM_Try, /*On fail goto*//*Label 938*/ GIMT_Encode4(28987), // Rule ID 64963 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs, 65535:{ *:[i32] }) => (ZEXT_H_RV64:{ *:[i32] } GPR:{ *:[i32] }:$rs) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ZEXT_H_RV64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64963, GIR_EraseRootFromParent_Done, // Label 938: @28987 GIM_Try, /*On fail goto*//*Label 939*/ GIMT_Encode4(29019), // Rule ID 64964 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_IsRV64_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs, 65535:{ *:[i32] }) => (ZEXT_H_RV64:{ *:[i32] } GPR:{ *:[i32] }:$rs) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ZEXT_H_RV64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64964, GIR_EraseRootFromParent_Done, // Label 939: @29019 GIM_Try, /*On fail goto*//*Label 940*/ GIMT_Encode4(29057), // Rule ID 64965 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbkb_IsRV64_NoStdExtZbb_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs, 65535:{ *:[i32] }) => (PACKW:{ *:[i32] } GPR:{ *:[i32] }:$rs, X0:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PACKW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64965, GIR_EraseRootFromParent_Done, // Label 940: @29057 GIM_Try, /*On fail goto*//*Label 941*/ GIMT_Encode4(29095), // Rule ID 64966 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbkb_IsRV64_NoStdExtZbb_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs, 65535:{ *:[i32] }) => (PACKW:{ *:[i32] } GPR:{ *:[i32] }:$rs, X0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PACKW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64966, GIR_EraseRootFromParent_Done, // Label 941: @29095 GIM_Try, /*On fail goto*//*Label 942*/ GIMT_Encode4(29133), // Rule ID 79 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm) => (ANDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 79, GIR_EraseRootFromParent_Done, // Label 942: @29133 GIM_Try, /*On fail goto*//*Label 943*/ GIMT_Encode4(29173), // Rule ID 64728 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12i32), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12i32>>:$imm) => (ANDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (as_i64imm:{ *:[i64] } ?:{ *:[i32] }:$imm)) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderImm), // imm GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64728, GIR_EraseRootFromParent_Done, // Label 943: @29173 GIM_Try, /*On fail goto*//*Label 944*/ GIMT_Encode4(29196), // Rule ID 77 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (AND:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AND), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 77, GIR_Done, // Label 944: @29196 GIM_Try, /*On fail goto*//*Label 945*/ GIMT_Encode4(29219), // Rule ID 64718 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (AND:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AND), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64718, GIR_Done, // Label 945: @29219 GIM_Try, /*On fail goto*//*Label 946*/ GIMT_Encode4(29242), // Rule ID 64719 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (AND:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AND), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64719, GIR_Done, // Label 946: @29242 GIM_Reject, // Label 912: @29243 GIM_Reject, // Label 881: @29244 GIM_Try, /*On fail goto*//*Label 947*/ GIMT_Encode4(30190), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_Try, /*On fail goto*//*Label 948*/ GIMT_Encode4(29334), // Rule ID 2288 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 1, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), // (and:{ *:[i64] } (xor:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)), -1:{ *:[i64] }), GPR:{ *:[i64] }:$rs1) => (BCLR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2288, GIR_EraseRootFromParent_Done, // Label 948: @29334 GIM_Try, /*On fail goto*//*Label 949*/ GIMT_Encode4(29409), // Rule ID 65122 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 1, GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/2, GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (xor:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)), -1:{ *:[i64] })) => (BCLR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65122, GIR_EraseRootFromParent_Done, // Label 949: @29409 GIM_Try, /*On fail goto*//*Label 950*/ GIMT_Encode4(29479), // Rule ID 65013 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_IsRV64_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*NumInsns*/2, GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), // (and:{ *:[i64] } (anyext:{ *:[i64] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2))), 1:{ *:[i64] }) => (BEXT:{ *:[i64] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BEXT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs1 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65013, GIR_EraseRootFromParent_Done, // Label 950: @29479 GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(29540), // Rule ID 2308 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[i64] } (srl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt), 1:{ *:[i64] }) => (BEXTI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BEXTI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shamt GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2308, GIR_EraseRootFromParent_Done, // Label 951: @29540 GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(29601), // Rule ID 62632 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXTHeadBs_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimmlog2xlen), // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[i64] } (srl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt), 1:{ *:[i64] }) => (TH_TST:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::TH_TST), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shamt GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 62632, GIR_EraseRootFromParent_Done, // Label 952: @29601 GIM_Try, /*On fail goto*//*Label 953*/ GIMT_Encode4(29659), // Rule ID 2296 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, GIM_CheckIsSafeToFold, /*NumInsns*/1, GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_GIShiftMaskXLen), // (and:{ *:[i64] } (srl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (shiftMaskXLen:{ *:[i64] } GPR:{ *:[i64] }:$rs2)), 1:{ *:[i64] }) => (BEXT:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BEXT), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2296, GIR_EraseRootFromParent_Done, // Label 953: @29659 GIM_Try, /*On fail goto*//*Label 954*/ GIMT_Encode4(29711), // Rule ID 2290 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ROTL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-2), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i64] } (rotl:{ *:[i64] } -2:{ *:[i64] }, GPR:{ *:[i64] }:$rs2), GPR:{ *:[i64] }:$rs1) => (BCLR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2290, GIR_EraseRootFromParent_Done, // Label 954: @29711 GIM_Try, /*On fail goto*//*Label 955*/ GIMT_Encode4(29763), // Rule ID 65114 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i64] } (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs2, -1:{ *:[i64] }), GPR:{ *:[i64] }:$rs1) => (ANDN:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65114, GIR_EraseRootFromParent_Done, // Label 955: @29763 GIM_Try, /*On fail goto*//*Label 956*/ GIMT_Encode4(29815), // Rule ID 65124 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbs_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ROTL), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-2), GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (rotl:{ *:[i64] } -2:{ *:[i64] }, GPR:{ *:[i64] }:$rs2)) => (BCLR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::BCLR), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 65124, GIR_EraseRootFromParent_Done, // Label 956: @29815 GIM_Try, /*On fail goto*//*Label 957*/ GIMT_Encode4(29867), // Rule ID 2270 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbbOrZbkb_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs2, -1:{ *:[i64] })) => (ANDN:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDN), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2270, GIR_EraseRootFromParent_Done, // Label 957: @29867 GIM_Try, /*On fail goto*//*Label 958*/ GIMT_Encode4(29899), // Rule ID 64546 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVendorXCValu_IsRV32_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 65535:{ *:[i64] }) => (CV_EXTHZ:{ *:[i64] } GPR:{ *:[i64] }:$rs1) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::CV_EXTHZ), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 64546, GIR_EraseRootFromParent_Done, // Label 958: @29899 GIM_Try, /*On fail goto*//*Label 959*/ GIMT_Encode4(29956), // Rule ID 241 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsRV64_NotHasStdExtZba_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294967295), // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }) => (SRLI:{ *:[i64] } (SLLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 32:{ *:[i64] }), 32:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SLLI), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 GIR_AddImm8, /*InsnID*/1, /*Imm*/32, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SRLI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_AddImm8, /*InsnID*/0, /*Imm*/32, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 241, GIR_EraseRootFromParent_Done, // Label 959: @29956 GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(29988), // Rule ID 2371 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbb_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs, 65535:{ *:[i64] }) => (ZEXT_H_RV64:{ *:[i64] } GPR:{ *:[i64] }:$rs) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ZEXT_H_RV64), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2371, GIR_EraseRootFromParent_Done, // Label 960: @29988 GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(30026), // Rule ID 2374 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZbkb_IsRV64_NoStdExtZbb_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs, 65535:{ *:[i64] }) => (PACKW:{ *:[i64] } GPR:{ *:[i64] }:$rs, X0:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PACKW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2374, GIR_EraseRootFromParent_Done, // Label 961: @30026 GIM_Try, /*On fail goto*//*Label 962*/ GIMT_Encode4(30064), // Rule ID 2417 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294967295), // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs, 4294967295:{ *:[i64] }) => (ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs, X0:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ADD_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(RISCV::X0), /*AddRegisterRegFlags*/GIMT_Encode2(0), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2417, GIR_EraseRootFromParent_Done, // Label 962: @30064 GIM_Try, /*On fail goto*//*Label 963*/ GIMT_Encode4(30102), // Rule ID 78 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm12), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm) => (ANDI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::ANDI), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 78, GIR_EraseRootFromParent_Done, // Label 963: @30102 GIM_Try, /*On fail goto*//*Label 964*/ GIMT_Encode4(30166), // Rule ID 2414 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdExtZba_IsRV64_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_Shifted32OnesMask), // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*NumInsns*/1, // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_Shifted32OnesMask>><<X:TrailingZeros>>:$mask) => (SLLI_UW:{ *:[i64] } (SRLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (TrailingZeros:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_Shifted32OnesMask>>:$mask)), (TrailingZeros:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_Shifted32OnesMask>>:$mask)) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(RISCV::SRLI), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderTrailingZeros), // mask GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::SLLI_UW), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderTrailingZeros), // mask GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 2414, GIR_EraseRootFromParent_Done, // Label 964: @30166 GIM_Try, /*On fail goto*//*Label 965*/ GIMT_Encode4(30189), // Rule ID 76 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::GPRRegClassID), // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (AND:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(RISCV::AND), GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 76, GIR_Done, // Label 965: @30189 GIM_Reject, // Label 947: @30190 GIM_Reject, // Label 882: @30191 GIM_Try, /*On fail goto*//*Label 966*/ GIMT_Encode4(30801), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 967*/ GIMT_Encode4(30272), // Rule ID 71178 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv1i1] }:$rs2), VR:{ *:[nxv1i1] }:$rs1) => (PseudoVMANDN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71178, GIR_EraseRootFromParent_Done, // Label 967: @30272 GIM_Try, /*On fail goto*//*Label 968*/ GIMT_Encode4(30338), // Rule ID 71179 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv1i1] }:$rs2), VR:{ *:[nxv1i1] }:$rs1) => (PseudoVMANDN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71179, GIR_EraseRootFromParent_Done, // Label 968: @30338 GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(30404), // Rule ID 71176 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv1i1] }:$rs1) => (PseudoVMANDN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71176, GIR_EraseRootFromParent_Done, // Label 969: @30404 GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(30470), // Rule ID 71177 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv1i1] }:$rs1) => (PseudoVMANDN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71177, GIR_EraseRootFromParent_Done, // Label 970: @30470 GIM_Try, /*On fail goto*//*Label 971*/ GIMT_Encode4(30536), // Rule ID 71174 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv1i1] }:$rs2)) => (PseudoVMANDN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71174, GIR_EraseRootFromParent_Done, // Label 971: @30536 GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(30602), // Rule ID 71175 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, (xor:{ *:[nxv1i1] } (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv1i1] }:$rs2)) => (PseudoVMANDN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71175, GIR_EraseRootFromParent_Done, // Label 972: @30602 GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(30668), // Rule ID 53354 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i64] }))) => (PseudoVMANDN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 53354, GIR_EraseRootFromParent_Done, // Label 973: @30668 GIM_Try, /*On fail goto*//*Label 974*/ GIMT_Encode4(30734), // Rule ID 53355 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv1i1] } srcvalue:{ *:[i32] }))) => (PseudoVMANDN_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 53355, GIR_EraseRootFromParent_Done, // Label 974: @30734 GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(30767), // Rule ID 53342 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), // (and:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2) => (PseudoVMAND_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAND_MM_MF8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 53342, GIR_EraseRootFromParent_Done, // Label 975: @30767 GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(30800), // Rule ID 53343 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), // (and:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2) => (PseudoVMAND_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAND_MM_MF8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 53343, GIR_EraseRootFromParent_Done, // Label 976: @30800 GIM_Reject, // Label 966: @30801 GIM_Reject, // Label 883: @30802 GIM_Try, /*On fail goto*//*Label 977*/ GIMT_Encode4(30916), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 978*/ GIMT_Encode4(30870), // Rule ID 47838 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (and:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVAND_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47838, GIR_EraseRootFromParent_Done, // Label 978: @30870 GIM_Try, /*On fail goto*//*Label 979*/ GIMT_Encode4(30915), // Rule ID 47839 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (and:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2) => (PseudoVAND_VV_MF8:{ *:[nxv1i8] } (IMPLICIT_DEF:{ *:[nxv1i8] }), VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF8), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47839, GIR_EraseRootFromParent_Done, // Label 979: @30915 GIM_Reject, // Label 977: @30916 GIM_Reject, // Label 884: @30917 GIM_Try, /*On fail goto*//*Label 980*/ GIMT_Encode4(31031), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 981*/ GIMT_Encode4(30985), // Rule ID 47850 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (and:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVAND_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47850, GIR_EraseRootFromParent_Done, // Label 981: @30985 GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(31030), // Rule ID 47851 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (and:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2) => (PseudoVAND_VV_MF4:{ *:[nxv1i16] } (IMPLICIT_DEF:{ *:[nxv1i16] }), VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47851, GIR_EraseRootFromParent_Done, // Label 982: @31030 GIM_Reject, // Label 980: @31031 GIM_Reject, // Label 885: @31032 GIM_Try, /*On fail goto*//*Label 983*/ GIMT_Encode4(31146), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(31100), // Rule ID 47858 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (and:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVAND_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47858, GIR_EraseRootFromParent_Done, // Label 984: @31100 GIM_Try, /*On fail goto*//*Label 985*/ GIMT_Encode4(31145), // Rule ID 47859 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (and:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2) => (PseudoVAND_VV_MF2:{ *:[nxv1i32] } (IMPLICIT_DEF:{ *:[nxv1i32] }), VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47859, GIR_EraseRootFromParent_Done, // Label 985: @31145 GIM_Reject, // Label 983: @31146 GIM_Reject, // Label 886: @31147 GIM_Try, /*On fail goto*//*Label 986*/ GIMT_Encode4(31261), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 987*/ GIMT_Encode4(31215), // Rule ID 47874 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (and:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVAND_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47874, GIR_EraseRootFromParent_Done, // Label 987: @31215 GIM_Try, /*On fail goto*//*Label 988*/ GIMT_Encode4(31260), // Rule ID 47875 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (and:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2) => (PseudoVAND_VV_M1:{ *:[nxv1i64] } (IMPLICIT_DEF:{ *:[nxv1i64] }), VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47875, GIR_EraseRootFromParent_Done, // Label 988: @31260 GIM_Reject, // Label 986: @31261 GIM_Reject, // Label 887: @31262 GIM_Try, /*On fail goto*//*Label 989*/ GIMT_Encode4(31872), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 990*/ GIMT_Encode4(31343), // Rule ID 71206 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv2i1] }:$rs2), VR:{ *:[nxv2i1] }:$rs1) => (PseudoVMANDN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71206, GIR_EraseRootFromParent_Done, // Label 990: @31343 GIM_Try, /*On fail goto*//*Label 991*/ GIMT_Encode4(31409), // Rule ID 71207 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv2i1] }:$rs2), VR:{ *:[nxv2i1] }:$rs1) => (PseudoVMANDN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71207, GIR_EraseRootFromParent_Done, // Label 991: @31409 GIM_Try, /*On fail goto*//*Label 992*/ GIMT_Encode4(31475), // Rule ID 71204 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv2i1] }:$rs1) => (PseudoVMANDN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71204, GIR_EraseRootFromParent_Done, // Label 992: @31475 GIM_Try, /*On fail goto*//*Label 993*/ GIMT_Encode4(31541), // Rule ID 71205 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv2i1] }:$rs1) => (PseudoVMANDN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71205, GIR_EraseRootFromParent_Done, // Label 993: @31541 GIM_Try, /*On fail goto*//*Label 994*/ GIMT_Encode4(31607), // Rule ID 71202 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv2i1] }:$rs2)) => (PseudoVMANDN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71202, GIR_EraseRootFromParent_Done, // Label 994: @31607 GIM_Try, /*On fail goto*//*Label 995*/ GIMT_Encode4(31673), // Rule ID 71203 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, (xor:{ *:[nxv2i1] } (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv2i1] }:$rs2)) => (PseudoVMANDN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71203, GIR_EraseRootFromParent_Done, // Label 995: @31673 GIM_Try, /*On fail goto*//*Label 996*/ GIMT_Encode4(31739), // Rule ID 53372 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i64] }))) => (PseudoVMANDN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 53372, GIR_EraseRootFromParent_Done, // Label 996: @31739 GIM_Try, /*On fail goto*//*Label 997*/ GIMT_Encode4(31805), // Rule ID 53373 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv2i1] } srcvalue:{ *:[i32] }))) => (PseudoVMANDN_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 53373, GIR_EraseRootFromParent_Done, // Label 997: @31805 GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(31838), // Rule ID 53360 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), // (and:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2) => (PseudoVMAND_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAND_MM_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 53360, GIR_EraseRootFromParent_Done, // Label 998: @31838 GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(31871), // Rule ID 53361 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), // (and:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2) => (PseudoVMAND_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAND_MM_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 53361, GIR_EraseRootFromParent_Done, // Label 999: @31871 GIM_Reject, // Label 989: @31872 GIM_Reject, // Label 888: @31873 GIM_Try, /*On fail goto*//*Label 1000*/ GIMT_Encode4(31987), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 1001*/ GIMT_Encode4(31941), // Rule ID 47842 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (and:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVAND_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47842, GIR_EraseRootFromParent_Done, // Label 1001: @31941 GIM_Try, /*On fail goto*//*Label 1002*/ GIMT_Encode4(31986), // Rule ID 47843 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (and:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2) => (PseudoVAND_VV_MF4:{ *:[nxv2i8] } (IMPLICIT_DEF:{ *:[nxv2i8] }), VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47843, GIR_EraseRootFromParent_Done, // Label 1002: @31986 GIM_Reject, // Label 1000: @31987 GIM_Reject, // Label 889: @31988 GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(32102), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(32056), // Rule ID 47854 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (and:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVAND_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47854, GIR_EraseRootFromParent_Done, // Label 1004: @32056 GIM_Try, /*On fail goto*//*Label 1005*/ GIMT_Encode4(32101), // Rule ID 47855 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (and:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2) => (PseudoVAND_VV_MF2:{ *:[nxv2i16] } (IMPLICIT_DEF:{ *:[nxv2i16] }), VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47855, GIR_EraseRootFromParent_Done, // Label 1005: @32101 GIM_Reject, // Label 1003: @32102 GIM_Reject, // Label 890: @32103 GIM_Try, /*On fail goto*//*Label 1006*/ GIMT_Encode4(32217), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 1007*/ GIMT_Encode4(32171), // Rule ID 47870 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (and:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVAND_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47870, GIR_EraseRootFromParent_Done, // Label 1007: @32171 GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(32216), // Rule ID 47871 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (and:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2) => (PseudoVAND_VV_M1:{ *:[nxv2i32] } (IMPLICIT_DEF:{ *:[nxv2i32] }), VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47871, GIR_EraseRootFromParent_Done, // Label 1008: @32216 GIM_Reject, // Label 1006: @32217 GIM_Reject, // Label 891: @32218 GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(32332), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 1010*/ GIMT_Encode4(32286), // Rule ID 47914 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (and:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVAND_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47914, GIR_EraseRootFromParent_Done, // Label 1010: @32286 GIM_Try, /*On fail goto*//*Label 1011*/ GIMT_Encode4(32331), // Rule ID 47915 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (and:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2) => (PseudoVAND_VV_M2:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv2i64] }), VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv2s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47915, GIR_EraseRootFromParent_Done, // Label 1011: @32331 GIM_Reject, // Label 1009: @32332 GIM_Reject, // Label 892: @32333 GIM_Try, /*On fail goto*//*Label 1012*/ GIMT_Encode4(32943), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 1013*/ GIMT_Encode4(32414), // Rule ID 71234 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv4i1] }:$rs2), VR:{ *:[nxv4i1] }:$rs1) => (PseudoVMANDN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71234, GIR_EraseRootFromParent_Done, // Label 1013: @32414 GIM_Try, /*On fail goto*//*Label 1014*/ GIMT_Encode4(32480), // Rule ID 71235 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv4i1] }:$rs2), VR:{ *:[nxv4i1] }:$rs1) => (PseudoVMANDN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71235, GIR_EraseRootFromParent_Done, // Label 1014: @32480 GIM_Try, /*On fail goto*//*Label 1015*/ GIMT_Encode4(32546), // Rule ID 71232 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv4i1] }:$rs1) => (PseudoVMANDN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71232, GIR_EraseRootFromParent_Done, // Label 1015: @32546 GIM_Try, /*On fail goto*//*Label 1016*/ GIMT_Encode4(32612), // Rule ID 71233 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] })), VR:{ *:[nxv4i1] }:$rs1) => (PseudoVMANDN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71233, GIR_EraseRootFromParent_Done, // Label 1016: @32612 GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(32678), // Rule ID 71230 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv4i1] }:$rs2)) => (PseudoVMANDN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71230, GIR_EraseRootFromParent_Done, // Label 1017: @32678 GIM_Try, /*On fail goto*//*Label 1018*/ GIMT_Encode4(32744), // Rule ID 71231 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, (xor:{ *:[nxv4i1] } (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv4i1] }:$rs2)) => (PseudoVMANDN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71231, GIR_EraseRootFromParent_Done, // Label 1018: @32744 GIM_Try, /*On fail goto*//*Label 1019*/ GIMT_Encode4(32810), // Rule ID 53390 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i64] }))) => (PseudoVMANDN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 53390, GIR_EraseRootFromParent_Done, // Label 1019: @32810 GIM_Try, /*On fail goto*//*Label 1020*/ GIMT_Encode4(32876), // Rule ID 53391 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv4i1] } srcvalue:{ *:[i32] }))) => (PseudoVMANDN_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 53391, GIR_EraseRootFromParent_Done, // Label 1020: @32876 GIM_Try, /*On fail goto*//*Label 1021*/ GIMT_Encode4(32909), // Rule ID 53378 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), // (and:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2) => (PseudoVMAND_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAND_MM_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 53378, GIR_EraseRootFromParent_Done, // Label 1021: @32909 GIM_Try, /*On fail goto*//*Label 1022*/ GIMT_Encode4(32942), // Rule ID 53379 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), // (and:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2) => (PseudoVMAND_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMAND_MM_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 53379, GIR_EraseRootFromParent_Done, // Label 1022: @32942 GIM_Reject, // Label 1012: @32943 GIM_Reject, // Label 893: @32944 GIM_Try, /*On fail goto*//*Label 1023*/ GIMT_Encode4(33058), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s8, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s8, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 1024*/ GIMT_Encode4(33012), // Rule ID 47846 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (and:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVAND_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47846, GIR_EraseRootFromParent_Done, // Label 1024: @33012 GIM_Try, /*On fail goto*//*Label 1025*/ GIMT_Encode4(33057), // Rule ID 47847 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (and:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2) => (PseudoVAND_VV_MF2:{ *:[nxv4i8] } (IMPLICIT_DEF:{ *:[nxv4i8] }), VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_MF2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47847, GIR_EraseRootFromParent_Done, // Label 1025: @33057 GIM_Reject, // Label 1023: @33058 GIM_Reject, // Label 894: @33059 GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(33173), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(33127), // Rule ID 47866 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (and:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVAND_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47866, GIR_EraseRootFromParent_Done, // Label 1027: @33127 GIM_Try, /*On fail goto*//*Label 1028*/ GIMT_Encode4(33172), // Rule ID 47867 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (and:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2) => (PseudoVAND_VV_M1:{ *:[nxv4i16] } (IMPLICIT_DEF:{ *:[nxv4i16] }), VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s16, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/4, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47867, GIR_EraseRootFromParent_Done, // Label 1028: @33172 GIM_Reject, // Label 1026: @33173 GIM_Reject, // Label 895: @33174 GIM_Try, /*On fail goto*//*Label 1029*/ GIMT_Encode4(33288), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM2RegClassID), GIM_Try, /*On fail goto*//*Label 1030*/ GIMT_Encode4(33242), // Rule ID 47902 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), // (and:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVAND_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47902, GIR_EraseRootFromParent_Done, // Label 1030: @33242 GIM_Try, /*On fail goto*//*Label 1031*/ GIMT_Encode4(33287), // Rule ID 47903 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), // (and:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2) => (PseudoVAND_VV_M2:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv4i32] }), VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M2), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/5, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47903, GIR_EraseRootFromParent_Done, // Label 1031: @33287 GIM_Reject, // Label 1029: @33288 GIM_Reject, // Label 896: @33289 GIM_Try, /*On fail goto*//*Label 1032*/ GIMT_Encode4(33403), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s64, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s64, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRM4RegClassID), GIM_Try, /*On fail goto*//*Label 1033*/ GIMT_Encode4(33357), // Rule ID 47918 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode0), // (and:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVAND_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 3:{ *:[i64] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47918, GIR_EraseRootFromParent_Done, // Label 1033: @33357 GIM_Try, /*On fail goto*//*Label 1034*/ GIMT_Encode4(33402), // Rule ID 47919 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructionsI64_HwMode1), // (and:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2) => (PseudoVAND_VV_M4:{ *:[nxv4i64] } (IMPLICIT_DEF:{ *:[nxv4i64] }), VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 3:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv4s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVAND_VV_M4), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, GIR_RootToRootCopy, /*OpIdx*/1, // rs1 GIR_RootToRootCopy, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/6, GIR_AddImm8, /*InsnID*/0, /*Imm*/3, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 47919, GIR_EraseRootFromParent_Done, // Label 1034: @33402 GIM_Reject, // Label 1032: @33403 GIM_Reject, // Label 897: @33404 GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(34014), GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1, GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1, GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_Try, /*On fail goto*//*Label 1036*/ GIMT_Encode4(33485), // Rule ID 71262 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] }), VR:{ *:[nxv8i1] }:$rs2), VR:{ *:[nxv8i1] }:$rs1) => (PseudoVMANDN_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71262, GIR_EraseRootFromParent_Done, // Label 1036: @33485 GIM_Try, /*On fail goto*//*Label 1037*/ GIMT_Encode4(33551), // Rule ID 71263 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i32] }), VR:{ *:[nxv8i1] }:$rs2), VR:{ *:[nxv8i1] }:$rs1) => (PseudoVMANDN_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71263, GIR_EraseRootFromParent_Done, // Label 1037: @33551 GIM_Try, /*On fail goto*//*Label 1038*/ GIMT_Encode4(33617), // Rule ID 71260 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode0), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold, /*NumInsns*/2, // (and:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs2, (riscv_vmset_vl:{ *:[nxv8i1] } srcvalue:{ *:[i64] })), VR:{ *:[nxv8i1] }:$rs1) => (PseudoVMANDN_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] }) GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(RISCV::PseudoVMANDN_MM_M1), GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] GIR_RootToRootCopy, /*OpIdx*/2, // rs1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), GIR_AddImm8, /*InsnID*/0, /*Imm*/0, GIR_RootConstrainSelectedInstOperands, // GIR_Coverage, 71260, GIR_EraseRootFromParent_Done, // Label 1038: @33617 GIM_Try, /*On fail goto*//*Label 1039*/ GIMT_Encode4(33683), // Rule ID 71261 // GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVInstructions_HwMode1), GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(RISCV::G_VMSET_VL), GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(RISCV::VRRegClassID), GIM_CheckIsSafeToFold<TRUNCATED>#undef GIMT_Encode2#undef GIMT_Encode4#undef GIMT_Encode8#endif // ifdef GET_GLOBALISEL_IMPL#ifdef GET_GLOBALISEL_PREDICATES_DECL#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL#ifdef GET_GLOBALISEL_PREDICATES_INIT#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT
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