#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
namespace llvm {
namespace SP {
enum { … };
}
}
#endif
#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM
namespace llvm {
namespace SP {
namespace Sched {
enum {
NoInstrModel = 0,
IIC_iu_instr = 1,
IIC_fpu_normal_instr = 2,
IIC_jmp_or_call = 3,
IIC_fpu_abs = 4,
IIC_fpu_fast_instr = 5,
IIC_fpu_divd = 6,
IIC_fpu_divs = 7,
IIC_fpu_muld = 8,
IIC_fpu_muls = 9,
IIC_fpu_negs = 10,
IIC_fpu_sqrtd = 11,
IIC_fpu_sqrts = 12,
IIC_fpu_stod = 13,
IIC_ldd = 14,
IIC_iu_or_fpu_instr = 15,
IIC_iu_div = 16,
IIC_smac_umac = 17,
IIC_iu_smul = 18,
IIC_st = 19,
IIC_std = 20,
IIC_iu_umul = 21,
SCHED_LIST_END = 22
};
}
}
}
#endif
#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
namespace llvm {
struct SparcInstrTable {
MCInstrDesc Insts[815];
static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
MCOperandInfo OperandInfo[544];
static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
MCPhysReg ImplicitOps[32];
};
}
#endif
#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC
namespace llvm {
static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
static constexpr unsigned SparcImpOpBase = sizeof SparcInstrTable::OperandInfo / (sizeof(MCPhysReg));
extern const SparcInstrTable SparcDescs = {
{
{ 814, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL },
{ 813, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0, 0x0ULL },
{ 812, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 811, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 810, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL },
{ 809, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 808, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 807, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 806, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 805, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 804, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 18, 375, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 803, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 18, 168, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 802, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 17, 375, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 801, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 17, 168, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 800, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 15, 375, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 799, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 15, 168, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 798, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 541, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 797, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 538, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 796, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 535, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 795, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 532, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 794, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 527, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 793, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 522, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 792, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 517, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 791, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 512, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 790, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 507, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 789, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 504, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 788, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 501, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 787, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 504, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 786, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 501, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 785, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 784, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 783, 1, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 782, 3, 1, 4, 21, 0, 1, SparcImpOpBase + 30, 176, 0, 0x0ULL },
{ 781, 3, 1, 4, 21, 0, 1, SparcImpOpBase + 30, 173, 0, 0x0ULL },
{ 780, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 779, 3, 1, 4, 21, 0, 2, SparcImpOpBase + 28, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 778, 3, 1, 4, 21, 0, 2, SparcImpOpBase + 28, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 777, 4, 1, 4, 17, 2, 2, SparcImpOpBase + 24, 405, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 776, 4, 1, 4, 17, 2, 2, SparcImpOpBase + 24, 401, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 775, 3, 1, 4, 16, 1, 1, SparcImpOpBase + 22, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 774, 3, 1, 4, 16, 1, 1, SparcImpOpBase + 22, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 773, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 772, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 771, 3, 1, 4, 16, 1, 2, SparcImpOpBase + 19, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 770, 3, 1, 4, 16, 1, 2, SparcImpOpBase + 19, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 769, 3, 0, 4, 0, 1, 0, SparcImpOpBase + 4, 398, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 768, 3, 0, 4, 0, 1, 0, SparcImpOpBase + 4, 494, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 767, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 766, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 765, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 764, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 763, 3, 0, 4, 0, 1, 0, SparcImpOpBase + 4, 398, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 762, 3, 0, 4, 0, 1, 0, SparcImpOpBase + 4, 494, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 761, 4, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 760, 4, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 759, 2, 0, 4, 3, 1, 0, SparcImpOpBase + 7, 13, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL },
{ 758, 4, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 497, 0, 0x0ULL },
{ 757, 3, 0, 4, 0, 1, 0, SparcImpOpBase + 4, 398, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 756, 3, 0, 4, 0, 1, 0, SparcImpOpBase + 4, 494, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 755, 2, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 35, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL },
{ 754, 1, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL },
{ 753, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 752, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 751, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 750, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 749, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 748, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 747, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 746, 4, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 490, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 745, 4, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 481, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 744, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 485, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 743, 4, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 481, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 742, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL },
{ 741, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0, 0x0ULL },
{ 740, 3, 1, 4, 1, 1, 1, SparcImpOpBase + 5, 176, 0, 0x0ULL },
{ 739, 3, 1, 4, 1, 1, 1, SparcImpOpBase + 5, 173, 0, 0x0ULL },
{ 738, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 737, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 736, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::HasPostISelHook), 0x0ULL },
{ 735, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::HasPostISelHook), 0x0ULL },
{ 734, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 416, 0|(1ULL<<MCID::MayStore), 0x0ULL },
{ 733, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 409, 0|(1ULL<<MCID::MayStore), 0x0ULL },
{ 732, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 478, 0|(1ULL<<MCID::MayStore), 0x0ULL },
{ 731, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 471, 0|(1ULL<<MCID::MayStore), 0x0ULL },
{ 730, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 10, 182, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 729, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 10, 35, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 728, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 474, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 727, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 471, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 726, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 468, 0|(1ULL<<MCID::MayStore), 0x0ULL },
{ 725, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 461, 0|(1ULL<<MCID::MayStore), 0x0ULL },
{ 724, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 464, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 723, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 461, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 722, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 416, 0|(1ULL<<MCID::MayStore), 0x0ULL },
{ 721, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 409, 0|(1ULL<<MCID::MayStore), 0x0ULL },
{ 720, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 412, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 719, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 409, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 718, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 458, 0|(1ULL<<MCID::MayStore), 0x0ULL },
{ 717, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 451, 0|(1ULL<<MCID::MayStore), 0x0ULL },
{ 716, 2, 0, 4, 19, 1, 0, SparcImpOpBase + 10, 182, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 715, 2, 0, 4, 19, 1, 0, SparcImpOpBase + 10, 35, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 714, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 454, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 713, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 451, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 712, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 448, 0|(1ULL<<MCID::MayStore), 0x0ULL },
{ 711, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 425, 0|(1ULL<<MCID::MayStore), 0x0ULL },
{ 710, 3, 0, 4, 20, 0, 0, SparcImpOpBase + 0, 445, 0|(1ULL<<MCID::MayStore), 0x0ULL },
{ 709, 3, 0, 4, 20, 0, 0, SparcImpOpBase + 0, 438, 0|(1ULL<<MCID::MayStore), 0x0ULL },
{ 708, 2, 0, 4, 20, 0, 1, SparcImpOpBase + 16, 182, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 707, 2, 0, 4, 20, 0, 1, SparcImpOpBase + 16, 35, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 706, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 441, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 705, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 438, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 704, 3, 0, 4, 20, 0, 0, SparcImpOpBase + 0, 435, 0|(1ULL<<MCID::MayStore), 0x0ULL },
{ 703, 3, 0, 4, 20, 0, 0, SparcImpOpBase + 0, 432, 0|(1ULL<<MCID::MayStore), 0x0ULL },
{ 702, 2, 0, 4, 20, 1, 0, SparcImpOpBase + 31, 182, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 701, 2, 0, 4, 20, 1, 0, SparcImpOpBase + 31, 35, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 700, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 428, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 699, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 425, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 698, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 422, 0|(1ULL<<MCID::MayStore), 0x0ULL },
{ 697, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 419, 0|(1ULL<<MCID::MayStore), 0x0ULL },
{ 696, 2, 0, 4, 19, 1, 0, SparcImpOpBase + 9, 182, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 695, 2, 0, 4, 19, 1, 0, SparcImpOpBase + 9, 35, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 694, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 416, 0|(1ULL<<MCID::MayStore), 0x0ULL },
{ 693, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 409, 0|(1ULL<<MCID::MayStore), 0x0ULL },
{ 692, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 412, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 691, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 409, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 690, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 689, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 412, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 688, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 409, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 687, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL },
{ 686, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 398, 0, 0x0ULL },
{ 685, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 395, 0, 0x0ULL },
{ 684, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 392, 0, 0x0ULL },
{ 683, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL },
{ 682, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 398, 0, 0x0ULL },
{ 681, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 395, 0, 0x0ULL },
{ 680, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 392, 0, 0x0ULL },
{ 679, 3, 1, 4, 18, 0, 1, SparcImpOpBase + 30, 176, 0, 0x0ULL },
{ 678, 3, 1, 4, 18, 0, 1, SparcImpOpBase + 30, 173, 0, 0x0ULL },
{ 677, 3, 1, 4, 18, 0, 2, SparcImpOpBase + 28, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 676, 3, 1, 4, 18, 0, 2, SparcImpOpBase + 28, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 675, 4, 1, 4, 17, 2, 2, SparcImpOpBase + 24, 405, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 674, 4, 1, 4, 17, 2, 2, SparcImpOpBase + 24, 401, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 673, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL },
{ 672, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 398, 0, 0x0ULL },
{ 671, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 395, 0, 0x0ULL },
{ 670, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 392, 0, 0x0ULL },
{ 669, 1, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 668, 0, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 667, 0, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 666, 2, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 168, 0, 0x0ULL },
{ 665, 3, 1, 4, 16, 1, 1, SparcImpOpBase + 22, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 664, 3, 1, 4, 16, 1, 1, SparcImpOpBase + 22, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 663, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 662, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 661, 3, 1, 4, 16, 1, 2, SparcImpOpBase + 19, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 660, 3, 1, 4, 16, 1, 2, SparcImpOpBase + 19, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 659, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 658, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 657, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 656, 2, 0, 4, 3, 0, 0, SparcImpOpBase + 0, 182, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 655, 2, 0, 4, 3, 0, 0, SparcImpOpBase + 0, 35, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 654, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 653, 1, 0, 4, 3, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },
{ 652, 1, 0, 4, 3, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 651, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 650, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 649, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 648, 1, 1, 4, 1, 1, 0, SparcImpOpBase + 18, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 647, 1, 1, 4, 1, 1, 0, SparcImpOpBase + 17, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 646, 1, 1, 4, 1, 1, 0, SparcImpOpBase + 15, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 645, 2, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 390, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 644, 1, 1, 4, 1, 1, 0, SparcImpOpBase + 16, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 643, 2, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 387, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 642, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 15, 375, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 641, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 15, 168, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 640, 3, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 639, 3, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 377, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 638, 4, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 380, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 637, 3, 0, 4, 1, 1, 0, SparcImpOpBase + 8, 377, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 636, 2, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 375, 0, 0x0ULL },
{ 635, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 634, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 633, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL },
{ 632, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0, 0x0ULL },
{ 631, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL },
{ 630, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 629, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 628, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 627, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 626, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 625, 0, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 624, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 179, 0, 0x0ULL },
{ 623, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0, 0x0ULL },
{ 622, 3, 1, 4, 1, 2, 2, SparcImpOpBase + 11, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 621, 3, 1, 4, 1, 2, 2, SparcImpOpBase + 11, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 620, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 373, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 619, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 359, 0, 0x0ULL },
{ 618, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 355, 0, 0x0ULL },
{ 617, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 373, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 616, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 353, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 615, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 353, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 614, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 368, 0, 0x0ULL },
{ 613, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 363, 0, 0x0ULL },
{ 612, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 359, 0, 0x0ULL },
{ 611, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 355, 0, 0x0ULL },
{ 610, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 359, 0, 0x0ULL },
{ 609, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 355, 0, 0x0ULL },
{ 608, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 353, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 607, 1, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 606, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 351, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 605, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 290, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 604, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 287, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 603, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 348, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 602, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 345, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 601, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 10, 182, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 600, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 10, 35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 599, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 279, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 598, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 345, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 597, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 290, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 596, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 287, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 595, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 594, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 287, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 593, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 290, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 592, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 287, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 591, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 590, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 287, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 589, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 348, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 588, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 345, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 587, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 279, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 586, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 345, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 585, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 290, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 584, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 287, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 583, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 582, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 287, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 581, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 290, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 580, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 287, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 579, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 578, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 287, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 577, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 290, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 576, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 287, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 575, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 574, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 287, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 573, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 342, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 572, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 335, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 571, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 338, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 570, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 335, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 569, 3, 1, 4, 15, 0, 0, SparcImpOpBase + 0, 332, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 568, 3, 1, 4, 15, 0, 0, SparcImpOpBase + 0, 325, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 567, 2, 0, 4, 15, 0, 1, SparcImpOpBase + 10, 182, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 566, 2, 0, 4, 15, 0, 1, SparcImpOpBase + 10, 35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 565, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 328, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 564, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 325, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 563, 3, 1, 4, 14, 0, 0, SparcImpOpBase + 0, 322, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 562, 3, 1, 4, 14, 0, 0, SparcImpOpBase + 0, 299, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 561, 3, 1, 4, 14, 0, 0, SparcImpOpBase + 0, 319, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 560, 3, 1, 4, 14, 0, 0, SparcImpOpBase + 0, 312, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 559, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 315, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 558, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 312, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 557, 3, 1, 4, 14, 0, 0, SparcImpOpBase + 0, 309, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 556, 3, 1, 4, 14, 0, 0, SparcImpOpBase + 0, 306, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 555, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 302, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 554, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 553, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 296, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 552, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 293, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 551, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 9, 182, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 550, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 9, 35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 549, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 548, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 287, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 547, 3, 1, 4, 3, 0, 0, SparcImpOpBase + 0, 290, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 546, 3, 1, 4, 3, 0, 0, SparcImpOpBase + 0, 287, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 545, 4, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 544, 4, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 279, 0|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 543, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 270, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 542, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 268, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 541, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 230, 0, 0x0ULL },
{ 540, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 232, 0, 0x0ULL },
{ 539, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0, 0x0ULL },
{ 538, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 537, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 536, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 535, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 534, 3, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 221, 0, 0x0ULL },
{ 533, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 218, 0, 0x0ULL },
{ 532, 3, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 190, 0, 0x0ULL },
{ 531, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 234, 0, 0x0ULL },
{ 530, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 236, 0, 0x0ULL },
{ 529, 2, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 216, 0, 0x0ULL },
{ 528, 2, 1, 4, 13, 0, 0, SparcImpOpBase + 0, 234, 0, 0x0ULL },
{ 527, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 526, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 525, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 524, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 523, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 522, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 521, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 520, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 519, 2, 1, 4, 12, 0, 0, SparcImpOpBase + 0, 216, 0, 0x0ULL },
{ 518, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 214, 0, 0x0ULL },
{ 517, 2, 1, 4, 11, 0, 0, SparcImpOpBase + 0, 212, 0, 0x0ULL },
{ 516, 3, 1, 4, 8, 0, 0, SparcImpOpBase + 0, 276, 0, 0x0ULL },
{ 515, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 514, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 513, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 512, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 511, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 272, 0, 0x0ULL },
{ 510, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 274, 0, 0x0ULL },
{ 509, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 274, 0, 0x0ULL },
{ 508, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 272, 0, 0x0ULL },
{ 507, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 506, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 505, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 504, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 503, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 502, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 501, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 500, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 499, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 498, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 497, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 496, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 495, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 494, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 493, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 492, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 491, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 490, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 489, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 488, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 270, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 487, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 268, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 486, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 485, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 484, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 483, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 482, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 481, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 480, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 479, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 478, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 477, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 476, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 475, 2, 1, 4, 10, 0, 0, SparcImpOpBase + 0, 216, 0, 0x0ULL },
{ 474, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 214, 0, 0x0ULL },
{ 473, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0, 0x0ULL },
{ 472, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 471, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 470, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 469, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 468, 3, 1, 4, 9, 0, 0, SparcImpOpBase + 0, 221, 0, 0x0ULL },
{ 467, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 218, 0, 0x0ULL },
{ 466, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 465, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 464, 3, 1, 4, 8, 0, 0, SparcImpOpBase + 0, 190, 0, 0x0ULL },
{ 463, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 462, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 461, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 460, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 459, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 458, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 264, 0, 0x0ULL },
{ 457, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 264, 0, 0x0ULL },
{ 456, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 264, 0, 0x0ULL },
{ 455, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 454, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 259, 0, 0x0ULL },
{ 453, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 254, 0, 0x0ULL },
{ 452, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 249, 0, 0x0ULL },
{ 451, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 245, 0, 0x0ULL },
{ 450, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 245, 0, 0x0ULL },
{ 449, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 245, 0, 0x0ULL },
{ 448, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 214, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 447, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 241, 0, 0x0ULL },
{ 446, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 241, 0, 0x0ULL },
{ 445, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 241, 0, 0x0ULL },
{ 444, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 443, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 442, 2, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 182, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 441, 2, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 440, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 439, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 438, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 437, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 436, 2, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 216, 0, 0x0ULL },
{ 435, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 236, 0, 0x0ULL },
{ 434, 2, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 234, 0, 0x0ULL },
{ 433, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 432, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 431, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 430, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 429, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 428, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0, 0x0ULL },
{ 427, 2, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 230, 0, 0x0ULL },
{ 426, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 232, 0, 0x0ULL },
{ 425, 2, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 230, 0, 0x0ULL },
{ 424, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 227, 0, 0x0ULL },
{ 423, 3, 1, 4, 7, 0, 0, SparcImpOpBase + 0, 221, 0, 0x0ULL },
{ 422, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 218, 0, 0x0ULL },
{ 421, 3, 1, 4, 6, 0, 0, SparcImpOpBase + 0, 190, 0, 0x0ULL },
{ 420, 2, 0, 4, 5, 0, 1, SparcImpOpBase + 3, 216, 0, 0x0ULL },
{ 419, 2, 0, 4, 5, 0, 1, SparcImpOpBase + 3, 216, 0, 0x0ULL },
{ 418, 2, 0, 4, 0, 0, 1, SparcImpOpBase + 3, 214, 0, 0x0ULL },
{ 417, 2, 0, 4, 0, 0, 1, SparcImpOpBase + 3, 214, 0, 0x0ULL },
{ 416, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 415, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 414, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 413, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 412, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 411, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 410, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 409, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 408, 2, 0, 4, 5, 0, 1, SparcImpOpBase + 3, 212, 0, 0x0ULL },
{ 407, 2, 0, 4, 5, 0, 1, SparcImpOpBase + 3, 212, 0, 0x0ULL },
{ 406, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 405, 2, 0, 4, 2, 1, 0, SparcImpOpBase + 3, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },
{ 404, 2, 0, 4, 2, 1, 0, SparcImpOpBase + 3, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },
{ 403, 2, 0, 4, 2, 1, 0, SparcImpOpBase + 3, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 402, 2, 0, 4, 2, 1, 0, SparcImpOpBase + 3, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },
{ 401, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 400, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 399, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 398, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 397, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 396, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 395, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 394, 3, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 221, 0, 0x0ULL },
{ 393, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 218, 0, 0x0ULL },
{ 392, 3, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 190, 0, 0x0ULL },
{ 391, 2, 1, 4, 4, 0, 0, SparcImpOpBase + 0, 216, 0, 0x0ULL },
{ 390, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 214, 0, 0x0ULL },
{ 389, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0, 0x0ULL },
{ 388, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 387, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 386, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 385, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 384, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 383, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 382, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 381, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 380, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 379, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 378, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 377, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 376, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 375, 1, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 211, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 374, 1, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 211, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 373, 1, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 211, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 372, 2, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 371, 2, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },
{ 370, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 369, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 8, 202, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 368, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 197, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 367, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 8, 193, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 366, 2, 0, 4, 3, 1, 0, SparcImpOpBase + 7, 182, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL },
{ 365, 2, 0, 4, 3, 1, 0, SparcImpOpBase + 7, 35, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL },
{ 364, 1, 0, 4, 3, 1, 0, SparcImpOpBase + 7, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL },
{ 363, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 362, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 361, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 360, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 359, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },
{ 358, 3, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 187, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 357, 3, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 187, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 356, 3, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 187, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 355, 3, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 187, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },
{ 354, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 353, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 352, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 351, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },
{ 350, 3, 0, 4, 2, 0, 0, SparcImpOpBase + 0, 184, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 349, 3, 0, 4, 2, 0, 0, SparcImpOpBase + 0, 184, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 348, 3, 0, 4, 2, 0, 0, SparcImpOpBase + 0, 184, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 347, 3, 0, 4, 2, 0, 0, SparcImpOpBase + 0, 184, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 346, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 345, 2, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },
{ 344, 2, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 35, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },
{ 343, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 342, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },
{ 341, 1, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },
{ 340, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 339, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 338, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 337, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL },
{ 336, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0, 0x0ULL },
{ 335, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL },
{ 334, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 333, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 332, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 331, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 330, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 329, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 328, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 327, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL },
{ 326, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0, 0x0ULL },
{ 325, 3, 1, 4, 0, 1, 1, SparcImpOpBase + 5, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 324, 3, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 323, 3, 1, 4, 1, 1, 1, SparcImpOpBase + 5, 176, 0, 0x0ULL },
{ 322, 3, 1, 4, 1, 1, 1, SparcImpOpBase + 5, 173, 0, 0x0ULL },
{ 321, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 320, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 319, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0, 0x0ULL },
{ 318, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0, 0x0ULL },
{ 317, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 170, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 316, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 168, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 315, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },
{ 314, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },
{ 313, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },
{ 312, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 160, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },
{ 311, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 160, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },
{ 310, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 160, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },
{ 309, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },
{ 308, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },
{ 307, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },
{ 306, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },
{ 305, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },
{ 304, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },
{ 303, 1, 1, 4, 0, 0, 1, SparcImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 302, 2, 0, 4, 0, 1, 1, SparcImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 301, 2, 0, 4, 0, 1, 1, SparcImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 300, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 299, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 298, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 297, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 296, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 295, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 294, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 293, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 292, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 291, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 290, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 289, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 288, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 287, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 286, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 285, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 284, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 283, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 282, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 281, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 280, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 279, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 278, 3, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 277, 4, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 276, 4, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 275, 3, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 274, 4, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 273, 2, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 272, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 271, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 270, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 269, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 268, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 267, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 266, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 265, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 264, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 263, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 262, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 261, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 260, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 259, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 258, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 257, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 256, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 255, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 254, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 253, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 252, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 251, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 250, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 249, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 248, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 247, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 246, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 245, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 244, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 243, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 242, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 241, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 240, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 239, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 238, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 237, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 236, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 235, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 234, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 233, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 232, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 231, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 230, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 229, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 228, 3, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },
{ 227, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },
{ 226, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 225, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 224, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 223, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 222, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 221, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 220, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 219, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 218, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 217, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 216, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 215, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 214, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 213, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 212, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 211, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 210, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 209, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 208, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 207, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 206, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 205, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 204, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 203, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 202, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 201, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 200, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 199, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 198, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 197, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 196, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 195, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 194, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 193, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 192, 3, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 191, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 190, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 189, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 188, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 187, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 186, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 185, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 184, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 183, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 182, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 181, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 180, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 179, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 178, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 177, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 176, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 175, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 174, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 173, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 172, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 171, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 170, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 169, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 168, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 167, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 166, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 165, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 164, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 163, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 162, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 161, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 160, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 159, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 158, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 157, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 156, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 155, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 154, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 153, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 152, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 151, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 150, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 149, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 148, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 147, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 146, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 145, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 144, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 143, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 142, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 141, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 140, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 139, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 138, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 137, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 136, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 135, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 134, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 133, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 132, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 131, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 130, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 129, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 128, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 127, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 126, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 125, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },
{ 124, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },
{ 123, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },
{ 122, 2, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL },
{ 121, 4, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 94, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 120, 2, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 119, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 118, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 117, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 116, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 115, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 114, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 113, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 112, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 111, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 110, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 109, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 108, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 107, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 106, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 105, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 104, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 103, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 102, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 101, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 100, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 99, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 98, 5, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 97, 2, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },
{ 96, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 95, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 94, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 93, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 92, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 91, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },
{ 90, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 89, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 88, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 87, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 86, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 85, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 84, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 83, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 82, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 81, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 80, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 79, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 78, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 77, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },
{ 76, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },
{ 75, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },
{ 74, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },
{ 73, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 72, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },
{ 71, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 70, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 69, 5, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 68, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 67, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 66, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },
{ 65, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 64, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 63, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 62, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 61, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 60, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 59, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 58, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 57, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 56, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 55, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 54, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 53, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },
{ 52, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 51, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 50, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 49, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 48, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 47, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 46, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 45, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },
{ 44, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 43, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },
{ 42, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 41, 3, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 40, 2, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 39, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 38, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 37, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 36, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 35, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 34, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 33, 2, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 32, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 31, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 30, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 29, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL },
{ 28, 6, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 27, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 26, 2, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 25, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },
{ 24, 4, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 23, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },
{ 22, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },
{ 21, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },
{ 20, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },
{ 19, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },
{ 18, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },
{ 17, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },
{ 16, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },
{ 15, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },
{ 14, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },
{ 13, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },
{ 12, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 11, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 10, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },
{ 9, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 8, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo), 0x0ULL },
{ 7, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },
{ 6, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL },
{ 5, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL },
{ 4, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL },
{ 3, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL },
{ 2, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },
{ 1, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },
{ 0, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },
}, {
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
{ -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
{ SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
{ SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
{ SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
{ SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
{ SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
{ SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
{ SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
{ SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
{ SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
{ SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
{ SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
}, {
SP::O6, SP::O6,
SP::O7,
SP::FCC0,
SP::ICC,
SP::ICC, SP::ICC,
SP::O6,
SP::ASR3,
SP::CPSR,
SP::FSR,
SP::Y, SP::ICC, SP::Y, SP::ICC,
SP::PSR,
SP::FQ,
SP::TBR,
SP::WIM,
SP::Y, SP::Y, SP::ICC,
SP::Y, SP::Y,
SP::Y, SP::ASR18, SP::Y, SP::ASR18,
SP::Y, SP::ICC,
SP::Y,
SP::CPQ,
}
};
#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char SparcInstrNameData[] = {
"G_FLOG10\0"
"G_FEXP10\0"
"TA1\0"
"FSRC1\0"
"FANDNOT1\0"
"FNOT1\0"
"FORNOT1\0"
"FSRA32\0"
"FPSUB32\0"
"FPADD32\0"
"EDGE32\0"
"FCMPLE32\0"
"FCMPNE32\0"
"FPACK32\0"
"CMASK32\0"
"FSLL32\0"
"FSRL32\0"
"FCMPEQ32\0"
"FSLAS32\0"
"FCMPGT32\0"
"ARRAY32\0"
"FSRC2\0"
"G_FLOG2\0"
"G_FEXP2\0"
"FANDNOT2\0"
"FNOT2\0"
"FORNOT2\0"
"TA3\0"
"FPADD64\0"
"TA5\0"
"FSRA16\0"
"FPSUB16\0"
"FPADD16\0"
"EDGE16\0"
"FCMPLE16\0"
"FCMPNE16\0"
"FPACK16\0"
"CMASK16\0"
"FSLL16\0"
"FSRL16\0"
"FCHKSM16\0"
"FMEAN16\0"
"FCMPEQ16\0"
"FSLAS16\0"
"FCMPGT16\0"
"FMUL8X16\0"
"FMULD8ULX16\0"
"FMUL8ULX16\0"
"FMULD8SUX16\0"
"FMUL8SUX16\0"
"ARRAY16\0"
"EDGE8\0"
"CMASK8\0"
"ARRAY8\0"
"FBCONDA_V9\0"
"FBCOND_V9\0"
"FCMPD_V9\0"
"FCMPQ_V9\0"
"FCMPS_V9\0"
"BA\0"
"BPFCCA\0"
"BPICCA\0"
"BPXCCA\0"
"CBCONDA\0"
"FBCONDA\0"
"G_FMA\0"
"G_STRICT_FMA\0"
"BPRA\0"
"FALIGNADATA\0"
"G_FSUB\0"
"G_STRICT_FSUB\0"
"G_ATOMICRMW_FSUB\0"
"G_SUB\0"
"G_ATOMICRMW_SUB\0"
"ADDXCCC\0"
"BPFCC\0"
"V9FMOVD_FCC\0"
"SELECT_CC_DFP_FCC\0"
"SELECT_CC_QFP_FCC\0"
"SELECT_CC_FP_FCC\0"
"V9FMOVQ_FCC\0"
"V9FMOVS_FCC\0"
"SELECT_CC_Int_FCC\0"
"BPICC\0"
"FMOVD_ICC\0"
"SELECT_CC_DFP_ICC\0"
"SELECT_CC_QFP_ICC\0"
"SELECT_CC_FP_ICC\0"
"FMOVQ_ICC\0"
"FMOVS_ICC\0"
"SELECT_CC_Int_ICC\0"
"BPXCC\0"
"FMOVD_XCC\0"
"SELECT_CC_DFP_XCC\0"
"SELECT_CC_QFP_XCC\0"
"SELECT_CC_FP_XCC\0"
"FMOVQ_XCC\0"
"FMOVS_XCC\0"
"SELECT_CC_Int_XCC\0"
"G_INTRINSIC\0"
"G_FPTRUNC\0"
"G_INTRINSIC_TRUNC\0"
"G_TRUNC\0"
"G_BUILD_VECTOR_TRUNC\0"
"G_DYN_STACKALLOC\0"
"ADDXC\0"
"G_FMAD\0"
"G_INDEXED_SEXTLOAD\0"
"G_SEXTLOAD\0"
"G_INDEXED_ZEXTLOAD\0"
"G_ZEXTLOAD\0"
"G_INDEXED_LOAD\0"
"G_LOAD\0"
"FSUBD\0"
"FHSUBD\0"
"G_VECREDUCE_FADD\0"
"G_FADD\0"
"G_VECREDUCE_SEQ_FADD\0"
"G_STRICT_FADD\0"
"G_ATOMICRMW_FADD\0"
"G_VECREDUCE_ADD\0"
"G_ADD\0"
"G_PTR_ADD\0"
"G_ATOMICRMW_ADD\0"
"FADDD\0"
"FHADDD\0"
"FNHADDD\0"
"FNADDD\0"
"V9FCMPED\0"
"RESTORED\0"
"SAVED\0"
"FNEGD\0"
"FMULD\0"
"FNMULD\0"
"FSMULD\0"
"FNSMULD\0"
"FAND\0"
"FNAND\0"
"G_ATOMICRMW_NAND\0"
"FEXPAND\0"
"G_VECREDUCE_AND\0"
"G_AND\0"
"G_ATOMICRMW_AND\0"
"LIFETIME_END\0"
"CBCOND\0"
"FBCOND\0"
"G_BRCOND\0"
"G_ATOMICRMW_USUB_COND\0"
"G_LLROUND\0"
"G_LROUND\0"
"G_INTRINSIC_ROUND\0"
"G_INTRINSIC_FPTRUNC_ROUND\0"
"FITOD\0"
"FQTOD\0"
"FSTOD\0"
"FXTOD\0"
"MOVXTOD\0"
"V9FCMPD\0"
"FLCMPD\0"
"LOAD_STACK_GUARD\0"
"FMOVRD\0"
"FABSD\0"
"FSQRTD\0"
"FDIVD\0"
"FMOVD\0"
"PSEUDO_PROBE\0"
"G_SSUBE\0"
"G_USUBE\0"
"G_FENCE\0"
"ARITH_FENCE\0"
"REG_SEQUENCE\0"
"G_SADDE\0"
"G_UADDE\0"
"G_GET_FPMODE\0"
"G_RESET_FPMODE\0"
"G_SET_FPMODE\0"
"G_FMINNUM_IEEE\0"
"G_FMAXNUM_IEEE\0"
"FPMERGE\0"
"G_VSCALE\0"
"G_JUMP_TABLE\0"
"BUNDLE\0"
"BSHUFFLE\0"
"G_MEMCPY_INLINE\0"
"DONE\0"
"FONE\0"
"LOCAL_ESCAPE\0"
"G_STACKRESTORE\0"
"G_INDEXED_STORE\0"
"G_STORE\0"
"G_BITREVERSE\0"
"FAKE_USE\0"
"DBG_VALUE\0"
"G_GLOBAL_VALUE\0"
"G_PTRAUTH_GLOBAL_VALUE\0"
"CONVERGENCECTRL_GLUE\0"
"G_STACKSAVE\0"
"G_MEMMOVE\0"
"G_FREEZE\0"
"G_FCANONICALIZE\0"
"G_CTLZ_ZERO_UNDEF\0"
"G_CTTZ_ZERO_UNDEF\0"
"INIT_UNDEF\0"
"G_IMPLICIT_DEF\0"
"DBG_INSTR_REF\0"
"G_FNEG\0"
"EXTRACT_SUBREG\0"
"INSERT_SUBREG\0"
"G_SEXT_INREG\0"
"SUBREG_TO_REG\0"
"G_ATOMIC_CMPXCHG\0"
"G_ATOMICRMW_XCHG\0"
"G_FLOG\0"
"G_VAARG\0"
"PREALLOCATED_ARG\0"
"G_PREFETCH\0"
"G_SMULH\0"
"G_UMULH\0"
"G_FTANH\0"
"G_FSINH\0"
"G_FCOSH\0"
"FLUSH\0"
"DBG_PHI\0"
"UMULXHI\0"
"XMULXHI\0"
"FDTOI\0"
"FQTOI\0"
"FSTOI\0"
"G_FPTOSI\0"
"G_FPTOUI\0"
"G_FPOWI\0"
"BMASK\0"
"G_PTRMASK\0"
"EDGE32L\0"
"EDGE16L\0"
"EDGE8L\0"
"FMUL8X16AL\0"
"GC_LABEL\0"
"DBG_LABEL\0"
"EH_LABEL\0"
"ANNOTATION_LABEL\0"
"ICALL_BRANCH_FUNNEL\0"
"G_FSHL\0"
"G_SHL\0"
"G_FCEIL\0"
"PATCHABLE_TAIL_CALL\0"
"TLS_CALL\0"
"PATCHABLE_TYPED_EVENT_CALL\0"
"PATCHABLE_EVENT_CALL\0"
"FENTRY_CALL\0"
"KILL\0"
"G_CONSTANT_POOL\0"
"ALIGNADDRL\0"
"RETL\0"
"G_ROTL\0"
"G_VECREDUCE_FMUL\0"
"G_FMUL\0"
"G_VECREDUCE_SEQ_FMUL\0"
"G_STRICT_FMUL\0"
"G_VECREDUCE_MUL\0"
"G_MUL\0"
"SIAM\0"
"G_FREM\0"
"G_STRICT_FREM\0"
"G_SREM\0"
"G_UREM\0"
"G_SDIVREM\0"
"G_UDIVREM\0"
"RDWIM\0"
"INLINEASM\0"
"G_VECREDUCE_FMINIMUM\0"
"G_FMINIMUM\0"
"G_VECREDUCE_FMAXIMUM\0"
"G_FMAXIMUM\0"
"G_FMINNUM\0"
"G_FMAXNUM\0"
"EDGE32N\0"
"EDGE16N\0"
"EDGE8N\0"
"G_FATAN\0"
"G_FTAN\0"
"G_INTRINSIC_ROUNDEVEN\0"
"G_ASSERT_ALIGN\0"
"G_FCOPYSIGN\0"
"G_VECREDUCE_FMIN\0"
"G_ATOMICRMW_FMIN\0"
"G_VECREDUCE_SMIN\0"
"G_SMIN\0"
"G_VECREDUCE_UMIN\0"
"G_UMIN\0"
"G_ATOMICRMW_UMIN\0"
"G_ATOMICRMW_MIN\0"
"G_FASIN\0"
"G_FSIN\0"
"EDGE32LN\0"
"EDGE16LN\0"
"EDGE8LN\0"
"CFI_INSTRUCTION\0"
"PDISTN\0"
"ADJCALLSTACKDOWN\0"
"SHUTDOWN\0"
"G_SSUBO\0"
"G_USUBO\0"
"G_SADDO\0"
"G_UADDO\0"
"JUMP_TABLE_DEBUG_INFO\0"
"G_SMULO\0"
"G_UMULO\0"
"G_BZERO\0"
"FZERO\0"
"STACKMAP\0"
"G_DEBUGTRAP\0"
"G_UBSANTRAP\0"
"G_TRAP\0"
"G_ATOMICRMW_UDEC_WRAP\0"
"G_ATOMICRMW_UINC_WRAP\0"
"G_BSWAP\0"
"G_SITOFP\0"
"G_UITOFP\0"
"G_FCMP\0"
"G_ICMP\0"
"G_SCMP\0"
"G_UCMP\0"
"UNIMP\0"
"NOP\0"
"CONVERGENCECTRL_LOOP\0"
"G_CTPOP\0"
"PATCHABLE_OP\0"
"FAULTING_OP\0"
"ADJCALLSTACKUP\0"
"PREALLOCATED_SETUP\0"
"G_FLDEXP\0"
"G_STRICT_FLDEXP\0"
"G_FEXP\0"
"G_FFREXP\0"
"FSUBQ\0"
"FADDQ\0"
"V9FCMPEQ\0"
"RDFQ\0"
"FNEGQ\0"
"FDMULQ\0"
"FMULQ\0"
"FDTOQ\0"
"FITOQ\0"
"FSTOQ\0"
"FXTOQ\0"
"V9FCMPQ\0"
"FMOVRQ\0"
"FABSQ\0"
"FSQRTQ\0"
"FDIVQ\0"
"FMOVQ\0"
"STBAR\0"
"RDTBR\0"
"G_BR\0"
"INLINEASM_BR\0"
"ALIGNADDR\0"
"G_BLOCK_ADDR\0"
"MEMBARRIER\0"
"G_CONSTANT_FOLD_BARRIER\0"
"PATCHABLE_FUNCTION_ENTER\0"
"G_READCYCLECOUNTER\0"
"G_READSTEADYCOUNTER\0"
"G_READ_REGISTER\0"
"G_WRITE_REGISTER\0"
"G_ASHR\0"
"G_FSHR\0"
"G_LSHR\0"
"SIR\0"
"FOR\0"
"CONVERGENCECTRL_ANCHOR\0"
"FNOR\0"
"FXNOR\0"
"G_FFLOOR\0"
"G_EXTRACT_SUBVECTOR\0"
"G_INSERT_SUBVECTOR\0"
"G_BUILD_VECTOR\0"
"G_SHUFFLE_VECTOR\0"
"G_SPLAT_VECTOR\0"
"FXOR\0"
"G_VECREDUCE_XOR\0"
"G_XOR\0"
"G_ATOMICRMW_XOR\0"
"G_VECREDUCE_OR\0"
"G_OR\0"
"G_ATOMICRMW_OR\0"
"BPR\0"
"RDPR\0"
"RDASR\0"
"RDPSR\0"
"G_ROTR\0"
"G_INTTOPTR\0"
"FSRC1S\0"
"FANDNOT1S\0"
"FNOT1S\0"
"FORNOT1S\0"
"FPSUB32S\0"
"FPADD32S\0"
"FSRC2S\0"
"FANDNOT2S\0"
"FNOT2S\0"
"FORNOT2S\0"
"FPSUB16S\0"
"FPADD16S\0"
"G_FABS\0"
"G_ABS\0"
"FSUBS\0"
"FHSUBS\0"
"FADDS\0"
"FHADDS\0"
"FNHADDS\0"
"FNADDS\0"
"FANDS\0"
"FNANDS\0"
"FONES\0"
"V9FCMPES\0"
"G_UNMERGE_VALUES\0"
"G_MERGE_VALUES\0"
"FNEGS\0"
"FMULS\0"
"FNMULS\0"
"G_FACOS\0"
"G_FCOS\0"
"FZEROS\0"
"FDTOS\0"
"FITOS\0"
"FQTOS\0"
"MOVWTOS\0"
"FXTOS\0"
"V9FCMPS\0"
"FLCMPS\0"
"FORS\0"
"FNORS\0"
"FXNORS\0"
"G_CONCAT_VECTORS\0"
"FXORS\0"
"FMOVRS\0"
"COPY_TO_REGCLASS\0"
"G_IS_FPCLASS\0"
"FABSS\0"
"G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
"G_VECTOR_COMPRESS\0"
"G_INTRINSIC_W_SIDE_EFFECTS\0"
"G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
"FSQRTS\0"
"FDIVS\0"
"FMOVS\0"
"G_SSUBSAT\0"
"G_USUBSAT\0"
"G_SADDSAT\0"
"G_UADDSAT\0"
"G_SSHLSAT\0"
"G_USHLSAT\0"
"G_SMULFIXSAT\0"
"G_UMULFIXSAT\0"
"G_SDIVFIXSAT\0"
"G_UDIVFIXSAT\0"
"G_ATOMICRMW_USUB_SAT\0"
"G_FPTOSI_SAT\0"
"G_FPTOUI_SAT\0"
"G_EXTRACT\0"
"G_SELECT\0"
"G_BRINDIRECT\0"
"PATCHABLE_RET\0"
"G_MEMSET\0"
"PATCHABLE_FUNCTION_EXIT\0"
"G_BRJT\0"
"G_EXTRACT_VECTOR_ELT\0"
"G_INSERT_VECTOR_ELT\0"
"BPFCCANT\0"
"BPICCANT\0"
"BPXCCANT\0"
"BPRANT\0"
"G_FCONSTANT\0"
"G_CONSTANT\0"
"BPFCCNT\0"
"BPICCNT\0"
"BPXCCNT\0"
"LZCNT\0"
"G_INTRINSIC_CONVERGENT\0"
"STATEPOINT\0"
"PATCHPOINT\0"
"G_PTRTOINT\0"
"G_FRINT\0"
"G_INTRINSIC_LLRINT\0"
"G_INTRINSIC_LRINT\0"
"G_FNEARBYINT\0"
"BPRNT\0"
"G_VASTART\0"
"LIFETIME_START\0"
"G_INVOKE_REGION_START\0"
"G_INSERT\0"
"G_FSQRT\0"
"G_STRICT_FSQRT\0"
"G_BITCAST\0"
"G_ADDRSPACE_CAST\0"
"PDIST\0"
"DBG_VALUE_LIST\0"
"G_FPEXT\0"
"G_SEXT\0"
"G_ASSERT_SEXT\0"
"G_ANYEXT\0"
"G_ZEXT\0"
"G_ASSERT_ZEXT\0"
"FMUL8X16AU\0"
"G_FDIV\0"
"G_STRICT_FDIV\0"
"G_SDIV\0"
"G_UDIV\0"
"G_GET_FPENV\0"
"G_RESET_FPENV\0"
"G_SET_FPENV\0"
"FLUSHW\0"
"G_FPOW\0"
"MOVSTOSW\0"
"MOVSTOUW\0"
"G_VECREDUCE_FMAX\0"
"G_ATOMICRMW_FMAX\0"
"G_VECREDUCE_SMAX\0"
"G_SMAX\0"
"G_VECREDUCE_UMAX\0"
"G_UMAX\0"
"G_ATOMICRMW_UMAX\0"
"G_ATOMICRMW_MAX\0"
"GETPCX\0"
"G_FRAME_INDEX\0"
"G_SBFX\0"
"G_UBFX\0"
"FPACKFIX\0"
"G_SMULFIX\0"
"G_UMULFIX\0"
"G_SDIVFIX\0"
"G_UDIVFIX\0"
"XMULX\0"
"FDTOX\0"
"MOVDTOX\0"
"FQTOX\0"
"FSTOX\0"
"SETX\0"
"G_MEMCPY\0"
"COPY\0"
"RETRY\0"
"CONVERGENCECTRL_ENTRY\0"
"G_CTLZ\0"
"G_CTTZ\0"
"PREFETCHAi\0"
"PREFETCHi\0"
"SETHIi\0"
"MEMBARi\0"
"LDSBAri\0"
"STBAri\0"
"LDUBAri\0"
"LDSTUBAri\0"
"LDDAri\0"
"LDAri\0"
"STDAri\0"
"LDDFAri\0"
"LDFAri\0"
"STDFAri\0"
"LDQFAri\0"
"STQFAri\0"
"STFAri\0"
"LDSHAri\0"
"STHAri\0"
"LDUHAri\0"
"SWAPAri\0"
"SRAri\0"
"CASAri\0"
"STAri\0"
"LDSWAri\0"
"LDXAri\0"
"CASXAri\0"
"STXAri\0"
"LDSBri\0"
"STBri\0"
"LDUBri\0"
"SUBri\0"
"LDSTUBri\0"
"SMACri\0"
"UMACri\0"
"SUBCri\0"
"TSUBCCri\0"
"TADDCCri\0"
"ANDCCri\0"
"V9MOVFCCri\0"
"TICCri\0"
"MOVICCri\0"
"SMULCCri\0"
"UMULCCri\0"
"ANDNCCri\0"
"ORNCCri\0"
"XNORCCri\0"
"XORCCri\0"
"MULSCCri\0"
"SDIVCCri\0"
"UDIVCCri\0"
"TXCCri\0"
"MOVXCCri\0"
"ADDCri\0"
"LDDCri\0"
"LDCri\0"
"STDCri\0"
"STCri\0"
"ADDri\0"
"LDDri\0"
"LDri\0"
"ANDri\0"
"BINDri\0"
"STDri\0"
"SUBEri\0"
"ADDEri\0"
"RESTOREri\0"
"SAVEri\0"
"LDDFri\0"
"LDFri\0"
"STDFri\0"
"LDQFri\0"
"STQFri\0"
"STFri\0"
"LDSHri\0"
"FLUSHri\0"
"STHri\0"
"LDUHri\0"
"TAIL_CALLri\0"
"SLLri\0"
"JMPLri\0"
"SRLri\0"
"SMULri\0"
"UMULri\0"
"WRWIMri\0"
"ANDNri\0"
"ORNri\0"
"TRAPri\0"
"SWAPri\0"
"STDCQri\0"
"STDFQri\0"
"WRTBRri\0"
"XNORri\0"
"XORri\0"
"WRPRri\0"
"WRASRri\0"
"LDCSRri\0"
"STCSRri\0"
"LDFSRri\0"
"STFSRri\0"
"LDXFSRri\0"
"STXFSRri\0"
"PWRPSRri\0"
"MOVRri\0"
"STri\0"
"RETTri\0"
"SDIVri\0"
"UDIVri\0"
"TSUBCCTVri\0"
"TADDCCTVri\0"
"LDSWri\0"
"SRAXri\0"
"LDXri\0"
"SLLXri\0"
"SRLXri\0"
"MULXri\0"
"STXri\0"
"SDIVXri\0"
"UDIVXri\0"
"PREFETCHAr\0"
"PREFETCHr\0"
"LDSBArr\0"
"STBArr\0"
"LDUBArr\0"
"LDSTUBArr\0"
"LDDArr\0"
"LDArr\0"
"STDArr\0"
"LDDFArr\0"
"LDFArr\0"
"STDFArr\0"
"LDQFArr\0"
"STQFArr\0"
"STFArr\0"
"LDSHArr\0"
"STHArr\0"
"LDUHArr\0"
"SWAPArr\0"
"SRArr\0"
"CASArr\0"
"STArr\0"
"LDSWArr\0"
"LDXArr\0"
"CASXArr\0"
"STXArr\0"
"LDSBrr\0"
"STBrr\0"
"LDUBrr\0"
"SUBrr\0"
"LDSTUBrr\0"
"SMACrr\0"
"UMACrr\0"
"SUBCrr\0"
"TSUBCCrr\0"
"TADDCCrr\0"
"ANDCCrr\0"
"V9MOVFCCrr\0"
"TICCrr\0"
"MOVICCrr\0"
"SMULCCrr\0"
"UMULCCrr\0"
"ANDNCCrr\0"
"ORNCCrr\0"
"XNORCCrr\0"
"XORCCrr\0"
"MULSCCrr\0"
"SDIVCCrr\0"
"UDIVCCrr\0"
"TXCCrr\0"
"MOVXCCrr\0"
"ADDCrr\0"
"LDDCrr\0"
"LDCrr\0"
"STDCrr\0"
"POPCrr\0"
"STCrr\0"
"TLS_ADDrr\0"
"LDDrr\0"
"GDOP_LDrr\0"
"TLS_LDrr\0"
"ANDrr\0"
"BINDrr\0"
"STDrr\0"
"SUBErr\0"
"ADDErr\0"
"RESTORErr\0"
"SAVErr\0"
"LDDFrr\0"
"LDFrr\0"
"STDFrr\0"
"LDQFrr\0"
"STQFrr\0"
"STFrr\0"
"LDSHrr\0"
"FLUSHrr\0"
"STHrr\0"
"LDUHrr\0"
"CALLrr\0"
"SLLrr\0"
"JMPLrr\0"
"SRLrr\0"
"SMULrr\0"
"UMULrr\0"
"WRWIMrr\0"
"ANDNrr\0"
"ORNrr\0"
"TRAPrr\0"
"SWAPrr\0"
"STDCQrr\0"
"STDFQrr\0"
"WRTBRrr\0"
"XNORrr\0"
"XORrr\0"
"WRPRrr\0"
"WRASRrr\0"
"LDCSRrr\0"
"STCSRrr\0"
"LDFSRrr\0"
"STFSRrr\0"
"LDXFSRrr\0"
"STXFSRrr\0"
"PWRPSRrr\0"
"MOVRrr\0"
"STrr\0"
"RETTrr\0"
"SDIVrr\0"
"UDIVrr\0"
"TSUBCCTVrr\0"
"TADDCCTVrr\0"
"LDSWrr\0"
"SRAXrr\0"
"GDOP_LDXrr\0"
"TLS_LDXrr\0"
"SLLXrr\0"
"SRLXrr\0"
"MULXrr\0"
"STXrr\0"
"SDIVXrr\0"
"UDIVXrr\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif
extern const unsigned SparcInstrNameIndices[] = {
2319U, 2799U, 3672U, 3136U, 2452U, 2433U, 2461U, 2608U,
2136U, 2151U, 2102U, 2089U, 2178U, 4467U, 1937U, 5240U,
2115U, 2315U, 2442U, 1691U, 5675U, 1821U, 5138U, 1425U,
1642U, 1679U, 3269U, 2596U, 5042U, 1593U, 3486U, 2241U,
5031U, 1863U, 3459U, 3446U, 3743U, 4826U, 4849U, 2519U,
2575U, 2548U, 2478U, 1928U, 3708U, 3217U, 5686U, 3869U,
3417U, 1985U, 5270U, 5300U, 2953U, 1233U, 590U, 2727U,
5346U, 5353U, 2759U, 2766U, 2773U, 2783U, 1403U, 4056U,
4019U, 2100U, 2317U, 5552U, 1947U, 1962U, 2613U, 4794U,
4299U, 5175U, 4316U, 3951U, 995U, 4437U, 5053U, 4104U,
5207U, 2028U, 3719U, 1520U, 969U, 1502U, 5091U, 5072U,
2931U, 3768U, 3787U, 1121U, 1065U, 1095U, 1106U, 1046U,
1076U, 1907U, 1891U, 4503U, 2192U, 2209U, 1249U, 596U,
1409U, 1362U, 4061U, 4025U, 5529U, 3079U, 5512U, 3062U,
1200U, 573U, 5447U, 2997U, 3331U, 3309U, 1461U, 4747U,
1671U, 2258U, 1452U, 4813U, 5153U, 947U, 4551U, 5008U,
4578U, 5284U, 987U, 4967U, 4955U, 5128U, 2233U, 5263U,
2165U, 5293U, 2505U, 3854U, 3840U, 2498U, 3847U, 4097U,
2645U, 3386U, 3379U, 3393U, 3400U, 4804U, 3209U, 1712U,
3193U, 1663U, 3201U, 1704U, 3185U, 1655U, 3247U, 3239U,
2277U, 2269U, 4665U, 4655U, 4645U, 4635U, 4685U, 4675U,
5589U, 5599U, 4695U, 4708U, 5609U, 5619U, 4721U, 4734U,
1158U, 552U, 2669U, 516U, 1039U, 5325U, 2738U, 5405U,
2375U, 3530U, 177U, 9U, 2226U, 169U, 0U, 3505U,
3537U, 2129U, 5255U, 959U, 2357U, 2366U, 3361U, 3370U,
4768U, 4781U, 4217U, 2968U, 4484U, 2037U, 2873U, 2883U,
1761U, 1776U, 2830U, 2862U, 5360U, 5386U, 5372U, 1720U,
1748U, 1733U, 1239U, 2389U, 3031U, 5481U, 3055U, 5505U,
4224U, 1493U, 1483U, 3667U, 4873U, 1799U, 3932U, 3912U,
4901U, 4880U, 3966U, 3983U, 4533U, 5715U, 2071U, 5708U,
2053U, 3438U, 3353U, 1915U, 2511U, 4358U, 3103U, 2924U,
4350U, 3095U, 2916U, 2301U, 2293U, 2285U, 5184U, 3903U,
5064U, 5109U, 5217U, 3695U, 1808U, 1016U, 2006U, 1876U,
1186U, 559U, 2697U, 5332U, 2745U, 522U, 5192U, 3514U,
3807U, 3823U, 5666U, 1837U, 2018U, 4840U, 3255U, 3302U,
3278U, 3290U, 1165U, 2676U, 1141U, 2652U, 5430U, 2980U,
2841U, 2809U, 1217U, 2711U, 1387U, 4041U, 4003U, 5464U,
3014U, 5488U, 3038U, 5566U, 5573U, 3159U, 3471U, 5545U,
638U, 749U, 856U, 674U, 785U, 892U, 715U, 822U,
929U, 656U, 767U, 874U, 4845U, 5661U, 6003U, 6884U,
6141U, 7022U, 6217U, 7123U, 1033U, 612U, 6174U, 7066U,
3685U, 2629U, 6011U, 6892U, 6064U, 6945U, 6362U, 7263U,
6191U, 7097U, 400U, 155U, 421U, 476U, 1439U, 501U,
6197U, 7103U, 2383U, 620U, 479U, 4921U, 4978U, 733U,
486U, 4930U, 4986U, 4076U, 535U, 4948U, 5122U, 840U,
493U, 4939U, 4994U, 1828U, 2534U, 6314U, 7215U, 5894U,
6775U, 5922U, 6803U, 1438U, 500U, 280U, 107U, 414U,
1853U, 247U, 2407U, 3119U, 2901U, 74U, 2399U, 3110U,
2893U, 408U, 2415U, 3128U, 2909U, 1617U, 3630U, 4497U,
1265U, 3552U, 4243U, 540U, 1351U, 28U, 4122U, 185U,
4173U, 4271U, 1445U, 508U, 428U, 439U, 302U, 1580U,
449U, 319U, 129U, 336U, 146U, 254U, 81U, 263U,
90U, 3617U, 458U, 4406U, 467U, 1630U, 3643U, 4623U,
3578U, 2339U, 3591U, 4372U, 5635U, 1379U, 1271U, 4249U,
1134U, 4236U, 1546U, 3597U, 4378U, 1586U, 4412U, 2309U,
5398U, 6288U, 7194U, 311U, 1636U, 628U, 739U, 846U,
3649U, 693U, 802U, 909U, 1610U, 3623U, 4460U, 4629U,
705U, 812U, 919U, 389U, 366U, 345U, 2422U, 5314U,
1323U, 377U, 354U, 3585U, 4337U, 1286U, 4264U, 1356U,
4277U, 1317U, 3572U, 4331U, 1278U, 4256U, 1329U, 4343U,
3892U, 4424U, 37U, 4132U, 194U, 4183U, 1343U, 1858U,
4284U, 3865U, 43U, 4139U, 200U, 4190U, 4419U, 272U,
99U, 5580U, 239U, 4208U, 66U, 4157U, 212U, 1791U,
231U, 4199U, 58U, 4148U, 1552U, 2345U, 4384U, 5649U,
328U, 138U, 288U, 115U, 1336U, 1623U, 3636U, 4616U,
224U, 51U, 22U, 4115U, 163U, 4166U, 295U, 122U,
1558U, 2351U, 3603U, 5655U, 1128U, 3546U, 4230U, 3897U,
4430U, 3998U, 4454U, 1564U, 3609U, 4398U, 3263U, 4365U,
7470U, 7078U, 6327U, 7228U, 5798U, 6679U, 6441U, 7342U,
6155U, 7036U, 5791U, 6672U, 6148U, 7029U, 5811U, 6692U,
6241U, 7147U, 6180U, 7072U, 5819U, 6700U, 6457U, 7358U,
6248U, 7154U, 5834U, 6715U, 6261U, 7167U, 5758U, 6639U,
5937U, 6818U, 5857U, 6738U, 6281U, 7187U, 5781U, 6662U,
5963U, 6844U, 5907U, 6788U, 6555U, 7456U, 5773U, 6654U,
5950U, 6831U, 5872U, 6753U, 6302U, 7208U, 5915U, 6796U,
6473U, 7374U, 6569U, 7475U, 6186U, 7083U, 5002U, 5750U,
5641U, 6021U, 6902U, 6037U, 6918U, 6500U, 7401U, 5412U,
5421U, 4390U, 6132U, 7013U, 1570U, 6098U, 6979U, 6589U,
7505U, 3413U, 6083U, 6964U, 6073U, 6954U, 6369U, 7270U,
6415U, 7316U, 5234U, 3152U, 7049U, 5722U, 6618U, 5733U,
6629U, 6491U, 7392U, 4085U, 3567U, 4080U, 4091U, 3661U,
2793U, 1302U, 6224U, 7130U, 4836U, 2640U, 5680U, 6512U,
7413U, 1311U, 6234U, 7140U, 6107U, 6988U, 6602U, 7518U,
6519U, 7420U, 5743U, 3176U, 2733U, 3861U, 6575U, 7491U,
6321U, 7222U, 5972U, 6853U, 6046U, 6927U, 6340U, 7241U,
6562U, 7463U, 5888U, 6769U, 6582U, 7498U, 6334U, 7235U,
5901U, 6782U, 3655U, 5766U, 6647U, 5944U, 6825U, 6449U,
7350U, 6168U, 7056U, 5804U, 6685U, 6389U, 7290U, 6161U,
7042U, 5826U, 6707U, 6397U, 7298U, 6254U, 7160U, 6204U,
7110U, 5850U, 6731U, 6465U, 7366U, 6275U, 7181U, 5865U,
6746U, 6296U, 7202U, 5842U, 6723U, 6268U, 7174U, 5930U,
6811U, 6482U, 7383U, 6596U, 7512U, 6507U, 7408U, 5994U,
6875U, 5986U, 6867U, 6210U, 7116U, 5957U, 6838U, 5880U,
6761U, 6382U, 7283U, 18U, 208U, 220U, 6544U, 7445U,
6002U, 6883U, 2529U, 6309U, 6030U, 6911U, 7062U, 2539U,
7481U, 7088U, 6375U, 7276U, 6533U, 7434U, 5993U, 6874U,
6125U, 7006U, 6116U, 6997U, 6610U, 7526U, 6526U, 7427U,
5979U, 6860U, 6055U, 6936U, 2323U, 6347U, 7248U, 3407U,
1578U, 1293U, 3558U, 4290U, 3615U, 4404U, 626U, 691U,
703U, 6019U, 6900U, 6433U, 7334U, 6426U, 7327U, 6492U,
7393U, 6405U, 7306U, 6354U, 7255U, 5629U, 2331U, 6081U,
6962U, 6413U, 7314U, 6090U, 6971U, 6420U, 7321U,
};
static inline void InitSparcMCInstrInfo(MCInstrInfo *II) {
II->InitMCInstrInfo(SparcDescs.Insts, SparcInstrNameIndices, SparcInstrNameData, nullptr, nullptr, 815);
}
}
#endif
#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER
namespace llvm {
struct SparcGenInstrInfo : public TargetInstrInfo {
explicit SparcGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
~SparcGenInstrInfo() override = default;
};
}
#endif
#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS
#endif
#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS
#endif
#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR
namespace llvm {
extern const SparcInstrTable SparcDescs;
extern const unsigned SparcInstrNameIndices[];
extern const char SparcInstrNameData[];
SparcGenInstrInfo::SparcGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
: TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
InitMCInstrInfo(SparcDescs.Insts, SparcInstrNameIndices, SparcInstrNameData, nullptr, nullptr, 815);
}
}
#endif
#ifdef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_OPERAND_ENUM
namespace llvm {
namespace SP {
namespace OpName {
enum {
OPERAND_LAST
};
}
}
}
#endif
#ifdef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_NAMED_OPS
namespace llvm {
namespace SP {
LLVM_READONLY
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
return -1;
}
}
}
#endif
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
namespace llvm {
namespace SP {
namespace OpTypes {
enum OperandType {
ASITag = 0,
CCOp = 1,
MEMri = 2,
MEMrr = 3,
MembarTag = 4,
PrefetchTag = 5,
RegCCOp = 6,
TailRelocSymGOTLoad = 7,
TailRelocSymTLSAdd = 8,
TailRelocSymTLSCall = 9,
TailRelocSymTLSLoad = 10,
bprtarget = 11,
bprtarget16 = 12,
brtarget = 13,
calltarget = 14,
f32imm = 15,
f64imm = 16,
getPCX = 17,
i1imm = 18,
i8imm = 19,
i16imm = 20,
i32imm = 21,
i64imm = 22,
ptype0 = 23,
ptype1 = 24,
ptype2 = 25,
ptype3 = 26,
ptype4 = 27,
ptype5 = 28,
shift_imm5 = 29,
shift_imm6 = 30,
simm13Op = 31,
type0 = 32,
type1 = 33,
type2 = 34,
type3 = 35,
type4 = 36,
type5 = 37,
untyped_imm_0 = 38,
ASRRegs = 39,
CoprocPair = 40,
CoprocRegs = 41,
DFPRegs = 42,
FCCRegs = 43,
FPRegs = 44,
GPRIncomingArg = 45,
GPROutgoingArg = 46,
I64Regs = 47,
IntPair = 48,
IntRegs = 49,
LowDFPRegs = 50,
LowQFPRegs = 51,
PRRegs = 52,
QFPRegs = 53,
OPERAND_TYPE_LIST_END
};
}
}
}
#endif
#ifdef GET_INSTRINFO_OPERAND_TYPE
#undef GET_INSTRINFO_OPERAND_TYPE
namespace llvm {
namespace SP {
LLVM_READONLY
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
static const uint16_t Offsets[] = {
0,
1,
1,
1,
2,
3,
4,
5,
5,
8,
12,
13,
14,
18,
21,
21,
21,
21,
21,
22,
24,
26,
26,
27,
28,
32,
34,
36,
36,
42,
43,
44,
47,
47,
49,
50,
50,
50,
50,
50,
50,
52,
55,
55,
55,
55,
56,
57,
58,
60,
61,
64,
67,
70,
73,
76,
79,
82,
85,
88,
91,
95,
99,
102,
105,
108,
109,
110,
112,
114,
119,
121,
124,
126,
130,
132,
134,
136,
138,
140,
142,
144,
146,
148,
151,
153,
155,
157,
159,
161,
162,
163,
165,
167,
169,
174,
179,
184,
186,
191,
196,
200,
203,
206,
209,
212,
215,
218,
221,
224,
227,
230,
233,
236,
239,
242,
245,
248,
251,
254,
257,
259,
263,
265,
266,
266,
267,
268,
269,
270,
272,
274,
276,
278,
279,
282,
284,
287,
289,
292,
295,
298,
302,
306,
309,
312,
316,
320,
323,
326,
330,
334,
339,
343,
348,
352,
357,
361,
366,
370,
374,
377,
380,
383,
386,
389,
392,
395,
398,
402,
406,
410,
414,
418,
422,
426,
430,
433,
436,
439,
443,
447,
450,
453,
456,
459,
461,
463,
465,
467,
469,
471,
474,
477,
479,
481,
483,
485,
487,
489,
491,
493,
495,
497,
500,
503,
505,
508,
511,
514,
517,
520,
523,
524,
525,
525,
526,
527,
527,
530,
533,
536,
539,
542,
545,
547,
549,
551,
552,
555,
557,
561,
564,
568,
571,
575,
577,
581,
583,
585,
587,
589,
591,
593,
595,
597,
599,
601,
603,
605,
607,
609,
611,
613,
615,
617,
619,
621,
623,
625,
627,
629,
632,
633,
634,
637,
640,
643,
646,
649,
653,
655,
658,
660,
662,
666,
669,
673,
677,
680,
680,
680,
681,
684,
687,
689,
691,
693,
695,
697,
699,
701,
703,
705,
707,
709,
711,
713,
715,
717,
721,
725,
727,
729,
730,
734,
738,
742,
746,
750,
754,
758,
762,
766,
770,
774,
778,
780,
783,
786,
789,
792,
795,
798,
801,
804,
807,
810,
813,
816,
819,
822,
825,
828,
831,
834,
837,
840,
843,
846,
849,
852,
853,
855,
857,
859,
861,
864,
867,
870,
873,
876,
878,
880,
882,
884,
887,
890,
893,
896,
898,
900,
902,
904,
907,
908,
910,
912,
916,
921,
925,
930,
932,
934,
935,
936,
937,
937,
940,
943,
946,
949,
952,
955,
958,
961,
964,
967,
970,
973,
975,
977,
979,
982,
985,
988,
991,
994,
997,
1000,
1003,
1006,
1009,
1011,
1013,
1015,
1017,
1020,
1022,
1024,
1027,
1030,
1033,
1036,
1039,
1042,
1045,
1048,
1050,
1052,
1054,
1056,
1059,
1062,
1065,
1068,
1070,
1072,
1074,
1076,
1078,
1081,
1084,
1087,
1090,
1092,
1094,
1096,
1099,
1102,
1102,
1102,
1104,
1106,
1109,
1111,
1115,
1119,
1123,
1125,
1129,
1133,
1137,
1142,
1147,
1152,
1154,
1158,
1162,
1166,
1169,
1172,
1175,
1178,
1181,
1184,
1187,
1190,
1193,
1196,
1199,
1202,
1205,
1208,
1210,
1212,
1214,
1217,
1220,
1223,
1226,
1229,
1232,
1234,
1236,
1238,
1240,
1243,
1245,
1247,
1250,
1253,
1256,
1259,
1262,
1265,
1267,
1270,
1272,
1275,
1278,
1281,
1284,
1287,
1290,
1293,
1296,
1299,
1302,
1304,
1306,
1308,
1310,
1313,
1316,
1319,
1322,
1325,
1327,
1329,
1331,
1334,
1337,
1339,
1341,
1343,
1345,
1348,
1351,
1353,
1355,
1357,
1359,
1362,
1365,
1368,
1371,
1374,
1377,
1380,
1382,
1384,
1386,
1388,
1390,
1394,
1398,
1401,
1404,
1407,
1411,
1413,
1415,
1418,
1421,
1424,
1428,
1431,
1434,
1437,
1441,
1444,
1447,
1450,
1453,
1456,
1460,
1462,
1464,
1467,
1470,
1473,
1477,
1480,
1483,
1486,
1490,
1493,
1496,
1499,
1503,
1506,
1509,
1512,
1516,
1519,
1522,
1525,
1529,
1532,
1535,
1538,
1542,
1545,
1548,
1551,
1555,
1558,
1561,
1564,
1568,
1570,
1572,
1575,
1578,
1581,
1584,
1586,
1587,
1589,
1593,
1597,
1601,
1605,
1610,
1615,
1617,
1619,
1621,
1625,
1629,
1631,
1634,
1637,
1640,
1643,
1643,
1646,
1649,
1652,
1655,
1658,
1661,
1664,
1667,
1670,
1673,
1675,
1678,
1682,
1685,
1688,
1690,
1692,
1694,
1695,
1697,
1698,
1699,
1700,
1700,
1703,
1706,
1707,
1708,
1708,
1710,
1712,
1712,
1715,
1718,
1721,
1724,
1727,
1730,
1733,
1736,
1738,
1738,
1738,
1739,
1742,
1745,
1748,
1751,
1755,
1759,
1762,
1765,
1768,
1771,
1774,
1777,
1780,
1783,
1786,
1789,
1792,
1795,
1798,
1802,
1802,
1805,
1809,
1812,
1815,
1817,
1819,
1822,
1825,
1828,
1832,
1834,
1836,
1839,
1842,
1845,
1849,
1851,
1853,
1856,
1859,
1862,
1865,
1868,
1872,
1874,
1876,
1879,
1882,
1885,
1889,
1892,
1895,
1898,
1902,
1905,
1908,
1911,
1915,
1917,
1919,
1922,
1925,
1928,
1931,
1934,
1937,
1940,
1943,
1946,
1949,
1952,
1955,
1959,
1964,
1968,
1972,
1972,
1972,
1972,
1975,
1978,
1981,
1984,
1985,
1987,
1990,
1993,
1997,
1999,
2003,
2007,
2010,
2013,
2016,
2019,
2022,
2025,
2028,
2031,
2034,
2037,
2040,
2043,
2046,
2049,
2053,
2057,
2060,
2063,
2066,
2069,
2072,
2073,
2076,
2079,
2082,
2085,
2088,
2091,
2096,
2101,
2106,
2111,
2116,
2119,
2122,
2125,
2128,
2130,
2132,
2134,
2136,
2138,
2140,
2143,
2146,
2149,
2152,
2155,
2158,
2161,
2164,
2167,
};
using namespace OpTypes;
static const int8_t OpcodeOperandTypes[] = {
-1,
i32imm,
i32imm,
i32imm,
i32imm,
-1, -1, i32imm,
-1, -1, -1, i32imm,
-1,
-1,
-1, -1, -1, i32imm,
-1, -1, i32imm,
-1,
-1, -1,
-1, -1,
i32imm,
i32imm,
i64imm, i64imm, i8imm, i32imm,
-1, -1,
i64imm, i32imm,
-1, i64imm, i32imm, -1, i32imm, i32imm,
-1,
i32imm,
-1, i32imm, i32imm,
-1, i32imm,
-1,
-1, -1,
-1, -1, -1,
i64imm,
-1,
-1,
-1, -1,
-1,
type0, type0, untyped_imm_0,
type0, type0, untyped_imm_0,
type0, type0, untyped_imm_0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0, type0,
type0, type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0,
type0,
type0, -1,
type0, -1,
type0, -1, i32imm, type1, i64imm,
type0, -1,
type0, type1, untyped_imm_0,
type0, type1,
type0, type0, type1, untyped_imm_0,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type0,
type0, type0,
type0, type1, i32imm,
type0, type0,
type0, type0,
type0, type1,
type0, type1,
type0, type0,
type0,
type0,
type0, ptype1,
type0, ptype1,
type0, ptype1,
type0, ptype1, ptype1, type2, -1,
type0, ptype1, ptype1, type2, -1,
type0, ptype1, ptype1, type2, -1,
type0, ptype1,
ptype0, type1, ptype0, ptype2, -1,
type0, type1, type2, type0, type0,
type0, ptype1, type0, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
i32imm, i32imm,
ptype0, i32imm, i32imm, i32imm,
type0, -1,
type0,
-1,
-1,
-1,
-1,
type0, type1,
type0, type1,
type0, -1,
type0, -1,
type0,
type0, type1, -1,
type0, type1,
type0, type0, untyped_imm_0,
type0, type1,
type0, type0, type1,
type0, type0, type1,
type0, type0, type1,
type0, type0, type0, type1,
type0, type0, type0, type1,
type0, type0, type1,
type0, type0, type1,
type0, -1, type1, type1,
type0, -1, type1, type1,
type0, type1, type1,
type0, type1, type1,
type0, type1, type0, type0,
type0, type1, type0, type0,
type0, type1, type0, type0, type1,
type0, type1, type0, type0,
type0, type1, type0, type0, type1,
type0, type1, type0, type0,
type0, type1, type0, type0, type1,
type0, type1, type0, type0,
type0, type1, type0, type0, type1,
type0, type1, type0, type0,
type0, type1, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type1,
type0, type0, type1,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0, type0,
type0, type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type1,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0, type1,
type0, type1, type0,
type0, type0,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type0,
type0, type0, type1,
type0, type1, -1,
type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0,
type0,
type0,
type0,
ptype0, ptype0, type1,
ptype0, ptype0, type1,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0,
type0, type1,
type0, type1,
-1,
ptype0, -1, type1,
type0, -1,
type0, type0, type1, untyped_imm_0,
type0, type0, untyped_imm_0,
type0, type0, type1, type2,
type0, type1, type2,
type0, type1, type1, -1,
type0, type1,
type0, type0, type1, type0,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type1,
type0, -1,
type0, -1,
ptype0, type1, i32imm,
ptype0,
ptype0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0, type0,
type0, type0,
type0, type0, type1,
type0, -1,
-1, type0,
ptype0, ptype1, type2, untyped_imm_0,
ptype0, ptype1, type2,
ptype0, ptype1, type2, untyped_imm_0,
ptype0, type1, type2, untyped_imm_0,
ptype0, type1, untyped_imm_0,
i8imm,
type0, type1, type2,
type0, type1, type2,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type0, type1, type1,
type0, type0, type1, type1,
i32imm, i32imm,
i32imm, i32imm,
getPCX,
DFPRegs, DFPRegs, DFPRegs, i32imm,
DFPRegs, DFPRegs, DFPRegs, i32imm,
DFPRegs, DFPRegs, DFPRegs, i32imm,
FPRegs, FPRegs, FPRegs, i32imm,
FPRegs, FPRegs, FPRegs, i32imm,
FPRegs, FPRegs, FPRegs, i32imm,
IntRegs, IntRegs, IntRegs, i32imm,
IntRegs, IntRegs, IntRegs, i32imm,
IntRegs, IntRegs, IntRegs, i32imm,
QFPRegs, QFPRegs, QFPRegs, i32imm,
QFPRegs, QFPRegs, QFPRegs, i32imm,
QFPRegs, QFPRegs, QFPRegs, i32imm,
IntRegs, i32imm,
I64Regs, i64imm, I64Regs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
I64Regs, I64Regs, I64Regs,
I64Regs, I64Regs, I64Regs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
I64Regs, I64Regs, I64Regs,
I64Regs, I64Regs, I64Regs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
I64Regs, I64Regs, I64Regs,
I64Regs, I64Regs, I64Regs,
I64Regs, I64Regs, I64Regs,
brtarget,
brtarget, CCOp,
brtarget, CCOp,
-1, i32imm,
-1, -1,
I64Regs, I64Regs, I64Regs,
bprtarget, CCOp, FCCRegs,
bprtarget, CCOp, FCCRegs,
bprtarget, CCOp, FCCRegs,
bprtarget, CCOp, FCCRegs,
bprtarget, CCOp,
bprtarget, CCOp,
bprtarget, CCOp,
bprtarget, CCOp,
bprtarget16, RegCCOp, I64Regs,
bprtarget16, RegCCOp, I64Regs,
bprtarget16, RegCCOp, I64Regs,
bprtarget16, RegCCOp, I64Regs,
bprtarget, CCOp,
bprtarget, CCOp,
bprtarget, CCOp,
bprtarget, CCOp,
DFPRegs, DFPRegs, DFPRegs,
calltarget,
-1, i32imm,
-1, -1,
IntRegs, IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, IntRegs, IntRegs, ASITag,
I64Regs, I64Regs, I64Regs, I64Regs,
I64Regs, I64Regs, I64Regs, I64Regs, ASITag,
brtarget, CCOp,
brtarget, CCOp,
I64Regs,
I64Regs,
I64Regs,
I64Regs, I64Regs, I64Regs,
I64Regs, I64Regs, I64Regs,
I64Regs, I64Regs, I64Regs,
I64Regs, I64Regs, I64Regs,
I64Regs, I64Regs, I64Regs,
I64Regs, I64Regs, I64Regs,
I64Regs, I64Regs, I64Regs,
I64Regs, I64Regs, I64Regs,
I64Regs, I64Regs, I64Regs,
I64Regs, I64Regs, I64Regs,
I64Regs, I64Regs, I64Regs,
I64Regs, I64Regs, I64Regs,
DFPRegs, DFPRegs,
QFPRegs, QFPRegs,
FPRegs, FPRegs,
DFPRegs, DFPRegs, DFPRegs,
QFPRegs, QFPRegs, QFPRegs,
FPRegs, FPRegs, FPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
FPRegs, FPRegs, FPRegs,
DFPRegs, DFPRegs, DFPRegs,
FPRegs, FPRegs, FPRegs,
FPRegs, FPRegs, FPRegs,
brtarget, CCOp,
brtarget, CCOp,
bprtarget, CCOp,
bprtarget, CCOp,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs,
DFPRegs, DFPRegs,
I64Regs, DFPRegs, DFPRegs,
I64Regs, DFPRegs, DFPRegs,
I64Regs, DFPRegs, DFPRegs,
I64Regs, DFPRegs, DFPRegs,
I64Regs, DFPRegs, DFPRegs,
I64Regs, DFPRegs, DFPRegs,
I64Regs, DFPRegs, DFPRegs,
I64Regs, DFPRegs, DFPRegs,
QFPRegs, QFPRegs,
QFPRegs, QFPRegs,
FPRegs, FPRegs,
FPRegs, FPRegs,
DFPRegs, DFPRegs, DFPRegs,
QFPRegs, QFPRegs, QFPRegs,
FPRegs, FPRegs, FPRegs,
QFPRegs, DFPRegs, DFPRegs,
FPRegs, DFPRegs,
QFPRegs, DFPRegs,
FPRegs, DFPRegs,
DFPRegs, DFPRegs,
DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, FPRegs,
QFPRegs, FPRegs,
FPRegs, FPRegs,
FCCRegs, DFPRegs, DFPRegs,
FCCRegs, DFPRegs, DFPRegs,
-1, i32imm,
-1, -1,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs, CCOp,
DFPRegs, DFPRegs, DFPRegs, CCOp,
DFPRegs, DFPRegs, DFPRegs, CCOp,
QFPRegs, QFPRegs,
QFPRegs, QFPRegs, QFPRegs, CCOp,
QFPRegs, QFPRegs, QFPRegs, CCOp,
QFPRegs, QFPRegs, QFPRegs, CCOp,
DFPRegs, I64Regs, DFPRegs, DFPRegs, RegCCOp,
QFPRegs, I64Regs, QFPRegs, QFPRegs, RegCCOp,
FPRegs, I64Regs, FPRegs, FPRegs, RegCCOp,
FPRegs, FPRegs,
FPRegs, FPRegs, FPRegs, CCOp,
FPRegs, FPRegs, FPRegs, CCOp,
FPRegs, FPRegs, FPRegs, CCOp,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
QFPRegs, QFPRegs, QFPRegs,
FPRegs, FPRegs, FPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
FPRegs, FPRegs, FPRegs,
DFPRegs, DFPRegs,
QFPRegs, QFPRegs,
FPRegs, FPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
FPRegs, FPRegs, FPRegs,
DFPRegs, DFPRegs,
FPRegs, FPRegs,
DFPRegs, DFPRegs,
FPRegs, FPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs,
FPRegs, FPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
FPRegs, FPRegs, FPRegs,
DFPRegs, DFPRegs, DFPRegs,
FPRegs, FPRegs, FPRegs,
FPRegs, FPRegs, FPRegs,
DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, QFPRegs,
FPRegs, QFPRegs,
FPRegs, QFPRegs,
DFPRegs, QFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, FPRegs, FPRegs,
DFPRegs, DFPRegs,
QFPRegs, QFPRegs,
FPRegs, FPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs,
FPRegs, FPRegs,
DFPRegs, DFPRegs,
FPRegs, FPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, FPRegs,
FPRegs, FPRegs,
QFPRegs, FPRegs,
DFPRegs, FPRegs,
DFPRegs, DFPRegs, DFPRegs,
QFPRegs, QFPRegs, QFPRegs,
FPRegs, FPRegs, FPRegs,
DFPRegs, DFPRegs, DFPRegs,
FPRegs, FPRegs, FPRegs,
DFPRegs, DFPRegs, DFPRegs,
FPRegs, FPRegs, FPRegs,
DFPRegs, DFPRegs,
QFPRegs, DFPRegs,
FPRegs, DFPRegs,
DFPRegs, DFPRegs,
FPRegs, FPRegs,
I64Regs, -1, -1, TailRelocSymGOTLoad,
IntRegs, -1, -1, TailRelocSymGOTLoad,
IntRegs, -1, i32imm,
IntRegs, -1, -1,
IntRegs, -1, i32imm,
IntRegs, -1, -1, ASITag,
-1, i32imm,
-1, -1,
CoprocRegs, -1, i32imm,
CoprocRegs, -1, -1,
IntPair, -1, i32imm,
IntPair, -1, -1, ASITag,
CoprocPair, -1, i32imm,
CoprocPair, -1, -1,
DFPRegs, -1, i32imm,
DFPRegs, -1, -1, ASITag,
DFPRegs, -1, i32imm,
DFPRegs, -1, -1,
IntPair, -1, i32imm,
IntPair, -1, -1,
FPRegs, -1, i32imm,
FPRegs, -1, -1, ASITag,
-1, i32imm,
-1, -1,
FPRegs, -1, i32imm,
FPRegs, -1, -1,
QFPRegs, -1, i32imm,
QFPRegs, -1, -1, ASITag,
QFPRegs, -1, i32imm,
QFPRegs, -1, -1,
IntRegs, -1, i32imm,
IntRegs, -1, -1, ASITag,
IntRegs, -1, i32imm,
IntRegs, -1, -1,
IntRegs, -1, i32imm,
IntRegs, -1, -1, ASITag,
IntRegs, -1, i32imm,
IntRegs, -1, -1,
IntRegs, -1, i32imm,
IntRegs, -1, -1, ASITag,
IntRegs, -1, i32imm,
IntRegs, -1, -1,
I64Regs, -1, i32imm,
I64Regs, -1, -1, ASITag,
I64Regs, -1, i32imm,
I64Regs, -1, -1,
IntRegs, -1, i32imm,
IntRegs, -1, -1, ASITag,
IntRegs, -1, i32imm,
IntRegs, -1, -1,
IntRegs, -1, i32imm,
IntRegs, -1, -1, ASITag,
IntRegs, -1, i32imm,
IntRegs, -1, -1,
I64Regs, -1, i32imm,
I64Regs, -1, -1, ASITag,
-1, i32imm,
-1, -1,
I64Regs, -1, i32imm,
I64Regs, -1, -1,
IntRegs, -1, i32imm,
IntRegs, -1, -1,
I64Regs, I64Regs,
MembarTag,
I64Regs, DFPRegs,
IntRegs, i32imm, IntRegs, CCOp,
IntRegs, IntRegs, IntRegs, CCOp,
IntRegs, i32imm, IntRegs, CCOp,
IntRegs, IntRegs, IntRegs, CCOp,
IntRegs, I64Regs, i32imm, IntRegs, RegCCOp,
IntRegs, I64Regs, IntRegs, IntRegs, RegCCOp,
I64Regs, DFPRegs,
I64Regs, DFPRegs,
DFPRegs, I64Regs,
IntRegs, i32imm, IntRegs, CCOp,
IntRegs, IntRegs, IntRegs, CCOp,
DFPRegs, I64Regs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, i64imm,
I64Regs, I64Regs, I64Regs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
DFPRegs, DFPRegs, DFPRegs,
DFPRegs, DFPRegs, DFPRegs,
IntRegs, IntRegs,
-1, i32imm, PrefetchTag,
-1, -1, ASITag, PrefetchTag,
-1, i32imm, PrefetchTag,
-1, -1, PrefetchTag,
IntRegs, simm13Op,
IntRegs, IntRegs,
IntRegs, ASRRegs,
IntRegs,
IntRegs, PRRegs,
IntRegs,
IntRegs,
IntRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
i32imm,
i32imm,
-1, i32imm,
-1, -1,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, i64imm,
I64Regs, I64Regs, I64Regs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, i32imm,
simm13Op,
I64Regs, I64Regs, shift_imm6,
I64Regs, I64Regs, IntRegs,
IntRegs, IntRegs, shift_imm5,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, simm13Op, ASRRegs,
IntRegs, IntRegs, IntRegs, ASRRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
I64Regs, I64Regs, shift_imm6,
I64Regs, I64Regs, IntRegs,
IntRegs, IntRegs, shift_imm5,
IntRegs, IntRegs, IntRegs,
I64Regs, I64Regs, shift_imm6,
I64Regs, I64Regs, IntRegs,
IntRegs, IntRegs, shift_imm5,
IntRegs, IntRegs, IntRegs,
-1, i32imm, IntRegs,
-1, -1, IntRegs, ASITag,
-1, i32imm, IntRegs,
-1, -1, IntRegs, ASITag,
-1, i32imm, IntRegs,
-1, -1, IntRegs,
-1, i32imm,
-1, -1,
-1, i32imm, CoprocRegs,
-1, -1, CoprocRegs,
-1, i32imm, IntPair,
-1, -1, IntPair, ASITag,
-1, i32imm,
-1, -1,
-1, i32imm, CoprocPair,
-1, -1, CoprocPair,
-1, i32imm, DFPRegs,
-1, -1, DFPRegs, ASITag,
-1, i32imm,
-1, -1,
-1, i32imm, DFPRegs,
-1, -1, DFPRegs,
-1, i32imm, IntPair,
-1, -1, IntPair,
-1, i32imm, FPRegs,
-1, -1, FPRegs, ASITag,
-1, i32imm,
-1, -1,
-1, i32imm, FPRegs,
-1, -1, FPRegs,
-1, i32imm, IntRegs,
-1, -1, IntRegs, ASITag,
-1, i32imm, IntRegs,
-1, -1, IntRegs,
-1, i32imm, QFPRegs,
-1, -1, QFPRegs, ASITag,
-1, i32imm, QFPRegs,
-1, -1, QFPRegs,
-1, i32imm, I64Regs,
-1, -1, I64Regs, ASITag,
-1, i32imm,
-1, -1,
-1, i32imm, I64Regs,
-1, -1, I64Regs,
-1, i32imm, IntRegs,
-1, -1, IntRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, -1, i32imm, IntRegs,
IntRegs, -1, -1, ASITag, IntRegs,
IntRegs, -1, i32imm, IntRegs,
IntRegs, -1, -1, IntRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
calltarget,
-1, i32imm,
IntRegs, i32imm, CCOp,
IntRegs, IntRegs, CCOp,
IntRegs, IntRegs, IntRegs, TailRelocSymTLSAdd,
calltarget, TailRelocSymTLSCall,
IntRegs, -1, -1, TailRelocSymTLSLoad,
IntRegs, -1, -1, TailRelocSymTLSLoad,
IntRegs, i32imm, CCOp,
IntRegs, IntRegs, CCOp,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, i32imm, CCOp,
IntRegs, IntRegs, CCOp,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, i64imm,
I64Regs, I64Regs, I64Regs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, simm13Op, ASRRegs,
IntRegs, IntRegs, IntRegs, ASRRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
I64Regs, I64Regs, I64Regs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
i32imm,
FCCRegs, DFPRegs, DFPRegs,
FCCRegs, DFPRegs, DFPRegs,
FCCRegs, QFPRegs, QFPRegs,
FCCRegs, FPRegs, FPRegs,
FCCRegs, QFPRegs, QFPRegs,
FCCRegs, FPRegs, FPRegs,
DFPRegs, FCCRegs, DFPRegs, DFPRegs, CCOp,
QFPRegs, FCCRegs, QFPRegs, QFPRegs, CCOp,
FPRegs, FCCRegs, FPRegs, FPRegs, CCOp,
IntRegs, FCCRegs, i32imm, IntRegs, CCOp,
IntRegs, FCCRegs, IntRegs, IntRegs, CCOp,
ASRRegs, IntRegs, simm13Op,
ASRRegs, IntRegs, IntRegs,
PRRegs, IntRegs, simm13Op,
PRRegs, IntRegs, IntRegs,
IntRegs, simm13Op,
IntRegs, IntRegs,
IntRegs, simm13Op,
IntRegs, IntRegs,
IntRegs, simm13Op,
IntRegs, IntRegs,
I64Regs, I64Regs, I64Regs,
I64Regs, I64Regs, I64Regs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
IntRegs, IntRegs, simm13Op,
IntRegs, IntRegs, IntRegs,
};
return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
}
}
}
#endif
#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
namespace llvm {
namespace SP {
LLVM_READONLY
static int getMemOperandSize(int OpType) {
switch (OpType) {
default: return 0;
}
}
}
}
#endif
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
namespace llvm {
namespace Sparc {
LLVM_READONLY static unsigned
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
return LogicalOpIdx;
}
LLVM_READONLY static inline unsigned
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
auto S = 0U;
for (auto i = 0U; i < LogicalOpIdx; ++i)
S += getLogicalOperandSize(Opcode, i);
return S;
}
}
}
#endif
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
namespace llvm {
namespace Sparc {
LLVM_READONLY static int
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
return -1;
}
}
}
#endif
#ifdef GET_INSTRINFO_MC_HELPER_DECLS
#undef GET_INSTRINFO_MC_HELPER_DECLS
namespace llvm {
class MCInst;
class FeatureBitset;
namespace Sparc_MC {
void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
}
}
#endif
#ifdef GET_INSTRINFO_MC_HELPERS
#undef GET_INSTRINFO_MC_HELPERS
namespace llvm {
namespace Sparc_MC {
}
}
#endif
#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
defined(GET_AVAILABLE_OPCODE_CHECKER)
#define GET_COMPUTE_FEATURES
#endif
#ifdef GET_COMPUTE_FEATURES
#undef GET_COMPUTE_FEATURES
namespace llvm {
namespace Sparc_MC {
enum SubtargetFeatureBits : uint8_t {
Feature_UseSoftMulDivBit = 6,
Feature_HasV9Bit = 2,
Feature_HasVISBit = 3,
Feature_HasVIS2Bit = 4,
Feature_HasVIS3Bit = 5,
Feature_HasCASABit = 0,
Feature_HasPWRPSRBit = 1,
};
inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
FeatureBitset Features;
if (FB[Sparc::FeatureSoftMulDiv])
Features.set(Feature_UseSoftMulDivBit);
if (FB[Sparc::FeatureV9])
Features.set(Feature_HasV9Bit);
if (FB[Sparc::FeatureVIS])
Features.set(Feature_HasVISBit);
if (FB[Sparc::FeatureVIS2])
Features.set(Feature_HasVIS2Bit);
if (FB[Sparc::FeatureVIS3])
Features.set(Feature_HasVIS3Bit);
if (FB[Sparc::LeonCASA] || FB[Sparc::FeatureV9])
Features.set(Feature_HasCASABit);
if (FB[Sparc::FeaturePWRPSR])
Features.set(Feature_HasPWRPSRBit);
return Features;
}
inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
enum : uint8_t {
CEFBS_None,
CEFBS_HasCASA,
CEFBS_HasPWRPSR,
CEFBS_HasV9,
CEFBS_HasVIS,
CEFBS_HasVIS2,
CEFBS_HasVIS3,
};
static constexpr FeatureBitset FeatureBitsets[] = {
{},
{Feature_HasCASABit, },
{Feature_HasPWRPSRBit, },
{Feature_HasV9Bit, },
{Feature_HasVISBit, },
{Feature_HasVIS2Bit, },
{Feature_HasVIS3Bit, },
};
static constexpr uint8_t RequiredFeaturesRefs[] = {
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS3,
CEFBS_HasVIS3,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS2,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS2,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_HasCASA,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS3,
CEFBS_HasVIS3,
CEFBS_HasVIS3,
CEFBS_HasV9,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS2,
CEFBS_HasVIS2,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS2,
CEFBS_HasVIS2,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS2,
CEFBS_HasVIS2,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasVIS3,
CEFBS_None,
CEFBS_HasV9,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_None,
CEFBS_HasV9,
CEFBS_None,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS,
CEFBS_HasVIS3,
CEFBS_HasVIS3,
CEFBS_HasVIS3,
CEFBS_HasVIS3,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS3,
CEFBS_HasVIS3,
CEFBS_None,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS3,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_None,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_None,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_None,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS3,
CEFBS_HasVIS3,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_None,
CEFBS_HasVIS3,
CEFBS_HasVIS3,
CEFBS_HasVIS3,
CEFBS_HasVIS3,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS3,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS3,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS3,
CEFBS_HasVIS3,
CEFBS_HasVIS3,
CEFBS_HasVIS3,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS3,
CEFBS_HasVIS3,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS3,
CEFBS_HasVIS3,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS,
CEFBS_HasVIS,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS3,
CEFBS_HasV9,
CEFBS_HasVIS3,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS3,
CEFBS_HasVIS3,
CEFBS_HasVIS3,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS3,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS,
CEFBS_HasVIS3,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasPWRPSR,
CEFBS_HasPWRPSR,
CEFBS_None,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS,
CEFBS_HasVIS2,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS3,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_HasV9,
CEFBS_HasV9,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_HasVIS3,
CEFBS_HasVIS3,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
};
assert(Opcode < 815);
return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
}
}
}
#endif
#ifdef GET_AVAILABLE_OPCODE_CHECKER
#undef GET_AVAILABLE_OPCODE_CHECKER
namespace llvm {
namespace Sparc_MC {
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
FeatureBitset MissingFeatures =
(AvailableFeatures & RequiredFeatures) ^
RequiredFeatures;
return !MissingFeatures.any();
}
}
}
#endif
#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
#undef ENABLE_INSTR_PREDICATE_VERIFIER
#include <sstream>
namespace llvm {
namespace Sparc_MC {
#ifndef NDEBUG
static const char *SubtargetFeatureNames[] = {
"Feature_HasCASA",
"Feature_HasPWRPSR",
"Feature_HasV9",
"Feature_HasVIS",
"Feature_HasVIS2",
"Feature_HasVIS3",
"Feature_UseSoftMulDiv",
nullptr
};
#endif
void verifyInstructionPredicates(
unsigned Opcode, const FeatureBitset &Features) {
#ifndef NDEBUG
FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
FeatureBitset MissingFeatures =
(AvailableFeatures & RequiredFeatures) ^
RequiredFeatures;
if (MissingFeatures.any()) {
std::ostringstream Msg;
Msg << "Attempting to emit " << &SparcInstrNameData[SparcInstrNameIndices[Opcode]]
<< " instruction but the ";
for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
if (MissingFeatures.test(i))
Msg << SubtargetFeatureNames[i] << " ";
Msg << "predicate(s) are not met";
report_fatal_error(Msg.str().c_str());
}
#endif
}
}
}
#endif