/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM namespace llvm { namespace WebAssembly { enum { … }; } // end namespace WebAssembly } // end namespace llvm #endif // GET_INSTRINFO_ENUM #ifdef GET_INSTRINFO_SCHED_ENUM #undef GET_INSTRINFO_SCHED_ENUM namespace llvm { namespace WebAssembly { namespace Sched { enum { NoInstrModel = 0, SCHED_LIST_END = 1 }; } // end namespace Sched } // end namespace WebAssembly } // end namespace llvm #endif // GET_INSTRINFO_SCHED_ENUM #if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) namespace llvm { struct WebAssemblyInstrTable { MCInstrDesc Insts[1917]; static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo"); MCOperandInfo OperandInfo[810]; static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps"); MCPhysReg ImplicitOps[10]; }; } // end namespace llvm #endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) #ifdef GET_INSTRINFO_MC_DESC #undef GET_INSTRINFO_MC_DESC namespace llvm { static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0); static constexpr unsigned WebAssemblyImpOpBase = sizeof WebAssemblyInstrTable::OperandInfo / (sizeof(MCPhysReg)); extern const WebAssemblyInstrTable WebAssemblyDescs = { { { 1916, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1916 = uint_to_fp_F32x4_S { 1915, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1915 = uint_to_fp_F32x4 { 1914, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1914 = uint_to_fp_F16x8_S { 1913, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1913 = uint_to_fp_F16x8 { 1912, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1912 = trunc_sat_zero_u_I32x4_S { 1911, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1911 = trunc_sat_zero_u_I32x4 { 1910, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1910 = trunc_sat_zero_s_I32x4_S { 1909, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1909 = trunc_sat_zero_s_I32x4 { 1908, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1908 = sint_to_fp_F32x4_S { 1907, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1907 = sint_to_fp_F32x4 { 1906, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1906 = sint_to_fp_F16x8_S { 1905, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1905 = sint_to_fp_F16x8 { 1904, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1904 = promote_low_F64x2_S { 1903, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1903 = promote_low_F64x2 { 1902, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1902 = int_wasm_relaxed_trunc_unsigned_zero_I32x4_S { 1901, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1901 = int_wasm_relaxed_trunc_unsigned_zero_I32x4 { 1900, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1900 = int_wasm_relaxed_trunc_unsigned_I32x4_S { 1899, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1899 = int_wasm_relaxed_trunc_unsigned_I32x4 { 1898, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1898 = int_wasm_relaxed_trunc_signed_zero_I32x4_S { 1897, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1897 = int_wasm_relaxed_trunc_signed_zero_I32x4 { 1896, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1896 = int_wasm_relaxed_trunc_signed_I32x4_S { 1895, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1895 = int_wasm_relaxed_trunc_signed_I32x4 { 1894, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1894 = int_wasm_extadd_pairwise_unsigned_I32x4_S { 1893, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1893 = int_wasm_extadd_pairwise_unsigned_I32x4 { 1892, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1892 = int_wasm_extadd_pairwise_unsigned_I16x8_S { 1891, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1891 = int_wasm_extadd_pairwise_unsigned_I16x8 { 1890, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1890 = int_wasm_extadd_pairwise_signed_I32x4_S { 1889, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1889 = int_wasm_extadd_pairwise_signed_I32x4 { 1888, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1888 = int_wasm_extadd_pairwise_signed_I16x8_S { 1887, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1887 = int_wasm_extadd_pairwise_signed_I16x8 { 1886, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1886 = fp_to_uint_I32x4_S { 1885, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1885 = fp_to_uint_I32x4 { 1884, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1884 = fp_to_uint_I16x8_S { 1883, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1883 = fp_to_uint_I16x8 { 1882, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1882 = fp_to_sint_I32x4_S { 1881, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1881 = fp_to_sint_I32x4 { 1880, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1880 = fp_to_sint_I16x8_S { 1879, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1879 = fp_to_sint_I16x8 { 1878, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1878 = extend_low_u_I64x2_S { 1877, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1877 = extend_low_u_I64x2 { 1876, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1876 = extend_low_u_I32x4_S { 1875, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1875 = extend_low_u_I32x4 { 1874, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1874 = extend_low_u_I16x8_S { 1873, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1873 = extend_low_u_I16x8 { 1872, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1872 = extend_low_s_I64x2_S { 1871, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1871 = extend_low_s_I64x2 { 1870, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1870 = extend_low_s_I32x4_S { 1869, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1869 = extend_low_s_I32x4 { 1868, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1868 = extend_low_s_I16x8_S { 1867, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1867 = extend_low_s_I16x8 { 1866, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1866 = extend_high_u_I64x2_S { 1865, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1865 = extend_high_u_I64x2 { 1864, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1864 = extend_high_u_I32x4_S { 1863, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1863 = extend_high_u_I32x4 { 1862, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1862 = extend_high_u_I16x8_S { 1861, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1861 = extend_high_u_I16x8 { 1860, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1860 = extend_high_s_I64x2_S { 1859, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1859 = extend_high_s_I64x2 { 1858, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1858 = extend_high_s_I32x4_S { 1857, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1857 = extend_high_s_I32x4 { 1856, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1856 = extend_high_s_I16x8_S { 1855, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1855 = extend_high_s_I16x8 { 1854, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1854 = demote_zero_F32x4_S { 1853, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1853 = demote_zero_F32x4 { 1852, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1852 = convert_low_u_F64x2_S { 1851, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1851 = convert_low_u_F64x2 { 1850, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1850 = convert_low_s_F64x2_S { 1849, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1849 = convert_low_s_F64x2 { 1848, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 790, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1848 = anonymous_8934MEMORY_INIT_A64_S { 1847, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 805, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1847 = anonymous_8934MEMORY_INIT_A64 { 1846, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 301, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1846 = anonymous_8934MEMORY_FILL_A64_S { 1845, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 801, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1845 = anonymous_8934MEMORY_FILL_A64 { 1844, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 790, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1844 = anonymous_8934MEMORY_COPY_A64_S { 1843, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 796, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1843 = anonymous_8934MEMORY_COPY_A64 { 1842, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 301, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1842 = anonymous_8934DATA_DROP_S { 1841, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 301, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1841 = anonymous_8934DATA_DROP { 1840, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 790, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1840 = anonymous_8933MEMORY_INIT_A32_S { 1839, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 785, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1839 = anonymous_8933MEMORY_INIT_A32 { 1838, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 301, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1838 = anonymous_8933MEMORY_FILL_A32_S { 1837, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 792, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1837 = anonymous_8933MEMORY_FILL_A32 { 1836, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 790, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1836 = anonymous_8933MEMORY_COPY_A32_S { 1835, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 785, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1835 = anonymous_8933MEMORY_COPY_A32 { 1834, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 301, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1834 = anonymous_8933DATA_DROP_S { 1833, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 301, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1833 = anonymous_8933DATA_DROP { 1832, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1832 = anonymous_8213MEMORY_SIZE_A64_S { 1831, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 190, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1831 = anonymous_8213MEMORY_SIZE_A64 { 1830, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1830 = anonymous_8213MEMORY_GROW_A64_S { 1829, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 782, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1829 = anonymous_8213MEMORY_GROW_A64 { 1828, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1828 = anonymous_8212MEMORY_SIZE_A32_S { 1827, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1827 = anonymous_8212MEMORY_SIZE_A32 { 1826, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1826 = anonymous_8212MEMORY_GROW_A32_S { 1825, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 779, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1825 = anonymous_8212MEMORY_GROW_A32 { 1824, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1824 = XOR_S { 1823, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1823 = XOR_I64_S { 1822, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1822 = XOR_I64 { 1821, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1821 = XOR_I32_S { 1820, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1820 = XOR_I32 { 1819, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1819 = XOR { 1818, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1818 = UNREACHABLE_S { 1817, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1817 = UNREACHABLE { 1816, 2, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 777, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1816 = TRY_TABLE_S { 1815, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1815 = TRY_TABLE { 1814, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1814 = TRY_S { 1813, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1813 = TRY { 1812, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1812 = TRUNC_F64x2_S { 1811, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1811 = TRUNC_F64x2 { 1810, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1810 = TRUNC_F64_S { 1809, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1809 = TRUNC_F64 { 1808, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1808 = TRUNC_F32x4_S { 1807, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1807 = TRUNC_F32x4 { 1806, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1806 = TRUNC_F32_S { 1805, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1805 = TRUNC_F32 { 1804, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1804 = TRUNC_F16x8_S { 1803, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1803 = TRUNC_F16x8 { 1802, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1802 = THROW_S { 1801, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1801 = THROW_REF_S { 1800, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1800 = THROW_REF { 1799, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1799 = THROW { 1798, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1798 = TEE_V128_S { 1797, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1797 = TEE_V128 { 1796, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1796 = TEE_I64_S { 1795, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1795 = TEE_I64 { 1794, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1794 = TEE_I32_S { 1793, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1793 = TEE_I32 { 1792, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1792 = TEE_FUNCREF_S { 1791, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 774, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1791 = TEE_FUNCREF { 1790, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1790 = TEE_F64_S { 1789, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1789 = TEE_F64 { 1788, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1788 = TEE_F32_S { 1787, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1787 = TEE_F32 { 1786, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1786 = TEE_EXTERNREF_S { 1785, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 771, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1785 = TEE_EXTERNREF { 1784, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1784 = TEE_EXNREF_S { 1783, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 768, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1783 = TEE_EXNREF { 1782, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1782 = TABLE_SIZE_S { 1781, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 766, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1781 = TABLE_SIZE { 1780, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1780 = TABLE_SET_FUNCREF_S { 1779, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 763, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1779 = TABLE_SET_FUNCREF { 1778, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1778 = TABLE_SET_EXTERNREF_S { 1777, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 760, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1777 = TABLE_SET_EXTERNREF { 1776, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1776 = TABLE_SET_EXNREF_S { 1775, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 757, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1775 = TABLE_SET_EXNREF { 1774, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1774 = TABLE_GROW_FUNCREF_S { 1773, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 753, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1773 = TABLE_GROW_FUNCREF { 1772, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1772 = TABLE_GROW_EXTERNREF_S { 1771, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 749, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1771 = TABLE_GROW_EXTERNREF { 1770, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1770 = TABLE_GROW_EXNREF_S { 1769, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 745, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1769 = TABLE_GROW_EXNREF { 1768, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1768 = TABLE_GET_FUNCREF_S { 1767, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 742, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1767 = TABLE_GET_FUNCREF { 1766, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1766 = TABLE_GET_EXTERNREF_S { 1765, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 739, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1765 = TABLE_GET_EXTERNREF { 1764, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1764 = TABLE_GET_EXNREF_S { 1763, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 736, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1763 = TABLE_GET_EXNREF { 1762, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1762 = TABLE_FILL_FUNCREF_S { 1761, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 732, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1761 = TABLE_FILL_FUNCREF { 1760, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1760 = TABLE_FILL_EXTERNREF_S { 1759, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 728, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1759 = TABLE_FILL_EXTERNREF { 1758, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1758 = TABLE_FILL_EXNREF_S { 1757, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 723, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1757 = TABLE_FILL_EXNREF { 1756, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 721, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1756 = TABLE_COPY_S { 1755, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 716, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1755 = TABLE_COPY { 1754, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1754 = SWIZZLE_S { 1753, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1753 = SWIZZLE { 1752, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1752 = SUB_SAT_U_I8x16_S { 1751, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1751 = SUB_SAT_U_I8x16 { 1750, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1750 = SUB_SAT_U_I16x8_S { 1749, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1749 = SUB_SAT_U_I16x8 { 1748, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1748 = SUB_SAT_S_I8x16_S { 1747, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1747 = SUB_SAT_S_I8x16 { 1746, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1746 = SUB_SAT_S_I16x8_S { 1745, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1745 = SUB_SAT_S_I16x8 { 1744, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1744 = SUB_I8x16_S { 1743, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1743 = SUB_I8x16 { 1742, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1742 = SUB_I64x2_S { 1741, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1741 = SUB_I64x2 { 1740, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1740 = SUB_I64_S { 1739, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1739 = SUB_I64 { 1738, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1738 = SUB_I32x4_S { 1737, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1737 = SUB_I32x4 { 1736, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1736 = SUB_I32_S { 1735, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1735 = SUB_I32 { 1734, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1734 = SUB_I16x8_S { 1733, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1733 = SUB_I16x8 { 1732, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1732 = SUB_F64x2_S { 1731, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1731 = SUB_F64x2 { 1730, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1730 = SUB_F64_S { 1729, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1729 = SUB_F64 { 1728, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1728 = SUB_F32x4_S { 1727, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1727 = SUB_F32x4 { 1726, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1726 = SUB_F32_S { 1725, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1725 = SUB_F32 { 1724, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1724 = SUB_F16x8_S { 1723, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1723 = SUB_F16x8 { 1722, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1722 = STORE_V128_A64_S { 1721, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 712, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1721 = STORE_V128_A64 { 1720, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1720 = STORE_V128_A32_S { 1719, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 708, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1719 = STORE_V128_A32 { 1718, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1718 = STORE_LANE_I8x16_A64_S { 1717, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 703, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1717 = STORE_LANE_I8x16_A64 { 1716, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1716 = STORE_LANE_I8x16_A32_S { 1715, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 698, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1715 = STORE_LANE_I8x16_A32 { 1714, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1714 = STORE_LANE_I64x2_A64_S { 1713, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 703, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1713 = STORE_LANE_I64x2_A64 { 1712, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1712 = STORE_LANE_I64x2_A32_S { 1711, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 698, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1711 = STORE_LANE_I64x2_A32 { 1710, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1710 = STORE_LANE_I32x4_A64_S { 1709, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 703, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1709 = STORE_LANE_I32x4_A64 { 1708, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1708 = STORE_LANE_I32x4_A32_S { 1707, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 698, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1707 = STORE_LANE_I32x4_A32 { 1706, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1706 = STORE_LANE_I16x8_A64_S { 1705, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 703, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1705 = STORE_LANE_I16x8_A64 { 1704, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1704 = STORE_LANE_I16x8_A32_S { 1703, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 698, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1703 = STORE_LANE_I16x8_A32 { 1702, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1702 = STORE_I64_A64_S { 1701, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1701 = STORE_I64_A64 { 1700, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1700 = STORE_I64_A32_S { 1699, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1699 = STORE_I64_A32 { 1698, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1698 = STORE_I32_A64_S { 1697, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1697 = STORE_I32_A64 { 1696, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1696 = STORE_I32_A32_S { 1695, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1695 = STORE_I32_A32 { 1694, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1694 = STORE_F64_A64_S { 1693, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 694, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1693 = STORE_F64_A64 { 1692, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1692 = STORE_F64_A32_S { 1691, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 690, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1691 = STORE_F64_A32 { 1690, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1690 = STORE_F32_A64_S { 1689, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 686, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1689 = STORE_F32_A64 { 1688, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1688 = STORE_F32_A32_S { 1687, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 682, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1687 = STORE_F32_A32 { 1686, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1686 = STORE_F16_F32_A64_S { 1685, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 686, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1685 = STORE_F16_F32_A64 { 1684, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1684 = STORE_F16_F32_A32_S { 1683, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 682, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1683 = STORE_F16_F32_A32 { 1682, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1682 = STORE8_I64_A64_S { 1681, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1681 = STORE8_I64_A64 { 1680, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1680 = STORE8_I64_A32_S { 1679, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1679 = STORE8_I64_A32 { 1678, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1678 = STORE8_I32_A64_S { 1677, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1677 = STORE8_I32_A64 { 1676, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1676 = STORE8_I32_A32_S { 1675, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1675 = STORE8_I32_A32 { 1674, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1674 = STORE32_I64_A64_S { 1673, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1673 = STORE32_I64_A64 { 1672, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1672 = STORE32_I64_A32_S { 1671, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1671 = STORE32_I64_A32 { 1670, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1670 = STORE16_I64_A64_S { 1669, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1669 = STORE16_I64_A64 { 1668, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1668 = STORE16_I64_A32_S { 1667, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1667 = STORE16_I64_A32 { 1666, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1666 = STORE16_I32_A64_S { 1665, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1665 = STORE16_I32_A64 { 1664, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1664 = STORE16_I32_A32_S { 1663, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1663 = STORE16_I32_A32 { 1662, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1662 = SQRT_F64x2_S { 1661, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1661 = SQRT_F64x2 { 1660, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1660 = SQRT_F64_S { 1659, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1659 = SQRT_F64 { 1658, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1658 = SQRT_F32x4_S { 1657, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1657 = SQRT_F32x4 { 1656, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1656 = SQRT_F32_S { 1655, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1655 = SQRT_F32 { 1654, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1654 = SQRT_F16x8_S { 1653, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1653 = SQRT_F16x8 { 1652, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1652 = SPLAT_I8x16_S { 1651, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 678, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1651 = SPLAT_I8x16 { 1650, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1650 = SPLAT_I64x2_S { 1649, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 680, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1649 = SPLAT_I64x2 { 1648, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1648 = SPLAT_I32x4_S { 1647, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 678, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1647 = SPLAT_I32x4 { 1646, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1646 = SPLAT_I16x8_S { 1645, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 678, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1645 = SPLAT_I16x8 { 1644, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1644 = SPLAT_F64x2_S { 1643, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 676, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1643 = SPLAT_F64x2 { 1642, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1642 = SPLAT_F32x4_S { 1641, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 674, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1641 = SPLAT_F32x4 { 1640, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1640 = SPLAT_F16x8_S { 1639, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 674, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1639 = SPLAT_F16x8 { 1638, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1638 = SIMD_RELAXED_FMIN_F64x2_S { 1637, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1637 = SIMD_RELAXED_FMIN_F64x2 { 1636, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1636 = SIMD_RELAXED_FMIN_F32x4_S { 1635, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1635 = SIMD_RELAXED_FMIN_F32x4 { 1634, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1634 = SIMD_RELAXED_FMAX_F64x2_S { 1633, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1633 = SIMD_RELAXED_FMAX_F64x2 { 1632, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1632 = SIMD_RELAXED_FMAX_F32x4_S { 1631, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1631 = SIMD_RELAXED_FMAX_F32x4 { 1630, 16, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 367, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1630 = SHUFFLE_S { 1629, 19, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 655, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1629 = SHUFFLE { 1628, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1628 = SHR_U_I8x16_S { 1627, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1627 = SHR_U_I8x16 { 1626, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1626 = SHR_U_I64x2_S { 1625, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1625 = SHR_U_I64x2 { 1624, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1624 = SHR_U_I64_S { 1623, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1623 = SHR_U_I64 { 1622, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1622 = SHR_U_I32x4_S { 1621, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1621 = SHR_U_I32x4 { 1620, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1620 = SHR_U_I32_S { 1619, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1619 = SHR_U_I32 { 1618, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1618 = SHR_U_I16x8_S { 1617, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1617 = SHR_U_I16x8 { 1616, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1616 = SHR_S_I8x16_S { 1615, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1615 = SHR_S_I8x16 { 1614, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1614 = SHR_S_I64x2_S { 1613, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1613 = SHR_S_I64x2 { 1612, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1612 = SHR_S_I64_S { 1611, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1611 = SHR_S_I64 { 1610, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1610 = SHR_S_I32x4_S { 1609, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1609 = SHR_S_I32x4 { 1608, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1608 = SHR_S_I32_S { 1607, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1607 = SHR_S_I32 { 1606, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1606 = SHR_S_I16x8_S { 1605, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1605 = SHR_S_I16x8 { 1604, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1604 = SHL_I8x16_S { 1603, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1603 = SHL_I8x16 { 1602, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1602 = SHL_I64x2_S { 1601, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1601 = SHL_I64x2 { 1600, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1600 = SHL_I64_S { 1599, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1599 = SHL_I64 { 1598, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1598 = SHL_I32x4_S { 1597, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1597 = SHL_I32x4 { 1596, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1596 = SHL_I32_S { 1595, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1595 = SHL_I32 { 1594, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1594 = SHL_I16x8_S { 1593, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1593 = SHL_I16x8 { 1592, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1592 = SELECT_V128_S { 1591, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 648, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1591 = SELECT_V128 { 1590, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1590 = SELECT_I64_S { 1589, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 644, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1589 = SELECT_I64 { 1588, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1588 = SELECT_I32_S { 1587, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 640, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1587 = SELECT_I32 { 1586, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1586 = SELECT_FUNCREF_S { 1585, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 636, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1585 = SELECT_FUNCREF { 1584, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1584 = SELECT_F64_S { 1583, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 632, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1583 = SELECT_F64 { 1582, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1582 = SELECT_F32_S { 1581, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 628, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1581 = SELECT_F32 { 1580, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1580 = SELECT_EXTERNREF_S { 1579, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 624, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1579 = SELECT_EXTERNREF { 1578, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1578 = SELECT_EXNREF_S { 1577, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 620, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1577 = SELECT_EXNREF { 1576, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1576 = ROTR_I64_S { 1575, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1575 = ROTR_I64 { 1574, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1574 = ROTR_I32_S { 1573, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1573 = ROTR_I32 { 1572, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1572 = ROTL_I64_S { 1571, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1571 = ROTL_I64 { 1570, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1570 = ROTL_I32_S { 1569, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1569 = ROTL_I32 { 1568, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1568 = RET_CALL_S { 1567, 2, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 285, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1567 = RET_CALL_INDIRECT_S { 1566, 2, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 285, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1566 = RET_CALL_INDIRECT { 1565, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1565 = RET_CALL { 1564, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1564 = RETURN_S { 1563, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1563 = RETURN { 1562, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1562 = RETHROW_S { 1561, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1561 = RETHROW { 1560, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1560 = REPLACE_LANE_I8x16_S { 1559, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 612, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1559 = REPLACE_LANE_I8x16 { 1558, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1558 = REPLACE_LANE_I64x2_S { 1557, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 616, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1557 = REPLACE_LANE_I64x2 { 1556, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1556 = REPLACE_LANE_I32x4_S { 1555, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 612, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1555 = REPLACE_LANE_I32x4 { 1554, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1554 = REPLACE_LANE_I16x8_S { 1553, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 612, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1553 = REPLACE_LANE_I16x8 { 1552, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1552 = REPLACE_LANE_F64x2_S { 1551, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 608, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1551 = REPLACE_LANE_F64x2 { 1550, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1550 = REPLACE_LANE_F32x4_S { 1549, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 604, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1549 = REPLACE_LANE_F32x4 { 1548, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1548 = REPLACE_LANE_F16x8_S { 1547, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 604, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1547 = REPLACE_LANE_F16x8 { 1546, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1546 = REM_U_I64_S { 1545, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1545 = REM_U_I64 { 1544, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1544 = REM_U_I32_S { 1543, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1543 = REM_U_I32 { 1542, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1542 = REM_S_I64_S { 1541, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1541 = REM_S_I64 { 1540, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1540 = REM_S_I32_S { 1539, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1539 = REM_S_I32 { 1538, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1538 = RELAXED_SWIZZLE_S { 1537, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1537 = RELAXED_SWIZZLE { 1536, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1536 = RELAXED_Q15MULR_S_I16x8_S { 1535, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1535 = RELAXED_Q15MULR_S_I16x8 { 1534, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1534 = RELAXED_DOT_S { 1533, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1533 = RELAXED_DOT_BFLOAT_S { 1532, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1532 = RELAXED_DOT_BFLOAT { 1531, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1531 = RELAXED_DOT_ADD_S { 1530, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1530 = RELAXED_DOT_ADD { 1529, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1529 = RELAXED_DOT { 1528, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1528 = REF_NULL_FUNCREF_S { 1527, 1, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 392, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1527 = REF_NULL_FUNCREF { 1526, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1526 = REF_NULL_EXTERNREF_S { 1525, 1, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 389, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1525 = REF_NULL_EXTERNREF { 1524, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1524 = REF_NULL_EXNREF_S { 1523, 1, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1523 = REF_NULL_EXNREF { 1522, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1522 = REF_IS_NULL_FUNCREF_S { 1521, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 602, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1521 = REF_IS_NULL_FUNCREF { 1520, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1520 = REF_IS_NULL_EXTERNREF_S { 1519, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 600, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1519 = REF_IS_NULL_EXTERNREF { 1518, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1518 = REF_IS_NULL_EXNREF_S { 1517, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 598, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1517 = REF_IS_NULL_EXNREF { 1516, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1516 = Q15MULR_SAT_S_I16x8_S { 1515, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1515 = Q15MULR_SAT_S_I16x8 { 1514, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1514 = POPCNT_I8x16_S { 1513, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1513 = POPCNT_I8x16 { 1512, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1512 = POPCNT_I64_S { 1511, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 291, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1511 = POPCNT_I64 { 1510, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1510 = POPCNT_I32_S { 1509, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 289, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1509 = POPCNT_I32 { 1508, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1508 = PMIN_F64x2_S { 1507, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1507 = PMIN_F64x2 { 1506, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1506 = PMIN_F32x4_S { 1505, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1505 = PMIN_F32x4 { 1504, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1504 = PMIN_F16x8_S { 1503, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1503 = PMIN_F16x8 { 1502, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1502 = PMAX_F64x2_S { 1501, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1501 = PMAX_F64x2 { 1500, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1500 = PMAX_F32x4_S { 1499, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1499 = PMAX_F32x4 { 1498, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1498 = PMAX_F16x8_S { 1497, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1497 = PMAX_F16x8 { 1496, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1496 = OR_S { 1495, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1495 = OR_I64_S { 1494, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1494 = OR_I64 { 1493, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1493 = OR_I32_S { 1492, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1492 = OR_I32 { 1491, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1491 = OR { 1490, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1490 = NOT_S { 1489, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1489 = NOT { 1488, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1488 = NOP_S { 1487, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1487 = NOP { 1486, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1486 = NMADD_F64x2_S { 1485, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1485 = NMADD_F64x2 { 1484, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1484 = NMADD_F32x4_S { 1483, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1483 = NMADD_F32x4 { 1482, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1482 = NMADD_F16x8_S { 1481, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1481 = NMADD_F16x8 { 1480, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1480 = NE_I8x16_S { 1479, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1479 = NE_I8x16 { 1478, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1478 = NE_I64x2_S { 1477, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1477 = NE_I64x2 { 1476, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1476 = NE_I64_S { 1475, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1475 = NE_I64 { 1474, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1474 = NE_I32x4_S { 1473, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1473 = NE_I32x4 { 1472, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1472 = NE_I32_S { 1471, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1471 = NE_I32 { 1470, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1470 = NE_I16x8_S { 1469, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1469 = NE_I16x8 { 1468, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1468 = NE_F64x2_S { 1467, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1467 = NE_F64x2 { 1466, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1466 = NE_F64_S { 1465, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1465 = NE_F64 { 1464, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1464 = NE_F32x4_S { 1463, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1463 = NE_F32x4 { 1462, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1462 = NE_F32_S { 1461, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1461 = NE_F32 { 1460, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1460 = NE_F16x8_S { 1459, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1459 = NE_F16x8 { 1458, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1458 = NEG_I8x16_S { 1457, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1457 = NEG_I8x16 { 1456, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1456 = NEG_I64x2_S { 1455, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1455 = NEG_I64x2 { 1454, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1454 = NEG_I32x4_S { 1453, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1453 = NEG_I32x4 { 1452, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1452 = NEG_I16x8_S { 1451, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1451 = NEG_I16x8 { 1450, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1450 = NEG_F64x2_S { 1449, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1449 = NEG_F64x2 { 1448, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1448 = NEG_F64_S { 1447, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1447 = NEG_F64 { 1446, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1446 = NEG_F32x4_S { 1445, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1445 = NEG_F32x4 { 1444, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1444 = NEG_F32_S { 1443, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1443 = NEG_F32 { 1442, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1442 = NEG_F16x8_S { 1441, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1441 = NEG_F16x8 { 1440, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1440 = NEAREST_F64x2_S { 1439, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1439 = NEAREST_F64x2 { 1438, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1438 = NEAREST_F64_S { 1437, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1437 = NEAREST_F64 { 1436, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1436 = NEAREST_F32x4_S { 1435, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1435 = NEAREST_F32x4 { 1434, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1434 = NEAREST_F32_S { 1433, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1433 = NEAREST_F32 { 1432, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1432 = NEAREST_F16x8_S { 1431, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1431 = NEAREST_F16x8 { 1430, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1430 = NARROW_U_I8x16_S { 1429, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1429 = NARROW_U_I8x16 { 1428, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1428 = NARROW_U_I16x8_S { 1427, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1427 = NARROW_U_I16x8 { 1426, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1426 = NARROW_S_I8x16_S { 1425, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1425 = NARROW_S_I8x16 { 1424, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1424 = NARROW_S_I16x8_S { 1423, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1423 = NARROW_S_I16x8 { 1422, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1422 = MUL_I64x2_S { 1421, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1421 = MUL_I64x2 { 1420, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1420 = MUL_I64_S { 1419, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1419 = MUL_I64 { 1418, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1418 = MUL_I32x4_S { 1417, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1417 = MUL_I32x4 { 1416, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1416 = MUL_I32_S { 1415, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1415 = MUL_I32 { 1414, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1414 = MUL_I16x8_S { 1413, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1413 = MUL_I16x8 { 1412, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1412 = MUL_F64x2_S { 1411, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1411 = MUL_F64x2 { 1410, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1410 = MUL_F64_S { 1409, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1409 = MUL_F64 { 1408, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1408 = MUL_F32x4_S { 1407, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1407 = MUL_F32x4 { 1406, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1406 = MUL_F32_S { 1405, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1405 = MUL_F32 { 1404, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1404 = MUL_F16x8_S { 1403, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1403 = MUL_F16x8 { 1402, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1402 = MIN_U_I8x16_S { 1401, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1401 = MIN_U_I8x16 { 1400, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1400 = MIN_U_I32x4_S { 1399, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1399 = MIN_U_I32x4 { 1398, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1398 = MIN_U_I16x8_S { 1397, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1397 = MIN_U_I16x8 { 1396, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1396 = MIN_S_I8x16_S { 1395, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1395 = MIN_S_I8x16 { 1394, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1394 = MIN_S_I32x4_S { 1393, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1393 = MIN_S_I32x4 { 1392, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1392 = MIN_S_I16x8_S { 1391, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1391 = MIN_S_I16x8 { 1390, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1390 = MIN_F64x2_S { 1389, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1389 = MIN_F64x2 { 1388, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1388 = MIN_F64_S { 1387, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1387 = MIN_F64 { 1386, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1386 = MIN_F32x4_S { 1385, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1385 = MIN_F32x4 { 1384, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1384 = MIN_F32_S { 1383, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1383 = MIN_F32 { 1382, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1382 = MIN_F16x8_S { 1381, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1381 = MIN_F16x8 { 1380, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1380 = MEMORY_ATOMIC_WAIT64_A64_S { 1379, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 592, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1379 = MEMORY_ATOMIC_WAIT64_A64 { 1378, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1378 = MEMORY_ATOMIC_WAIT64_A32_S { 1377, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1377 = MEMORY_ATOMIC_WAIT64_A32 { 1376, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1376 = MEMORY_ATOMIC_WAIT32_A64_S { 1375, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 580, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1375 = MEMORY_ATOMIC_WAIT32_A64 { 1374, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1374 = MEMORY_ATOMIC_WAIT32_A32_S { 1373, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 574, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1373 = MEMORY_ATOMIC_WAIT32_A32 { 1372, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1372 = MEMORY_ATOMIC_NOTIFY_A64_S { 1371, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1371 = MEMORY_ATOMIC_NOTIFY_A64 { 1370, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1370 = MEMORY_ATOMIC_NOTIFY_A32_S { 1369, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1369 = MEMORY_ATOMIC_NOTIFY_A32 { 1368, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1368 = MAX_U_I8x16_S { 1367, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1367 = MAX_U_I8x16 { 1366, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1366 = MAX_U_I32x4_S { 1365, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1365 = MAX_U_I32x4 { 1364, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1364 = MAX_U_I16x8_S { 1363, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1363 = MAX_U_I16x8 { 1362, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1362 = MAX_S_I8x16_S { 1361, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1361 = MAX_S_I8x16 { 1360, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1360 = MAX_S_I32x4_S { 1359, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1359 = MAX_S_I32x4 { 1358, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1358 = MAX_S_I16x8_S { 1357, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1357 = MAX_S_I16x8 { 1356, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1356 = MAX_F64x2_S { 1355, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1355 = MAX_F64x2 { 1354, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1354 = MAX_F64_S { 1353, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1353 = MAX_F64 { 1352, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1352 = MAX_F32x4_S { 1351, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1351 = MAX_F32x4 { 1350, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1350 = MAX_F32_S { 1349, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1349 = MAX_F32 { 1348, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1348 = MAX_F16x8_S { 1347, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1347 = MAX_F16x8 { 1346, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1346 = MADD_F64x2_S { 1345, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1345 = MADD_F64x2 { 1344, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1344 = MADD_F32x4_S { 1343, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1343 = MADD_F32x4 { 1342, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1342 = MADD_F16x8_S { 1341, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1341 = MADD_F16x8 { 1340, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1340 = LT_U_I8x16_S { 1339, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1339 = LT_U_I8x16 { 1338, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1338 = LT_U_I64_S { 1337, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1337 = LT_U_I64 { 1336, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1336 = LT_U_I32x4_S { 1335, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1335 = LT_U_I32x4 { 1334, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1334 = LT_U_I32_S { 1333, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1333 = LT_U_I32 { 1332, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1332 = LT_U_I16x8_S { 1331, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1331 = LT_U_I16x8 { 1330, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1330 = LT_S_I8x16_S { 1329, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1329 = LT_S_I8x16 { 1328, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1328 = LT_S_I64x2_S { 1327, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1327 = LT_S_I64x2 { 1326, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1326 = LT_S_I64_S { 1325, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1325 = LT_S_I64 { 1324, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1324 = LT_S_I32x4_S { 1323, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1323 = LT_S_I32x4 { 1322, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1322 = LT_S_I32_S { 1321, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1321 = LT_S_I32 { 1320, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1320 = LT_S_I16x8_S { 1319, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1319 = LT_S_I16x8 { 1318, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1318 = LT_F64x2_S { 1317, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1317 = LT_F64x2 { 1316, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1316 = LT_F64_S { 1315, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1315 = LT_F64 { 1314, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1314 = LT_F32x4_S { 1313, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1313 = LT_F32x4 { 1312, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1312 = LT_F32_S { 1311, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1311 = LT_F32 { 1310, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1310 = LT_F16x8_S { 1309, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1309 = LT_F16x8 { 1308, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1308 = LOOP_S { 1307, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1307 = LOOP { 1306, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1306 = LOCAL_TEE_V128_S { 1305, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 571, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1305 = LOCAL_TEE_V128 { 1304, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1304 = LOCAL_TEE_I64_S { 1303, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 568, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1303 = LOCAL_TEE_I64 { 1302, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1302 = LOCAL_TEE_I32_S { 1301, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 565, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1301 = LOCAL_TEE_I32 { 1300, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1300 = LOCAL_TEE_FUNCREF_S { 1299, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 562, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1299 = LOCAL_TEE_FUNCREF { 1298, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1298 = LOCAL_TEE_F64_S { 1297, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 559, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1297 = LOCAL_TEE_F64 { 1296, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1296 = LOCAL_TEE_F32_S { 1295, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 556, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1295 = LOCAL_TEE_F32 { 1294, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1294 = LOCAL_TEE_EXTERNREF_S { 1293, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 553, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1293 = LOCAL_TEE_EXTERNREF { 1292, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1292 = LOCAL_TEE_EXNREF_S { 1291, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 550, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1291 = LOCAL_TEE_EXNREF { 1290, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1290 = LOCAL_SET_V128_S { 1289, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 548, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1289 = LOCAL_SET_V128 { 1288, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1288 = LOCAL_SET_I64_S { 1287, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 546, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1287 = LOCAL_SET_I64 { 1286, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1286 = LOCAL_SET_I32_S { 1285, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 544, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1285 = LOCAL_SET_I32 { 1284, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1284 = LOCAL_SET_FUNCREF_S { 1283, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 542, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1283 = LOCAL_SET_FUNCREF { 1282, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1282 = LOCAL_SET_F64_S { 1281, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 540, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1281 = LOCAL_SET_F64 { 1280, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1280 = LOCAL_SET_F32_S { 1279, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 538, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1279 = LOCAL_SET_F32 { 1278, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1278 = LOCAL_SET_EXTERNREF_S { 1277, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 536, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1277 = LOCAL_SET_EXTERNREF { 1276, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1276 = LOCAL_SET_EXNREF_S { 1275, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 534, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1275 = LOCAL_SET_EXNREF { 1274, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1274 = LOCAL_GET_V128_S { 1273, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 532, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1273 = LOCAL_GET_V128 { 1272, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1272 = LOCAL_GET_I64_S { 1271, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 530, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1271 = LOCAL_GET_I64 { 1270, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1270 = LOCAL_GET_I32_S { 1269, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 528, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1269 = LOCAL_GET_I32 { 1268, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1268 = LOCAL_GET_FUNCREF_S { 1267, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 526, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1267 = LOCAL_GET_FUNCREF { 1266, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1266 = LOCAL_GET_F64_S { 1265, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 524, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1265 = LOCAL_GET_F64 { 1264, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1264 = LOCAL_GET_F32_S { 1263, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 522, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1263 = LOCAL_GET_F32 { 1262, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1262 = LOCAL_GET_EXTERNREF_S { 1261, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 520, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1261 = LOCAL_GET_EXTERNREF { 1260, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1260 = LOCAL_GET_EXNREF_S { 1259, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 517, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1259 = LOCAL_GET_EXNREF { 1258, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1258 = LOAD_ZERO_64_A64_S { 1257, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1257 = LOAD_ZERO_64_A64 { 1256, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1256 = LOAD_ZERO_64_A32_S { 1255, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1255 = LOAD_ZERO_64_A32 { 1254, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1254 = LOAD_ZERO_32_A64_S { 1253, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1253 = LOAD_ZERO_32_A64 { 1252, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1252 = LOAD_ZERO_32_A32_S { 1251, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1251 = LOAD_ZERO_32_A32 { 1250, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1250 = LOAD_V128_A64_S { 1249, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1249 = LOAD_V128_A64 { 1248, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1248 = LOAD_V128_A32_S { 1247, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1247 = LOAD_V128_A32 { 1246, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1246 = LOAD_LANE_8_A64_S { 1245, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 508, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1245 = LOAD_LANE_8_A64 { 1244, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1244 = LOAD_LANE_8_A32_S { 1243, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 499, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1243 = LOAD_LANE_8_A32 { 1242, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1242 = LOAD_LANE_64_A64_S { 1241, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 508, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1241 = LOAD_LANE_64_A64 { 1240, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1240 = LOAD_LANE_64_A32_S { 1239, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 499, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1239 = LOAD_LANE_64_A32 { 1238, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1238 = LOAD_LANE_32_A64_S { 1237, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 508, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1237 = LOAD_LANE_32_A64 { 1236, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1236 = LOAD_LANE_32_A32_S { 1235, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 499, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1235 = LOAD_LANE_32_A32 { 1234, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1234 = LOAD_LANE_16_A64_S { 1233, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 508, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1233 = LOAD_LANE_16_A64 { 1232, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1232 = LOAD_LANE_16_A32_S { 1231, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 499, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1231 = LOAD_LANE_16_A32 { 1230, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1230 = LOAD_I64_A64_S { 1229, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1229 = LOAD_I64_A64 { 1228, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1228 = LOAD_I64_A32_S { 1227, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1227 = LOAD_I64_A32 { 1226, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1226 = LOAD_I32_A64_S { 1225, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1225 = LOAD_I32_A64 { 1224, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1224 = LOAD_I32_A32_S { 1223, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1223 = LOAD_I32_A32 { 1222, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1222 = LOAD_F64_A64_S { 1221, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 495, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1221 = LOAD_F64_A64 { 1220, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1220 = LOAD_F64_A32_S { 1219, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 491, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1219 = LOAD_F64_A32 { 1218, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1218 = LOAD_F32_A64_S { 1217, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 487, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1217 = LOAD_F32_A64 { 1216, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1216 = LOAD_F32_A32_S { 1215, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 483, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1215 = LOAD_F32_A32 { 1214, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1214 = LOAD_F16_F32_A64_S { 1213, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 487, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1213 = LOAD_F16_F32_A64 { 1212, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1212 = LOAD_F16_F32_A32_S { 1211, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 483, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1211 = LOAD_F16_F32_A32 { 1210, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1210 = LOAD_EXTEND_U_I64x2_A64_S { 1209, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1209 = LOAD_EXTEND_U_I64x2_A64 { 1208, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1208 = LOAD_EXTEND_U_I64x2_A32_S { 1207, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1207 = LOAD_EXTEND_U_I64x2_A32 { 1206, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1206 = LOAD_EXTEND_U_I32x4_A64_S { 1205, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1205 = LOAD_EXTEND_U_I32x4_A64 { 1204, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1204 = LOAD_EXTEND_U_I32x4_A32_S { 1203, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1203 = LOAD_EXTEND_U_I32x4_A32 { 1202, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1202 = LOAD_EXTEND_U_I16x8_A64_S { 1201, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1201 = LOAD_EXTEND_U_I16x8_A64 { 1200, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1200 = LOAD_EXTEND_U_I16x8_A32_S { 1199, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1199 = LOAD_EXTEND_U_I16x8_A32 { 1198, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1198 = LOAD_EXTEND_S_I64x2_A64_S { 1197, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1197 = LOAD_EXTEND_S_I64x2_A64 { 1196, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1196 = LOAD_EXTEND_S_I64x2_A32_S { 1195, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1195 = LOAD_EXTEND_S_I64x2_A32 { 1194, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1194 = LOAD_EXTEND_S_I32x4_A64_S { 1193, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1193 = LOAD_EXTEND_S_I32x4_A64 { 1192, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1192 = LOAD_EXTEND_S_I32x4_A32_S { 1191, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1191 = LOAD_EXTEND_S_I32x4_A32 { 1190, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1190 = LOAD_EXTEND_S_I16x8_A64_S { 1189, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1189 = LOAD_EXTEND_S_I16x8_A64 { 1188, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1188 = LOAD_EXTEND_S_I16x8_A32_S { 1187, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1187 = LOAD_EXTEND_S_I16x8_A32 { 1186, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1186 = LOAD8_U_I64_A64_S { 1185, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1185 = LOAD8_U_I64_A64 { 1184, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1184 = LOAD8_U_I64_A32_S { 1183, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1183 = LOAD8_U_I64_A32 { 1182, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1182 = LOAD8_U_I32_A64_S { 1181, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1181 = LOAD8_U_I32_A64 { 1180, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1180 = LOAD8_U_I32_A32_S { 1179, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1179 = LOAD8_U_I32_A32 { 1178, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1178 = LOAD8_S_I64_A64_S { 1177, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1177 = LOAD8_S_I64_A64 { 1176, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1176 = LOAD8_S_I64_A32_S { 1175, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1175 = LOAD8_S_I64_A32 { 1174, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1174 = LOAD8_S_I32_A64_S { 1173, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1173 = LOAD8_S_I32_A64 { 1172, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1172 = LOAD8_S_I32_A32_S { 1171, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1171 = LOAD8_S_I32_A32 { 1170, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1170 = LOAD8_SPLAT_A64_S { 1169, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1169 = LOAD8_SPLAT_A64 { 1168, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1168 = LOAD8_SPLAT_A32_S { 1167, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1167 = LOAD8_SPLAT_A32 { 1166, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1166 = LOAD64_SPLAT_A64_S { 1165, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1165 = LOAD64_SPLAT_A64 { 1164, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1164 = LOAD64_SPLAT_A32_S { 1163, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1163 = LOAD64_SPLAT_A32 { 1162, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1162 = LOAD32_U_I64_A64_S { 1161, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1161 = LOAD32_U_I64_A64 { 1160, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1160 = LOAD32_U_I64_A32_S { 1159, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1159 = LOAD32_U_I64_A32 { 1158, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1158 = LOAD32_S_I64_A64_S { 1157, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1157 = LOAD32_S_I64_A64 { 1156, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1156 = LOAD32_S_I64_A32_S { 1155, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1155 = LOAD32_S_I64_A32 { 1154, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1154 = LOAD32_SPLAT_A64_S { 1153, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1153 = LOAD32_SPLAT_A64 { 1152, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1152 = LOAD32_SPLAT_A32_S { 1151, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1151 = LOAD32_SPLAT_A32 { 1150, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1150 = LOAD16_U_I64_A64_S { 1149, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1149 = LOAD16_U_I64_A64 { 1148, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1148 = LOAD16_U_I64_A32_S { 1147, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1147 = LOAD16_U_I64_A32 { 1146, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1146 = LOAD16_U_I32_A64_S { 1145, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1145 = LOAD16_U_I32_A64 { 1144, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1144 = LOAD16_U_I32_A32_S { 1143, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1143 = LOAD16_U_I32_A32 { 1142, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1142 = LOAD16_S_I64_A64_S { 1141, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1141 = LOAD16_S_I64_A64 { 1140, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1140 = LOAD16_S_I64_A32_S { 1139, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1139 = LOAD16_S_I64_A32 { 1138, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1138 = LOAD16_S_I32_A64_S { 1137, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1137 = LOAD16_S_I32_A64 { 1136, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1136 = LOAD16_S_I32_A32_S { 1135, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1135 = LOAD16_S_I32_A32 { 1134, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1134 = LOAD16_SPLAT_A64_S { 1133, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1133 = LOAD16_SPLAT_A64 { 1132, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1132 = LOAD16_SPLAT_A32_S { 1131, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1131 = LOAD16_SPLAT_A32 { 1130, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1130 = LE_U_I8x16_S { 1129, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1129 = LE_U_I8x16 { 1128, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1128 = LE_U_I64_S { 1127, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1127 = LE_U_I64 { 1126, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1126 = LE_U_I32x4_S { 1125, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1125 = LE_U_I32x4 { 1124, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1124 = LE_U_I32_S { 1123, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1123 = LE_U_I32 { 1122, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1122 = LE_U_I16x8_S { 1121, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1121 = LE_U_I16x8 { 1120, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1120 = LE_S_I8x16_S { 1119, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1119 = LE_S_I8x16 { 1118, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1118 = LE_S_I64x2_S { 1117, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1117 = LE_S_I64x2 { 1116, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1116 = LE_S_I64_S { 1115, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1115 = LE_S_I64 { 1114, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1114 = LE_S_I32x4_S { 1113, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1113 = LE_S_I32x4 { 1112, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1112 = LE_S_I32_S { 1111, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1111 = LE_S_I32 { 1110, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1110 = LE_S_I16x8_S { 1109, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1109 = LE_S_I16x8 { 1108, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1108 = LE_F64x2_S { 1107, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1107 = LE_F64x2 { 1106, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1106 = LE_F64_S { 1105, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1105 = LE_F64 { 1104, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1104 = LE_F32x4_S { 1103, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1103 = LE_F32x4 { 1102, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1102 = LE_F32_S { 1101, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1101 = LE_F32 { 1100, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1100 = LE_F16x8_S { 1099, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1099 = LE_F16x8 { 1098, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1098 = LANESELECT_I8x16_S { 1097, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1097 = LANESELECT_I8x16 { 1096, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1096 = LANESELECT_I64x2_S { 1095, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1095 = LANESELECT_I64x2 { 1094, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1094 = LANESELECT_I32x4_S { 1093, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1093 = LANESELECT_I32x4 { 1092, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1092 = LANESELECT_I16x8_S { 1091, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1091 = LANESELECT_I16x8 { 1090, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1090 = IF_S { 1089, 2, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 473, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1089 = IF { 1088, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1088 = I64_TRUNC_U_SAT_F64_S { 1087, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1087 = I64_TRUNC_U_SAT_F64 { 1086, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1086 = I64_TRUNC_U_SAT_F32_S { 1085, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1085 = I64_TRUNC_U_SAT_F32 { 1084, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1084 = I64_TRUNC_U_F64_S { 1083, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1083 = I64_TRUNC_U_F64 { 1082, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1082 = I64_TRUNC_U_F32_S { 1081, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1081 = I64_TRUNC_U_F32 { 1080, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1080 = I64_TRUNC_S_SAT_F64_S { 1079, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1079 = I64_TRUNC_S_SAT_F64 { 1078, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1078 = I64_TRUNC_S_SAT_F32_S { 1077, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1077 = I64_TRUNC_S_SAT_F32 { 1076, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1076 = I64_TRUNC_S_F64_S { 1075, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1075 = I64_TRUNC_S_F64 { 1074, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1074 = I64_TRUNC_S_F32_S { 1073, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1073 = I64_TRUNC_S_F32 { 1072, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1072 = I64_REINTERPRET_F64_S { 1071, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1071 = I64_REINTERPRET_F64 { 1070, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1070 = I64_EXTEND_U_I32_S { 1069, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 471, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1069 = I64_EXTEND_U_I32 { 1068, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1068 = I64_EXTEND_S_I32_S { 1067, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 471, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1067 = I64_EXTEND_S_I32 { 1066, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1066 = I64_EXTEND8_S_I64_S { 1065, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 291, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1065 = I64_EXTEND8_S_I64 { 1064, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1064 = I64_EXTEND32_S_I64_S { 1063, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 291, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1063 = I64_EXTEND32_S_I64 { 1062, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1062 = I64_EXTEND16_S_I64_S { 1061, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 291, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1061 = I64_EXTEND16_S_I64 { 1060, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1060 = I32_WRAP_I64_S { 1059, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 394, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1059 = I32_WRAP_I64 { 1058, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1058 = I32_TRUNC_U_SAT_F64_S { 1057, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1057 = I32_TRUNC_U_SAT_F64 { 1056, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1056 = I32_TRUNC_U_SAT_F32_S { 1055, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1055 = I32_TRUNC_U_SAT_F32 { 1054, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1054 = I32_TRUNC_U_F64_S { 1053, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1053 = I32_TRUNC_U_F64 { 1052, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1052 = I32_TRUNC_U_F32_S { 1051, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1051 = I32_TRUNC_U_F32 { 1050, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1050 = I32_TRUNC_S_SAT_F64_S { 1049, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1049 = I32_TRUNC_S_SAT_F64 { 1048, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1048 = I32_TRUNC_S_SAT_F32_S { 1047, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1047 = I32_TRUNC_S_SAT_F32 { 1046, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1046 = I32_TRUNC_S_F64_S { 1045, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1045 = I32_TRUNC_S_F64 { 1044, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1044 = I32_TRUNC_S_F32_S { 1043, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1043 = I32_TRUNC_S_F32 { 1042, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1042 = I32_REINTERPRET_F32_S { 1041, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1041 = I32_REINTERPRET_F32 { 1040, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1040 = I32_EXTEND8_S_I32_S { 1039, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 289, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1039 = I32_EXTEND8_S_I32 { 1038, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1038 = I32_EXTEND16_S_I32_S { 1037, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 289, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1037 = I32_EXTEND16_S_I32 { 1036, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1036 = GT_U_I8x16_S { 1035, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1035 = GT_U_I8x16 { 1034, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1034 = GT_U_I64_S { 1033, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1033 = GT_U_I64 { 1032, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1032 = GT_U_I32x4_S { 1031, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1031 = GT_U_I32x4 { 1030, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1030 = GT_U_I32_S { 1029, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1029 = GT_U_I32 { 1028, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1028 = GT_U_I16x8_S { 1027, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1027 = GT_U_I16x8 { 1026, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1026 = GT_S_I8x16_S { 1025, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1025 = GT_S_I8x16 { 1024, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1024 = GT_S_I64x2_S { 1023, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1023 = GT_S_I64x2 { 1022, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1022 = GT_S_I64_S { 1021, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1021 = GT_S_I64 { 1020, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1020 = GT_S_I32x4_S { 1019, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1019 = GT_S_I32x4 { 1018, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1018 = GT_S_I32_S { 1017, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1017 = GT_S_I32 { 1016, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1016 = GT_S_I16x8_S { 1015, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1015 = GT_S_I16x8 { 1014, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1014 = GT_F64x2_S { 1013, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1013 = GT_F64x2 { 1012, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1012 = GT_F64_S { 1011, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1011 = GT_F64 { 1010, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1010 = GT_F32x4_S { 1009, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1009 = GT_F32x4 { 1008, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1008 = GT_F32_S { 1007, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1007 = GT_F32 { 1006, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1006 = GT_F16x8_S { 1005, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1005 = GT_F16x8 { 1004, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1004 = GLOBAL_SET_V128_S { 1003, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 469, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1003 = GLOBAL_SET_V128 { 1002, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1002 = GLOBAL_SET_I64_S { 1001, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 467, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1001 = GLOBAL_SET_I64 { 1000, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1000 = GLOBAL_SET_I32_S { 999, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 465, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #999 = GLOBAL_SET_I32 { 998, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #998 = GLOBAL_SET_FUNCREF_S { 997, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 463, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #997 = GLOBAL_SET_FUNCREF { 996, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #996 = GLOBAL_SET_F64_S { 995, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 461, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #995 = GLOBAL_SET_F64 { 994, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #994 = GLOBAL_SET_F32_S { 993, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 459, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #993 = GLOBAL_SET_F32 { 992, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #992 = GLOBAL_SET_EXTERNREF_S { 991, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 457, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #991 = GLOBAL_SET_EXTERNREF { 990, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #990 = GLOBAL_SET_EXNREF_S { 989, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 455, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #989 = GLOBAL_SET_EXNREF { 988, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #988 = GLOBAL_GET_V128_S { 987, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 453, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #987 = GLOBAL_GET_V128 { 986, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #986 = GLOBAL_GET_I64_S { 985, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 451, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #985 = GLOBAL_GET_I64 { 984, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #984 = GLOBAL_GET_I32_S { 983, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 449, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #983 = GLOBAL_GET_I32 { 982, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #982 = GLOBAL_GET_FUNCREF_S { 981, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 447, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #981 = GLOBAL_GET_FUNCREF { 980, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #980 = GLOBAL_GET_F64_S { 979, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 445, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #979 = GLOBAL_GET_F64 { 978, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #978 = GLOBAL_GET_F32_S { 977, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 443, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #977 = GLOBAL_GET_F32 { 976, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #976 = GLOBAL_GET_EXTERNREF_S { 975, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 441, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #975 = GLOBAL_GET_EXTERNREF { 974, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #974 = GLOBAL_GET_EXNREF_S { 973, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 438, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #973 = GLOBAL_GET_EXNREF { 972, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #972 = GE_U_I8x16_S { 971, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #971 = GE_U_I8x16 { 970, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #970 = GE_U_I64_S { 969, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #969 = GE_U_I64 { 968, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #968 = GE_U_I32x4_S { 967, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #967 = GE_U_I32x4 { 966, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #966 = GE_U_I32_S { 965, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #965 = GE_U_I32 { 964, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #964 = GE_U_I16x8_S { 963, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #963 = GE_U_I16x8 { 962, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #962 = GE_S_I8x16_S { 961, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #961 = GE_S_I8x16 { 960, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #960 = GE_S_I64x2_S { 959, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #959 = GE_S_I64x2 { 958, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #958 = GE_S_I64_S { 957, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #957 = GE_S_I64 { 956, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #956 = GE_S_I32x4_S { 955, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #955 = GE_S_I32x4 { 954, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #954 = GE_S_I32_S { 953, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #953 = GE_S_I32 { 952, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #952 = GE_S_I16x8_S { 951, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #951 = GE_S_I16x8 { 950, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #950 = GE_F64x2_S { 949, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #949 = GE_F64x2 { 948, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #948 = GE_F64_S { 947, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #947 = GE_F64 { 946, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #946 = GE_F32x4_S { 945, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #945 = GE_F32x4 { 944, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #944 = GE_F32_S { 943, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #943 = GE_F32 { 942, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #942 = GE_F16x8_S { 941, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #941 = GE_F16x8 { 940, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #940 = FP_TO_UINT_I64_F64_S { 939, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #939 = FP_TO_UINT_I64_F64 { 938, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #938 = FP_TO_UINT_I64_F32_S { 937, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #937 = FP_TO_UINT_I64_F32 { 936, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #936 = FP_TO_UINT_I32_F64_S { 935, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #935 = FP_TO_UINT_I32_F64 { 934, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #934 = FP_TO_UINT_I32_F32_S { 933, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #933 = FP_TO_UINT_I32_F32 { 932, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #932 = FP_TO_SINT_I64_F64_S { 931, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #931 = FP_TO_SINT_I64_F64 { 930, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #930 = FP_TO_SINT_I64_F32_S { 929, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #929 = FP_TO_SINT_I64_F32 { 928, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #928 = FP_TO_SINT_I32_F64_S { 927, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #927 = FP_TO_SINT_I32_F64 { 926, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #926 = FP_TO_SINT_I32_F32_S { 925, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #925 = FP_TO_SINT_I32_F32 { 924, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #924 = FLOOR_F64x2_S { 923, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #923 = FLOOR_F64x2 { 922, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #922 = FLOOR_F64_S { 921, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #921 = FLOOR_F64 { 920, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #920 = FLOOR_F32x4_S { 919, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #919 = FLOOR_F32x4 { 918, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #918 = FLOOR_F32_S { 917, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #917 = FLOOR_F32 { 916, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #916 = FLOOR_F16x8_S { 915, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #915 = FLOOR_F16x8 { 914, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #914 = FALLTHROUGH_RETURN_S { 913, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #913 = FALLTHROUGH_RETURN { 912, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #912 = F64_REINTERPRET_I64_S { 911, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 426, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #911 = F64_REINTERPRET_I64 { 910, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #910 = F64_PROMOTE_F32_S { 909, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 428, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #909 = F64_PROMOTE_F32 { 908, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #908 = F64_CONVERT_U_I64_S { 907, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 426, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #907 = F64_CONVERT_U_I64 { 906, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #906 = F64_CONVERT_U_I32_S { 905, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 424, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #905 = F64_CONVERT_U_I32 { 904, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #904 = F64_CONVERT_S_I64_S { 903, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 426, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #903 = F64_CONVERT_S_I64 { 902, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #902 = F64_CONVERT_S_I32_S { 901, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 424, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #901 = F64_CONVERT_S_I32 { 900, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #900 = F32_REINTERPRET_I32_S { 899, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 418, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #899 = F32_REINTERPRET_I32 { 898, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #898 = F32_DEMOTE_F64_S { 897, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 422, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #897 = F32_DEMOTE_F64 { 896, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #896 = F32_CONVERT_U_I64_S { 895, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 420, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #895 = F32_CONVERT_U_I64 { 894, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #894 = F32_CONVERT_U_I32_S { 893, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 418, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #893 = F32_CONVERT_U_I32 { 892, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #892 = F32_CONVERT_S_I64_S { 891, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 420, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #891 = F32_CONVERT_S_I64 { 890, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #890 = F32_CONVERT_S_I32_S { 889, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 418, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #889 = F32_CONVERT_S_I32 { 888, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #888 = EXTRACT_LANE_I8x16_u_S { 887, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 412, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #887 = EXTRACT_LANE_I8x16_u { 886, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #886 = EXTRACT_LANE_I8x16_s_S { 885, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 412, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #885 = EXTRACT_LANE_I8x16_s { 884, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #884 = EXTRACT_LANE_I64x2_S { 883, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 415, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #883 = EXTRACT_LANE_I64x2 { 882, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #882 = EXTRACT_LANE_I32x4_S { 881, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 412, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #881 = EXTRACT_LANE_I32x4 { 880, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #880 = EXTRACT_LANE_I16x8_u_S { 879, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 412, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #879 = EXTRACT_LANE_I16x8_u { 878, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #878 = EXTRACT_LANE_I16x8_s_S { 877, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 412, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #877 = EXTRACT_LANE_I16x8_s { 876, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #876 = EXTRACT_LANE_F64x2_S { 875, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 409, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #875 = EXTRACT_LANE_F64x2 { 874, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #874 = EXTRACT_LANE_F32x4_S { 873, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 405, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #873 = EXTRACT_LANE_F32x4 { 872, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #872 = EXTRACT_LANE_F16x8_S { 871, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 405, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #871 = EXTRACT_LANE_F16x8 { 870, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #870 = EXTMUL_LOW_U_I64x2_S { 869, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #869 = EXTMUL_LOW_U_I64x2 { 868, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #868 = EXTMUL_LOW_U_I32x4_S { 867, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #867 = EXTMUL_LOW_U_I32x4 { 866, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #866 = EXTMUL_LOW_U_I16x8_S { 865, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #865 = EXTMUL_LOW_U_I16x8 { 864, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #864 = EXTMUL_LOW_S_I64x2_S { 863, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #863 = EXTMUL_LOW_S_I64x2 { 862, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #862 = EXTMUL_LOW_S_I32x4_S { 861, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #861 = EXTMUL_LOW_S_I32x4 { 860, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #860 = EXTMUL_LOW_S_I16x8_S { 859, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #859 = EXTMUL_LOW_S_I16x8 { 858, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #858 = EXTMUL_HIGH_U_I64x2_S { 857, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #857 = EXTMUL_HIGH_U_I64x2 { 856, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #856 = EXTMUL_HIGH_U_I32x4_S { 855, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #855 = EXTMUL_HIGH_U_I32x4 { 854, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #854 = EXTMUL_HIGH_U_I16x8_S { 853, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #853 = EXTMUL_HIGH_U_I16x8 { 852, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #852 = EXTMUL_HIGH_S_I64x2_S { 851, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #851 = EXTMUL_HIGH_S_I64x2 { 850, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #850 = EXTMUL_HIGH_S_I32x4_S { 849, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #849 = EXTMUL_HIGH_S_I32x4 { 848, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #848 = EXTMUL_HIGH_S_I16x8_S { 847, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #847 = EXTMUL_HIGH_S_I16x8 { 846, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #846 = EQ_I8x16_S { 845, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #845 = EQ_I8x16 { 844, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #844 = EQ_I64x2_S { 843, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #843 = EQ_I64x2 { 842, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #842 = EQ_I64_S { 841, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #841 = EQ_I64 { 840, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #840 = EQ_I32x4_S { 839, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #839 = EQ_I32x4 { 838, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #838 = EQ_I32_S { 837, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #837 = EQ_I32 { 836, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #836 = EQ_I16x8_S { 835, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #835 = EQ_I16x8 { 834, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #834 = EQ_F64x2_S { 833, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #833 = EQ_F64x2 { 832, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #832 = EQ_F64_S { 831, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #831 = EQ_F64 { 830, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #830 = EQ_F32x4_S { 829, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #829 = EQ_F32x4 { 828, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #828 = EQ_F32_S { 827, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #827 = EQ_F32 { 826, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #826 = EQ_F16x8_S { 825, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #825 = EQ_F16x8 { 824, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #824 = EQZ_I64_S { 823, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 394, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #823 = EQZ_I64 { 822, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #822 = EQZ_I32_S { 821, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 289, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #821 = EQZ_I32 { 820, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #820 = END_TRY_TABLE_S { 819, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #819 = END_TRY_TABLE { 818, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #818 = END_TRY_S { 817, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #817 = END_TRY { 816, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #816 = END_S { 815, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #815 = END_LOOP_S { 814, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #814 = END_LOOP { 813, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #813 = END_IF_S { 812, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #812 = END_IF { 811, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #811 = END_FUNCTION_S { 810, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #810 = END_FUNCTION { 809, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #809 = END_BLOCK_S { 808, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #808 = END_BLOCK { 807, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #807 = END { 806, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #806 = ELSE_S { 805, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #805 = ELSE { 804, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #804 = DROP_V128_S { 803, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 393, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #803 = DROP_V128 { 802, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #802 = DROP_I64_S { 801, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 284, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #801 = DROP_I64 { 800, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #800 = DROP_I32_S { 799, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 282, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #799 = DROP_I32 { 798, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #798 = DROP_FUNCREF_S { 797, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 392, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #797 = DROP_FUNCREF { 796, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #796 = DROP_F64_S { 795, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 391, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #795 = DROP_F64 { 794, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #794 = DROP_F32_S { 793, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 390, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #793 = DROP_F32 { 792, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #792 = DROP_EXTERNREF_S { 791, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 389, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #791 = DROP_EXTERNREF { 790, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #790 = DROP_EXNREF_S { 789, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #789 = DROP_EXNREF { 788, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #788 = DOT_S { 787, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #787 = DOT { 786, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #786 = DIV_U_I64_S { 785, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #785 = DIV_U_I64 { 784, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #784 = DIV_U_I32_S { 783, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #783 = DIV_U_I32 { 782, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #782 = DIV_S_I64_S { 781, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #781 = DIV_S_I64 { 780, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #780 = DIV_S_I32_S { 779, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #779 = DIV_S_I32 { 778, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #778 = DIV_F64x2_S { 777, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #777 = DIV_F64x2 { 776, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #776 = DIV_F64_S { 775, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #775 = DIV_F64 { 774, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #774 = DIV_F32x4_S { 773, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #773 = DIV_F32x4 { 772, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #772 = DIV_F32_S { 771, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #771 = DIV_F32 { 770, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #770 = DIV_F16x8_S { 769, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #769 = DIV_F16x8 { 768, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #768 = DELEGATE_S { 767, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #767 = DELEGATE { 766, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #766 = DEBUG_UNREACHABLE_S { 765, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #765 = DEBUG_UNREACHABLE { 764, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #764 = CTZ_I64_S { 763, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 291, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #763 = CTZ_I64 { 762, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #762 = CTZ_I32_S { 761, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 289, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #761 = CTZ_I32 { 760, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #760 = COPY_V128_S { 759, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #759 = COPY_V128 { 758, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #758 = COPY_I64_S { 757, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 291, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #757 = COPY_I64 { 756, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #756 = COPY_I32_S { 755, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 289, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #755 = COPY_I32 { 754, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #754 = COPY_FUNCREF_S { 753, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 387, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #753 = COPY_FUNCREF { 752, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #752 = COPY_F64_S { 751, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #751 = COPY_F64 { 750, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #750 = COPY_F32_S { 749, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #749 = COPY_F32 { 748, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #748 = COPY_EXTERNREF_S { 747, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 385, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #747 = COPY_EXTERNREF { 746, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #746 = COPY_EXNREF_S { 745, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 383, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #745 = COPY_EXNREF { 744, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #744 = COPYSIGN_F64_S { 743, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #743 = COPYSIGN_F64 { 742, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #742 = COPYSIGN_F32_S { 741, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #741 = COPYSIGN_F32 { 740, 16, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 367, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #740 = CONST_V128_I8x16_S { 739, 17, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 350, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #739 = CONST_V128_I8x16 { 738, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 348, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #738 = CONST_V128_I64x2_S { 737, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 345, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #737 = CONST_V128_I64x2 { 736, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 341, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #736 = CONST_V128_I32x4_S { 735, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 336, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #735 = CONST_V128_I32x4 { 734, 8, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 328, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #734 = CONST_V128_I16x8_S { 733, 9, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 319, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #733 = CONST_V128_I16x8 { 732, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 317, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #732 = CONST_V128_F64x2_S { 731, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 314, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #731 = CONST_V128_F64x2 { 730, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 310, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #730 = CONST_V128_F32x4_S { 729, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 305, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #729 = CONST_V128_F32x4 { 728, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 304, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #728 = CONST_I64_S { 727, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 302, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #727 = CONST_I64 { 726, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 301, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #726 = CONST_I32_S { 725, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 299, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #725 = CONST_I32 { 724, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 298, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #724 = CONST_F64_S { 723, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 296, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #723 = CONST_F64 { 722, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 295, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #722 = CONST_F32_S { 721, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 293, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #721 = CONST_F32 { 720, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #720 = CLZ_I64_S { 719, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 291, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #719 = CLZ_I64 { 718, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #718 = CLZ_I32_S { 717, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 289, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #717 = CLZ_I32 { 716, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #716 = CEIL_F64x2_S { 715, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #715 = CEIL_F64x2 { 714, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #714 = CEIL_F64_S { 713, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #713 = CEIL_F64 { 712, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #712 = CEIL_F32x4_S { 711, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #711 = CEIL_F32x4 { 710, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #710 = CEIL_F32_S { 709, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #709 = CEIL_F32 { 708, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #708 = CEIL_F16x8_S { 707, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #707 = CEIL_F16x8 { 706, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #706 = CATCH_S { 705, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #705 = CATCH_REF_S { 704, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #704 = CATCH_REF { 703, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #703 = CATCH_LEGACY_S { 702, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #702 = CATCH_LEGACY { 701, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #701 = CATCH_ALL_S { 700, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #700 = CATCH_ALL_REF_S { 699, 1, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #699 = CATCH_ALL_REF { 698, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #698 = CATCH_ALL_LEGACY_S { 697, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #697 = CATCH_ALL_LEGACY { 696, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #696 = CATCH_ALL { 695, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #695 = CATCH { 694, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #694 = CALL_S { 693, 2, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 285, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #693 = CALL_INDIRECT_S { 692, 2, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 285, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #692 = CALL_INDIRECT { 691, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #691 = CALL { 690, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #690 = BR_UNLESS_S { 689, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 280, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #689 = BR_UNLESS { 688, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 283, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #688 = BR_TABLE_I64_S { 687, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 284, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #687 = BR_TABLE_I64 { 686, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 283, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #686 = BR_TABLE_I32_S { 685, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 282, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #685 = BR_TABLE_I32 { 684, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #684 = BR_S { 683, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #683 = BR_IF_S { 682, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 280, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #682 = BR_IF { 681, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #681 = BR { 680, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #680 = BLOCK_S { 679, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #679 = BLOCK { 678, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #678 = BITSELECT_S { 677, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #677 = BITSELECT { 676, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #676 = BITMASK_I8x16_S { 675, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #675 = BITMASK_I8x16 { 674, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #674 = BITMASK_I64x2_S { 673, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #673 = BITMASK_I64x2 { 672, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #672 = BITMASK_I32x4_S { 671, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #671 = BITMASK_I32x4 { 670, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #670 = BITMASK_I16x8_S { 669, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #669 = BITMASK_I16x8 { 668, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #668 = AVGR_U_I8x16_S { 667, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #667 = AVGR_U_I8x16 { 666, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #666 = AVGR_U_I16x8_S { 665, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #665 = AVGR_U_I16x8 { 664, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #664 = ATOMIC_STORE_I64_A64_S { 663, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #663 = ATOMIC_STORE_I64_A64 { 662, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #662 = ATOMIC_STORE_I64_A32_S { 661, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #661 = ATOMIC_STORE_I64_A32 { 660, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #660 = ATOMIC_STORE_I32_A64_S { 659, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #659 = ATOMIC_STORE_I32_A64 { 658, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #658 = ATOMIC_STORE_I32_A32_S { 657, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #657 = ATOMIC_STORE_I32_A32 { 656, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #656 = ATOMIC_STORE8_I64_A64_S { 655, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #655 = ATOMIC_STORE8_I64_A64 { 654, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #654 = ATOMIC_STORE8_I64_A32_S { 653, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #653 = ATOMIC_STORE8_I64_A32 { 652, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #652 = ATOMIC_STORE8_I32_A64_S { 651, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #651 = ATOMIC_STORE8_I32_A64 { 650, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #650 = ATOMIC_STORE8_I32_A32_S { 649, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #649 = ATOMIC_STORE8_I32_A32 { 648, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #648 = ATOMIC_STORE32_I64_A64_S { 647, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #647 = ATOMIC_STORE32_I64_A64 { 646, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #646 = ATOMIC_STORE32_I64_A32_S { 645, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #645 = ATOMIC_STORE32_I64_A32 { 644, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #644 = ATOMIC_STORE16_I64_A64_S { 643, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #643 = ATOMIC_STORE16_I64_A64 { 642, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #642 = ATOMIC_STORE16_I64_A32_S { 641, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #641 = ATOMIC_STORE16_I64_A32 { 640, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #640 = ATOMIC_STORE16_I32_A64_S { 639, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #639 = ATOMIC_STORE16_I32_A64 { 638, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #638 = ATOMIC_STORE16_I32_A32_S { 637, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #637 = ATOMIC_STORE16_I32_A32 { 636, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #636 = ATOMIC_RMW_XOR_I64_A64_S { 635, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #635 = ATOMIC_RMW_XOR_I64_A64 { 634, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #634 = ATOMIC_RMW_XOR_I64_A32_S { 633, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #633 = ATOMIC_RMW_XOR_I64_A32 { 632, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #632 = ATOMIC_RMW_XOR_I32_A64_S { 631, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #631 = ATOMIC_RMW_XOR_I32_A64 { 630, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #630 = ATOMIC_RMW_XOR_I32_A32_S { 629, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #629 = ATOMIC_RMW_XOR_I32_A32 { 628, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #628 = ATOMIC_RMW_XCHG_I64_A64_S { 627, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #627 = ATOMIC_RMW_XCHG_I64_A64 { 626, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #626 = ATOMIC_RMW_XCHG_I64_A32_S { 625, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #625 = ATOMIC_RMW_XCHG_I64_A32 { 624, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #624 = ATOMIC_RMW_XCHG_I32_A64_S { 623, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #623 = ATOMIC_RMW_XCHG_I32_A64 { 622, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #622 = ATOMIC_RMW_XCHG_I32_A32_S { 621, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #621 = ATOMIC_RMW_XCHG_I32_A32 { 620, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #620 = ATOMIC_RMW_SUB_I64_A64_S { 619, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #619 = ATOMIC_RMW_SUB_I64_A64 { 618, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #618 = ATOMIC_RMW_SUB_I64_A32_S { 617, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #617 = ATOMIC_RMW_SUB_I64_A32 { 616, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #616 = ATOMIC_RMW_SUB_I32_A64_S { 615, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #615 = ATOMIC_RMW_SUB_I32_A64 { 614, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #614 = ATOMIC_RMW_SUB_I32_A32_S { 613, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #613 = ATOMIC_RMW_SUB_I32_A32 { 612, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #612 = ATOMIC_RMW_OR_I64_A64_S { 611, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #611 = ATOMIC_RMW_OR_I64_A64 { 610, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #610 = ATOMIC_RMW_OR_I64_A32_S { 609, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #609 = ATOMIC_RMW_OR_I64_A32 { 608, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #608 = ATOMIC_RMW_OR_I32_A64_S { 607, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #607 = ATOMIC_RMW_OR_I32_A64 { 606, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #606 = ATOMIC_RMW_OR_I32_A32_S { 605, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #605 = ATOMIC_RMW_OR_I32_A32 { 604, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #604 = ATOMIC_RMW_CMPXCHG_I64_A64_S { 603, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 252, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #603 = ATOMIC_RMW_CMPXCHG_I64_A64 { 602, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #602 = ATOMIC_RMW_CMPXCHG_I64_A32_S { 601, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 246, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #601 = ATOMIC_RMW_CMPXCHG_I64_A32 { 600, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #600 = ATOMIC_RMW_CMPXCHG_I32_A64_S { 599, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 240, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #599 = ATOMIC_RMW_CMPXCHG_I32_A64 { 598, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #598 = ATOMIC_RMW_CMPXCHG_I32_A32_S { 597, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #597 = ATOMIC_RMW_CMPXCHG_I32_A32 { 596, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #596 = ATOMIC_RMW_AND_I64_A64_S { 595, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #595 = ATOMIC_RMW_AND_I64_A64 { 594, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #594 = ATOMIC_RMW_AND_I64_A32_S { 593, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #593 = ATOMIC_RMW_AND_I64_A32 { 592, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #592 = ATOMIC_RMW_AND_I32_A64_S { 591, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #591 = ATOMIC_RMW_AND_I32_A64 { 590, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #590 = ATOMIC_RMW_AND_I32_A32_S { 589, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #589 = ATOMIC_RMW_AND_I32_A32 { 588, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #588 = ATOMIC_RMW_ADD_I64_A64_S { 587, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #587 = ATOMIC_RMW_ADD_I64_A64 { 586, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #586 = ATOMIC_RMW_ADD_I64_A32_S { 585, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #585 = ATOMIC_RMW_ADD_I64_A32 { 584, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #584 = ATOMIC_RMW_ADD_I32_A64_S { 583, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #583 = ATOMIC_RMW_ADD_I32_A64 { 582, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #582 = ATOMIC_RMW_ADD_I32_A32_S { 581, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #581 = ATOMIC_RMW_ADD_I32_A32 { 580, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #580 = ATOMIC_RMW8_U_XOR_I64_A64_S { 579, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #579 = ATOMIC_RMW8_U_XOR_I64_A64 { 578, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #578 = ATOMIC_RMW8_U_XOR_I64_A32_S { 577, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #577 = ATOMIC_RMW8_U_XOR_I64_A32 { 576, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #576 = ATOMIC_RMW8_U_XOR_I32_A64_S { 575, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #575 = ATOMIC_RMW8_U_XOR_I32_A64 { 574, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #574 = ATOMIC_RMW8_U_XOR_I32_A32_S { 573, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #573 = ATOMIC_RMW8_U_XOR_I32_A32 { 572, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #572 = ATOMIC_RMW8_U_XCHG_I64_A64_S { 571, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #571 = ATOMIC_RMW8_U_XCHG_I64_A64 { 570, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #570 = ATOMIC_RMW8_U_XCHG_I64_A32_S { 569, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #569 = ATOMIC_RMW8_U_XCHG_I64_A32 { 568, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #568 = ATOMIC_RMW8_U_XCHG_I32_A64_S { 567, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #567 = ATOMIC_RMW8_U_XCHG_I32_A64 { 566, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #566 = ATOMIC_RMW8_U_XCHG_I32_A32_S { 565, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #565 = ATOMIC_RMW8_U_XCHG_I32_A32 { 564, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #564 = ATOMIC_RMW8_U_SUB_I64_A64_S { 563, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #563 = ATOMIC_RMW8_U_SUB_I64_A64 { 562, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #562 = ATOMIC_RMW8_U_SUB_I64_A32_S { 561, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #561 = ATOMIC_RMW8_U_SUB_I64_A32 { 560, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #560 = ATOMIC_RMW8_U_SUB_I32_A64_S { 559, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #559 = ATOMIC_RMW8_U_SUB_I32_A64 { 558, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #558 = ATOMIC_RMW8_U_SUB_I32_A32_S { 557, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #557 = ATOMIC_RMW8_U_SUB_I32_A32 { 556, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #556 = ATOMIC_RMW8_U_OR_I64_A64_S { 555, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #555 = ATOMIC_RMW8_U_OR_I64_A64 { 554, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #554 = ATOMIC_RMW8_U_OR_I64_A32_S { 553, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #553 = ATOMIC_RMW8_U_OR_I64_A32 { 552, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #552 = ATOMIC_RMW8_U_OR_I32_A64_S { 551, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #551 = ATOMIC_RMW8_U_OR_I32_A64 { 550, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #550 = ATOMIC_RMW8_U_OR_I32_A32_S { 549, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #549 = ATOMIC_RMW8_U_OR_I32_A32 { 548, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #548 = ATOMIC_RMW8_U_CMPXCHG_I64_A64_S { 547, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 252, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #547 = ATOMIC_RMW8_U_CMPXCHG_I64_A64 { 546, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #546 = ATOMIC_RMW8_U_CMPXCHG_I64_A32_S { 545, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 246, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #545 = ATOMIC_RMW8_U_CMPXCHG_I64_A32 { 544, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #544 = ATOMIC_RMW8_U_CMPXCHG_I32_A64_S { 543, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 240, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #543 = ATOMIC_RMW8_U_CMPXCHG_I32_A64 { 542, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #542 = ATOMIC_RMW8_U_CMPXCHG_I32_A32_S { 541, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #541 = ATOMIC_RMW8_U_CMPXCHG_I32_A32 { 540, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #540 = ATOMIC_RMW8_U_AND_I64_A64_S { 539, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #539 = ATOMIC_RMW8_U_AND_I64_A64 { 538, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #538 = ATOMIC_RMW8_U_AND_I64_A32_S { 537, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #537 = ATOMIC_RMW8_U_AND_I64_A32 { 536, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #536 = ATOMIC_RMW8_U_AND_I32_A64_S { 535, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #535 = ATOMIC_RMW8_U_AND_I32_A64 { 534, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #534 = ATOMIC_RMW8_U_AND_I32_A32_S { 533, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #533 = ATOMIC_RMW8_U_AND_I32_A32 { 532, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #532 = ATOMIC_RMW8_U_ADD_I64_A64_S { 531, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #531 = ATOMIC_RMW8_U_ADD_I64_A64 { 530, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #530 = ATOMIC_RMW8_U_ADD_I64_A32_S { 529, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #529 = ATOMIC_RMW8_U_ADD_I64_A32 { 528, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #528 = ATOMIC_RMW8_U_ADD_I32_A64_S { 527, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #527 = ATOMIC_RMW8_U_ADD_I32_A64 { 526, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #526 = ATOMIC_RMW8_U_ADD_I32_A32_S { 525, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #525 = ATOMIC_RMW8_U_ADD_I32_A32 { 524, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #524 = ATOMIC_RMW32_U_XOR_I64_A64_S { 523, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #523 = ATOMIC_RMW32_U_XOR_I64_A64 { 522, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #522 = ATOMIC_RMW32_U_XOR_I64_A32_S { 521, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #521 = ATOMIC_RMW32_U_XOR_I64_A32 { 520, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #520 = ATOMIC_RMW32_U_XCHG_I64_A64_S { 519, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #519 = ATOMIC_RMW32_U_XCHG_I64_A64 { 518, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #518 = ATOMIC_RMW32_U_XCHG_I64_A32_S { 517, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #517 = ATOMIC_RMW32_U_XCHG_I64_A32 { 516, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #516 = ATOMIC_RMW32_U_SUB_I64_A64_S { 515, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #515 = ATOMIC_RMW32_U_SUB_I64_A64 { 514, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #514 = ATOMIC_RMW32_U_SUB_I64_A32_S { 513, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #513 = ATOMIC_RMW32_U_SUB_I64_A32 { 512, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #512 = ATOMIC_RMW32_U_OR_I64_A64_S { 511, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #511 = ATOMIC_RMW32_U_OR_I64_A64 { 510, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #510 = ATOMIC_RMW32_U_OR_I64_A32_S { 509, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #509 = ATOMIC_RMW32_U_OR_I64_A32 { 508, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #508 = ATOMIC_RMW32_U_CMPXCHG_I64_A64_S { 507, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 252, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #507 = ATOMIC_RMW32_U_CMPXCHG_I64_A64 { 506, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #506 = ATOMIC_RMW32_U_CMPXCHG_I64_A32_S { 505, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 246, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #505 = ATOMIC_RMW32_U_CMPXCHG_I64_A32 { 504, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #504 = ATOMIC_RMW32_U_AND_I64_A64_S { 503, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #503 = ATOMIC_RMW32_U_AND_I64_A64 { 502, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #502 = ATOMIC_RMW32_U_AND_I64_A32_S { 501, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #501 = ATOMIC_RMW32_U_AND_I64_A32 { 500, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #500 = ATOMIC_RMW32_U_ADD_I64_A64_S { 499, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #499 = ATOMIC_RMW32_U_ADD_I64_A64 { 498, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #498 = ATOMIC_RMW32_U_ADD_I64_A32_S { 497, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #497 = ATOMIC_RMW32_U_ADD_I64_A32 { 496, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #496 = ATOMIC_RMW16_U_XOR_I64_A64_S { 495, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #495 = ATOMIC_RMW16_U_XOR_I64_A64 { 494, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #494 = ATOMIC_RMW16_U_XOR_I64_A32_S { 493, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #493 = ATOMIC_RMW16_U_XOR_I64_A32 { 492, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #492 = ATOMIC_RMW16_U_XOR_I32_A64_S { 491, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #491 = ATOMIC_RMW16_U_XOR_I32_A64 { 490, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #490 = ATOMIC_RMW16_U_XOR_I32_A32_S { 489, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #489 = ATOMIC_RMW16_U_XOR_I32_A32 { 488, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #488 = ATOMIC_RMW16_U_XCHG_I64_A64_S { 487, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #487 = ATOMIC_RMW16_U_XCHG_I64_A64 { 486, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #486 = ATOMIC_RMW16_U_XCHG_I64_A32_S { 485, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #485 = ATOMIC_RMW16_U_XCHG_I64_A32 { 484, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #484 = ATOMIC_RMW16_U_XCHG_I32_A64_S { 483, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #483 = ATOMIC_RMW16_U_XCHG_I32_A64 { 482, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #482 = ATOMIC_RMW16_U_XCHG_I32_A32_S { 481, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #481 = ATOMIC_RMW16_U_XCHG_I32_A32 { 480, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #480 = ATOMIC_RMW16_U_SUB_I64_A64_S { 479, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #479 = ATOMIC_RMW16_U_SUB_I64_A64 { 478, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #478 = ATOMIC_RMW16_U_SUB_I64_A32_S { 477, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #477 = ATOMIC_RMW16_U_SUB_I64_A32 { 476, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #476 = ATOMIC_RMW16_U_SUB_I32_A64_S { 475, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #475 = ATOMIC_RMW16_U_SUB_I32_A64 { 474, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #474 = ATOMIC_RMW16_U_SUB_I32_A32_S { 473, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #473 = ATOMIC_RMW16_U_SUB_I32_A32 { 472, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #472 = ATOMIC_RMW16_U_OR_I64_A64_S { 471, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #471 = ATOMIC_RMW16_U_OR_I64_A64 { 470, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #470 = ATOMIC_RMW16_U_OR_I64_A32_S { 469, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #469 = ATOMIC_RMW16_U_OR_I64_A32 { 468, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #468 = ATOMIC_RMW16_U_OR_I32_A64_S { 467, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #467 = ATOMIC_RMW16_U_OR_I32_A64 { 466, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #466 = ATOMIC_RMW16_U_OR_I32_A32_S { 465, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #465 = ATOMIC_RMW16_U_OR_I32_A32 { 464, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #464 = ATOMIC_RMW16_U_CMPXCHG_I64_A64_S { 463, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 252, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #463 = ATOMIC_RMW16_U_CMPXCHG_I64_A64 { 462, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #462 = ATOMIC_RMW16_U_CMPXCHG_I64_A32_S { 461, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 246, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #461 = ATOMIC_RMW16_U_CMPXCHG_I64_A32 { 460, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #460 = ATOMIC_RMW16_U_CMPXCHG_I32_A64_S { 459, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 240, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #459 = ATOMIC_RMW16_U_CMPXCHG_I32_A64 { 458, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #458 = ATOMIC_RMW16_U_CMPXCHG_I32_A32_S { 457, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #457 = ATOMIC_RMW16_U_CMPXCHG_I32_A32 { 456, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #456 = ATOMIC_RMW16_U_AND_I64_A64_S { 455, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #455 = ATOMIC_RMW16_U_AND_I64_A64 { 454, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #454 = ATOMIC_RMW16_U_AND_I64_A32_S { 453, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #453 = ATOMIC_RMW16_U_AND_I64_A32 { 452, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #452 = ATOMIC_RMW16_U_AND_I32_A64_S { 451, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #451 = ATOMIC_RMW16_U_AND_I32_A64 { 450, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #450 = ATOMIC_RMW16_U_AND_I32_A32_S { 449, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #449 = ATOMIC_RMW16_U_AND_I32_A32 { 448, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #448 = ATOMIC_RMW16_U_ADD_I64_A64_S { 447, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #447 = ATOMIC_RMW16_U_ADD_I64_A64 { 446, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #446 = ATOMIC_RMW16_U_ADD_I64_A32_S { 445, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #445 = ATOMIC_RMW16_U_ADD_I64_A32 { 444, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #444 = ATOMIC_RMW16_U_ADD_I32_A64_S { 443, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #443 = ATOMIC_RMW16_U_ADD_I32_A64 { 442, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #442 = ATOMIC_RMW16_U_ADD_I32_A32_S { 441, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #441 = ATOMIC_RMW16_U_ADD_I32_A32 { 440, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #440 = ATOMIC_LOAD_I64_A64_S { 439, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #439 = ATOMIC_LOAD_I64_A64 { 438, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #438 = ATOMIC_LOAD_I64_A32_S { 437, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #437 = ATOMIC_LOAD_I64_A32 { 436, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #436 = ATOMIC_LOAD_I32_A64_S { 435, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #435 = ATOMIC_LOAD_I32_A64 { 434, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #434 = ATOMIC_LOAD_I32_A32_S { 433, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #433 = ATOMIC_LOAD_I32_A32 { 432, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #432 = ATOMIC_LOAD8_U_I64_A64_S { 431, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #431 = ATOMIC_LOAD8_U_I64_A64 { 430, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #430 = ATOMIC_LOAD8_U_I64_A32_S { 429, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #429 = ATOMIC_LOAD8_U_I64_A32 { 428, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #428 = ATOMIC_LOAD8_U_I32_A64_S { 427, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #427 = ATOMIC_LOAD8_U_I32_A64 { 426, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #426 = ATOMIC_LOAD8_U_I32_A32_S { 425, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #425 = ATOMIC_LOAD8_U_I32_A32 { 424, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #424 = ATOMIC_LOAD32_U_I64_A64_S { 423, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #423 = ATOMIC_LOAD32_U_I64_A64 { 422, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #422 = ATOMIC_LOAD32_U_I64_A32_S { 421, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #421 = ATOMIC_LOAD32_U_I64_A32 { 420, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #420 = ATOMIC_LOAD16_U_I64_A64_S { 419, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #419 = ATOMIC_LOAD16_U_I64_A64 { 418, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #418 = ATOMIC_LOAD16_U_I64_A32_S { 417, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #417 = ATOMIC_LOAD16_U_I64_A32 { 416, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #416 = ATOMIC_LOAD16_U_I32_A64_S { 415, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #415 = ATOMIC_LOAD16_U_I32_A64 { 414, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #414 = ATOMIC_LOAD16_U_I32_A32_S { 413, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #413 = ATOMIC_LOAD16_U_I32_A32 { 412, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #412 = ATOMIC_FENCE_S { 411, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #411 = ATOMIC_FENCE { 410, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #410 = ARGUMENT_v8i16_S { 409, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #409 = ARGUMENT_v8i16 { 408, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #408 = ARGUMENT_v8f16_S { 407, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #407 = ARGUMENT_v8f16 { 406, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #406 = ARGUMENT_v4i32_S { 405, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #405 = ARGUMENT_v4i32 { 404, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #404 = ARGUMENT_v4f32_S { 403, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #403 = ARGUMENT_v4f32 { 402, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #402 = ARGUMENT_v2i64_S { 401, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #401 = ARGUMENT_v2i64 { 400, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #400 = ARGUMENT_v2f64_S { 399, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #399 = ARGUMENT_v2f64 { 398, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #398 = ARGUMENT_v16i8_S { 397, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #397 = ARGUMENT_v16i8 { 396, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #396 = ARGUMENT_i64_S { 395, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 190, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #395 = ARGUMENT_i64 { 394, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #394 = ARGUMENT_i32_S { 393, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 188, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #393 = ARGUMENT_i32 { 392, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #392 = ARGUMENT_funcref_S { 391, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 186, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #391 = ARGUMENT_funcref { 390, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #390 = ARGUMENT_f64_S { 389, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 184, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #389 = ARGUMENT_f64 { 388, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #388 = ARGUMENT_f32_S { 387, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 182, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #387 = ARGUMENT_f32 { 386, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #386 = ARGUMENT_externref_S { 385, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 180, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #385 = ARGUMENT_externref { 384, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #384 = ARGUMENT_exnref_S { 383, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 178, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #383 = ARGUMENT_exnref { 382, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #382 = ANYTRUE_S { 381, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #381 = ANYTRUE { 380, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #380 = AND_S { 379, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #379 = AND_I64_S { 378, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #378 = AND_I64 { 377, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #377 = AND_I32_S { 376, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #376 = AND_I32 { 375, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #375 = ANDNOT_S { 374, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #374 = ANDNOT { 373, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #373 = AND { 372, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #372 = ALLTRUE_I8x16_S { 371, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #371 = ALLTRUE_I8x16 { 370, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #370 = ALLTRUE_I64x2_S { 369, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #369 = ALLTRUE_I64x2 { 368, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #368 = ALLTRUE_I32x4_S { 367, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #367 = ALLTRUE_I32x4 { 366, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #366 = ALLTRUE_I16x8_S { 365, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #365 = ALLTRUE_I16x8 { 364, 2, 0, 0, 0, 2, 2, WebAssemblyImpOpBase + 4, 21, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #364 = ADJCALLSTACKUP_S { 363, 2, 0, 0, 0, 2, 2, WebAssemblyImpOpBase + 4, 21, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #363 = ADJCALLSTACKUP { 362, 2, 0, 0, 0, 2, 2, WebAssemblyImpOpBase + 4, 21, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #362 = ADJCALLSTACKDOWN_S { 361, 2, 0, 0, 0, 2, 2, WebAssemblyImpOpBase + 4, 21, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #361 = ADJCALLSTACKDOWN { 360, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #360 = ADD_SAT_U_I8x16_S { 359, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #359 = ADD_SAT_U_I8x16 { 358, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #358 = ADD_SAT_U_I16x8_S { 357, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #357 = ADD_SAT_U_I16x8 { 356, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #356 = ADD_SAT_S_I8x16_S { 355, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #355 = ADD_SAT_S_I8x16 { 354, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #354 = ADD_SAT_S_I16x8_S { 353, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #353 = ADD_SAT_S_I16x8 { 352, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #352 = ADD_I8x16_S { 351, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #351 = ADD_I8x16 { 350, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #350 = ADD_I64x2_S { 349, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #349 = ADD_I64x2 { 348, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #348 = ADD_I64_S { 347, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #347 = ADD_I64 { 346, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #346 = ADD_I32x4_S { 345, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #345 = ADD_I32x4 { 344, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #344 = ADD_I32_S { 343, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #343 = ADD_I32 { 342, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #342 = ADD_I16x8_S { 341, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #341 = ADD_I16x8 { 340, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #340 = ADD_F64x2_S { 339, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #339 = ADD_F64x2 { 338, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #338 = ADD_F64_S { 337, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #337 = ADD_F64 { 336, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #336 = ADD_F32x4_S { 335, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #335 = ADD_F32x4 { 334, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #334 = ADD_F32_S { 333, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #333 = ADD_F32 { 332, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #332 = ADD_F16x8_S { 331, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #331 = ADD_F16x8 { 330, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #330 = ABS_I8x16_S { 329, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #329 = ABS_I8x16 { 328, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #328 = ABS_I64x2_S { 327, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #327 = ABS_I64x2 { 326, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #326 = ABS_I32x4_S { 325, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #325 = ABS_I32x4 { 324, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #324 = ABS_I16x8_S { 323, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #323 = ABS_I16x8 { 322, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #322 = ABS_F64x2_S { 321, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #321 = ABS_F64x2 { 320, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #320 = ABS_F64_S { 319, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #319 = ABS_F64 { 318, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #318 = ABS_F32x4_S { 317, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #317 = ABS_F32x4 { 316, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #316 = ABS_F32_S { 315, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #315 = ABS_F32 { 314, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #314 = ABS_F16x8_S { 313, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #313 = ABS_F16x8 { 312, 0, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #312 = RET_CALL_RESULTS_S { 311, 0, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #311 = RET_CALL_RESULTS { 310, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #310 = COMPILER_FENCE_S { 309, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #309 = COMPILER_FENCE { 308, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #308 = CLEANUPRET_S { 307, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #307 = CLEANUPRET { 306, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 153, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #306 = CATCHRET_S { 305, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 153, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #305 = CATCHRET { 304, 0, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #304 = CALL_RESULTS_S { 303, 0, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #303 = CALL_RESULTS { 302, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #302 = CALL_PARAMS_S { 301, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #301 = CALL_PARAMS { 300, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #300 = G_UBFX { 299, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #299 = G_SBFX { 298, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #298 = G_VECREDUCE_UMIN { 297, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #297 = G_VECREDUCE_UMAX { 296, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #296 = G_VECREDUCE_SMIN { 295, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #295 = G_VECREDUCE_SMAX { 294, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #294 = G_VECREDUCE_XOR { 293, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #293 = G_VECREDUCE_OR { 292, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #292 = G_VECREDUCE_AND { 291, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #291 = G_VECREDUCE_MUL { 290, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #290 = G_VECREDUCE_ADD { 289, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #289 = G_VECREDUCE_FMINIMUM { 288, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #288 = G_VECREDUCE_FMAXIMUM { 287, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #287 = G_VECREDUCE_FMIN { 286, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #286 = G_VECREDUCE_FMAX { 285, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #285 = G_VECREDUCE_FMUL { 284, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #284 = G_VECREDUCE_FADD { 283, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #283 = G_VECREDUCE_SEQ_FMUL { 282, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #282 = G_VECREDUCE_SEQ_FADD { 281, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #281 = G_UBSANTRAP { 280, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #280 = G_DEBUGTRAP { 279, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #279 = G_TRAP { 278, 3, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #278 = G_BZERO { 277, 4, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #277 = G_MEMSET { 276, 4, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #276 = G_MEMMOVE { 275, 3, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #275 = G_MEMCPY_INLINE { 274, 4, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #274 = G_MEMCPY { 273, 2, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #273 = G_WRITE_REGISTER { 272, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #272 = G_READ_REGISTER { 271, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #271 = G_STRICT_FLDEXP { 270, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #270 = G_STRICT_FSQRT { 269, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #269 = G_STRICT_FMA { 268, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #268 = G_STRICT_FREM { 267, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #267 = G_STRICT_FDIV { 266, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #266 = G_STRICT_FMUL { 265, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #265 = G_STRICT_FSUB { 264, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #264 = G_STRICT_FADD { 263, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #263 = G_STACKRESTORE { 262, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #262 = G_STACKSAVE { 261, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #261 = G_DYN_STACKALLOC { 260, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #260 = G_JUMP_TABLE { 259, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #259 = G_BLOCK_ADDR { 258, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #258 = G_ADDRSPACE_CAST { 257, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #257 = G_FNEARBYINT { 256, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #256 = G_FRINT { 255, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #255 = G_FFLOOR { 254, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #254 = G_FSQRT { 253, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #253 = G_FTANH { 252, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #252 = G_FSINH { 251, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #251 = G_FCOSH { 250, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #250 = G_FATAN { 249, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #249 = G_FASIN { 248, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #248 = G_FACOS { 247, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #247 = G_FTAN { 246, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #246 = G_FSIN { 245, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #245 = G_FCOS { 244, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #244 = G_FCEIL { 243, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #243 = G_BITREVERSE { 242, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #242 = G_BSWAP { 241, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #241 = G_CTPOP { 240, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #240 = G_CTLZ_ZERO_UNDEF { 239, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #239 = G_CTLZ { 238, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #238 = G_CTTZ_ZERO_UNDEF { 237, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #237 = G_CTTZ { 236, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #236 = G_VECTOR_COMPRESS { 235, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #235 = G_SPLAT_VECTOR { 234, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #234 = G_SHUFFLE_VECTOR { 233, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #233 = G_EXTRACT_VECTOR_ELT { 232, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #232 = G_INSERT_VECTOR_ELT { 231, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #231 = G_EXTRACT_SUBVECTOR { 230, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #230 = G_INSERT_SUBVECTOR { 229, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #229 = G_VSCALE { 228, 3, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #228 = G_BRJT { 227, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #227 = G_BR { 226, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #226 = G_LLROUND { 225, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #225 = G_LROUND { 224, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #224 = G_ABS { 223, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #223 = G_UMAX { 222, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #222 = G_UMIN { 221, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #221 = G_SMAX { 220, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #220 = G_SMIN { 219, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #219 = G_PTRMASK { 218, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #218 = G_PTR_ADD { 217, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #217 = G_RESET_FPMODE { 216, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #216 = G_SET_FPMODE { 215, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #215 = G_GET_FPMODE { 214, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #214 = G_RESET_FPENV { 213, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #213 = G_SET_FPENV { 212, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #212 = G_GET_FPENV { 211, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #211 = G_FMAXIMUM { 210, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #210 = G_FMINIMUM { 209, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #209 = G_FMAXNUM_IEEE { 208, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #208 = G_FMINNUM_IEEE { 207, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #207 = G_FMAXNUM { 206, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #206 = G_FMINNUM { 205, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #205 = G_FCANONICALIZE { 204, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #204 = G_IS_FPCLASS { 203, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #203 = G_FCOPYSIGN { 202, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #202 = G_FABS { 201, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #201 = G_FPTOUI_SAT { 200, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #200 = G_FPTOSI_SAT { 199, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #199 = G_UITOFP { 198, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #198 = G_SITOFP { 197, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #197 = G_FPTOUI { 196, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #196 = G_FPTOSI { 195, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #195 = G_FPTRUNC { 194, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #194 = G_FPEXT { 193, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #193 = G_FNEG { 192, 3, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #192 = G_FFREXP { 191, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #191 = G_FLDEXP { 190, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #190 = G_FLOG10 { 189, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #189 = G_FLOG2 { 188, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #188 = G_FLOG { 187, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #187 = G_FEXP10 { 186, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #186 = G_FEXP2 { 185, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #185 = G_FEXP { 184, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #184 = G_FPOWI { 183, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #183 = G_FPOW { 182, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #182 = G_FREM { 181, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #181 = G_FDIV { 180, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #180 = G_FMAD { 179, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #179 = G_FMA { 178, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(<TRUNCATED>#ifdef __GNUC__#pragma GCC diagnostic push#pragma GCC diagnostic ignored "-Woverlength-strings"#endif#ifdef __GNUC__#pragma GCC diagnostic pop#endif#endif // GET_INSTRINFO_MC_DESC#ifdef GET_INSTRINFO_HEADER#undef GET_INSTRINFO_HEADER#endif // GET_INSTRINFO_HEADER#ifdef GET_INSTRINFO_HELPER_DECLS#undef GET_INSTRINFO_HELPER_DECLS#endif // GET_INSTRINFO_HELPER_DECLS#ifdef GET_INSTRINFO_HELPERS#undef GET_INSTRINFO_HELPERS#endif // GET_INSTRINFO_HELPERS#ifdef GET_INSTRINFO_CTOR_DTOR#undef GET_INSTRINFO_CTOR_DTOR#endif // GET_INSTRINFO_CTOR_DTOR#ifdef GET_INSTRINFO_OPERAND_ENUM#undef GET_INSTRINFO_OPERAND_ENUM#endif //GET_INSTRINFO_OPERAND_ENUM#ifdef GET_INSTRINFO_NAMED_OPS#undef GET_INSTRINFO_NAMED_OPS#endif //GET_INSTRINFO_NAMED_OPS#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM#undef GET_INSTRINFO_OPERAND_TYPES_ENUM#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM#ifdef GET_INSTRINFO_OPERAND_TYPE#undef GET_INSTRINFO_OPERAND_TYPE#endif // GET_INSTRINFO_OPERAND_TYPE#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE#undef GET_INSTRINFO_MEM_OPERAND_SIZE#endif // GET_INSTRINFO_MEM_OPERAND_SIZE#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP#ifdef GET_INSTRINFO_MC_HELPER_DECLS#undef GET_INSTRINFO_MC_HELPER_DECLSclass MCInstclass FeatureBitsetvoid verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features)#endif // GET_INSTRINFO_MC_HELPER_DECLS#ifdef GET_INSTRINFO_MC_HELPERS#undef GET_INSTRINFO_MC_HELPERS#endif // GET_GENISTRINFO_MC_HELPERS#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\ defined(GET_AVAILABLE_OPCODE_CHECKER)#define GET_COMPUTE_FEATURES#endif#ifdef GET_COMPUTE_FEATURES#undef GET_COMPUTE_FEATURES#endif // GET_COMPUTE_FEATURES#ifdef GET_AVAILABLE_OPCODE_CHECKER#undef GET_AVAILABLE_OPCODE_CHECKER#endif // GET_AVAILABLE_OPCODE_CHECKER#ifdef ENABLE_INSTR_PREDICATE_VERIFIER#undef ENABLE_INSTR_PREDICATE_VERIFIER#include <sstream>#ifndef NDEBUG#endif // NDEBUG#ifndef NDEBUG#endif // NDEBUG#endif // ENABLE_INSTR_PREDICATE_VERIFIER#ifdef GET_INSTRMAP_INFO#undef GET_INSTRMAP_INFO#endif // GET_INSTRMAP_INFO
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