llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck %s -check-prefix=SI
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s -check-prefix=VI
---
name: test_sextload_flat_i32_i8
body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; SI-LABEL: name: test_sextload_flat_i32_i8
    ; SI: liveins: $vgpr0_vgpr1
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
    ; SI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
    ; SI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
    ; VI-LABEL: name: test_sextload_flat_i32_i8
    ; VI: liveins: $vgpr0_vgpr1
    ; VI-NEXT: {{  $}}
    ; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
    ; VI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
    ; VI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
    %0:_(p0) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_SEXTLOAD %0 :: (load (s8), addrspace 0)
    $vgpr0 = COPY %1
...
---
name: test_sextload_flat_i32_i16
body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; SI-LABEL: name: test_sextload_flat_i32_i16
    ; SI: liveins: $vgpr0_vgpr1
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
    ; SI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
    ; SI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
    ; VI-LABEL: name: test_sextload_flat_i32_i16
    ; VI: liveins: $vgpr0_vgpr1
    ; VI-NEXT: {{  $}}
    ; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
    ; VI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
    ; VI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
     %0:_(p0) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_SEXTLOAD %0 :: (load (s16), addrspace 0)
    $vgpr0 = COPY %1
...
---
name: test_sextload_flat_i31_i8
body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; SI-LABEL: name: test_sextload_flat_i31_i8
    ; SI: liveins: $vgpr0_vgpr1
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
    ; SI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
    ; SI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
    ; VI-LABEL: name: test_sextload_flat_i31_i8
    ; VI: liveins: $vgpr0_vgpr1
    ; VI-NEXT: {{  $}}
    ; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
    ; VI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
    ; VI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
    %0:_(p0) = COPY $vgpr0_vgpr1
    %1:_(s31) = G_SEXTLOAD %0 :: (load (s8), addrspace 0)
    %2:_(s32) = G_ANYEXT %1
    $vgpr0 = COPY %2
...
---
name: test_sextload_flat_i64_i8
body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; SI-LABEL: name: test_sextload_flat_i64_i8
    ; SI: liveins: $vgpr0_vgpr1
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
    ; SI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
    ; SI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
    ; SI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
    ; VI-LABEL: name: test_sextload_flat_i64_i8
    ; VI: liveins: $vgpr0_vgpr1
    ; VI-NEXT: {{  $}}
    ; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
    ; VI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
    ; VI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
    ; VI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
    %0:_(p0) = COPY $vgpr0_vgpr1
    %1:_(s64) = G_SEXTLOAD %0 :: (load (s8), addrspace 0)
    $vgpr0_vgpr1 = COPY %1
...
---
name: test_sextload_flat_i64_i16
body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; SI-LABEL: name: test_sextload_flat_i64_i16
    ; SI: liveins: $vgpr0_vgpr1
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
    ; SI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
    ; SI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
    ; SI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
    ; VI-LABEL: name: test_sextload_flat_i64_i16
    ; VI: liveins: $vgpr0_vgpr1
    ; VI-NEXT: {{  $}}
    ; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
    ; VI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
    ; VI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
    ; VI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
    %0:_(p0) = COPY $vgpr0_vgpr1
    %1:_(s64) = G_SEXTLOAD %0 :: (load (s16), addrspace 0)
    $vgpr0_vgpr1 = COPY %1
...
---
name: test_sextload_flat_i64_i32
body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; SI-LABEL: name: test_sextload_flat_i64_i32
    ; SI: liveins: $vgpr0_vgpr1
    ; SI-NEXT: {{  $}}
    ; SI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
    ; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
    ; SI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
    ; SI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
    ; VI-LABEL: name: test_sextload_flat_i64_i32
    ; VI: liveins: $vgpr0_vgpr1
    ; VI-NEXT: {{  $}}
    ; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
    ; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
    ; VI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
    ; VI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
    %0:_(p0) = COPY $vgpr0_vgpr1
    %1:_(s64) = G_SEXTLOAD %0 :: (load (s32), addrspace 0)
    $vgpr0_vgpr1 = COPY %1
...