# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GCN %s
---
name: implicit_def_s32_sgpr
legalized: true
regBankSelected: true
body: |
bb.0:
; GCN-LABEL: name: implicit_def_s32_sgpr
; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]
%0:sgpr(s32) = G_IMPLICIT_DEF
S_ENDPGM 0, implicit %0
...
---
name: implicit_def_s32_vgpr
legalized: true
regBankSelected: true
body: |
bb.0:
; GCN-LABEL: name: implicit_def_s32_vgpr
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]
%0:vgpr(s32) = G_IMPLICIT_DEF
S_ENDPGM 0, implicit %0
...
---
name: implicit_def_s64_sgpr
legalized: true
regBankSelected: true
body: |
bb.0:
; GCN-LABEL: name: implicit_def_s64_sgpr
; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]
%0:sgpr(s64) = G_IMPLICIT_DEF
S_ENDPGM 0, implicit %0
...
---
name: implicit_def_s64_vgpr
legalized: true
regBankSelected: true
body: |
bb.0:
; GCN-LABEL: name: implicit_def_s64_vgpr
; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]
%0:vgpr(s64) = G_IMPLICIT_DEF
S_ENDPGM 0, implicit %0
...
---
name: implicit_def_p0_sgpr
legalized: true
regBankSelected: true
body: |
bb.0:
; GCN-LABEL: name: implicit_def_p0_sgpr
; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]
%0:sgpr(p0) = G_IMPLICIT_DEF
S_ENDPGM 0, implicit %0
...
---
name: implicit_def_p0_vgpr
legalized: true
regBankSelected: true
body: |
bb.0:
; GCN-LABEL: name: implicit_def_p0_vgpr
; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]
%0:vgpr(p0) = G_IMPLICIT_DEF
S_ENDPGM 0, implicit %0
...
---
name: implicit_def_p1_vgpr
legalized: true
regBankSelected: true
body: |
bb.0:
; GCN-LABEL: name: implicit_def_p1_vgpr
; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
; GCN-NEXT: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32), addrspace 1)
%0:vgpr(p1) = G_IMPLICIT_DEF
%1:vgpr(s32) = G_CONSTANT i32 4
G_STORE %1, %0 :: (store (s32), addrspace 1)
...
---
name: implicit_def_p3_vgpr
legalized: true
regBankSelected: true
body: |
bb.0:
; GCN-LABEL: name: implicit_def_p3_vgpr
; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
; GCN-NEXT: $m0 = S_MOV_B32 -1
; GCN-NEXT: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32), addrspace 1)
%0:vgpr(p3) = G_IMPLICIT_DEF
%1:vgpr(s32) = G_CONSTANT i32 4
G_STORE %1, %0 :: (store (s32), addrspace 1)
...
---
name: implicit_def_p4_vgpr
legalized: true
regBankSelected: true
body: |
bb.0:
; GCN-LABEL: name: implicit_def_p4_vgpr
; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
; GCN-NEXT: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32), addrspace 1)
%0:vgpr(p4) = G_IMPLICIT_DEF
%1:vgpr(s32) = G_CONSTANT i32 4
G_STORE %1, %0 :: (store (s32), addrspace 1)
...
---
name: implicit_def_s1_vgpr
legalized: true
regBankSelected: true
body: |
bb.0:
; GCN-LABEL: name: implicit_def_s1_vgpr
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]
%0:vgpr(s1) = G_IMPLICIT_DEF
S_ENDPGM 0, implicit %0
...
---
name: implicit_def_s1_sgpr
legalized: true
regBankSelected: true
body: |
bb.0:
; GCN-LABEL: name: implicit_def_s1_sgpr
; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]
%0:sgpr(s1) = G_IMPLICIT_DEF
S_ENDPGM 0, implicit %0
...
---
name: implicit_def_s1_vcc
legalized: true
regBankSelected: true
body: |
bb.0:
; GCN-LABEL: name: implicit_def_s1_vcc
; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]
%0:vcc(s1) = G_IMPLICIT_DEF
S_ENDPGM 0, implicit %0
...
---
name: implicit_def_s1024_sgpr
legalized: true
regBankSelected: true
body: |
bb.0:
; GCN-LABEL: name: implicit_def_s1024_sgpr
; GCN: [[DEF:%[0-9]+]]:sgpr_1024 = IMPLICIT_DEF
; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]
%0:sgpr(s1024) = G_IMPLICIT_DEF
S_ENDPGM 0, implicit %0
...
---
name: implicit_def_s1024_vgpr
legalized: true
regBankSelected: true
body: |
bb.0:
; GCN-LABEL: name: implicit_def_s1024_vgpr
; GCN: [[DEF:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF
; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]
%0:vgpr(s1024) = G_IMPLICIT_DEF
S_ENDPGM 0, implicit %0
...
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