llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s

---
name: fsqrt_s
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: fsqrt_s
    ; CHECK: liveins: $sgpr0_sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
    ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:vgpr(s32) = G_FSQRT [[COPY1]]
    ; CHECK-NEXT: $vgpr0 = COPY [[FSQRT]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = G_FSQRT %0
    $vgpr0 = COPY %1
...

---
name: fsqrt_v
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1
    ; CHECK-LABEL: name: fsqrt_v
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:vgpr(s32) = G_FSQRT [[COPY]]
    ; CHECK-NEXT: $vgpr0 = COPY [[FSQRT]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = G_FSQRT %0
    $vgpr0 = COPY %1
...