llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s

---
name: atomic_cmpxchg_local_i32

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1, $sgpr2
    ; CHECK-LABEL: name: atomic_cmpxchg_local_i32
    ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr2
    ; CHECK-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p3), [[COPY1]], [[COPY2]] :: (load store seq_cst (s32), addrspace 3)
    %0:_(p3) = COPY $sgpr0
    %1:_(s32) = COPY $sgpr1
    %2:_(s32) = COPY $sgpr2
    %3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst (s32), addrspace 3)
...

---
name: atomic_cmpxchg_local_i64

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1, $sgpr2
    ; CHECK-LABEL: name: atomic_cmpxchg_local_i64
    ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr2
    ; CHECK-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p3), [[COPY1]], [[COPY2]] :: (load store seq_cst (s64), addrspace 3)
    %0:_(p3) = COPY $sgpr0
    %1:_(s32) = COPY $sgpr1
    %2:_(s32) = COPY $sgpr2
    %3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst (s64), addrspace 3)
...

---
name: atomic_cmpxchg_global_i32

body: |
  bb.0:
    liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
    ; CHECK-LABEL: name: atomic_cmpxchg_global_i32
    ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $sgpr0_sgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr3
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32)
    ; CHECK-NEXT: [[AMDGPU_ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_AMDGPU_ATOMIC_CMPXCHG [[COPY]](p1), [[BUILD_VECTOR]] :: (load store seq_cst (s32), addrspace 1)
    %0:_(p1) = COPY $sgpr0_sgpr1
    %1:_(s32) = COPY $sgpr2
    %2:_(s32) = COPY $sgpr3
    %3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst (s32), addrspace 1)
...

---
name: atomic_cmpxchg_global_i64

body: |
  bb.0:
    liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
    ; CHECK-LABEL: name: atomic_cmpxchg_global_i64
    ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $sgpr0_sgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr3
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32)
    ; CHECK-NEXT: [[AMDGPU_ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_AMDGPU_ATOMIC_CMPXCHG [[COPY]](p1), [[BUILD_VECTOR]] :: (load store seq_cst (s64), addrspace 1)
    %0:_(p1) = COPY $sgpr0_sgpr1
    %1:_(s32) = COPY $sgpr2
    %2:_(s32) = COPY $sgpr3
    %3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst (s64), addrspace 1)
...

---
name: atomic_cmpxchg_flat_i32

body: |
  bb.0:
    liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3

    ; CHECK-LABEL: name: atomic_cmpxchg_flat_i32
    ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sgpr0_sgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr3
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32)
    ; CHECK-NEXT: [[AMDGPU_ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_AMDGPU_ATOMIC_CMPXCHG [[COPY]](p0), [[BUILD_VECTOR]] :: (load store seq_cst (s32))
    %0:_(p0) = COPY $sgpr0_sgpr1
    %1:_(s32) = COPY $sgpr2
    %2:_(s32) = COPY $sgpr3
    %3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst (s32), addrspace 0)
...

---
name: atomic_cmpxchg_flat_i64

body: |
  bb.0:
    liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3

    ; CHECK-LABEL: name: atomic_cmpxchg_flat_i64
    ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sgpr0_sgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr3
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32)
    ; CHECK-NEXT: [[AMDGPU_ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_AMDGPU_ATOMIC_CMPXCHG [[COPY]](p0), [[BUILD_VECTOR]] :: (load store seq_cst (s64))
    %0:_(p0) = COPY $sgpr0_sgpr1
    %1:_(s32) = COPY $sgpr2
    %2:_(s32) = COPY $sgpr3
    %3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst (s64), addrspace 0)
...