; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
; PR4572
; Don't coalesce with %esp if it would end up putting %esp in
; the index position of an address, because that can't be
; encoded on x86. It would actually be slightly better to
; swap the address operands though, since there's no scale.
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
target triple = "i386-pc-mingw32"
%"struct.std::valarray<unsigned int>" = type { i32, ptr }
define void @_ZSt17__gslice_to_indexjRKSt8valarrayIjES2_RS0_(i32 %__o, ptr nocapture %__l, ptr nocapture %__s, ptr nocapture %__i) nounwind {
; CHECK-LABEL: _ZSt17__gslice_to_indexjRKSt8valarrayIjES2_RS0_:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: movl %esp, %eax
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testb %cl, %cl
; CHECK-NEXT: je .LBB0_1
; CHECK-NEXT: # %bb.5: # %return
; CHECK-NEXT: movl %ebp, %esp
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB0_1: # %bb4.preheader
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: jmp .LBB0_2
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_4: # %bb7.backedge
; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: addl $-4, %edx
; CHECK-NEXT: .LBB0_2: # %bb4
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: testb %cl, %cl
; CHECK-NEXT: jne .LBB0_4
; CHECK-NEXT: # %bb.3: # %bb5
; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: movl $0, (%eax,%edx)
; CHECK-NEXT: jmp .LBB0_4
entry:
%0 = alloca i32, i32 undef, align 4 ; <ptr> [#uses=1]
br i1 undef, label %return, label %bb4
bb4: ; preds = %bb7.backedge, %entry
%indvar = phi i32 [ %indvar.next, %bb7.backedge ], [ 0, %entry ] ; <i32> [#uses=2]
%scevgep24.sum = sub i32 undef, %indvar ; <i32> [#uses=2]
%scevgep25 = getelementptr i32, ptr %0, i32 %scevgep24.sum ; <ptr> [#uses=1]
%scevgep27 = getelementptr i32, ptr undef, i32 %scevgep24.sum ; <ptr> [#uses=1]
%1 = load i32, ptr %scevgep27, align 4 ; <i32> [#uses=0]
br i1 undef, label %bb7.backedge, label %bb5
bb5: ; preds = %bb4
store i32 0, ptr %scevgep25, align 4
br label %bb7.backedge
bb7.backedge: ; preds = %bb5, %bb4
%indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
br label %bb4
return: ; preds = %entry
ret void
}
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