llvm/llvm/test/MC/Disassembler/ARM/unpredictable-MVN-arm.txt

# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s

# A8.8.116 MVN (register)
# MVN(S)<c> <Rd>, <Rm>{, <shift>}
#
#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
# -------------------------------------------------------------------------------------------------
# | cond      | 0  0| 0| 1  1  1  1| S|(0)(0)(0)(0)| Rd       |  imm5        |type | 0| Rm        |
# -------------------------------------------------------------------------------------------------

# MVN  r2, r3  ; with bit 16 == 1 => Unpredictable
# CHECK: potentially undefined
# CHECK: 0x03 0x20 0xe1 0xe1
0x03 0x20 0xe1 0xe1

# A8.8.117 MVN (register-shifted register)
# MVN(S)<c> <Rd>, <Rm>, <type> <Rs>
#
#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
# -------------------------------------------------------------------------------------------------
# | cond      | 0  0| 0| 1  1  1  1| S|(0)(0)(0)(0)| Rd       | Rs        | 0|type | 1| Rm        |
# -------------------------------------------------------------------------------------------------
# if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;

# MVN  r5, pc, lsl r7
# CHECK: potentially undefined
# CHECK: 0x1f 0x57 0xe0 0xe1
0x1f 0x57 0xe0 0xe1

# MVN  pc, r6, lsl r7
# CHECK: potentially undefined
# CHECK: 0x16 0xf7 0xe0 0xe1
0x16 0xf7 0xe0 0xe1

# MVN  r5, r6, lsl pc
# CHECK: potentially undefined
# CHECK: 0x16 0x5f 0xe0 0xe1
0x16 0x5f 0xe0 0xe1