# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
# VNNI FP16
# ATT: vdpphps %xmm24, %xmm23, %xmm22
# INTEL: vdpphps xmm22, xmm23, xmm24
0x62,0x82,0x44,0x00,0x52,0xf0
# ATT: vdpphps %xmm24, %xmm23, %xmm22 {%k7}
# INTEL: vdpphps xmm22 {k7}, xmm23, xmm24
0x62,0x82,0x44,0x07,0x52,0xf0
# ATT: vdpphps %xmm24, %xmm23, %xmm22 {%k7} {z}
# INTEL: vdpphps xmm22 {k7} {z}, xmm23, xmm24
0x62,0x82,0x44,0x87,0x52,0xf0
# ATT: vdpphps %ymm24, %ymm23, %ymm22
# INTEL: vdpphps ymm22, ymm23, ymm24
0x62,0x82,0x44,0x20,0x52,0xf0
# ATT: vdpphps %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vdpphps ymm22 {k7}, ymm23, ymm24
0x62,0x82,0x44,0x27,0x52,0xf0
# ATT: vdpphps %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vdpphps ymm22 {k7} {z}, ymm23, ymm24
0x62,0x82,0x44,0xa7,0x52,0xf0
# ATT: vdpphps %zmm24, %zmm23, %zmm22
# INTEL: vdpphps zmm22, zmm23, zmm24
0x62,0x82,0x44,0x40,0x52,0xf0
# ATT: vdpphps %zmm24, %zmm23, %zmm22 {%k7}
# INTEL: vdpphps zmm22 {k7}, zmm23, zmm24
0x62,0x82,0x44,0x47,0x52,0xf0
# ATT: vdpphps %zmm24, %zmm23, %zmm22 {%k7} {z}
# INTEL: vdpphps zmm22 {k7} {z}, zmm23, zmm24
0x62,0x82,0x44,0xc7,0x52,0xf0
# ATT: vdpphps 268435456(%rbp,%r14,8), %xmm23, %xmm22
# INTEL: vdpphps xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x44,0x00,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vdpphps 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
# INTEL: vdpphps xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x44,0x07,0x52,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vdpphps (%rip){1to4}, %xmm23, %xmm22
# INTEL: vdpphps xmm22, xmm23, dword ptr [rip]{1to4}
0x62,0xe2,0x44,0x10,0x52,0x35,0x00,0x00,0x00,0x00
# ATT: vdpphps -512(,%rbp,2), %xmm23, %xmm22
# INTEL: vdpphps xmm22, xmm23, xmmword ptr [2*rbp - 512]
0x62,0xe2,0x44,0x00,0x52,0x34,0x6d,0x00,0xfe,0xff,0xff
# ATT: vdpphps 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
# INTEL: vdpphps xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032]
0x62,0xe2,0x44,0x87,0x52,0x71,0x7f
# ATT: vdpphps -512(%rdx){1to4}, %xmm23, %xmm22 {%k7} {z}
# INTEL: vdpphps xmm22 {k7} {z}, xmm23, dword ptr [rdx - 512]{1to4}
0x62,0xe2,0x44,0x97,0x52,0x72,0x80
# ATT: vdpphps 268435456(%rbp,%r14,8), %ymm23, %ymm22
# INTEL: vdpphps ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x44,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vdpphps 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
# INTEL: vdpphps ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x44,0x27,0x52,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vdpphps (%rip){1to8}, %ymm23, %ymm22
# INTEL: vdpphps ymm22, ymm23, dword ptr [rip]{1to8}
0x62,0xe2,0x44,0x30,0x52,0x35,0x00,0x00,0x00,0x00
# ATT: vdpphps -1024(,%rbp,2), %ymm23, %ymm22
# INTEL: vdpphps ymm22, ymm23, ymmword ptr [2*rbp - 1024]
0x62,0xe2,0x44,0x20,0x52,0x34,0x6d,0x00,0xfc,0xff,0xff
# ATT: vdpphps 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
# INTEL: vdpphps ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064]
0x62,0xe2,0x44,0xa7,0x52,0x71,0x7f
# ATT: vdpphps -512(%rdx){1to8}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vdpphps ymm22 {k7} {z}, ymm23, dword ptr [rdx - 512]{1to8}
0x62,0xe2,0x44,0xb7,0x52,0x72,0x80
# ATT: vdpphps 268435456(%rbp,%r14,8), %zmm23, %zmm22
# INTEL: vdpphps zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x44,0x40,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vdpphps 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
# INTEL: vdpphps zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x44,0x47,0x52,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vdpphps (%rip){1to16}, %zmm23, %zmm22
# INTEL: vdpphps zmm22, zmm23, dword ptr [rip]{1to16}
0x62,0xe2,0x44,0x50,0x52,0x35,0x00,0x00,0x00,0x00
# ATT: vdpphps -2048(,%rbp,2), %zmm23, %zmm22
# INTEL: vdpphps zmm22, zmm23, zmmword ptr [2*rbp - 2048]
0x62,0xe2,0x44,0x40,0x52,0x34,0x6d,0x00,0xf8,0xff,0xff
# ATT: vdpphps 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
# INTEL: vdpphps zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128]
0x62,0xe2,0x44,0xc7,0x52,0x71,0x7f
# ATT: vdpphps -512(%rdx){1to16}, %zmm23, %zmm22 {%k7} {z}
# INTEL: vdpphps zmm22 {k7} {z}, zmm23, dword ptr [rdx - 512]{1to16}
0x62,0xe2,0x44,0xd7,0x52,0x72,0x80
# VNNI INT8
# ATT: vpdpbssd %xmm24, %xmm23, %xmm22
# INTEL: vpdpbssd xmm22, xmm23, xmm24
0x62,0x82,0x47,0x00,0x50,0xf0
# ATT: vpdpbssd %xmm24, %xmm23, %xmm22 {%k7}
# INTEL: vpdpbssd xmm22 {k7}, xmm23, xmm24
0x62,0x82,0x47,0x07,0x50,0xf0
# ATT: vpdpbssd %xmm24, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpbssd xmm22 {k7} {z}, xmm23, xmm24
0x62,0x82,0x47,0x87,0x50,0xf0
# ATT: vpdpbssd %ymm24, %ymm23, %ymm22
# INTEL: vpdpbssd ymm22, ymm23, ymm24
0x62,0x82,0x47,0x20,0x50,0xf0
# ATT: vpdpbssd %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vpdpbssd ymm22 {k7}, ymm23, ymm24
0x62,0x82,0x47,0x27,0x50,0xf0
# ATT: vpdpbssd %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpbssd ymm22 {k7} {z}, ymm23, ymm24
0x62,0x82,0x47,0xa7,0x50,0xf0
# ATT: vpdpbssd %zmm24, %zmm23, %zmm22
# INTEL: vpdpbssd zmm22, zmm23, zmm24
0x62,0x82,0x47,0x40,0x50,0xf0
# ATT: vpdpbssd %zmm24, %zmm23, %zmm22 {%k7}
# INTEL: vpdpbssd zmm22 {k7}, zmm23, zmm24
0x62,0x82,0x47,0x47,0x50,0xf0
# ATT: vpdpbssd %zmm24, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpbssd zmm22 {k7} {z}, zmm23, zmm24
0x62,0x82,0x47,0xc7,0x50,0xf0
# ATT: vpdpbssd 268435456(%rbp,%r14,8), %xmm23, %xmm22
# INTEL: vpdpbssd xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x47,0x00,0x50,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpbssd 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
# INTEL: vpdpbssd xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x47,0x07,0x50,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpbssd (%rip){1to4}, %xmm23, %xmm22
# INTEL: vpdpbssd xmm22, xmm23, dword ptr [rip]{1to4}
0x62,0xe2,0x47,0x10,0x50,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpbssd -512(,%rbp,2), %xmm23, %xmm22
# INTEL: vpdpbssd xmm22, xmm23, xmmword ptr [2*rbp - 512]
0x62,0xe2,0x47,0x00,0x50,0x34,0x6d,0x00,0xfe,0xff,0xff
# ATT: vpdpbssd 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpbssd xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032]
0x62,0xe2,0x47,0x87,0x50,0x71,0x7f
# ATT: vpdpbssd -512(%rdx){1to4}, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpbssd xmm22 {k7} {z}, xmm23, dword ptr [rdx - 512]{1to4}
0x62,0xe2,0x47,0x97,0x50,0x72,0x80
# ATT: vpdpbssd 268435456(%rbp,%r14,8), %ymm23, %ymm22
# INTEL: vpdpbssd ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x47,0x20,0x50,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpbssd 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
# INTEL: vpdpbssd ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x47,0x27,0x50,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpbssd (%rip){1to8}, %ymm23, %ymm22
# INTEL: vpdpbssd ymm22, ymm23, dword ptr [rip]{1to8}
0x62,0xe2,0x47,0x30,0x50,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpbssd -1024(,%rbp,2), %ymm23, %ymm22
# INTEL: vpdpbssd ymm22, ymm23, ymmword ptr [2*rbp - 1024]
0x62,0xe2,0x47,0x20,0x50,0x34,0x6d,0x00,0xfc,0xff,0xff
# ATT: vpdpbssd 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpbssd ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064]
0x62,0xe2,0x47,0xa7,0x50,0x71,0x7f
# ATT: vpdpbssd -512(%rdx){1to8}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpbssd ymm22 {k7} {z}, ymm23, dword ptr [rdx - 512]{1to8}
0x62,0xe2,0x47,0xb7,0x50,0x72,0x80
# ATT: vpdpbssd 268435456(%rbp,%r14,8), %zmm23, %zmm22
# INTEL: vpdpbssd zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x47,0x40,0x50,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpbssd 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
# INTEL: vpdpbssd zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x47,0x47,0x50,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpbssd (%rip){1to16}, %zmm23, %zmm22
# INTEL: vpdpbssd zmm22, zmm23, dword ptr [rip]{1to16}
0x62,0xe2,0x47,0x50,0x50,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpbssd -2048(,%rbp,2), %zmm23, %zmm22
# INTEL: vpdpbssd zmm22, zmm23, zmmword ptr [2*rbp - 2048]
0x62,0xe2,0x47,0x40,0x50,0x34,0x6d,0x00,0xf8,0xff,0xff
# ATT: vpdpbssd 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpbssd zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128]
0x62,0xe2,0x47,0xc7,0x50,0x71,0x7f
# ATT: vpdpbssd -512(%rdx){1to16}, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpbssd zmm22 {k7} {z}, zmm23, dword ptr [rdx - 512]{1to16}
0x62,0xe2,0x47,0xd7,0x50,0x72,0x80
# ATT: vpdpbssds %xmm24, %xmm23, %xmm22
# INTEL: vpdpbssds xmm22, xmm23, xmm24
0x62,0x82,0x47,0x00,0x51,0xf0
# ATT: vpdpbssds %xmm24, %xmm23, %xmm22 {%k7}
# INTEL: vpdpbssds xmm22 {k7}, xmm23, xmm24
0x62,0x82,0x47,0x07,0x51,0xf0
# ATT: vpdpbssds %xmm24, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpbssds xmm22 {k7} {z}, xmm23, xmm24
0x62,0x82,0x47,0x87,0x51,0xf0
# ATT: vpdpbssds %ymm24, %ymm23, %ymm22
# INTEL: vpdpbssds ymm22, ymm23, ymm24
0x62,0x82,0x47,0x20,0x51,0xf0
# ATT: vpdpbssds %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vpdpbssds ymm22 {k7}, ymm23, ymm24
0x62,0x82,0x47,0x27,0x51,0xf0
# ATT: vpdpbssds %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpbssds ymm22 {k7} {z}, ymm23, ymm24
0x62,0x82,0x47,0xa7,0x51,0xf0
# ATT: vpdpbssds %zmm24, %zmm23, %zmm22
# INTEL: vpdpbssds zmm22, zmm23, zmm24
0x62,0x82,0x47,0x40,0x51,0xf0
# ATT: vpdpbssds %zmm24, %zmm23, %zmm22 {%k7}
# INTEL: vpdpbssds zmm22 {k7}, zmm23, zmm24
0x62,0x82,0x47,0x47,0x51,0xf0
# ATT: vpdpbssds %zmm24, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpbssds zmm22 {k7} {z}, zmm23, zmm24
0x62,0x82,0x47,0xc7,0x51,0xf0
# ATT: vpdpbssds 268435456(%rbp,%r14,8), %xmm23, %xmm22
# INTEL: vpdpbssds xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x47,0x00,0x51,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpbssds 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
# INTEL: vpdpbssds xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x47,0x07,0x51,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpbssds (%rip){1to4}, %xmm23, %xmm22
# INTEL: vpdpbssds xmm22, xmm23, dword ptr [rip]{1to4}
0x62,0xe2,0x47,0x10,0x51,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpbssds -512(,%rbp,2), %xmm23, %xmm22
# INTEL: vpdpbssds xmm22, xmm23, xmmword ptr [2*rbp - 512]
0x62,0xe2,0x47,0x00,0x51,0x34,0x6d,0x00,0xfe,0xff,0xff
# ATT: vpdpbssds 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpbssds xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032]
0x62,0xe2,0x47,0x87,0x51,0x71,0x7f
# ATT: vpdpbssds -512(%rdx){1to4}, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpbssds xmm22 {k7} {z}, xmm23, dword ptr [rdx - 512]{1to4}
0x62,0xe2,0x47,0x97,0x51,0x72,0x80
# ATT: vpdpbssds 268435456(%rbp,%r14,8), %ymm23, %ymm22
# INTEL: vpdpbssds ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x47,0x20,0x51,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpbssds 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
# INTEL: vpdpbssds ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x47,0x27,0x51,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpbssds (%rip){1to8}, %ymm23, %ymm22
# INTEL: vpdpbssds ymm22, ymm23, dword ptr [rip]{1to8}
0x62,0xe2,0x47,0x30,0x51,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpbssds -1024(,%rbp,2), %ymm23, %ymm22
# INTEL: vpdpbssds ymm22, ymm23, ymmword ptr [2*rbp - 1024]
0x62,0xe2,0x47,0x20,0x51,0x34,0x6d,0x00,0xfc,0xff,0xff
# ATT: vpdpbssds 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpbssds ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064]
0x62,0xe2,0x47,0xa7,0x51,0x71,0x7f
# ATT: vpdpbssds -512(%rdx){1to8}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpbssds ymm22 {k7} {z}, ymm23, dword ptr [rdx - 512]{1to8}
0x62,0xe2,0x47,0xb7,0x51,0x72,0x80
# ATT: vpdpbssds 268435456(%rbp,%r14,8), %zmm23, %zmm22
# INTEL: vpdpbssds zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x47,0x40,0x51,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpbssds 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
# INTEL: vpdpbssds zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x47,0x47,0x51,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpbssds (%rip){1to16}, %zmm23, %zmm22
# INTEL: vpdpbssds zmm22, zmm23, dword ptr [rip]{1to16}
0x62,0xe2,0x47,0x50,0x51,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpbssds -2048(,%rbp,2), %zmm23, %zmm22
# INTEL: vpdpbssds zmm22, zmm23, zmmword ptr [2*rbp - 2048]
0x62,0xe2,0x47,0x40,0x51,0x34,0x6d,0x00,0xf8,0xff,0xff
# ATT: vpdpbssds 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpbssds zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128]
0x62,0xe2,0x47,0xc7,0x51,0x71,0x7f
# ATT: vpdpbssds -512(%rdx){1to16}, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpbssds zmm22 {k7} {z}, zmm23, dword ptr [rdx - 512]{1to16}
0x62,0xe2,0x47,0xd7,0x51,0x72,0x80
# ATT: vpdpbsud %xmm24, %xmm23, %xmm22
# INTEL: vpdpbsud xmm22, xmm23, xmm24
0x62,0x82,0x46,0x00,0x50,0xf0
# ATT: vpdpbsud %xmm24, %xmm23, %xmm22 {%k7}
# INTEL: vpdpbsud xmm22 {k7}, xmm23, xmm24
0x62,0x82,0x46,0x07,0x50,0xf0
# ATT: vpdpbsud %xmm24, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpbsud xmm22 {k7} {z}, xmm23, xmm24
0x62,0x82,0x46,0x87,0x50,0xf0
# ATT: vpdpbsud %ymm24, %ymm23, %ymm22
# INTEL: vpdpbsud ymm22, ymm23, ymm24
0x62,0x82,0x46,0x20,0x50,0xf0
# ATT: vpdpbsud %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vpdpbsud ymm22 {k7}, ymm23, ymm24
0x62,0x82,0x46,0x27,0x50,0xf0
# ATT: vpdpbsud %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpbsud ymm22 {k7} {z}, ymm23, ymm24
0x62,0x82,0x46,0xa7,0x50,0xf0
# ATT: vpdpbsud %zmm24, %zmm23, %zmm22
# INTEL: vpdpbsud zmm22, zmm23, zmm24
0x62,0x82,0x46,0x40,0x50,0xf0
# ATT: vpdpbsud %zmm24, %zmm23, %zmm22 {%k7}
# INTEL: vpdpbsud zmm22 {k7}, zmm23, zmm24
0x62,0x82,0x46,0x47,0x50,0xf0
# ATT: vpdpbsud %zmm24, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpbsud zmm22 {k7} {z}, zmm23, zmm24
0x62,0x82,0x46,0xc7,0x50,0xf0
# ATT: vpdpbsud 268435456(%rbp,%r14,8), %xmm23, %xmm22
# INTEL: vpdpbsud xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x46,0x00,0x50,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpbsud 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
# INTEL: vpdpbsud xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x46,0x07,0x50,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpbsud (%rip){1to4}, %xmm23, %xmm22
# INTEL: vpdpbsud xmm22, xmm23, dword ptr [rip]{1to4}
0x62,0xe2,0x46,0x10,0x50,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpbsud -512(,%rbp,2), %xmm23, %xmm22
# INTEL: vpdpbsud xmm22, xmm23, xmmword ptr [2*rbp - 512]
0x62,0xe2,0x46,0x00,0x50,0x34,0x6d,0x00,0xfe,0xff,0xff
# ATT: vpdpbsud 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpbsud xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032]
0x62,0xe2,0x46,0x87,0x50,0x71,0x7f
# ATT: vpdpbsud -512(%rdx){1to4}, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpbsud xmm22 {k7} {z}, xmm23, dword ptr [rdx - 512]{1to4}
0x62,0xe2,0x46,0x97,0x50,0x72,0x80
# ATT: vpdpbsud 268435456(%rbp,%r14,8), %ymm23, %ymm22
# INTEL: vpdpbsud ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x46,0x20,0x50,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpbsud 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
# INTEL: vpdpbsud ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x46,0x27,0x50,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpbsud (%rip){1to8}, %ymm23, %ymm22
# INTEL: vpdpbsud ymm22, ymm23, dword ptr [rip]{1to8}
0x62,0xe2,0x46,0x30,0x50,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpbsud -1024(,%rbp,2), %ymm23, %ymm22
# INTEL: vpdpbsud ymm22, ymm23, ymmword ptr [2*rbp - 1024]
0x62,0xe2,0x46,0x20,0x50,0x34,0x6d,0x00,0xfc,0xff,0xff
# ATT: vpdpbsud 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpbsud ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064]
0x62,0xe2,0x46,0xa7,0x50,0x71,0x7f
# ATT: vpdpbsud -512(%rdx){1to8}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpbsud ymm22 {k7} {z}, ymm23, dword ptr [rdx - 512]{1to8}
0x62,0xe2,0x46,0xb7,0x50,0x72,0x80
# ATT: vpdpbsud 268435456(%rbp,%r14,8), %zmm23, %zmm22
# INTEL: vpdpbsud zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x46,0x40,0x50,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpbsud 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
# INTEL: vpdpbsud zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x46,0x47,0x50,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpbsud (%rip){1to16}, %zmm23, %zmm22
# INTEL: vpdpbsud zmm22, zmm23, dword ptr [rip]{1to16}
0x62,0xe2,0x46,0x50,0x50,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpbsud -2048(,%rbp,2), %zmm23, %zmm22
# INTEL: vpdpbsud zmm22, zmm23, zmmword ptr [2*rbp - 2048]
0x62,0xe2,0x46,0x40,0x50,0x34,0x6d,0x00,0xf8,0xff,0xff
# ATT: vpdpbsud 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpbsud zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128]
0x62,0xe2,0x46,0xc7,0x50,0x71,0x7f
# ATT: vpdpbsud -512(%rdx){1to16}, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpbsud zmm22 {k7} {z}, zmm23, dword ptr [rdx - 512]{1to16}
0x62,0xe2,0x46,0xd7,0x50,0x72,0x80
# ATT: vpdpbsuds %xmm24, %xmm23, %xmm22
# INTEL: vpdpbsuds xmm22, xmm23, xmm24
0x62,0x82,0x46,0x00,0x51,0xf0
# ATT: vpdpbsuds %xmm24, %xmm23, %xmm22 {%k7}
# INTEL: vpdpbsuds xmm22 {k7}, xmm23, xmm24
0x62,0x82,0x46,0x07,0x51,0xf0
# ATT: vpdpbsuds %xmm24, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpbsuds xmm22 {k7} {z}, xmm23, xmm24
0x62,0x82,0x46,0x87,0x51,0xf0
# ATT: vpdpbsuds %ymm24, %ymm23, %ymm22
# INTEL: vpdpbsuds ymm22, ymm23, ymm24
0x62,0x82,0x46,0x20,0x51,0xf0
# ATT: vpdpbsuds %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vpdpbsuds ymm22 {k7}, ymm23, ymm24
0x62,0x82,0x46,0x27,0x51,0xf0
# ATT: vpdpbsuds %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpbsuds ymm22 {k7} {z}, ymm23, ymm24
0x62,0x82,0x46,0xa7,0x51,0xf0
# ATT: vpdpbsuds %zmm24, %zmm23, %zmm22
# INTEL: vpdpbsuds zmm22, zmm23, zmm24
0x62,0x82,0x46,0x40,0x51,0xf0
# ATT: vpdpbsuds %zmm24, %zmm23, %zmm22 {%k7}
# INTEL: vpdpbsuds zmm22 {k7}, zmm23, zmm24
0x62,0x82,0x46,0x47,0x51,0xf0
# ATT: vpdpbsuds %zmm24, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpbsuds zmm22 {k7} {z}, zmm23, zmm24
0x62,0x82,0x46,0xc7,0x51,0xf0
# ATT: vpdpbsuds 268435456(%rbp,%r14,8), %xmm23, %xmm22
# INTEL: vpdpbsuds xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x46,0x00,0x51,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpbsuds 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
# INTEL: vpdpbsuds xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x46,0x07,0x51,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpbsuds (%rip){1to4}, %xmm23, %xmm22
# INTEL: vpdpbsuds xmm22, xmm23, dword ptr [rip]{1to4}
0x62,0xe2,0x46,0x10,0x51,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpbsuds -512(,%rbp,2), %xmm23, %xmm22
# INTEL: vpdpbsuds xmm22, xmm23, xmmword ptr [2*rbp - 512]
0x62,0xe2,0x46,0x00,0x51,0x34,0x6d,0x00,0xfe,0xff,0xff
# ATT: vpdpbsuds 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpbsuds xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032]
0x62,0xe2,0x46,0x87,0x51,0x71,0x7f
# ATT: vpdpbsuds -512(%rdx){1to4}, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpbsuds xmm22 {k7} {z}, xmm23, dword ptr [rdx - 512]{1to4}
0x62,0xe2,0x46,0x97,0x51,0x72,0x80
# ATT: vpdpbsuds 268435456(%rbp,%r14,8), %ymm23, %ymm22
# INTEL: vpdpbsuds ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x46,0x20,0x51,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpbsuds 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
# INTEL: vpdpbsuds ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x46,0x27,0x51,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpbsuds (%rip){1to8}, %ymm23, %ymm22
# INTEL: vpdpbsuds ymm22, ymm23, dword ptr [rip]{1to8}
0x62,0xe2,0x46,0x30,0x51,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpbsuds -1024(,%rbp,2), %ymm23, %ymm22
# INTEL: vpdpbsuds ymm22, ymm23, ymmword ptr [2*rbp - 1024]
0x62,0xe2,0x46,0x20,0x51,0x34,0x6d,0x00,0xfc,0xff,0xff
# ATT: vpdpbsuds 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpbsuds ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064]
0x62,0xe2,0x46,0xa7,0x51,0x71,0x7f
# ATT: vpdpbsuds -512(%rdx){1to8}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpbsuds ymm22 {k7} {z}, ymm23, dword ptr [rdx - 512]{1to8}
0x62,0xe2,0x46,0xb7,0x51,0x72,0x80
# ATT: vpdpbsuds 268435456(%rbp,%r14,8), %zmm23, %zmm22
# INTEL: vpdpbsuds zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x46,0x40,0x51,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpbsuds 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
# INTEL: vpdpbsuds zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x46,0x47,0x51,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpbsuds (%rip){1to16}, %zmm23, %zmm22
# INTEL: vpdpbsuds zmm22, zmm23, dword ptr [rip]{1to16}
0x62,0xe2,0x46,0x50,0x51,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpbsuds -2048(,%rbp,2), %zmm23, %zmm22
# INTEL: vpdpbsuds zmm22, zmm23, zmmword ptr [2*rbp - 2048]
0x62,0xe2,0x46,0x40,0x51,0x34,0x6d,0x00,0xf8,0xff,0xff
# ATT: vpdpbsuds 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpbsuds zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128]
0x62,0xe2,0x46,0xc7,0x51,0x71,0x7f
# ATT: vpdpbsuds -512(%rdx){1to16}, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpbsuds zmm22 {k7} {z}, zmm23, dword ptr [rdx - 512]{1to16}
0x62,0xe2,0x46,0xd7,0x51,0x72,0x80
# ATT: vpdpbuud %xmm24, %xmm23, %xmm22
# INTEL: vpdpbuud xmm22, xmm23, xmm24
0x62,0x82,0x44,0x00,0x50,0xf0
# ATT: vpdpbuud %xmm24, %xmm23, %xmm22 {%k7}
# INTEL: vpdpbuud xmm22 {k7}, xmm23, xmm24
0x62,0x82,0x44,0x07,0x50,0xf0
# ATT: vpdpbuud %xmm24, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpbuud xmm22 {k7} {z}, xmm23, xmm24
0x62,0x82,0x44,0x87,0x50,0xf0
# ATT: vpdpbuud %ymm24, %ymm23, %ymm22
# INTEL: vpdpbuud ymm22, ymm23, ymm24
0x62,0x82,0x44,0x20,0x50,0xf0
# ATT: vpdpbuud %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vpdpbuud ymm22 {k7}, ymm23, ymm24
0x62,0x82,0x44,0x27,0x50,0xf0
# ATT: vpdpbuud %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpbuud ymm22 {k7} {z}, ymm23, ymm24
0x62,0x82,0x44,0xa7,0x50,0xf0
# ATT: vpdpbuud %zmm24, %zmm23, %zmm22
# INTEL: vpdpbuud zmm22, zmm23, zmm24
0x62,0x82,0x44,0x40,0x50,0xf0
# ATT: vpdpbuud %zmm24, %zmm23, %zmm22 {%k7}
# INTEL: vpdpbuud zmm22 {k7}, zmm23, zmm24
0x62,0x82,0x44,0x47,0x50,0xf0
# ATT: vpdpbuud %zmm24, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpbuud zmm22 {k7} {z}, zmm23, zmm24
0x62,0x82,0x44,0xc7,0x50,0xf0
# ATT: vpdpbuud 268435456(%rbp,%r14,8), %xmm23, %xmm22
# INTEL: vpdpbuud xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x44,0x00,0x50,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpbuud 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
# INTEL: vpdpbuud xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x44,0x07,0x50,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpbuud (%rip){1to4}, %xmm23, %xmm22
# INTEL: vpdpbuud xmm22, xmm23, dword ptr [rip]{1to4}
0x62,0xe2,0x44,0x10,0x50,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpbuud -512(,%rbp,2), %xmm23, %xmm22
# INTEL: vpdpbuud xmm22, xmm23, xmmword ptr [2*rbp - 512]
0x62,0xe2,0x44,0x00,0x50,0x34,0x6d,0x00,0xfe,0xff,0xff
# ATT: vpdpbuud 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpbuud xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032]
0x62,0xe2,0x44,0x87,0x50,0x71,0x7f
# ATT: vpdpbuud -512(%rdx){1to4}, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpbuud xmm22 {k7} {z}, xmm23, dword ptr [rdx - 512]{1to4}
0x62,0xe2,0x44,0x97,0x50,0x72,0x80
# ATT: vpdpbuud 268435456(%rbp,%r14,8), %ymm23, %ymm22
# INTEL: vpdpbuud ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x44,0x20,0x50,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpbuud 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
# INTEL: vpdpbuud ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x44,0x27,0x50,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpbuud (%rip){1to8}, %ymm23, %ymm22
# INTEL: vpdpbuud ymm22, ymm23, dword ptr [rip]{1to8}
0x62,0xe2,0x44,0x30,0x50,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpbuud -1024(,%rbp,2), %ymm23, %ymm22
# INTEL: vpdpbuud ymm22, ymm23, ymmword ptr [2*rbp - 1024]
0x62,0xe2,0x44,0x20,0x50,0x34,0x6d,0x00,0xfc,0xff,0xff
# ATT: vpdpbuud 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpbuud ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064]
0x62,0xe2,0x44,0xa7,0x50,0x71,0x7f
# ATT: vpdpbuud -512(%rdx){1to8}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpbuud ymm22 {k7} {z}, ymm23, dword ptr [rdx - 512]{1to8}
0x62,0xe2,0x44,0xb7,0x50,0x72,0x80
# ATT: vpdpbuud 268435456(%rbp,%r14,8), %zmm23, %zmm22
# INTEL: vpdpbuud zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x44,0x40,0x50,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpbuud 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
# INTEL: vpdpbuud zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x44,0x47,0x50,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpbuud (%rip){1to16}, %zmm23, %zmm22
# INTEL: vpdpbuud zmm22, zmm23, dword ptr [rip]{1to16}
0x62,0xe2,0x44,0x50,0x50,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpbuud -2048(,%rbp,2), %zmm23, %zmm22
# INTEL: vpdpbuud zmm22, zmm23, zmmword ptr [2*rbp - 2048]
0x62,0xe2,0x44,0x40,0x50,0x34,0x6d,0x00,0xf8,0xff,0xff
# ATT: vpdpbuud 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpbuud zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128]
0x62,0xe2,0x44,0xc7,0x50,0x71,0x7f
# ATT: vpdpbuud -512(%rdx){1to16}, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpbuud zmm22 {k7} {z}, zmm23, dword ptr [rdx - 512]{1to16}
0x62,0xe2,0x44,0xd7,0x50,0x72,0x80
# ATT: vpdpbuuds %xmm24, %xmm23, %xmm22
# INTEL: vpdpbuuds xmm22, xmm23, xmm24
0x62,0x82,0x44,0x00,0x51,0xf0
# ATT: vpdpbuuds %xmm24, %xmm23, %xmm22 {%k7}
# INTEL: vpdpbuuds xmm22 {k7}, xmm23, xmm24
0x62,0x82,0x44,0x07,0x51,0xf0
# ATT: vpdpbuuds %xmm24, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpbuuds xmm22 {k7} {z}, xmm23, xmm24
0x62,0x82,0x44,0x87,0x51,0xf0
# ATT: vpdpbuuds %ymm24, %ymm23, %ymm22
# INTEL: vpdpbuuds ymm22, ymm23, ymm24
0x62,0x82,0x44,0x20,0x51,0xf0
# ATT: vpdpbuuds %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vpdpbuuds ymm22 {k7}, ymm23, ymm24
0x62,0x82,0x44,0x27,0x51,0xf0
# ATT: vpdpbuuds %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpbuuds ymm22 {k7} {z}, ymm23, ymm24
0x62,0x82,0x44,0xa7,0x51,0xf0
# ATT: vpdpbuuds %zmm24, %zmm23, %zmm22
# INTEL: vpdpbuuds zmm22, zmm23, zmm24
0x62,0x82,0x44,0x40,0x51,0xf0
# ATT: vpdpbuuds %zmm24, %zmm23, %zmm22 {%k7}
# INTEL: vpdpbuuds zmm22 {k7}, zmm23, zmm24
0x62,0x82,0x44,0x47,0x51,0xf0
# ATT: vpdpbuuds %zmm24, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpbuuds zmm22 {k7} {z}, zmm23, zmm24
0x62,0x82,0x44,0xc7,0x51,0xf0
# ATT: vpdpbuuds 268435456(%rbp,%r14,8), %xmm23, %xmm22
# INTEL: vpdpbuuds xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x44,0x00,0x51,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpbuuds 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
# INTEL: vpdpbuuds xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x44,0x07,0x51,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpbuuds (%rip){1to4}, %xmm23, %xmm22
# INTEL: vpdpbuuds xmm22, xmm23, dword ptr [rip]{1to4}
0x62,0xe2,0x44,0x10,0x51,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpbuuds -512(,%rbp,2), %xmm23, %xmm22
# INTEL: vpdpbuuds xmm22, xmm23, xmmword ptr [2*rbp - 512]
0x62,0xe2,0x44,0x00,0x51,0x34,0x6d,0x00,0xfe,0xff,0xff
# ATT: vpdpbuuds 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpbuuds xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032]
0x62,0xe2,0x44,0x87,0x51,0x71,0x7f
# ATT: vpdpbuuds -512(%rdx){1to4}, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpbuuds xmm22 {k7} {z}, xmm23, dword ptr [rdx - 512]{1to4}
0x62,0xe2,0x44,0x97,0x51,0x72,0x80
# ATT: vpdpbuuds 268435456(%rbp,%r14,8), %ymm23, %ymm22
# INTEL: vpdpbuuds ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x44,0x20,0x51,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpbuuds 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
# INTEL: vpdpbuuds ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x44,0x27,0x51,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpbuuds (%rip){1to8}, %ymm23, %ymm22
# INTEL: vpdpbuuds ymm22, ymm23, dword ptr [rip]{1to8}
0x62,0xe2,0x44,0x30,0x51,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpbuuds -1024(,%rbp,2), %ymm23, %ymm22
# INTEL: vpdpbuuds ymm22, ymm23, ymmword ptr [2*rbp - 1024]
0x62,0xe2,0x44,0x20,0x51,0x34,0x6d,0x00,0xfc,0xff,0xff
# ATT: vpdpbuuds 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpbuuds ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064]
0x62,0xe2,0x44,0xa7,0x51,0x71,0x7f
# ATT: vpdpbuuds -512(%rdx){1to8}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpbuuds ymm22 {k7} {z}, ymm23, dword ptr [rdx - 512]{1to8}
0x62,0xe2,0x44,0xb7,0x51,0x72,0x80
# ATT: vpdpbuuds 268435456(%rbp,%r14,8), %zmm23, %zmm22
# INTEL: vpdpbuuds zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x44,0x40,0x51,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpbuuds 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
# INTEL: vpdpbuuds zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x44,0x47,0x51,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpbuuds (%rip){1to16}, %zmm23, %zmm22
# INTEL: vpdpbuuds zmm22, zmm23, dword ptr [rip]{1to16}
0x62,0xe2,0x44,0x50,0x51,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpbuuds -2048(,%rbp,2), %zmm23, %zmm22
# INTEL: vpdpbuuds zmm22, zmm23, zmmword ptr [2*rbp - 2048]
0x62,0xe2,0x44,0x40,0x51,0x34,0x6d,0x00,0xf8,0xff,0xff
# ATT: vpdpbuuds 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpbuuds zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128]
0x62,0xe2,0x44,0xc7,0x51,0x71,0x7f
# ATT: vpdpbuuds -512(%rdx){1to16}, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpbuuds zmm22 {k7} {z}, zmm23, dword ptr [rdx - 512]{1to16}
0x62,0xe2,0x44,0xd7,0x51,0x72,0x80
# VNNI INT16
# ATT: vpdpwsud %xmm24, %xmm23, %xmm22
# INTEL: vpdpwsud xmm22, xmm23, xmm24
0x62,0x82,0x46,0x00,0xd2,0xf0
# ATT: vpdpwsud %xmm24, %xmm23, %xmm22 {%k7}
# INTEL: vpdpwsud xmm22 {k7}, xmm23, xmm24
0x62,0x82,0x46,0x07,0xd2,0xf0
# ATT: vpdpwsud %xmm24, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpwsud xmm22 {k7} {z}, xmm23, xmm24
0x62,0x82,0x46,0x87,0xd2,0xf0
# ATT: vpdpwsud %ymm24, %ymm23, %ymm22
# INTEL: vpdpwsud ymm22, ymm23, ymm24
0x62,0x82,0x46,0x20,0xd2,0xf0
# ATT: vpdpwsud %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vpdpwsud ymm22 {k7}, ymm23, ymm24
0x62,0x82,0x46,0x27,0xd2,0xf0
# ATT: vpdpwsud %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpwsud ymm22 {k7} {z}, ymm23, ymm24
0x62,0x82,0x46,0xa7,0xd2,0xf0
# ATT: vpdpwsud %zmm24, %zmm23, %zmm22
# INTEL: vpdpwsud zmm22, zmm23, zmm24
0x62,0x82,0x46,0x40,0xd2,0xf0
# ATT: vpdpwsud %zmm24, %zmm23, %zmm22 {%k7}
# INTEL: vpdpwsud zmm22 {k7}, zmm23, zmm24
0x62,0x82,0x46,0x47,0xd2,0xf0
# ATT: vpdpwsud %zmm24, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpwsud zmm22 {k7} {z}, zmm23, zmm24
0x62,0x82,0x46,0xc7,0xd2,0xf0
# ATT: vpdpwsud 268435456(%rbp,%r14,8), %xmm23, %xmm22
# INTEL: vpdpwsud xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x46,0x00,0xd2,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpwsud 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
# INTEL: vpdpwsud xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x46,0x07,0xd2,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpwsud (%rip){1to4}, %xmm23, %xmm22
# INTEL: vpdpwsud xmm22, xmm23, dword ptr [rip]{1to4}
0x62,0xe2,0x46,0x10,0xd2,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpwsud -512(,%rbp,2), %xmm23, %xmm22
# INTEL: vpdpwsud xmm22, xmm23, xmmword ptr [2*rbp - 512]
0x62,0xe2,0x46,0x00,0xd2,0x34,0x6d,0x00,0xfe,0xff,0xff
# ATT: vpdpwsud 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpwsud xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032]
0x62,0xe2,0x46,0x87,0xd2,0x71,0x7f
# ATT: vpdpwsud -512(%rdx){1to4}, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpwsud xmm22 {k7} {z}, xmm23, dword ptr [rdx - 512]{1to4}
0x62,0xe2,0x46,0x97,0xd2,0x72,0x80
# ATT: vpdpwsud 268435456(%rbp,%r14,8), %ymm23, %ymm22
# INTEL: vpdpwsud ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x46,0x20,0xd2,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpwsud 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
# INTEL: vpdpwsud ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x46,0x27,0xd2,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpwsud (%rip){1to8}, %ymm23, %ymm22
# INTEL: vpdpwsud ymm22, ymm23, dword ptr [rip]{1to8}
0x62,0xe2,0x46,0x30,0xd2,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpwsud -1024(,%rbp,2), %ymm23, %ymm22
# INTEL: vpdpwsud ymm22, ymm23, ymmword ptr [2*rbp - 1024]
0x62,0xe2,0x46,0x20,0xd2,0x34,0x6d,0x00,0xfc,0xff,0xff
# ATT: vpdpwsud 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpwsud ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064]
0x62,0xe2,0x46,0xa7,0xd2,0x71,0x7f
# ATT: vpdpwsud -512(%rdx){1to8}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpwsud ymm22 {k7} {z}, ymm23, dword ptr [rdx - 512]{1to8}
0x62,0xe2,0x46,0xb7,0xd2,0x72,0x80
# ATT: vpdpwsud 268435456(%rbp,%r14,8), %zmm23, %zmm22
# INTEL: vpdpwsud zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x46,0x40,0xd2,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpwsud 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
# INTEL: vpdpwsud zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x46,0x47,0xd2,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpwsud (%rip){1to16}, %zmm23, %zmm22
# INTEL: vpdpwsud zmm22, zmm23, dword ptr [rip]{1to16}
0x62,0xe2,0x46,0x50,0xd2,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpwsud -2048(,%rbp,2), %zmm23, %zmm22
# INTEL: vpdpwsud zmm22, zmm23, zmmword ptr [2*rbp - 2048]
0x62,0xe2,0x46,0x40,0xd2,0x34,0x6d,0x00,0xf8,0xff,0xff
# ATT: vpdpwsud 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpwsud zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128]
0x62,0xe2,0x46,0xc7,0xd2,0x71,0x7f
# ATT: vpdpwsud -512(%rdx){1to16}, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpwsud zmm22 {k7} {z}, zmm23, dword ptr [rdx - 512]{1to16}
0x62,0xe2,0x46,0xd7,0xd2,0x72,0x80
# ATT: vpdpwsuds %xmm24, %xmm23, %xmm22
# INTEL: vpdpwsuds xmm22, xmm23, xmm24
0x62,0x82,0x46,0x00,0xd3,0xf0
# ATT: vpdpwsuds %xmm24, %xmm23, %xmm22 {%k7}
# INTEL: vpdpwsuds xmm22 {k7}, xmm23, xmm24
0x62,0x82,0x46,0x07,0xd3,0xf0
# ATT: vpdpwsuds %xmm24, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpwsuds xmm22 {k7} {z}, xmm23, xmm24
0x62,0x82,0x46,0x87,0xd3,0xf0
# ATT: vpdpwsuds %ymm24, %ymm23, %ymm22
# INTEL: vpdpwsuds ymm22, ymm23, ymm24
0x62,0x82,0x46,0x20,0xd3,0xf0
# ATT: vpdpwsuds %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vpdpwsuds ymm22 {k7}, ymm23, ymm24
0x62,0x82,0x46,0x27,0xd3,0xf0
# ATT: vpdpwsuds %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpwsuds ymm22 {k7} {z}, ymm23, ymm24
0x62,0x82,0x46,0xa7,0xd3,0xf0
# ATT: vpdpwsuds %zmm24, %zmm23, %zmm22
# INTEL: vpdpwsuds zmm22, zmm23, zmm24
0x62,0x82,0x46,0x40,0xd3,0xf0
# ATT: vpdpwsuds %zmm24, %zmm23, %zmm22 {%k7}
# INTEL: vpdpwsuds zmm22 {k7}, zmm23, zmm24
0x62,0x82,0x46,0x47,0xd3,0xf0
# ATT: vpdpwsuds %zmm24, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpwsuds zmm22 {k7} {z}, zmm23, zmm24
0x62,0x82,0x46,0xc7,0xd3,0xf0
# ATT: vpdpwsuds 268435456(%rbp,%r14,8), %xmm23, %xmm22
# INTEL: vpdpwsuds xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x46,0x00,0xd3,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpwsuds 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
# INTEL: vpdpwsuds xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x46,0x07,0xd3,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpwsuds (%rip){1to4}, %xmm23, %xmm22
# INTEL: vpdpwsuds xmm22, xmm23, dword ptr [rip]{1to4}
0x62,0xe2,0x46,0x10,0xd3,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpwsuds -512(,%rbp,2), %xmm23, %xmm22
# INTEL: vpdpwsuds xmm22, xmm23, xmmword ptr [2*rbp - 512]
0x62,0xe2,0x46,0x00,0xd3,0x34,0x6d,0x00,0xfe,0xff,0xff
# ATT: vpdpwsuds 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpwsuds xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032]
0x62,0xe2,0x46,0x87,0xd3,0x71,0x7f
# ATT: vpdpwsuds -512(%rdx){1to4}, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpwsuds xmm22 {k7} {z}, xmm23, dword ptr [rdx - 512]{1to4}
0x62,0xe2,0x46,0x97,0xd3,0x72,0x80
# ATT: vpdpwsuds 268435456(%rbp,%r14,8), %ymm23, %ymm22
# INTEL: vpdpwsuds ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x46,0x20,0xd3,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpwsuds 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
# INTEL: vpdpwsuds ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x46,0x27,0xd3,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpwsuds (%rip){1to8}, %ymm23, %ymm22
# INTEL: vpdpwsuds ymm22, ymm23, dword ptr [rip]{1to8}
0x62,0xe2,0x46,0x30,0xd3,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpwsuds -1024(,%rbp,2), %ymm23, %ymm22
# INTEL: vpdpwsuds ymm22, ymm23, ymmword ptr [2*rbp - 1024]
0x62,0xe2,0x46,0x20,0xd3,0x34,0x6d,0x00,0xfc,0xff,0xff
# ATT: vpdpwsuds 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpwsuds ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064]
0x62,0xe2,0x46,0xa7,0xd3,0x71,0x7f
# ATT: vpdpwsuds -512(%rdx){1to8}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpwsuds ymm22 {k7} {z}, ymm23, dword ptr [rdx - 512]{1to8}
0x62,0xe2,0x46,0xb7,0xd3,0x72,0x80
# ATT: vpdpwsuds 268435456(%rbp,%r14,8), %zmm23, %zmm22
# INTEL: vpdpwsuds zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x46,0x40,0xd3,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpwsuds 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
# INTEL: vpdpwsuds zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x46,0x47,0xd3,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpwsuds (%rip){1to16}, %zmm23, %zmm22
# INTEL: vpdpwsuds zmm22, zmm23, dword ptr [rip]{1to16}
0x62,0xe2,0x46,0x50,0xd3,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpwsuds -2048(,%rbp,2), %zmm23, %zmm22
# INTEL: vpdpwsuds zmm22, zmm23, zmmword ptr [2*rbp - 2048]
0x62,0xe2,0x46,0x40,0xd3,0x34,0x6d,0x00,0xf8,0xff,0xff
# ATT: vpdpwsuds 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpwsuds zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128]
0x62,0xe2,0x46,0xc7,0xd3,0x71,0x7f
# ATT: vpdpwsuds -512(%rdx){1to16}, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpwsuds zmm22 {k7} {z}, zmm23, dword ptr [rdx - 512]{1to16}
0x62,0xe2,0x46,0xd7,0xd3,0x72,0x80
# ATT: vpdpwusd %xmm24, %xmm23, %xmm22
# INTEL: vpdpwusd xmm22, xmm23, xmm24
0x62,0x82,0x45,0x00,0xd2,0xf0
# ATT: vpdpwusd %xmm24, %xmm23, %xmm22 {%k7}
# INTEL: vpdpwusd xmm22 {k7}, xmm23, xmm24
0x62,0x82,0x45,0x07,0xd2,0xf0
# ATT: vpdpwusd %xmm24, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpwusd xmm22 {k7} {z}, xmm23, xmm24
0x62,0x82,0x45,0x87,0xd2,0xf0
# ATT: vpdpwusd %ymm24, %ymm23, %ymm22
# INTEL: vpdpwusd ymm22, ymm23, ymm24
0x62,0x82,0x45,0x20,0xd2,0xf0
# ATT: vpdpwusd %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vpdpwusd ymm22 {k7}, ymm23, ymm24
0x62,0x82,0x45,0x27,0xd2,0xf0
# ATT: vpdpwusd %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpwusd ymm22 {k7} {z}, ymm23, ymm24
0x62,0x82,0x45,0xa7,0xd2,0xf0
# ATT: vpdpwusd %zmm24, %zmm23, %zmm22
# INTEL: vpdpwusd zmm22, zmm23, zmm24
0x62,0x82,0x45,0x40,0xd2,0xf0
# ATT: vpdpwusd %zmm24, %zmm23, %zmm22 {%k7}
# INTEL: vpdpwusd zmm22 {k7}, zmm23, zmm24
0x62,0x82,0x45,0x47,0xd2,0xf0
# ATT: vpdpwusd %zmm24, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpwusd zmm22 {k7} {z}, zmm23, zmm24
0x62,0x82,0x45,0xc7,0xd2,0xf0
# ATT: vpdpwusd 268435456(%rbp,%r14,8), %xmm23, %xmm22
# INTEL: vpdpwusd xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x45,0x00,0xd2,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpwusd 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
# INTEL: vpdpwusd xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x45,0x07,0xd2,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpwusd (%rip){1to4}, %xmm23, %xmm22
# INTEL: vpdpwusd xmm22, xmm23, dword ptr [rip]{1to4}
0x62,0xe2,0x45,0x10,0xd2,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpwusd -512(,%rbp,2), %xmm23, %xmm22
# INTEL: vpdpwusd xmm22, xmm23, xmmword ptr [2*rbp - 512]
0x62,0xe2,0x45,0x00,0xd2,0x34,0x6d,0x00,0xfe,0xff,0xff
# ATT: vpdpwusd 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpwusd xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032]
0x62,0xe2,0x45,0x87,0xd2,0x71,0x7f
# ATT: vpdpwusd -512(%rdx){1to4}, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpwusd xmm22 {k7} {z}, xmm23, dword ptr [rdx - 512]{1to4}
0x62,0xe2,0x45,0x97,0xd2,0x72,0x80
# ATT: vpdpwusd 268435456(%rbp,%r14,8), %ymm23, %ymm22
# INTEL: vpdpwusd ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x45,0x20,0xd2,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpwusd 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
# INTEL: vpdpwusd ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x45,0x27,0xd2,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpwusd (%rip){1to8}, %ymm23, %ymm22
# INTEL: vpdpwusd ymm22, ymm23, dword ptr [rip]{1to8}
0x62,0xe2,0x45,0x30,0xd2,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpwusd -1024(,%rbp,2), %ymm23, %ymm22
# INTEL: vpdpwusd ymm22, ymm23, ymmword ptr [2*rbp - 1024]
0x62,0xe2,0x45,0x20,0xd2,0x34,0x6d,0x00,0xfc,0xff,0xff
# ATT: vpdpwusd 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpwusd ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064]
0x62,0xe2,0x45,0xa7,0xd2,0x71,0x7f
# ATT: vpdpwusd -512(%rdx){1to8}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpwusd ymm22 {k7} {z}, ymm23, dword ptr [rdx - 512]{1to8}
0x62,0xe2,0x45,0xb7,0xd2,0x72,0x80
# ATT: vpdpwusd 268435456(%rbp,%r14,8), %zmm23, %zmm22
# INTEL: vpdpwusd zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x45,0x40,0xd2,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpwusd 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
# INTEL: vpdpwusd zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x45,0x47,0xd2,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpwusd (%rip){1to16}, %zmm23, %zmm22
# INTEL: vpdpwusd zmm22, zmm23, dword ptr [rip]{1to16}
0x62,0xe2,0x45,0x50,0xd2,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpwusd -2048(,%rbp,2), %zmm23, %zmm22
# INTEL: vpdpwusd zmm22, zmm23, zmmword ptr [2*rbp - 2048]
0x62,0xe2,0x45,0x40,0xd2,0x34,0x6d,0x00,0xf8,0xff,0xff
# ATT: vpdpwusd 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpwusd zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128]
0x62,0xe2,0x45,0xc7,0xd2,0x71,0x7f
# ATT: vpdpwusd -512(%rdx){1to16}, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpwusd zmm22 {k7} {z}, zmm23, dword ptr [rdx - 512]{1to16}
0x62,0xe2,0x45,0xd7,0xd2,0x72,0x80
# ATT: vpdpwusds %xmm24, %xmm23, %xmm22
# INTEL: vpdpwusds xmm22, xmm23, xmm24
0x62,0x82,0x45,0x00,0xd3,0xf0
# ATT: vpdpwusds %xmm24, %xmm23, %xmm22 {%k7}
# INTEL: vpdpwusds xmm22 {k7}, xmm23, xmm24
0x62,0x82,0x45,0x07,0xd3,0xf0
# ATT: vpdpwusds %xmm24, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpwusds xmm22 {k7} {z}, xmm23, xmm24
0x62,0x82,0x45,0x87,0xd3,0xf0
# ATT: vpdpwusds %ymm24, %ymm23, %ymm22
# INTEL: vpdpwusds ymm22, ymm23, ymm24
0x62,0x82,0x45,0x20,0xd3,0xf0
# ATT: vpdpwusds %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vpdpwusds ymm22 {k7}, ymm23, ymm24
0x62,0x82,0x45,0x27,0xd3,0xf0
# ATT: vpdpwusds %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpwusds ymm22 {k7} {z}, ymm23, ymm24
0x62,0x82,0x45,0xa7,0xd3,0xf0
# ATT: vpdpwusds %zmm24, %zmm23, %zmm22
# INTEL: vpdpwusds zmm22, zmm23, zmm24
0x62,0x82,0x45,0x40,0xd3,0xf0
# ATT: vpdpwusds %zmm24, %zmm23, %zmm22 {%k7}
# INTEL: vpdpwusds zmm22 {k7}, zmm23, zmm24
0x62,0x82,0x45,0x47,0xd3,0xf0
# ATT: vpdpwusds %zmm24, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpwusds zmm22 {k7} {z}, zmm23, zmm24
0x62,0x82,0x45,0xc7,0xd3,0xf0
# ATT: vpdpwusds 268435456(%rbp,%r14,8), %xmm23, %xmm22
# INTEL: vpdpwusds xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x45,0x00,0xd3,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpwusds 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
# INTEL: vpdpwusds xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x45,0x07,0xd3,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpwusds (%rip){1to4}, %xmm23, %xmm22
# INTEL: vpdpwusds xmm22, xmm23, dword ptr [rip]{1to4}
0x62,0xe2,0x45,0x10,0xd3,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpwusds -512(,%rbp,2), %xmm23, %xmm22
# INTEL: vpdpwusds xmm22, xmm23, xmmword ptr [2*rbp - 512]
0x62,0xe2,0x45,0x00,0xd3,0x34,0x6d,0x00,0xfe,0xff,0xff
# ATT: vpdpwusds 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpwusds xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032]
0x62,0xe2,0x45,0x87,0xd3,0x71,0x7f
# ATT: vpdpwusds -512(%rdx){1to4}, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpwusds xmm22 {k7} {z}, xmm23, dword ptr [rdx - 512]{1to4}
0x62,0xe2,0x45,0x97,0xd3,0x72,0x80
# ATT: vpdpwusds 268435456(%rbp,%r14,8), %ymm23, %ymm22
# INTEL: vpdpwusds ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x45,0x20,0xd3,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpwusds 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
# INTEL: vpdpwusds ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x45,0x27,0xd3,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpwusds (%rip){1to8}, %ymm23, %ymm22
# INTEL: vpdpwusds ymm22, ymm23, dword ptr [rip]{1to8}
0x62,0xe2,0x45,0x30,0xd3,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpwusds -1024(,%rbp,2), %ymm23, %ymm22
# INTEL: vpdpwusds ymm22, ymm23, ymmword ptr [2*rbp - 1024]
0x62,0xe2,0x45,0x20,0xd3,0x34,0x6d,0x00,0xfc,0xff,0xff
# ATT: vpdpwusds 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpwusds ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064]
0x62,0xe2,0x45,0xa7,0xd3,0x71,0x7f
# ATT: vpdpwusds -512(%rdx){1to8}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpwusds ymm22 {k7} {z}, ymm23, dword ptr [rdx - 512]{1to8}
0x62,0xe2,0x45,0xb7,0xd3,0x72,0x80
# ATT: vpdpwusds 268435456(%rbp,%r14,8), %zmm23, %zmm22
# INTEL: vpdpwusds zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x45,0x40,0xd3,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpwusds 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
# INTEL: vpdpwusds zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x45,0x47,0xd3,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpwusds (%rip){1to16}, %zmm23, %zmm22
# INTEL: vpdpwusds zmm22, zmm23, dword ptr [rip]{1to16}
0x62,0xe2,0x45,0x50,0xd3,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpwusds -2048(,%rbp,2), %zmm23, %zmm22
# INTEL: vpdpwusds zmm22, zmm23, zmmword ptr [2*rbp - 2048]
0x62,0xe2,0x45,0x40,0xd3,0x34,0x6d,0x00,0xf8,0xff,0xff
# ATT: vpdpwusds 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpwusds zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128]
0x62,0xe2,0x45,0xc7,0xd3,0x71,0x7f
# ATT: vpdpwusds -512(%rdx){1to16}, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpwusds zmm22 {k7} {z}, zmm23, dword ptr [rdx - 512]{1to16}
0x62,0xe2,0x45,0xd7,0xd3,0x72,0x80
# ATT: vpdpwuud %xmm24, %xmm23, %xmm22
# INTEL: vpdpwuud xmm22, xmm23, xmm24
0x62,0x82,0x44,0x00,0xd2,0xf0
# ATT: vpdpwuud %xmm24, %xmm23, %xmm22 {%k7}
# INTEL: vpdpwuud xmm22 {k7}, xmm23, xmm24
0x62,0x82,0x44,0x07,0xd2,0xf0
# ATT: vpdpwuud %xmm24, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpwuud xmm22 {k7} {z}, xmm23, xmm24
0x62,0x82,0x44,0x87,0xd2,0xf0
# ATT: vpdpwuud %ymm24, %ymm23, %ymm22
# INTEL: vpdpwuud ymm22, ymm23, ymm24
0x62,0x82,0x44,0x20,0xd2,0xf0
# ATT: vpdpwuud %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vpdpwuud ymm22 {k7}, ymm23, ymm24
0x62,0x82,0x44,0x27,0xd2,0xf0
# ATT: vpdpwuud %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpwuud ymm22 {k7} {z}, ymm23, ymm24
0x62,0x82,0x44,0xa7,0xd2,0xf0
# ATT: vpdpwuud %zmm24, %zmm23, %zmm22
# INTEL: vpdpwuud zmm22, zmm23, zmm24
0x62,0x82,0x44,0x40,0xd2,0xf0
# ATT: vpdpwuud %zmm24, %zmm23, %zmm22 {%k7}
# INTEL: vpdpwuud zmm22 {k7}, zmm23, zmm24
0x62,0x82,0x44,0x47,0xd2,0xf0
# ATT: vpdpwuud %zmm24, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpwuud zmm22 {k7} {z}, zmm23, zmm24
0x62,0x82,0x44,0xc7,0xd2,0xf0
# ATT: vpdpwuud 268435456(%rbp,%r14,8), %xmm23, %xmm22
# INTEL: vpdpwuud xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x44,0x00,0xd2,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpwuud 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
# INTEL: vpdpwuud xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x44,0x07,0xd2,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpwuud (%rip){1to4}, %xmm23, %xmm22
# INTEL: vpdpwuud xmm22, xmm23, dword ptr [rip]{1to4}
0x62,0xe2,0x44,0x10,0xd2,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpwuud -512(,%rbp,2), %xmm23, %xmm22
# INTEL: vpdpwuud xmm22, xmm23, xmmword ptr [2*rbp - 512]
0x62,0xe2,0x44,0x00,0xd2,0x34,0x6d,0x00,0xfe,0xff,0xff
# ATT: vpdpwuud 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpwuud xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032]
0x62,0xe2,0x44,0x87,0xd2,0x71,0x7f
# ATT: vpdpwuud -512(%rdx){1to4}, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpwuud xmm22 {k7} {z}, xmm23, dword ptr [rdx - 512]{1to4}
0x62,0xe2,0x44,0x97,0xd2,0x72,0x80
# ATT: vpdpwuud 268435456(%rbp,%r14,8), %ymm23, %ymm22
# INTEL: vpdpwuud ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x44,0x20,0xd2,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpwuud 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
# INTEL: vpdpwuud ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x44,0x27,0xd2,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpwuud (%rip){1to8}, %ymm23, %ymm22
# INTEL: vpdpwuud ymm22, ymm23, dword ptr [rip]{1to8}
0x62,0xe2,0x44,0x30,0xd2,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpwuud -1024(,%rbp,2), %ymm23, %ymm22
# INTEL: vpdpwuud ymm22, ymm23, ymmword ptr [2*rbp - 1024]
0x62,0xe2,0x44,0x20,0xd2,0x34,0x6d,0x00,0xfc,0xff,0xff
# ATT: vpdpwuud 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpwuud ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064]
0x62,0xe2,0x44,0xa7,0xd2,0x71,0x7f
# ATT: vpdpwuud -512(%rdx){1to8}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpwuud ymm22 {k7} {z}, ymm23, dword ptr [rdx - 512]{1to8}
0x62,0xe2,0x44,0xb7,0xd2,0x72,0x80
# ATT: vpdpwuud 268435456(%rbp,%r14,8), %zmm23, %zmm22
# INTEL: vpdpwuud zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x44,0x40,0xd2,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpwuud 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
# INTEL: vpdpwuud zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x44,0x47,0xd2,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpwuud (%rip){1to16}, %zmm23, %zmm22
# INTEL: vpdpwuud zmm22, zmm23, dword ptr [rip]{1to16}
0x62,0xe2,0x44,0x50,0xd2,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpwuud -2048(,%rbp,2), %zmm23, %zmm22
# INTEL: vpdpwuud zmm22, zmm23, zmmword ptr [2*rbp - 2048]
0x62,0xe2,0x44,0x40,0xd2,0x34,0x6d,0x00,0xf8,0xff,0xff
# ATT: vpdpwuud 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpwuud zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128]
0x62,0xe2,0x44,0xc7,0xd2,0x71,0x7f
# ATT: vpdpwuud -512(%rdx){1to16}, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpwuud zmm22 {k7} {z}, zmm23, dword ptr [rdx - 512]{1to16}
0x62,0xe2,0x44,0xd7,0xd2,0x72,0x80
# ATT: vpdpwuuds %xmm24, %xmm23, %xmm22
# INTEL: vpdpwuuds xmm22, xmm23, xmm24
0x62,0x82,0x44,0x00,0xd3,0xf0
# ATT: vpdpwuuds %xmm24, %xmm23, %xmm22 {%k7}
# INTEL: vpdpwuuds xmm22 {k7}, xmm23, xmm24
0x62,0x82,0x44,0x07,0xd3,0xf0
# ATT: vpdpwuuds %xmm24, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpwuuds xmm22 {k7} {z}, xmm23, xmm24
0x62,0x82,0x44,0x87,0xd3,0xf0
# ATT: vpdpwuuds %ymm24, %ymm23, %ymm22
# INTEL: vpdpwuuds ymm22, ymm23, ymm24
0x62,0x82,0x44,0x20,0xd3,0xf0
# ATT: vpdpwuuds %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vpdpwuuds ymm22 {k7}, ymm23, ymm24
0x62,0x82,0x44,0x27,0xd3,0xf0
# ATT: vpdpwuuds %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpwuuds ymm22 {k7} {z}, ymm23, ymm24
0x62,0x82,0x44,0xa7,0xd3,0xf0
# ATT: vpdpwuuds %zmm24, %zmm23, %zmm22
# INTEL: vpdpwuuds zmm22, zmm23, zmm24
0x62,0x82,0x44,0x40,0xd3,0xf0
# ATT: vpdpwuuds %zmm24, %zmm23, %zmm22 {%k7}
# INTEL: vpdpwuuds zmm22 {k7}, zmm23, zmm24
0x62,0x82,0x44,0x47,0xd3,0xf0
# ATT: vpdpwuuds %zmm24, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpwuuds zmm22 {k7} {z}, zmm23, zmm24
0x62,0x82,0x44,0xc7,0xd3,0xf0
# ATT: vpdpwuuds 268435456(%rbp,%r14,8), %xmm23, %xmm22
# INTEL: vpdpwuuds xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x44,0x00,0xd3,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpwuuds 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
# INTEL: vpdpwuuds xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x44,0x07,0xd3,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpwuuds (%rip){1to4}, %xmm23, %xmm22
# INTEL: vpdpwuuds xmm22, xmm23, dword ptr [rip]{1to4}
0x62,0xe2,0x44,0x10,0xd3,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpwuuds -512(,%rbp,2), %xmm23, %xmm22
# INTEL: vpdpwuuds xmm22, xmm23, xmmword ptr [2*rbp - 512]
0x62,0xe2,0x44,0x00,0xd3,0x34,0x6d,0x00,0xfe,0xff,0xff
# ATT: vpdpwuuds 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpwuuds xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032]
0x62,0xe2,0x44,0x87,0xd3,0x71,0x7f
# ATT: vpdpwuuds -512(%rdx){1to4}, %xmm23, %xmm22 {%k7} {z}
# INTEL: vpdpwuuds xmm22 {k7} {z}, xmm23, dword ptr [rdx - 512]{1to4}
0x62,0xe2,0x44,0x97,0xd3,0x72,0x80
# ATT: vpdpwuuds 268435456(%rbp,%r14,8), %ymm23, %ymm22
# INTEL: vpdpwuuds ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x44,0x20,0xd3,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpwuuds 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
# INTEL: vpdpwuuds ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x44,0x27,0xd3,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpwuuds (%rip){1to8}, %ymm23, %ymm22
# INTEL: vpdpwuuds ymm22, ymm23, dword ptr [rip]{1to8}
0x62,0xe2,0x44,0x30,0xd3,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpwuuds -1024(,%rbp,2), %ymm23, %ymm22
# INTEL: vpdpwuuds ymm22, ymm23, ymmword ptr [2*rbp - 1024]
0x62,0xe2,0x44,0x20,0xd3,0x34,0x6d,0x00,0xfc,0xff,0xff
# ATT: vpdpwuuds 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpwuuds ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064]
0x62,0xe2,0x44,0xa7,0xd3,0x71,0x7f
# ATT: vpdpwuuds -512(%rdx){1to8}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vpdpwuuds ymm22 {k7} {z}, ymm23, dword ptr [rdx - 512]{1to8}
0x62,0xe2,0x44,0xb7,0xd3,0x72,0x80
# ATT: vpdpwuuds 268435456(%rbp,%r14,8), %zmm23, %zmm22
# INTEL: vpdpwuuds zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456]
0x62,0xa2,0x44,0x40,0xd3,0xb4,0xf5,0x00,0x00,0x00,0x10
# ATT: vpdpwuuds 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
# INTEL: vpdpwuuds zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291]
0x62,0xc2,0x44,0x47,0xd3,0xb4,0x80,0x23,0x01,0x00,0x00
# ATT: vpdpwuuds (%rip){1to16}, %zmm23, %zmm22
# INTEL: vpdpwuuds zmm22, zmm23, dword ptr [rip]{1to16}
0x62,0xe2,0x44,0x50,0xd3,0x35,0x00,0x00,0x00,0x00
# ATT: vpdpwuuds -2048(,%rbp,2), %zmm23, %zmm22
# INTEL: vpdpwuuds zmm22, zmm23, zmmword ptr [2*rbp - 2048]
0x62,0xe2,0x44,0x40,0xd3,0x34,0x6d,0x00,0xf8,0xff,0xff
# ATT: vpdpwuuds 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpwuuds zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128]
0x62,0xe2,0x44,0xc7,0xd3,0x71,0x7f
# ATT: vpdpwuuds -512(%rdx){1to16}, %zmm23, %zmm22 {%k7} {z}
# INTEL: vpdpwuuds zmm22 {k7} {z}, zmm23, dword ptr [rdx - 512]{1to16}
0x62,0xe2,0x44,0xd7,0xd3,0x72,0x80
# VMPSADBW
# ATT: vmpsadbw $123, %xmm24, %xmm23, %xmm22
# INTEL: vmpsadbw xmm22, xmm23, xmm24, 123
0x62,0x83,0x46,0x00,0x42,0xf0,0x7b
# ATT: vmpsadbw $123, %xmm24, %xmm23, %xmm22 {%k7}
# INTEL: vmpsadbw xmm22 {k7}, xmm23, xmm24, 123
0x62,0x83,0x46,0x07,0x42,0xf0,0x7b
# ATT: vmpsadbw $123, %xmm24, %xmm23, %xmm22 {%k7} {z}
# INTEL: vmpsadbw xmm22 {k7} {z}, xmm23, xmm24, 123
0x62,0x83,0x46,0x87,0x42,0xf0,0x7b
# ATT: vmpsadbw $123, %ymm24, %ymm23, %ymm22
# INTEL: vmpsadbw ymm22, ymm23, ymm24, 123
0x62,0x83,0x46,0x20,0x42,0xf0,0x7b
# ATT: vmpsadbw $123, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vmpsadbw ymm22 {k7}, ymm23, ymm24, 123
0x62,0x83,0x46,0x27,0x42,0xf0,0x7b
# ATT: vmpsadbw $123, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vmpsadbw ymm22 {k7} {z}, ymm23, ymm24, 123
0x62,0x83,0x46,0xa7,0x42,0xf0,0x7b
# ATT: vmpsadbw $123, %zmm24, %zmm23, %zmm22
# INTEL: vmpsadbw zmm22, zmm23, zmm24, 123
0x62,0x83,0x46,0x40,0x42,0xf0,0x7b
# ATT: vmpsadbw $123, %zmm24, %zmm23, %zmm22 {%k7}
# INTEL: vmpsadbw zmm22 {k7}, zmm23, zmm24, 123
0x62,0x83,0x46,0x47,0x42,0xf0,0x7b
# ATT: vmpsadbw $123, %zmm24, %zmm23, %zmm22 {%k7} {z}
# INTEL: vmpsadbw zmm22 {k7} {z}, zmm23, zmm24, 123
0x62,0x83,0x46,0xc7,0x42,0xf0,0x7b
# ATT: vmpsadbw $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
# INTEL: vmpsadbw xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456], 123
0x62,0xa3,0x46,0x00,0x42,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b
# ATT: vmpsadbw $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
# INTEL: vmpsadbw xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291], 123
0x62,0xc3,0x46,0x07,0x42,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b
# ATT: vmpsadbw $123, (%rip), %xmm23, %xmm22
# INTEL: vmpsadbw xmm22, xmm23, xmmword ptr [rip], 123
0x62,0xe3,0x46,0x00,0x42,0x35,0x00,0x00,0x00,0x00,0x7b
# ATT: vmpsadbw $123, -512(,%rbp,2), %xmm23, %xmm22
# INTEL: vmpsadbw xmm22, xmm23, xmmword ptr [2*rbp - 512], 123
0x62,0xe3,0x46,0x00,0x42,0x34,0x6d,0x00,0xfe,0xff,0xff,0x7b
# ATT: vmpsadbw $123, 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
# INTEL: vmpsadbw xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032], 123
0x62,0xe3,0x46,0x87,0x42,0x71,0x7f,0x7b
# ATT: vmpsadbw $123, -2048(%rdx), %xmm23, %xmm22 {%k7} {z}
# INTEL: vmpsadbw xmm22 {k7} {z}, xmm23, xmmword ptr [rdx - 2048], 123
0x62,0xe3,0x46,0x87,0x42,0x72,0x80,0x7b
# ATT: vmpsadbw $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22
# INTEL: vmpsadbw ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123
0x62,0xa3,0x46,0x20,0x42,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b
# ATT: vmpsadbw $123, 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
# INTEL: vmpsadbw ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291], 123
0x62,0xc3,0x46,0x27,0x42,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b
# ATT: vmpsadbw $123, (%rip), %ymm23, %ymm22
# INTEL: vmpsadbw ymm22, ymm23, ymmword ptr [rip], 123
0x62,0xe3,0x46,0x20,0x42,0x35,0x00,0x00,0x00,0x00,0x7b
# ATT: vmpsadbw $123, -1024(,%rbp,2), %ymm23, %ymm22
# INTEL: vmpsadbw ymm22, ymm23, ymmword ptr [2*rbp - 1024], 123
0x62,0xe3,0x46,0x20,0x42,0x34,0x6d,0x00,0xfc,0xff,0xff,0x7b
# ATT: vmpsadbw $123, 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
# INTEL: vmpsadbw ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064], 123
0x62,0xe3,0x46,0xa7,0x42,0x71,0x7f,0x7b
# ATT: vmpsadbw $123, -4096(%rdx), %ymm23, %ymm22 {%k7} {z}
# INTEL: vmpsadbw ymm22 {k7} {z}, ymm23, ymmword ptr [rdx - 4096], 123
0x62,0xe3,0x46,0xa7,0x42,0x72,0x80,0x7b
# ATT: vmpsadbw $123, 268435456(%rbp,%r14,8), %zmm23, %zmm22
# INTEL: vmpsadbw zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456], 123
0x62,0xa3,0x46,0x40,0x42,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b
# ATT: vmpsadbw $123, 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
# INTEL: vmpsadbw zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291], 123
0x62,0xc3,0x46,0x47,0x42,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b
# ATT: vmpsadbw $123, (%rip), %zmm23, %zmm22
# INTEL: vmpsadbw zmm22, zmm23, zmmword ptr [rip], 123
0x62,0xe3,0x46,0x40,0x42,0x35,0x00,0x00,0x00,0x00,0x7b
# ATT: vmpsadbw $123, -2048(,%rbp,2), %zmm23, %zmm22
# INTEL: vmpsadbw zmm22, zmm23, zmmword ptr [2*rbp - 2048], 123
0x62,0xe3,0x46,0x40,0x42,0x34,0x6d,0x00,0xf8,0xff,0xff,0x7b
# ATT: vmpsadbw $123, 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
# INTEL: vmpsadbw zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128], 123
0x62,0xe3,0x46,0xc7,0x42,0x71,0x7f,0x7b
# ATT: vmpsadbw $123, -8192(%rdx), %zmm23, %zmm22 {%k7} {z}
# INTEL: vmpsadbw zmm22 {k7} {z}, zmm23, zmmword ptr [rdx - 8192], 123
0x62,0xe3,0x46,0xc7,0x42,0x72,0x80,0x7b
# YMM Rounding
# ATT: vaddpd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vaddpd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x81,0xc1,0x10,0x58,0xf0
# ATT: vaddpd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vaddpd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x81,0xc1,0x37,0x58,0xf0
# ATT: vaddpd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vaddpd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x81,0xc1,0xf7,0x58,0xf0
# ATT: vaddph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vaddph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x85,0x40,0x10,0x58,0xf0
# ATT: vaddph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vaddph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x85,0x40,0x37,0x58,0xf0
# ATT: vaddph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vaddph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x85,0x40,0xf7,0x58,0xf0
# ATT: vaddps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vaddps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x81,0x40,0x10,0x58,0xf0
# ATT: vaddps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vaddps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x81,0x40,0x37,0x58,0xf0
# ATT: vaddps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vaddps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x81,0x40,0xf7,0x58,0xf0
# ATT: vcmppd $123, {sae}, %ymm24, %ymm23, %k5
# INTEL: vcmppd k5, ymm23, ymm24, {sae}, 123
0x62,0x91,0xc1,0x10,0xc2,0xe8,0x7b
# ATT: vcmppd $123, {sae}, %ymm24, %ymm23, %k5 {%k7}
# INTEL: vcmppd k5 {k7}, ymm23, ymm24, {sae}, 123
0x62,0x91,0xc1,0x17,0xc2,0xe8,0x7b
# ATT: vcmpph $123, {sae}, %ymm24, %ymm23, %k5
# INTEL: vcmpph k5, ymm23, ymm24, {sae}, 123
0x62,0x93,0x40,0x10,0xc2,0xe8,0x7b
# ATT: vcmpph $123, {sae}, %ymm24, %ymm23, %k5 {%k7}
# INTEL: vcmpph k5 {k7}, ymm23, ymm24, {sae}, 123
0x62,0x93,0x40,0x17,0xc2,0xe8,0x7b
# ATT: vcmpps $123, {sae}, %ymm24, %ymm23, %k5
# INTEL: vcmpps k5, ymm23, ymm24, {sae}, 123
0x62,0x91,0x40,0x10,0xc2,0xe8,0x7b
# ATT: vcmpps $123, {sae}, %ymm24, %ymm23, %k5 {%k7}
# INTEL: vcmpps k5 {k7}, ymm23, ymm24, {sae}, 123
0x62,0x91,0x40,0x17,0xc2,0xe8,0x7b
# ATT: vcvtdq2ph {rn-sae}, %ymm23, %xmm22
# INTEL: vcvtdq2ph xmm22, ymm23, {rn-sae}
0x62,0xa5,0x78,0x18,0x5b,0xf7
# ATT: vcvtdq2ph {rd-sae}, %ymm23, %xmm22 {%k7}
# INTEL: vcvtdq2ph xmm22 {k7}, ymm23, {rd-sae}
0x62,0xa5,0x78,0x3f,0x5b,0xf7
# ATT: vcvtdq2ph {rz-sae}, %ymm23, %xmm22 {%k7} {z}
# INTEL: vcvtdq2ph xmm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa5,0x78,0xff,0x5b,0xf7
# ATT: vcvtdq2ps {rn-sae}, %ymm23, %ymm22
# INTEL: vcvtdq2ps ymm22, ymm23, {rn-sae}
0x62,0xa1,0x78,0x18,0x5b,0xf7
# ATT: vcvtdq2ps {rd-sae}, %ymm23, %ymm22 {%k7}
# INTEL: vcvtdq2ps ymm22 {k7}, ymm23, {rd-sae}
0x62,0xa1,0x78,0x3f,0x5b,0xf7
# ATT: vcvtdq2ps {rz-sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vcvtdq2ps ymm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa1,0x78,0xff,0x5b,0xf7
# ATT: vcvtpd2dq {rn-sae}, %ymm23, %xmm22
# INTEL: vcvtpd2dq xmm22, ymm23, {rn-sae}
0x62,0xa1,0xfb,0x18,0xe6,0xf7
# ATT: vcvtpd2dq {rd-sae}, %ymm23, %xmm22 {%k7}
# INTEL: vcvtpd2dq xmm22 {k7}, ymm23, {rd-sae}
0x62,0xa1,0xfb,0x3f,0xe6,0xf7
# ATT: vcvtpd2dq {rz-sae}, %ymm23, %xmm22 {%k7} {z}
# INTEL: vcvtpd2dq xmm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa1,0xfb,0xff,0xe6,0xf7
# ATT: vcvtpd2ph {rn-sae}, %ymm23, %xmm22
# INTEL: vcvtpd2ph xmm22, ymm23, {rn-sae}
0x62,0xa5,0xf9,0x18,0x5a,0xf7
# ATT: vcvtpd2ph {rd-sae}, %ymm23, %xmm22 {%k7}
# INTEL: vcvtpd2ph xmm22 {k7}, ymm23, {rd-sae}
0x62,0xa5,0xf9,0x3f,0x5a,0xf7
# ATT: vcvtpd2ph {rz-sae}, %ymm23, %xmm22 {%k7} {z}
# INTEL: vcvtpd2ph xmm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa5,0xf9,0xff,0x5a,0xf7
# ATT: vcvtpd2ps {rn-sae}, %ymm23, %xmm22
# INTEL: vcvtpd2ps xmm22, ymm23, {rn-sae}
0x62,0xa1,0xf9,0x18,0x5a,0xf7
# ATT: vcvtpd2ps {rd-sae}, %ymm23, %xmm22 {%k7}
# INTEL: vcvtpd2ps xmm22 {k7}, ymm23, {rd-sae}
0x62,0xa1,0xf9,0x3f,0x5a,0xf7
# ATT: vcvtpd2ps {rz-sae}, %ymm23, %xmm22 {%k7} {z}
# INTEL: vcvtpd2ps xmm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa1,0xf9,0xff,0x5a,0xf7
# ATT: vcvtpd2qq {rn-sae}, %ymm23, %ymm22
# INTEL: vcvtpd2qq ymm22, ymm23, {rn-sae}
0x62,0xa1,0xf9,0x18,0x7b,0xf7
# ATT: vcvtpd2qq {rd-sae}, %ymm23, %ymm22 {%k7}
# INTEL: vcvtpd2qq ymm22 {k7}, ymm23, {rd-sae}
0x62,0xa1,0xf9,0x3f,0x7b,0xf7
# ATT: vcvtpd2qq {rz-sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vcvtpd2qq ymm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa1,0xf9,0xff,0x7b,0xf7
# ATT: vcvtpd2udq {rn-sae}, %ymm23, %xmm22
# INTEL: vcvtpd2udq xmm22, ymm23, {rn-sae}
0x62,0xa1,0xf8,0x18,0x79,0xf7
# ATT: vcvtpd2udq {rd-sae}, %ymm23, %xmm22 {%k7}
# INTEL: vcvtpd2udq xmm22 {k7}, ymm23, {rd-sae}
0x62,0xa1,0xf8,0x3f,0x79,0xf7
# ATT: vcvtpd2udq {rz-sae}, %ymm23, %xmm22 {%k7} {z}
# INTEL: vcvtpd2udq xmm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa1,0xf8,0xff,0x79,0xf7
# ATT: vcvtpd2uqq {rn-sae}, %ymm23, %ymm22
# INTEL: vcvtpd2uqq ymm22, ymm23, {rn-sae}
0x62,0xa1,0xf9,0x18,0x79,0xf7
# ATT: vcvtpd2uqq {rd-sae}, %ymm23, %ymm22 {%k7}
# INTEL: vcvtpd2uqq ymm22 {k7}, ymm23, {rd-sae}
0x62,0xa1,0xf9,0x3f,0x79,0xf7
# ATT: vcvtpd2uqq {rz-sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vcvtpd2uqq ymm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa1,0xf9,0xff,0x79,0xf7
# ATT: vcvtph2dq {rn-sae}, %xmm23, %ymm22
# INTEL: vcvtph2dq ymm22, xmm23, {rn-sae}
0x62,0xa5,0x79,0x18,0x5b,0xf7
# ATT: vcvtph2dq {rd-sae}, %xmm23, %ymm22 {%k7}
# INTEL: vcvtph2dq ymm22 {k7}, xmm23, {rd-sae}
0x62,0xa5,0x79,0x3f,0x5b,0xf7
# ATT: vcvtph2dq {rz-sae}, %xmm23, %ymm22 {%k7} {z}
# INTEL: vcvtph2dq ymm22 {k7} {z}, xmm23, {rz-sae}
0x62,0xa5,0x79,0xff,0x5b,0xf7
# ATT: vcvtph2pd {sae}, %xmm23, %ymm22
# INTEL: vcvtph2pd ymm22, xmm23, {sae}
0x62,0xa5,0x78,0x18,0x5a,0xf7
# ATT: vcvtph2pd {sae}, %xmm23, %ymm22 {%k7}
# INTEL: vcvtph2pd ymm22 {k7}, xmm23, {sae}
0x62,0xa5,0x78,0x1f,0x5a,0xf7
# ATT: vcvtph2pd {sae}, %xmm23, %ymm22 {%k7} {z}
# INTEL: vcvtph2pd ymm22 {k7} {z}, xmm23, {sae}
0x62,0xa5,0x78,0x9f,0x5a,0xf7
# ATT: vcvtph2ps {sae}, %xmm23, %ymm22
# INTEL: vcvtph2ps ymm22, xmm23, {sae}
0x62,0xa2,0x79,0x18,0x13,0xf7
# ATT: vcvtph2ps {sae}, %xmm23, %ymm22 {%k7}
# INTEL: vcvtph2ps ymm22 {k7}, xmm23, {sae}
0x62,0xa2,0x79,0x1f,0x13,0xf7
# ATT: vcvtph2ps {sae}, %xmm23, %ymm22 {%k7} {z}
# INTEL: vcvtph2ps ymm22 {k7} {z}, xmm23, {sae}
0x62,0xa2,0x79,0x9f,0x13,0xf7
# ATT: vcvtph2psx {sae}, %xmm23, %ymm22
# INTEL: vcvtph2psx ymm22, xmm23, {sae}
0x62,0xa6,0x79,0x18,0x13,0xf7
# ATT: vcvtph2psx {sae}, %xmm23, %ymm22 {%k7}
# INTEL: vcvtph2psx ymm22 {k7}, xmm23, {sae}
0x62,0xa6,0x79,0x1f,0x13,0xf7
# ATT: vcvtph2psx {sae}, %xmm23, %ymm22 {%k7} {z}
# INTEL: vcvtph2psx ymm22 {k7} {z}, xmm23, {sae}
0x62,0xa6,0x79,0x9f,0x13,0xf7
# ATT: vcvtph2qq {rn-sae}, %xmm23, %ymm22
# INTEL: vcvtph2qq ymm22, xmm23, {rn-sae}
0x62,0xa5,0x79,0x18,0x7b,0xf7
# ATT: vcvtph2qq {rd-sae}, %xmm23, %ymm22 {%k7}
# INTEL: vcvtph2qq ymm22 {k7}, xmm23, {rd-sae}
0x62,0xa5,0x79,0x3f,0x7b,0xf7
# ATT: vcvtph2qq {rz-sae}, %xmm23, %ymm22 {%k7} {z}
# INTEL: vcvtph2qq ymm22 {k7} {z}, xmm23, {rz-sae}
0x62,0xa5,0x79,0xff,0x7b,0xf7
# ATT: vcvtph2udq {rn-sae}, %xmm23, %ymm22
# INTEL: vcvtph2udq ymm22, xmm23, {rn-sae}
0x62,0xa5,0x78,0x18,0x79,0xf7
# ATT: vcvtph2udq {rd-sae}, %xmm23, %ymm22 {%k7}
# INTEL: vcvtph2udq ymm22 {k7}, xmm23, {rd-sae}
0x62,0xa5,0x78,0x3f,0x79,0xf7
# ATT: vcvtph2udq {rz-sae}, %xmm23, %ymm22 {%k7} {z}
# INTEL: vcvtph2udq ymm22 {k7} {z}, xmm23, {rz-sae}
0x62,0xa5,0x78,0xff,0x79,0xf7
# ATT: vcvtph2uqq {rn-sae}, %xmm23, %ymm22
# INTEL: vcvtph2uqq ymm22, xmm23, {rn-sae}
0x62,0xa5,0x79,0x18,0x79,0xf7
# ATT: vcvtph2uqq {rd-sae}, %xmm23, %ymm22 {%k7}
# INTEL: vcvtph2uqq ymm22 {k7}, xmm23, {rd-sae}
0x62,0xa5,0x79,0x3f,0x79,0xf7
# ATT: vcvtph2uqq {rz-sae}, %xmm23, %ymm22 {%k7} {z}
# INTEL: vcvtph2uqq ymm22 {k7} {z}, xmm23, {rz-sae}
0x62,0xa5,0x79,0xff,0x79,0xf7
# ATT: vcvtph2uw {rn-sae}, %ymm23, %ymm22
# INTEL: vcvtph2uw ymm22, ymm23, {rn-sae}
0x62,0xa5,0x78,0x18,0x7d,0xf7
# ATT: vcvtph2uw {rd-sae}, %ymm23, %ymm22 {%k7}
# INTEL: vcvtph2uw ymm22 {k7}, ymm23, {rd-sae}
0x62,0xa5,0x78,0x3f,0x7d,0xf7
# ATT: vcvtph2uw {rz-sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vcvtph2uw ymm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa5,0x78,0xff,0x7d,0xf7
# ATT: vcvtph2w {rn-sae}, %ymm23, %ymm22
# INTEL: vcvtph2w ymm22, ymm23, {rn-sae}
0x62,0xa5,0x79,0x18,0x7d,0xf7
# ATT: vcvtph2w {rd-sae}, %ymm23, %ymm22 {%k7}
# INTEL: vcvtph2w ymm22 {k7}, ymm23, {rd-sae}
0x62,0xa5,0x79,0x3f,0x7d,0xf7
# ATT: vcvtph2w {rz-sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vcvtph2w ymm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa5,0x79,0xff,0x7d,0xf7
# ATT: vcvtps2dq {rn-sae}, %ymm23, %ymm22
# INTEL: vcvtps2dq ymm22, ymm23, {rn-sae}
0x62,0xa1,0x79,0x18,0x5b,0xf7
# ATT: vcvtps2dq {rd-sae}, %ymm23, %ymm22 {%k7}
# INTEL: vcvtps2dq ymm22 {k7}, ymm23, {rd-sae}
0x62,0xa1,0x79,0x3f,0x5b,0xf7
# ATT: vcvtps2dq {rz-sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vcvtps2dq ymm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa1,0x79,0xff,0x5b,0xf7
# ATT: vcvtps2pd {sae}, %xmm23, %ymm22
# INTEL: vcvtps2pd ymm22, xmm23, {sae}
0x62,0xa1,0x78,0x18,0x5a,0xf7
# ATT: vcvtps2pd {sae}, %xmm23, %ymm22 {%k7}
# INTEL: vcvtps2pd ymm22 {k7}, xmm23, {sae}
0x62,0xa1,0x78,0x1f,0x5a,0xf7
# ATT: vcvtps2pd {sae}, %xmm23, %ymm22 {%k7} {z}
# INTEL: vcvtps2pd ymm22 {k7} {z}, xmm23, {sae}
0x62,0xa1,0x78,0x9f,0x5a,0xf7
# ATT: vcvtps2ph $123, {sae}, %ymm23, %xmm22
# INTEL: vcvtps2ph xmm22, ymm23, {sae}, 123
0x62,0xa3,0x79,0x18,0x1d,0xfe,0x7b
# ATT: vcvtps2ph $123, {sae}, %ymm23, %xmm22 {%k7}
# INTEL: vcvtps2ph xmm22 {k7}, ymm23, {sae}, 123
0x62,0xa3,0x79,0x1f,0x1d,0xfe,0x7b
# ATT: vcvtps2ph $123, {sae}, %ymm23, %xmm22 {%k7} {z}
# INTEL: vcvtps2ph xmm22 {k7} {z}, ymm23, {sae}, 123
0x62,0xa3,0x79,0x9f,0x1d,0xfe,0x7b
# ATT: vcvtps2phx {rn-sae}, %ymm23, %xmm22
# INTEL: vcvtps2phx xmm22, ymm23, {rn-sae}
0x62,0xa5,0x79,0x18,0x1d,0xf7
# ATT: vcvtps2phx {rd-sae}, %ymm23, %xmm22 {%k7}
# INTEL: vcvtps2phx xmm22 {k7}, ymm23, {rd-sae}
0x62,0xa5,0x79,0x3f,0x1d,0xf7
# ATT: vcvtps2phx {rz-sae}, %ymm23, %xmm22 {%k7} {z}
# INTEL: vcvtps2phx xmm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa5,0x79,0xff,0x1d,0xf7
# ATT: vcvtps2qq {rn-sae}, %xmm23, %ymm22
# INTEL: vcvtps2qq ymm22, xmm23, {rn-sae}
0x62,0xa1,0x79,0x18,0x7b,0xf7
# ATT: vcvtps2qq {rd-sae}, %xmm23, %ymm22 {%k7}
# INTEL: vcvtps2qq ymm22 {k7}, xmm23, {rd-sae}
0x62,0xa1,0x79,0x3f,0x7b,0xf7
# ATT: vcvtps2qq {rz-sae}, %xmm23, %ymm22 {%k7} {z}
# INTEL: vcvtps2qq ymm22 {k7} {z}, xmm23, {rz-sae}
0x62,0xa1,0x79,0xff,0x7b,0xf7
# ATT: vcvtps2udq {rn-sae}, %ymm23, %ymm22
# INTEL: vcvtps2udq ymm22, ymm23, {rn-sae}
0x62,0xa1,0x78,0x18,0x79,0xf7
# ATT: vcvtps2udq {rd-sae}, %ymm23, %ymm22 {%k7}
# INTEL: vcvtps2udq ymm22 {k7}, ymm23, {rd-sae}
0x62,0xa1,0x78,0x3f,0x79,0xf7
# ATT: vcvtps2udq {rz-sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vcvtps2udq ymm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa1,0x78,0xff,0x79,0xf7
# ATT: vcvtps2uqq {rn-sae}, %xmm23, %ymm22
# INTEL: vcvtps2uqq ymm22, xmm23, {rn-sae}
0x62,0xa1,0x79,0x18,0x79,0xf7
# ATT: vcvtps2uqq {rd-sae}, %xmm23, %ymm22 {%k7}
# INTEL: vcvtps2uqq ymm22 {k7}, xmm23, {rd-sae}
0x62,0xa1,0x79,0x3f,0x79,0xf7
# ATT: vcvtps2uqq {rz-sae}, %xmm23, %ymm22 {%k7} {z}
# INTEL: vcvtps2uqq ymm22 {k7} {z}, xmm23, {rz-sae}
0x62,0xa1,0x79,0xff,0x79,0xf7
# ATT: vcvtqq2pd {rn-sae}, %ymm23, %ymm22
# INTEL: vcvtqq2pd ymm22, ymm23, {rn-sae}
0x62,0xa1,0xfa,0x18,0xe6,0xf7
# ATT: vcvtqq2pd {rd-sae}, %ymm23, %ymm22 {%k7}
# INTEL: vcvtqq2pd ymm22 {k7}, ymm23, {rd-sae}
0x62,0xa1,0xfa,0x3f,0xe6,0xf7
# ATT: vcvtqq2pd {rz-sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vcvtqq2pd ymm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa1,0xfa,0xff,0xe6,0xf7
# ATT: vcvtqq2ph {rn-sae}, %ymm23, %xmm22
# INTEL: vcvtqq2ph xmm22, ymm23, {rn-sae}
0x62,0xa5,0xf8,0x18,0x5b,0xf7
# ATT: vcvtqq2ph {rd-sae}, %ymm23, %xmm22 {%k7}
# INTEL: vcvtqq2ph xmm22 {k7}, ymm23, {rd-sae}
0x62,0xa5,0xf8,0x3f,0x5b,0xf7
# ATT: vcvtqq2ph {rz-sae}, %ymm23, %xmm22 {%k7} {z}
# INTEL: vcvtqq2ph xmm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa5,0xf8,0xff,0x5b,0xf7
# ATT: vcvtqq2ps {rn-sae}, %ymm23, %xmm22
# INTEL: vcvtqq2ps xmm22, ymm23, {rn-sae}
0x62,0xa1,0xf8,0x18,0x5b,0xf7
# ATT: vcvtqq2ps {rd-sae}, %ymm23, %xmm22 {%k7}
# INTEL: vcvtqq2ps xmm22 {k7}, ymm23, {rd-sae}
0x62,0xa1,0xf8,0x3f,0x5b,0xf7
# ATT: vcvtqq2ps {rz-sae}, %ymm23, %xmm22 {%k7} {z}
# INTEL: vcvtqq2ps xmm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa1,0xf8,0xff,0x5b,0xf7
# ATT: vcvttpd2dq {sae}, %ymm23, %xmm22
# INTEL: vcvttpd2dq xmm22, ymm23, {sae}
0x62,0xa1,0xf9,0x18,0xe6,0xf7
# ATT: vcvttpd2dq {sae}, %ymm23, %xmm22 {%k7}
# INTEL: vcvttpd2dq xmm22 {k7}, ymm23, {sae}
0x62,0xa1,0xf9,0x1f,0xe6,0xf7
# ATT: vcvttpd2dq {sae}, %ymm23, %xmm22 {%k7} {z}
# INTEL: vcvttpd2dq xmm22 {k7} {z}, ymm23, {sae}
0x62,0xa1,0xf9,0x9f,0xe6,0xf7
# ATT: vcvttpd2qq {sae}, %ymm23, %ymm22
# INTEL: vcvttpd2qq ymm22, ymm23, {sae}
0x62,0xa1,0xf9,0x18,0x7a,0xf7
# ATT: vcvttpd2qq {sae}, %ymm23, %ymm22 {%k7}
# INTEL: vcvttpd2qq ymm22 {k7}, ymm23, {sae}
0x62,0xa1,0xf9,0x1f,0x7a,0xf7
# ATT: vcvttpd2qq {sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vcvttpd2qq ymm22 {k7} {z}, ymm23, {sae}
0x62,0xa1,0xf9,0x9f,0x7a,0xf7
# ATT: vcvttpd2udq {sae}, %ymm23, %xmm22
# INTEL: vcvttpd2udq xmm22, ymm23, {sae}
0x62,0xa1,0xf8,0x18,0x78,0xf7
# ATT: vcvttpd2udq {sae}, %ymm23, %xmm22 {%k7}
# INTEL: vcvttpd2udq xmm22 {k7}, ymm23, {sae}
0x62,0xa1,0xf8,0x1f,0x78,0xf7
# ATT: vcvttpd2udq {sae}, %ymm23, %xmm22 {%k7} {z}
# INTEL: vcvttpd2udq xmm22 {k7} {z}, ymm23, {sae}
0x62,0xa1,0xf8,0x9f,0x78,0xf7
# ATT: vcvttpd2uqq {sae}, %ymm23, %ymm22
# INTEL: vcvttpd2uqq ymm22, ymm23, {sae}
0x62,0xa1,0xf9,0x18,0x78,0xf7
# ATT: vcvttpd2uqq {sae}, %ymm23, %ymm22 {%k7}
# INTEL: vcvttpd2uqq ymm22 {k7}, ymm23, {sae}
0x62,0xa1,0xf9,0x1f,0x78,0xf7
# ATT: vcvttpd2uqq {sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vcvttpd2uqq ymm22 {k7} {z}, ymm23, {sae}
0x62,0xa1,0xf9,0x9f,0x78,0xf7
# ATT: vcvttph2dq {sae}, %xmm23, %ymm22
# INTEL: vcvttph2dq ymm22, xmm23, {sae}
0x62,0xa5,0x7a,0x18,0x5b,0xf7
# ATT: vcvttph2dq {sae}, %xmm23, %ymm22 {%k7}
# INTEL: vcvttph2dq ymm22 {k7}, xmm23, {sae}
0x62,0xa5,0x7a,0x1f,0x5b,0xf7
# ATT: vcvttph2dq {sae}, %xmm23, %ymm22 {%k7} {z}
# INTEL: vcvttph2dq ymm22 {k7} {z}, xmm23, {sae}
0x62,0xa5,0x7a,0x9f,0x5b,0xf7
# ATT: vcvttph2qq {sae}, %xmm23, %ymm22
# INTEL: vcvttph2qq ymm22, xmm23, {sae}
0x62,0xa5,0x79,0x18,0x7a,0xf7
# ATT: vcvttph2qq {sae}, %xmm23, %ymm22 {%k7}
# INTEL: vcvttph2qq ymm22 {k7}, xmm23, {sae}
0x62,0xa5,0x79,0x1f,0x7a,0xf7
# ATT: vcvttph2qq {sae}, %xmm23, %ymm22 {%k7} {z}
# INTEL: vcvttph2qq ymm22 {k7} {z}, xmm23, {sae}
0x62,0xa5,0x79,0x9f,0x7a,0xf7
# ATT: vcvttph2udq {sae}, %xmm23, %ymm22
# INTEL: vcvttph2udq ymm22, xmm23, {sae}
0x62,0xa5,0x78,0x18,0x78,0xf7
# ATT: vcvttph2udq {sae}, %xmm23, %ymm22 {%k7}
# INTEL: vcvttph2udq ymm22 {k7}, xmm23, {sae}
0x62,0xa5,0x78,0x1f,0x78,0xf7
# ATT: vcvttph2udq {sae}, %xmm23, %ymm22 {%k7} {z}
# INTEL: vcvttph2udq ymm22 {k7} {z}, xmm23, {sae}
0x62,0xa5,0x78,0x9f,0x78,0xf7
# ATT: vcvttph2uqq {sae}, %xmm23, %ymm22
# INTEL: vcvttph2uqq ymm22, xmm23, {sae}
0x62,0xa5,0x79,0x18,0x78,0xf7
# ATT: vcvttph2uqq {sae}, %xmm23, %ymm22 {%k7}
# INTEL: vcvttph2uqq ymm22 {k7}, xmm23, {sae}
0x62,0xa5,0x79,0x1f,0x78,0xf7
# ATT: vcvttph2uqq {sae}, %xmm23, %ymm22 {%k7} {z}
# INTEL: vcvttph2uqq ymm22 {k7} {z}, xmm23, {sae}
0x62,0xa5,0x79,0x9f,0x78,0xf7
# ATT: vcvttph2uw {sae}, %ymm23, %ymm22
# INTEL: vcvttph2uw ymm22, ymm23, {sae}
0x62,0xa5,0x78,0x18,0x7c,0xf7
# ATT: vcvttph2uw {sae}, %ymm23, %ymm22 {%k7}
# INTEL: vcvttph2uw ymm22 {k7}, ymm23, {sae}
0x62,0xa5,0x78,0x1f,0x7c,0xf7
# ATT: vcvttph2uw {sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vcvttph2uw ymm22 {k7} {z}, ymm23, {sae}
0x62,0xa5,0x78,0x9f,0x7c,0xf7
# ATT: vcvttph2w {sae}, %ymm23, %ymm22
# INTEL: vcvttph2w ymm22, ymm23, {sae}
0x62,0xa5,0x79,0x18,0x7c,0xf7
# ATT: vcvttph2w {sae}, %ymm23, %ymm22 {%k7}
# INTEL: vcvttph2w ymm22 {k7}, ymm23, {sae}
0x62,0xa5,0x79,0x1f,0x7c,0xf7
# ATT: vcvttph2w {sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vcvttph2w ymm22 {k7} {z}, ymm23, {sae}
0x62,0xa5,0x79,0x9f,0x7c,0xf7
# ATT: vcvttps2dq {sae}, %ymm23, %ymm22
# INTEL: vcvttps2dq ymm22, ymm23, {sae}
0x62,0xa1,0x7a,0x18,0x5b,0xf7
# ATT: vcvttps2dq {sae}, %ymm23, %ymm22 {%k7}
# INTEL: vcvttps2dq ymm22 {k7}, ymm23, {sae}
0x62,0xa1,0x7a,0x1f,0x5b,0xf7
# ATT: vcvttps2dq {sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vcvttps2dq ymm22 {k7} {z}, ymm23, {sae}
0x62,0xa1,0x7a,0x9f,0x5b,0xf7
# ATT: vcvttps2qq {sae}, %xmm23, %ymm22
# INTEL: vcvttps2qq ymm22, xmm23, {sae}
0x62,0xa1,0x79,0x18,0x7a,0xf7
# ATT: vcvttps2qq {sae}, %xmm23, %ymm22 {%k7}
# INTEL: vcvttps2qq ymm22 {k7}, xmm23, {sae}
0x62,0xa1,0x79,0x1f,0x7a,0xf7
# ATT: vcvttps2qq {sae}, %xmm23, %ymm22 {%k7} {z}
# INTEL: vcvttps2qq ymm22 {k7} {z}, xmm23, {sae}
0x62,0xa1,0x79,0x9f,0x7a,0xf7
# ATT: vcvttps2udq {sae}, %ymm23, %ymm22
# INTEL: vcvttps2udq ymm22, ymm23, {sae}
0x62,0xa1,0x78,0x18,0x78,0xf7
# ATT: vcvttps2udq {sae}, %ymm23, %ymm22 {%k7}
# INTEL: vcvttps2udq ymm22 {k7}, ymm23, {sae}
0x62,0xa1,0x78,0x1f,0x78,0xf7
# ATT: vcvttps2udq {sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vcvttps2udq ymm22 {k7} {z}, ymm23, {sae}
0x62,0xa1,0x78,0x9f,0x78,0xf7
# ATT: vcvttps2uqq {sae}, %xmm23, %ymm22
# INTEL: vcvttps2uqq ymm22, xmm23, {sae}
0x62,0xa1,0x79,0x18,0x78,0xf7
# ATT: vcvttps2uqq {sae}, %xmm23, %ymm22 {%k7}
# INTEL: vcvttps2uqq ymm22 {k7}, xmm23, {sae}
0x62,0xa1,0x79,0x1f,0x78,0xf7
# ATT: vcvttps2uqq {sae}, %xmm23, %ymm22 {%k7} {z}
# INTEL: vcvttps2uqq ymm22 {k7} {z}, xmm23, {sae}
0x62,0xa1,0x79,0x9f,0x78,0xf7
# ATT: vcvtudq2ph {rn-sae}, %ymm23, %xmm22
# INTEL: vcvtudq2ph xmm22, ymm23, {rn-sae}
0x62,0xa5,0x7b,0x18,0x7a,0xf7
# ATT: vcvtudq2ph {rd-sae}, %ymm23, %xmm22 {%k7}
# INTEL: vcvtudq2ph xmm22 {k7}, ymm23, {rd-sae}
0x62,0xa5,0x7b,0x3f,0x7a,0xf7
# ATT: vcvtudq2ph {rz-sae}, %ymm23, %xmm22 {%k7} {z}
# INTEL: vcvtudq2ph xmm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa5,0x7b,0xff,0x7a,0xf7
# ATT: vcvtudq2ps {rn-sae}, %ymm23, %ymm22
# INTEL: vcvtudq2ps ymm22, ymm23, {rn-sae}
0x62,0xa1,0x7b,0x18,0x7a,0xf7
# ATT: vcvtudq2ps {rd-sae}, %ymm23, %ymm22 {%k7}
# INTEL: vcvtudq2ps ymm22 {k7}, ymm23, {rd-sae}
0x62,0xa1,0x7b,0x3f,0x7a,0xf7
# ATT: vcvtudq2ps {rz-sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vcvtudq2ps ymm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa1,0x7b,0xff,0x7a,0xf7
# ATT: vcvtuqq2pd {rn-sae}, %ymm23, %ymm22
# INTEL: vcvtuqq2pd ymm22, ymm23, {rn-sae}
0x62,0xa1,0xfa,0x18,0x7a,0xf7
# ATT: vcvtuqq2pd {rd-sae}, %ymm23, %ymm22 {%k7}
# INTEL: vcvtuqq2pd ymm22 {k7}, ymm23, {rd-sae}
0x62,0xa1,0xfa,0x3f,0x7a,0xf7
# ATT: vcvtuqq2pd {rz-sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vcvtuqq2pd ymm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa1,0xfa,0xff,0x7a,0xf7
# ATT: vcvtuqq2ph {rn-sae}, %ymm23, %xmm22
# INTEL: vcvtuqq2ph xmm22, ymm23, {rn-sae}
0x62,0xa5,0xfb,0x18,0x7a,0xf7
# ATT: vcvtuqq2ph {rd-sae}, %ymm23, %xmm22 {%k7}
# INTEL: vcvtuqq2ph xmm22 {k7}, ymm23, {rd-sae}
0x62,0xa5,0xfb,0x3f,0x7a,0xf7
# ATT: vcvtuqq2ph {rz-sae}, %ymm23, %xmm22 {%k7} {z}
# INTEL: vcvtuqq2ph xmm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa5,0xfb,0xff,0x7a,0xf7
# ATT: vcvtuqq2ps {rn-sae}, %ymm23, %xmm22
# INTEL: vcvtuqq2ps xmm22, ymm23, {rn-sae}
0x62,0xa1,0xfb,0x18,0x7a,0xf7
# ATT: vcvtuqq2ps {rd-sae}, %ymm23, %xmm22 {%k7}
# INTEL: vcvtuqq2ps xmm22 {k7}, ymm23, {rd-sae}
0x62,0xa1,0xfb,0x3f,0x7a,0xf7
# ATT: vcvtuqq2ps {rz-sae}, %ymm23, %xmm22 {%k7} {z}
# INTEL: vcvtuqq2ps xmm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa1,0xfb,0xff,0x7a,0xf7
# ATT: vcvtuw2ph {rn-sae}, %ymm23, %ymm22
# INTEL: vcvtuw2ph ymm22, ymm23, {rn-sae}
0x62,0xa5,0x7b,0x18,0x7d,0xf7
# ATT: vcvtuw2ph {rd-sae}, %ymm23, %ymm22 {%k7}
# INTEL: vcvtuw2ph ymm22 {k7}, ymm23, {rd-sae}
0x62,0xa5,0x7b,0x3f,0x7d,0xf7
# ATT: vcvtuw2ph {rz-sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vcvtuw2ph ymm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa5,0x7b,0xff,0x7d,0xf7
# ATT: vcvtw2ph {rn-sae}, %ymm23, %ymm22
# INTEL: vcvtw2ph ymm22, ymm23, {rn-sae}
0x62,0xa5,0x7a,0x18,0x7d,0xf7
# ATT: vcvtw2ph {rd-sae}, %ymm23, %ymm22 {%k7}
# INTEL: vcvtw2ph ymm22 {k7}, ymm23, {rd-sae}
0x62,0xa5,0x7a,0x3f,0x7d,0xf7
# ATT: vcvtw2ph {rz-sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vcvtw2ph ymm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa5,0x7a,0xff,0x7d,0xf7
# ATT: vdivpd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vdivpd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x81,0xc1,0x10,0x5e,0xf0
# ATT: vdivpd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vdivpd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x81,0xc1,0x37,0x5e,0xf0
# ATT: vdivpd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vdivpd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x81,0xc1,0xf7,0x5e,0xf0
# ATT: vdivph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vdivph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x85,0x40,0x10,0x5e,0xf0
# ATT: vdivph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vdivph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x85,0x40,0x37,0x5e,0xf0
# ATT: vdivph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vdivph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x85,0x40,0xf7,0x5e,0xf0
# ATT: vdivps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vdivps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x81,0x40,0x10,0x5e,0xf0
# ATT: vdivps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vdivps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x81,0x40,0x37,0x5e,0xf0
# ATT: vdivps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vdivps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x81,0x40,0xf7,0x5e,0xf0
# ATT: vfcmaddcph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfcmaddcph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x43,0x10,0x56,0xf0
# ATT: vfcmaddcph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfcmaddcph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x43,0x37,0x56,0xf0
# ATT: vfcmaddcph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfcmaddcph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x43,0xf7,0x56,0xf0
# ATT: vfcmulcph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfcmulcph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x43,0x10,0xd6,0xf0
# ATT: vfcmulcph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfcmulcph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x43,0x37,0xd6,0xf0
# ATT: vfcmulcph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfcmulcph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x43,0xf7,0xd6,0xf0
# ATT: vfixupimmpd $123, {sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfixupimmpd ymm22, ymm23, ymm24, {sae}, 123
0x62,0x83,0xc1,0x10,0x54,0xf0,0x7b
# ATT: vfixupimmpd $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfixupimmpd ymm22 {k7}, ymm23, ymm24, {sae}, 123
0x62,0x83,0xc1,0x17,0x54,0xf0,0x7b
# ATT: vfixupimmpd $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfixupimmpd ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123
0x62,0x83,0xc1,0x97,0x54,0xf0,0x7b
# ATT: vfixupimmps $123, {sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfixupimmps ymm22, ymm23, ymm24, {sae}, 123
0x62,0x83,0x41,0x10,0x54,0xf0,0x7b
# ATT: vfixupimmps $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfixupimmps ymm22 {k7}, ymm23, ymm24, {sae}, 123
0x62,0x83,0x41,0x17,0x54,0xf0,0x7b
# ATT: vfixupimmps $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfixupimmps ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123
0x62,0x83,0x41,0x97,0x54,0xf0,0x7b
# ATT: vfmadd132pd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmadd132pd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0xc1,0x10,0x98,0xf0
# ATT: vfmadd132pd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmadd132pd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0xc1,0x37,0x98,0xf0
# ATT: vfmadd132pd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmadd132pd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0xc1,0xf7,0x98,0xf0
# ATT: vfmadd132ph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmadd132ph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x41,0x10,0x98,0xf0
# ATT: vfmadd132ph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmadd132ph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x41,0x37,0x98,0xf0
# ATT: vfmadd132ph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmadd132ph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x41,0xf7,0x98,0xf0
# ATT: vfmadd132ps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmadd132ps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0x41,0x10,0x98,0xf0
# ATT: vfmadd132ps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmadd132ps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0x41,0x37,0x98,0xf0
# ATT: vfmadd132ps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmadd132ps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0x41,0xf7,0x98,0xf0
# ATT: vfmadd213pd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmadd213pd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0xc1,0x10,0xa8,0xf0
# ATT: vfmadd213pd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmadd213pd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0xc1,0x37,0xa8,0xf0
# ATT: vfmadd213pd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmadd213pd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0xc1,0xf7,0xa8,0xf0
# ATT: vfmadd213ph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmadd213ph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x41,0x10,0xa8,0xf0
# ATT: vfmadd213ph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmadd213ph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x41,0x37,0xa8,0xf0
# ATT: vfmadd213ph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmadd213ph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x41,0xf7,0xa8,0xf0
# ATT: vfmadd213ps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmadd213ps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0x41,0x10,0xa8,0xf0
# ATT: vfmadd213ps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmadd213ps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0x41,0x37,0xa8,0xf0
# ATT: vfmadd213ps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmadd213ps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0x41,0xf7,0xa8,0xf0
# ATT: vfmadd231pd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmadd231pd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0xc1,0x10,0xb8,0xf0
# ATT: vfmadd231pd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmadd231pd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0xc1,0x37,0xb8,0xf0
# ATT: vfmadd231pd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmadd231pd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0xc1,0xf7,0xb8,0xf0
# ATT: vfmadd231ph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmadd231ph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x41,0x10,0xb8,0xf0
# ATT: vfmadd231ph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmadd231ph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x41,0x37,0xb8,0xf0
# ATT: vfmadd231ph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmadd231ph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x41,0xf7,0xb8,0xf0
# ATT: vfmadd231ps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmadd231ps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0x41,0x10,0xb8,0xf0
# ATT: vfmadd231ps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmadd231ps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0x41,0x37,0xb8,0xf0
# ATT: vfmadd231ps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmadd231ps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0x41,0xf7,0xb8,0xf0
# ATT: vfmaddcph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmaddcph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x42,0x10,0x56,0xf0
# ATT: vfmaddcph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmaddcph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x42,0x37,0x56,0xf0
# ATT: vfmaddcph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmaddcph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x42,0xf7,0x56,0xf0
# ATT: vfmaddsub132pd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmaddsub132pd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0xc1,0x10,0x96,0xf0
# ATT: vfmaddsub132pd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmaddsub132pd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0xc1,0x37,0x96,0xf0
# ATT: vfmaddsub132pd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmaddsub132pd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0xc1,0xf7,0x96,0xf0
# ATT: vfmaddsub132ph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmaddsub132ph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x41,0x10,0x96,0xf0
# ATT: vfmaddsub132ph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmaddsub132ph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x41,0x37,0x96,0xf0
# ATT: vfmaddsub132ph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmaddsub132ph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x41,0xf7,0x96,0xf0
# ATT: vfmaddsub132ps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmaddsub132ps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0x41,0x10,0x96,0xf0
# ATT: vfmaddsub132ps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmaddsub132ps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0x41,0x37,0x96,0xf0
# ATT: vfmaddsub132ps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmaddsub132ps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0x41,0xf7,0x96,0xf0
# ATT: vfmaddsub213pd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmaddsub213pd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0xc1,0x10,0xa6,0xf0
# ATT: vfmaddsub213pd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmaddsub213pd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0xc1,0x37,0xa6,0xf0
# ATT: vfmaddsub213pd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmaddsub213pd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0xc1,0xf7,0xa6,0xf0
# ATT: vfmaddsub213ph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmaddsub213ph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x41,0x10,0xa6,0xf0
# ATT: vfmaddsub213ph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmaddsub213ph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x41,0x37,0xa6,0xf0
# ATT: vfmaddsub213ph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmaddsub213ph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x41,0xf7,0xa6,0xf0
# ATT: vfmaddsub213ps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmaddsub213ps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0x41,0x10,0xa6,0xf0
# ATT: vfmaddsub213ps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmaddsub213ps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0x41,0x37,0xa6,0xf0
# ATT: vfmaddsub213ps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmaddsub213ps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0x41,0xf7,0xa6,0xf0
# ATT: vfmaddsub231pd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmaddsub231pd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0xc1,0x10,0xb6,0xf0
# ATT: vfmaddsub231pd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmaddsub231pd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0xc1,0x37,0xb6,0xf0
# ATT: vfmaddsub231pd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmaddsub231pd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0xc1,0xf7,0xb6,0xf0
# ATT: vfmaddsub231ph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmaddsub231ph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x41,0x10,0xb6,0xf0
# ATT: vfmaddsub231ph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmaddsub231ph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x41,0x37,0xb6,0xf0
# ATT: vfmaddsub231ph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmaddsub231ph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x41,0xf7,0xb6,0xf0
# ATT: vfmaddsub231ps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmaddsub231ps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0x41,0x10,0xb6,0xf0
# ATT: vfmaddsub231ps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmaddsub231ps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0x41,0x37,0xb6,0xf0
# ATT: vfmaddsub231ps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmaddsub231ps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0x41,0xf7,0xb6,0xf0
# ATT: vfmsub132pd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmsub132pd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0xc1,0x10,0x9a,0xf0
# ATT: vfmsub132pd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmsub132pd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0xc1,0x37,0x9a,0xf0
# ATT: vfmsub132pd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmsub132pd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0xc1,0xf7,0x9a,0xf0
# ATT: vfmsub132ph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmsub132ph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x41,0x10,0x9a,0xf0
# ATT: vfmsub132ph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmsub132ph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x41,0x37,0x9a,0xf0
# ATT: vfmsub132ph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmsub132ph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x41,0xf7,0x9a,0xf0
# ATT: vfmsub132ps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmsub132ps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0x41,0x10,0x9a,0xf0
# ATT: vfmsub132ps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmsub132ps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0x41,0x37,0x9a,0xf0
# ATT: vfmsub132ps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmsub132ps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0x41,0xf7,0x9a,0xf0
# ATT: vfmsub213pd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmsub213pd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0xc1,0x10,0xaa,0xf0
# ATT: vfmsub213pd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmsub213pd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0xc1,0x37,0xaa,0xf0
# ATT: vfmsub213pd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmsub213pd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0xc1,0xf7,0xaa,0xf0
# ATT: vfmsub213ph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmsub213ph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x41,0x10,0xaa,0xf0
# ATT: vfmsub213ph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmsub213ph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x41,0x37,0xaa,0xf0
# ATT: vfmsub213ph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmsub213ph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x41,0xf7,0xaa,0xf0
# ATT: vfmsub213ps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmsub213ps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0x41,0x10,0xaa,0xf0
# ATT: vfmsub213ps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmsub213ps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0x41,0x37,0xaa,0xf0
# ATT: vfmsub213ps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmsub213ps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0x41,0xf7,0xaa,0xf0
# ATT: vfmsub231pd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmsub231pd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0xc1,0x10,0xba,0xf0
# ATT: vfmsub231pd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmsub231pd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0xc1,0x37,0xba,0xf0
# ATT: vfmsub231pd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmsub231pd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0xc1,0xf7,0xba,0xf0
# ATT: vfmsub231ph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmsub231ph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x41,0x10,0xba,0xf0
# ATT: vfmsub231ph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmsub231ph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x41,0x37,0xba,0xf0
# ATT: vfmsub231ph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmsub231ph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x41,0xf7,0xba,0xf0
# ATT: vfmsub231ps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmsub231ps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0x41,0x10,0xba,0xf0
# ATT: vfmsub231ps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmsub231ps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0x41,0x37,0xba,0xf0
# ATT: vfmsub231ps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmsub231ps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0x41,0xf7,0xba,0xf0
# ATT: vfmsubadd132pd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmsubadd132pd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0xc1,0x10,0x97,0xf0
# ATT: vfmsubadd132pd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmsubadd132pd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0xc1,0x37,0x97,0xf0
# ATT: vfmsubadd132pd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmsubadd132pd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0xc1,0xf7,0x97,0xf0
# ATT: vfmsubadd132ph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmsubadd132ph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x41,0x10,0x97,0xf0
# ATT: vfmsubadd132ph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmsubadd132ph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x41,0x37,0x97,0xf0
# ATT: vfmsubadd132ph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmsubadd132ph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x41,0xf7,0x97,0xf0
# ATT: vfmsubadd132ps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmsubadd132ps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0x41,0x10,0x97,0xf0
# ATT: vfmsubadd132ps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmsubadd132ps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0x41,0x37,0x97,0xf0
# ATT: vfmsubadd132ps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmsubadd132ps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0x41,0xf7,0x97,0xf0
# ATT: vfmsubadd213pd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmsubadd213pd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0xc1,0x10,0xa7,0xf0
# ATT: vfmsubadd213pd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmsubadd213pd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0xc1,0x37,0xa7,0xf0
# ATT: vfmsubadd213pd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmsubadd213pd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0xc1,0xf7,0xa7,0xf0
# ATT: vfmsubadd213ph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmsubadd213ph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x41,0x10,0xa7,0xf0
# ATT: vfmsubadd213ph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmsubadd213ph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x41,0x37,0xa7,0xf0
# ATT: vfmsubadd213ph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmsubadd213ph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x41,0xf7,0xa7,0xf0
# ATT: vfmsubadd213ps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmsubadd213ps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0x41,0x10,0xa7,0xf0
# ATT: vfmsubadd213ps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmsubadd213ps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0x41,0x37,0xa7,0xf0
# ATT: vfmsubadd213ps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmsubadd213ps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0x41,0xf7,0xa7,0xf0
# ATT: vfmsubadd231pd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmsubadd231pd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0xc1,0x10,0xb7,0xf0
# ATT: vfmsubadd231pd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmsubadd231pd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0xc1,0x37,0xb7,0xf0
# ATT: vfmsubadd231pd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmsubadd231pd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0xc1,0xf7,0xb7,0xf0
# ATT: vfmsubadd231ph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmsubadd231ph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x41,0x10,0xb7,0xf0
# ATT: vfmsubadd231ph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmsubadd231ph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x41,0x37,0xb7,0xf0
# ATT: vfmsubadd231ph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmsubadd231ph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x41,0xf7,0xb7,0xf0
# ATT: vfmsubadd231ps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmsubadd231ps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0x41,0x10,0xb7,0xf0
# ATT: vfmsubadd231ps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmsubadd231ps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0x41,0x37,0xb7,0xf0
# ATT: vfmsubadd231ps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmsubadd231ps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0x41,0xf7,0xb7,0xf0
# ATT: vfmulcph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfmulcph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x42,0x10,0xd6,0xf0
# ATT: vfmulcph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfmulcph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x42,0x37,0xd6,0xf0
# ATT: vfmulcph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfmulcph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x42,0xf7,0xd6,0xf0
# ATT: vfnmadd132pd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfnmadd132pd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0xc1,0x10,0x9c,0xf0
# ATT: vfnmadd132pd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfnmadd132pd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0xc1,0x37,0x9c,0xf0
# ATT: vfnmadd132pd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfnmadd132pd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0xc1,0xf7,0x9c,0xf0
# ATT: vfnmadd132ph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfnmadd132ph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x41,0x10,0x9c,0xf0
# ATT: vfnmadd132ph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfnmadd132ph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x41,0x37,0x9c,0xf0
# ATT: vfnmadd132ph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfnmadd132ph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x41,0xf7,0x9c,0xf0
# ATT: vfnmadd132ps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfnmadd132ps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0x41,0x10,0x9c,0xf0
# ATT: vfnmadd132ps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfnmadd132ps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0x41,0x37,0x9c,0xf0
# ATT: vfnmadd132ps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfnmadd132ps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0x41,0xf7,0x9c,0xf0
# ATT: vfnmadd213pd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfnmadd213pd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0xc1,0x10,0xac,0xf0
# ATT: vfnmadd213pd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfnmadd213pd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0xc1,0x37,0xac,0xf0
# ATT: vfnmadd213pd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfnmadd213pd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0xc1,0xf7,0xac,0xf0
# ATT: vfnmadd213ph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfnmadd213ph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x41,0x10,0xac,0xf0
# ATT: vfnmadd213ph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfnmadd213ph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x41,0x37,0xac,0xf0
# ATT: vfnmadd213ph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfnmadd213ph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x41,0xf7,0xac,0xf0
# ATT: vfnmadd213ps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfnmadd213ps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0x41,0x10,0xac,0xf0
# ATT: vfnmadd213ps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfnmadd213ps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0x41,0x37,0xac,0xf0
# ATT: vfnmadd213ps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfnmadd213ps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0x41,0xf7,0xac,0xf0
# ATT: vfnmadd231pd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfnmadd231pd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0xc1,0x10,0xbc,0xf0
# ATT: vfnmadd231pd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfnmadd231pd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0xc1,0x37,0xbc,0xf0
# ATT: vfnmadd231pd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfnmadd231pd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0xc1,0xf7,0xbc,0xf0
# ATT: vfnmadd231ph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfnmadd231ph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x41,0x10,0xbc,0xf0
# ATT: vfnmadd231ph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfnmadd231ph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x41,0x37,0xbc,0xf0
# ATT: vfnmadd231ph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfnmadd231ph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x41,0xf7,0xbc,0xf0
# ATT: vfnmadd231ps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfnmadd231ps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0x41,0x10,0xbc,0xf0
# ATT: vfnmadd231ps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfnmadd231ps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0x41,0x37,0xbc,0xf0
# ATT: vfnmadd231ps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfnmadd231ps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0x41,0xf7,0xbc,0xf0
# ATT: vfnmsub132pd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfnmsub132pd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0xc1,0x10,0x9e,0xf0
# ATT: vfnmsub132pd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfnmsub132pd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0xc1,0x37,0x9e,0xf0
# ATT: vfnmsub132pd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfnmsub132pd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0xc1,0xf7,0x9e,0xf0
# ATT: vfnmsub132ph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfnmsub132ph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x41,0x10,0x9e,0xf0
# ATT: vfnmsub132ph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfnmsub132ph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x41,0x37,0x9e,0xf0
# ATT: vfnmsub132ph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfnmsub132ph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x41,0xf7,0x9e,0xf0
# ATT: vfnmsub132ps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfnmsub132ps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0x41,0x10,0x9e,0xf0
# ATT: vfnmsub132ps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfnmsub132ps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0x41,0x37,0x9e,0xf0
# ATT: vfnmsub132ps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfnmsub132ps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0x41,0xf7,0x9e,0xf0
# ATT: vfnmsub213pd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfnmsub213pd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0xc1,0x10,0xae,0xf0
# ATT: vfnmsub213pd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfnmsub213pd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0xc1,0x37,0xae,0xf0
# ATT: vfnmsub213pd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfnmsub213pd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0xc1,0xf7,0xae,0xf0
# ATT: vfnmsub213ph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfnmsub213ph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x41,0x10,0xae,0xf0
# ATT: vfnmsub213ph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfnmsub213ph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x41,0x37,0xae,0xf0
# ATT: vfnmsub213ph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfnmsub213ph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x41,0xf7,0xae,0xf0
# ATT: vfnmsub213ps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfnmsub213ps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0x41,0x10,0xae,0xf0
# ATT: vfnmsub213ps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfnmsub213ps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0x41,0x37,0xae,0xf0
# ATT: vfnmsub213ps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfnmsub213ps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0x41,0xf7,0xae,0xf0
# ATT: vfnmsub231pd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfnmsub231pd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0xc1,0x10,0xbe,0xf0
# ATT: vfnmsub231pd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfnmsub231pd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0xc1,0x37,0xbe,0xf0
# ATT: vfnmsub231pd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfnmsub231pd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0xc1,0xf7,0xbe,0xf0
# ATT: vfnmsub231ph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfnmsub231ph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x41,0x10,0xbe,0xf0
# ATT: vfnmsub231ph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfnmsub231ph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x41,0x37,0xbe,0xf0
# ATT: vfnmsub231ph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfnmsub231ph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x41,0xf7,0xbe,0xf0
# ATT: vfnmsub231ps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vfnmsub231ps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0x41,0x10,0xbe,0xf0
# ATT: vfnmsub231ps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vfnmsub231ps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0x41,0x37,0xbe,0xf0
# ATT: vfnmsub231ps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vfnmsub231ps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0x41,0xf7,0xbe,0xf0
# ATT: vgetexppd {sae}, %ymm23, %ymm22
# INTEL: vgetexppd ymm22, ymm23, {sae}
0x62,0xa2,0xf9,0x18,0x42,0xf7
# ATT: vgetexppd {sae}, %ymm23, %ymm22 {%k7}
# INTEL: vgetexppd ymm22 {k7}, ymm23, {sae}
0x62,0xa2,0xf9,0x1f,0x42,0xf7
# ATT: vgetexppd {sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vgetexppd ymm22 {k7} {z}, ymm23, {sae}
0x62,0xa2,0xf9,0x9f,0x42,0xf7
# ATT: vgetexpph {sae}, %ymm23, %ymm22
# INTEL: vgetexpph ymm22, ymm23, {sae}
0x62,0xa6,0x79,0x18,0x42,0xf7
# ATT: vgetexpph {sae}, %ymm23, %ymm22 {%k7}
# INTEL: vgetexpph ymm22 {k7}, ymm23, {sae}
0x62,0xa6,0x79,0x1f,0x42,0xf7
# ATT: vgetexpph {sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vgetexpph ymm22 {k7} {z}, ymm23, {sae}
0x62,0xa6,0x79,0x9f,0x42,0xf7
# ATT: vgetexpps {sae}, %ymm23, %ymm22
# INTEL: vgetexpps ymm22, ymm23, {sae}
0x62,0xa2,0x79,0x18,0x42,0xf7
# ATT: vgetexpps {sae}, %ymm23, %ymm22 {%k7}
# INTEL: vgetexpps ymm22 {k7}, ymm23, {sae}
0x62,0xa2,0x79,0x1f,0x42,0xf7
# ATT: vgetexpps {sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vgetexpps ymm22 {k7} {z}, ymm23, {sae}
0x62,0xa2,0x79,0x9f,0x42,0xf7
# ATT: vgetmantpd $123, {sae}, %ymm23, %ymm22
# INTEL: vgetmantpd ymm22, ymm23, {sae}, 123
0x62,0xa3,0xf9,0x18,0x26,0xf7,0x7b
# ATT: vgetmantpd $123, {sae}, %ymm23, %ymm22 {%k7}
# INTEL: vgetmantpd ymm22 {k7}, ymm23, {sae}, 123
0x62,0xa3,0xf9,0x1f,0x26,0xf7,0x7b
# ATT: vgetmantpd $123, {sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vgetmantpd ymm22 {k7} {z}, ymm23, {sae}, 123
0x62,0xa3,0xf9,0x9f,0x26,0xf7,0x7b
# ATT: vgetmantph $123, {sae}, %ymm23, %ymm22
# INTEL: vgetmantph ymm22, ymm23, {sae}, 123
0x62,0xa3,0x78,0x18,0x26,0xf7,0x7b
# ATT: vgetmantph $123, {sae}, %ymm23, %ymm22 {%k7}
# INTEL: vgetmantph ymm22 {k7}, ymm23, {sae}, 123
0x62,0xa3,0x78,0x1f,0x26,0xf7,0x7b
# ATT: vgetmantph $123, {sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vgetmantph ymm22 {k7} {z}, ymm23, {sae}, 123
0x62,0xa3,0x78,0x9f,0x26,0xf7,0x7b
# ATT: vgetmantps $123, {sae}, %ymm23, %ymm22
# INTEL: vgetmantps ymm22, ymm23, {sae}, 123
0x62,0xa3,0x79,0x18,0x26,0xf7,0x7b
# ATT: vgetmantps $123, {sae}, %ymm23, %ymm22 {%k7}
# INTEL: vgetmantps ymm22 {k7}, ymm23, {sae}, 123
0x62,0xa3,0x79,0x1f,0x26,0xf7,0x7b
# ATT: vgetmantps $123, {sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vgetmantps ymm22 {k7} {z}, ymm23, {sae}, 123
0x62,0xa3,0x79,0x9f,0x26,0xf7,0x7b
# ATT: vmaxpd {sae}, %ymm24, %ymm23, %ymm22
# INTEL: vmaxpd ymm22, ymm23, ymm24, {sae}
0x62,0x81,0xc1,0x10,0x5f,0xf0
# ATT: vmaxpd {sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vmaxpd ymm22 {k7}, ymm23, ymm24, {sae}
0x62,0x81,0xc1,0x17,0x5f,0xf0
# ATT: vmaxpd {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vmaxpd ymm22 {k7} {z}, ymm23, ymm24, {sae}
0x62,0x81,0xc1,0x97,0x5f,0xf0
# ATT: vmaxph {sae}, %ymm24, %ymm23, %ymm22
# INTEL: vmaxph ymm22, ymm23, ymm24, {sae}
0x62,0x85,0x40,0x10,0x5f,0xf0
# ATT: vmaxph {sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vmaxph ymm22 {k7}, ymm23, ymm24, {sae}
0x62,0x85,0x40,0x17,0x5f,0xf0
# ATT: vmaxph {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vmaxph ymm22 {k7} {z}, ymm23, ymm24, {sae}
0x62,0x85,0x40,0x97,0x5f,0xf0
# ATT: vmaxps {sae}, %ymm24, %ymm23, %ymm22
# INTEL: vmaxps ymm22, ymm23, ymm24, {sae}
0x62,0x81,0x40,0x10,0x5f,0xf0
# ATT: vmaxps {sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vmaxps ymm22 {k7}, ymm23, ymm24, {sae}
0x62,0x81,0x40,0x17,0x5f,0xf0
# ATT: vmaxps {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vmaxps ymm22 {k7} {z}, ymm23, ymm24, {sae}
0x62,0x81,0x40,0x97,0x5f,0xf0
# ATT: vminpd {sae}, %ymm24, %ymm23, %ymm22
# INTEL: vminpd ymm22, ymm23, ymm24, {sae}
0x62,0x81,0xc1,0x10,0x5d,0xf0
# ATT: vminpd {sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vminpd ymm22 {k7}, ymm23, ymm24, {sae}
0x62,0x81,0xc1,0x17,0x5d,0xf0
# ATT: vminpd {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vminpd ymm22 {k7} {z}, ymm23, ymm24, {sae}
0x62,0x81,0xc1,0x97,0x5d,0xf0
# ATT: vminph {sae}, %ymm24, %ymm23, %ymm22
# INTEL: vminph ymm22, ymm23, ymm24, {sae}
0x62,0x85,0x40,0x10,0x5d,0xf0
# ATT: vminph {sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vminph ymm22 {k7}, ymm23, ymm24, {sae}
0x62,0x85,0x40,0x17,0x5d,0xf0
# ATT: vminph {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vminph ymm22 {k7} {z}, ymm23, ymm24, {sae}
0x62,0x85,0x40,0x97,0x5d,0xf0
# ATT: vminps {sae}, %ymm24, %ymm23, %ymm22
# INTEL: vminps ymm22, ymm23, ymm24, {sae}
0x62,0x81,0x40,0x10,0x5d,0xf0
# ATT: vminps {sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vminps ymm22 {k7}, ymm23, ymm24, {sae}
0x62,0x81,0x40,0x17,0x5d,0xf0
# ATT: vminps {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vminps ymm22 {k7} {z}, ymm23, ymm24, {sae}
0x62,0x81,0x40,0x97,0x5d,0xf0
# ATT: vmulpd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vmulpd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x81,0xc1,0x10,0x59,0xf0
# ATT: vmulpd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vmulpd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x81,0xc1,0x37,0x59,0xf0
# ATT: vmulpd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vmulpd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x81,0xc1,0xf7,0x59,0xf0
# ATT: vmulph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vmulph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x85,0x40,0x10,0x59,0xf0
# ATT: vmulph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vmulph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x85,0x40,0x37,0x59,0xf0
# ATT: vmulph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vmulph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x85,0x40,0xf7,0x59,0xf0
# ATT: vmulps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vmulps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x81,0x40,0x10,0x59,0xf0
# ATT: vmulps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vmulps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x81,0x40,0x37,0x59,0xf0
# ATT: vmulps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vmulps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x81,0x40,0xf7,0x59,0xf0
# ATT: vrangepd $123, {sae}, %ymm24, %ymm23, %ymm22
# INTEL: vrangepd ymm22, ymm23, ymm24, {sae}, 123
0x62,0x83,0xc1,0x10,0x50,0xf0,0x7b
# ATT: vrangepd $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vrangepd ymm22 {k7}, ymm23, ymm24, {sae}, 123
0x62,0x83,0xc1,0x17,0x50,0xf0,0x7b
# ATT: vrangepd $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vrangepd ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123
0x62,0x83,0xc1,0x97,0x50,0xf0,0x7b
# ATT: vrangeps $123, {sae}, %ymm24, %ymm23, %ymm22
# INTEL: vrangeps ymm22, ymm23, ymm24, {sae}, 123
0x62,0x83,0x41,0x10,0x50,0xf0,0x7b
# ATT: vrangeps $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vrangeps ymm22 {k7}, ymm23, ymm24, {sae}, 123
0x62,0x83,0x41,0x17,0x50,0xf0,0x7b
# ATT: vrangeps $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vrangeps ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123
0x62,0x83,0x41,0x97,0x50,0xf0,0x7b
# ATT: vreducepd $123, {sae}, %ymm23, %ymm22
# INTEL: vreducepd ymm22, ymm23, {sae}, 123
0x62,0xa3,0xf9,0x18,0x56,0xf7,0x7b
# ATT: vreducepd $123, {sae}, %ymm23, %ymm22 {%k7}
# INTEL: vreducepd ymm22 {k7}, ymm23, {sae}, 123
0x62,0xa3,0xf9,0x1f,0x56,0xf7,0x7b
# ATT: vreducepd $123, {sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vreducepd ymm22 {k7} {z}, ymm23, {sae}, 123
0x62,0xa3,0xf9,0x9f,0x56,0xf7,0x7b
# ATT: vreduceph $123, {sae}, %ymm23, %ymm22
# INTEL: vreduceph ymm22, ymm23, {sae}, 123
0x62,0xa3,0x78,0x18,0x56,0xf7,0x7b
# ATT: vreduceph $123, {sae}, %ymm23, %ymm22 {%k7}
# INTEL: vreduceph ymm22 {k7}, ymm23, {sae}, 123
0x62,0xa3,0x78,0x1f,0x56,0xf7,0x7b
# ATT: vreduceph $123, {sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vreduceph ymm22 {k7} {z}, ymm23, {sae}, 123
0x62,0xa3,0x78,0x9f,0x56,0xf7,0x7b
# ATT: vreduceps $123, {sae}, %ymm23, %ymm22
# INTEL: vreduceps ymm22, ymm23, {sae}, 123
0x62,0xa3,0x79,0x18,0x56,0xf7,0x7b
# ATT: vreduceps $123, {sae}, %ymm23, %ymm22 {%k7}
# INTEL: vreduceps ymm22 {k7}, ymm23, {sae}, 123
0x62,0xa3,0x79,0x1f,0x56,0xf7,0x7b
# ATT: vreduceps $123, {sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vreduceps ymm22 {k7} {z}, ymm23, {sae}, 123
0x62,0xa3,0x79,0x9f,0x56,0xf7,0x7b
# ATT: vrndscalepd $123, {sae}, %ymm23, %ymm22
# INTEL: vrndscalepd ymm22, ymm23, {sae}, 123
0x62,0xa3,0xf9,0x18,0x09,0xf7,0x7b
# ATT: vrndscalepd $123, {sae}, %ymm23, %ymm22 {%k7}
# INTEL: vrndscalepd ymm22 {k7}, ymm23, {sae}, 123
0x62,0xa3,0xf9,0x1f,0x09,0xf7,0x7b
# ATT: vrndscalepd $123, {sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vrndscalepd ymm22 {k7} {z}, ymm23, {sae}, 123
0x62,0xa3,0xf9,0x9f,0x09,0xf7,0x7b
# ATT: vrndscaleph $123, {sae}, %ymm23, %ymm22
# INTEL: vrndscaleph ymm22, ymm23, {sae}, 123
0x62,0xa3,0x78,0x18,0x08,0xf7,0x7b
# ATT: vrndscaleph $123, {sae}, %ymm23, %ymm22 {%k7}
# INTEL: vrndscaleph ymm22 {k7}, ymm23, {sae}, 123
0x62,0xa3,0x78,0x1f,0x08,0xf7,0x7b
# ATT: vrndscaleph $123, {sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vrndscaleph ymm22 {k7} {z}, ymm23, {sae}, 123
0x62,0xa3,0x78,0x9f,0x08,0xf7,0x7b
# ATT: vrndscaleps $123, {sae}, %ymm23, %ymm22
# INTEL: vrndscaleps ymm22, ymm23, {sae}, 123
0x62,0xa3,0x79,0x18,0x08,0xf7,0x7b
# ATT: vrndscaleps $123, {sae}, %ymm23, %ymm22 {%k7}
# INTEL: vrndscaleps ymm22 {k7}, ymm23, {sae}, 123
0x62,0xa3,0x79,0x1f,0x08,0xf7,0x7b
# ATT: vrndscaleps $123, {sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vrndscaleps ymm22 {k7} {z}, ymm23, {sae}, 123
0x62,0xa3,0x79,0x9f,0x08,0xf7,0x7b
# ATT: vscalefpd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vscalefpd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0xc1,0x10,0x2c,0xf0
# ATT: vscalefpd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vscalefpd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0xc1,0x37,0x2c,0xf0
# ATT: vscalefpd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vscalefpd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0xc1,0xf7,0x2c,0xf0
# ATT: vscalefph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vscalefph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x86,0x41,0x10,0x2c,0xf0
# ATT: vscalefph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vscalefph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x86,0x41,0x37,0x2c,0xf0
# ATT: vscalefph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vscalefph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x86,0x41,0xf7,0x2c,0xf0
# ATT: vscalefps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vscalefps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x82,0x41,0x10,0x2c,0xf0
# ATT: vscalefps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vscalefps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x82,0x41,0x37,0x2c,0xf0
# ATT: vscalefps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vscalefps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x82,0x41,0xf7,0x2c,0xf0
# ATT: vsqrtpd {rn-sae}, %ymm23, %ymm22
# INTEL: vsqrtpd ymm22, ymm23, {rn-sae}
0x62,0xa1,0xf9,0x18,0x51,0xf7
# ATT: vsqrtpd {rd-sae}, %ymm23, %ymm22 {%k7}
# INTEL: vsqrtpd ymm22 {k7}, ymm23, {rd-sae}
0x62,0xa1,0xf9,0x3f,0x51,0xf7
# ATT: vsqrtpd {rz-sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vsqrtpd ymm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa1,0xf9,0xff,0x51,0xf7
# ATT: vsqrtph {rn-sae}, %ymm23, %ymm22
# INTEL: vsqrtph ymm22, ymm23, {rn-sae}
0x62,0xa5,0x78,0x18,0x51,0xf7
# ATT: vsqrtph {rd-sae}, %ymm23, %ymm22 {%k7}
# INTEL: vsqrtph ymm22 {k7}, ymm23, {rd-sae}
0x62,0xa5,0x78,0x3f,0x51,0xf7
# ATT: vsqrtph {rz-sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vsqrtph ymm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa5,0x78,0xff,0x51,0xf7
# ATT: vsqrtps {rn-sae}, %ymm23, %ymm22
# INTEL: vsqrtps ymm22, ymm23, {rn-sae}
0x62,0xa1,0x78,0x18,0x51,0xf7
# ATT: vsqrtps {rd-sae}, %ymm23, %ymm22 {%k7}
# INTEL: vsqrtps ymm22 {k7}, ymm23, {rd-sae}
0x62,0xa1,0x78,0x3f,0x51,0xf7
# ATT: vsqrtps {rz-sae}, %ymm23, %ymm22 {%k7} {z}
# INTEL: vsqrtps ymm22 {k7} {z}, ymm23, {rz-sae}
0x62,0xa1,0x78,0xff,0x51,0xf7
# ATT: vsubpd {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vsubpd ymm22, ymm23, ymm24, {rn-sae}
0x62,0x81,0xc1,0x10,0x5c,0xf0
# ATT: vsubpd {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vsubpd ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x81,0xc1,0x37,0x5c,0xf0
# ATT: vsubpd {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vsubpd ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x81,0xc1,0xf7,0x5c,0xf0
# ATT: vsubph {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vsubph ymm22, ymm23, ymm24, {rn-sae}
0x62,0x85,0x40,0x10,0x5c,0xf0
# ATT: vsubph {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vsubph ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x85,0x40,0x37,0x5c,0xf0
# ATT: vsubph {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vsubph ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x85,0x40,0xf7,0x5c,0xf0
# ATT: vsubps {rn-sae}, %ymm24, %ymm23, %ymm22
# INTEL: vsubps ymm22, ymm23, ymm24, {rn-sae}
0x62,0x81,0x40,0x10,0x5c,0xf0
# ATT: vsubps {rd-sae}, %ymm24, %ymm23, %ymm22 {%k7}
# INTEL: vsubps ymm22 {k7}, ymm23, ymm24, {rd-sae}
0x62,0x81,0x40,0x37,0x5c,0xf0
# ATT: vsubps {rz-sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
# INTEL: vsubps ymm22 {k7} {z}, ymm23, ymm24, {rz-sae}
0x62,0x81,0x40,0xf7,0x5c,0xf0
Codebase Browser
llvm