neon-partial-reduce-dot-product.ll | Explore in Territory

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple aarch64 -mattr=+neon,+dotprod < %s | FileCheck %s --check-prefixes=CHECK,CHECK-DOT
; RUN: llc -mtriple aarch64 -mattr=+neon < %s | FileCheck %s --check-prefixes=CHECK,CHECK-NODOT

define <4 x i32> @udot(<4 x i32> %acc, <16 x i8> %u, <16 x i8> %s) {
; CHECK-DOT-LABEL: udot:
; CHECK-DOT:       // %bb.0:
; CHECK-DOT-NEXT:    udot v0.4s, v2.16b, v1.16b
; CHECK-DOT-NEXT:    ret
;
; CHECK-NODOT-LABEL: udot:
; CHECK-NODOT:       // %bb.0:
; CHECK-NODOT-NEXT:    umull v3.8h, v2.8b, v1.8b
; CHECK-NODOT-NEXT:    umull2 v1.8h, v2.16b, v1.16b
; CHECK-NODOT-NEXT:    ushll v2.4s, v1.4h, #0
; CHECK-NODOT-NEXT:    uaddw v0.4s, v0.4s, v3.4h
; CHECK-NODOT-NEXT:    uaddw2 v2.4s, v2.4s, v3.8h
; CHECK-NODOT-NEXT:    uaddw2 v0.4s, v0.4s, v1.8h
; CHECK-NODOT-NEXT:    add v0.4s, v2.4s, v0.4s
; CHECK-NODOT-NEXT:    ret
  %u.wide = zext <16 x i8> %u to <16 x i32>
  %s.wide = zext <16 x i8> %s to <16 x i32>
  %mult = mul nuw nsw <16 x i32> %s.wide, %u.wide
  %partial.reduce = tail call <4 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> %acc, <16 x i32> %mult)
  ret <4 x i32> %partial.reduce
}

define <2 x i32> @udot_narrow(<2 x i32> %acc, <8 x i8> %u, <8 x i8> %s) {
; CHECK-DOT-LABEL: udot_narrow:
; CHECK-DOT:       // %bb.0:
; CHECK-DOT-NEXT:    udot v0.2s, v2.8b, v1.8b
; CHECK-DOT-NEXT:    ret
;
; CHECK-NODOT-LABEL: udot_narrow:
; CHECK-NODOT:       // %bb.0:
; CHECK-NODOT-NEXT:    umull v1.8h, v2.8b, v1.8b
; CHECK-NODOT-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-NODOT-NEXT:    ushll v2.4s, v1.4h, #0
; CHECK-NODOT-NEXT:    ushll2 v3.4s, v1.8h, #0
; CHECK-NODOT-NEXT:    ext v4.16b, v1.16b, v1.16b, #8
; CHECK-NODOT-NEXT:    uaddw v0.4s, v0.4s, v1.4h
; CHECK-NODOT-NEXT:    ext v3.16b, v3.16b, v3.16b, #8
; CHECK-NODOT-NEXT:    ext v2.16b, v2.16b, v2.16b, #8
; CHECK-NODOT-NEXT:    add v0.2s, v3.2s, v0.2s
; CHECK-NODOT-NEXT:    uaddw v1.4s, v2.4s, v4.4h
; CHECK-NODOT-NEXT:    add v0.2s, v1.2s, v0.2s
; CHECK-NODOT-NEXT:    ret
  %u.wide = zext <8 x i8> %u to <8 x i32>
  %s.wide = zext <8 x i8> %s to <8 x i32>
  %mult = mul nuw nsw <8 x i32> %s.wide, %u.wide
  %partial.reduce = tail call <2 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v16i32(<2 x i32> %acc, <8 x i32> %mult)
  ret <2 x i32> %partial.reduce
}

define <4 x i32> @sdot(<4 x i32> %acc, <16 x i8> %u, <16 x i8> %s) {
; CHECK-DOT-LABEL: sdot:
; CHECK-DOT:       // %bb.0:
; CHECK-DOT-NEXT:    sdot v0.4s, v2.16b, v1.16b
; CHECK-DOT-NEXT:    ret
;
; CHECK-NODOT-LABEL: sdot:
; CHECK-NODOT:       // %bb.0:
; CHECK-NODOT-NEXT:    smull v3.8h, v2.8b, v1.8b
; CHECK-NODOT-NEXT:    smull2 v1.8h, v2.16b, v1.16b
; CHECK-NODOT-NEXT:    sshll v2.4s, v1.4h, #0
; CHECK-NODOT-NEXT:    saddw v0.4s, v0.4s, v3.4h
; CHECK-NODOT-NEXT:    saddw2 v2.4s, v2.4s, v3.8h
; CHECK-NODOT-NEXT:    saddw2 v0.4s, v0.4s, v1.8h
; CHECK-NODOT-NEXT:    add v0.4s, v2.4s, v0.4s
; CHECK-NODOT-NEXT:    ret
  %u.wide = sext <16 x i8> %u to <16 x i32>
  %s.wide = sext <16 x i8> %s to <16 x i32>
  %mult = mul nuw nsw <16 x i32> %s.wide, %u.wide
  %partial.reduce = tail call <4 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> %acc, <16 x i32> %mult)
  ret <4 x i32> %partial.reduce
}

define <2 x i32> @sdot_narrow(<2 x i32> %acc, <8 x i8> %u, <8 x i8> %s) {
; CHECK-DOT-LABEL: sdot_narrow:
; CHECK-DOT:       // %bb.0:
; CHECK-DOT-NEXT:    sdot v0.2s, v2.8b, v1.8b
; CHECK-DOT-NEXT:    ret
;
; CHECK-NODOT-LABEL: sdot_narrow:
; CHECK-NODOT:       // %bb.0:
; CHECK-NODOT-NEXT:    smull v1.8h, v2.8b, v1.8b
; CHECK-NODOT-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-NODOT-NEXT:    sshll v2.4s, v1.4h, #0
; CHECK-NODOT-NEXT:    sshll2 v3.4s, v1.8h, #0
; CHECK-NODOT-NEXT:    ext v4.16b, v1.16b, v1.16b, #8
; CHECK-NODOT-NEXT:    saddw v0.4s, v0.4s, v1.4h
; CHECK-NODOT-NEXT:    ext v3.16b, v3.16b, v3.16b, #8
; CHECK-NODOT-NEXT:    ext v2.16b, v2.16b, v2.16b, #8
; CHECK-NODOT-NEXT:    add v0.2s, v3.2s, v0.2s
; CHECK-NODOT-NEXT:    saddw v1.4s, v2.4s, v4.4h
; CHECK-NODOT-NEXT:    add v0.2s, v1.2s, v0.2s
; CHECK-NODOT-NEXT:    ret
  %u.wide = sext <8 x i8> %u to <8 x i32>
  %s.wide = sext <8 x i8> %s to <8 x i32>
  %mult = mul nuw nsw <8 x i32> %s.wide, %u.wide
  %partial.reduce = tail call <2 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v16i32(<2 x i32> %acc, <8 x i32> %mult)
  ret <2 x i32> %partial.reduce
}

define <4 x i32> @not_udot(<4 x i32> %acc, <8 x i8> %u, <8 x i8> %s) {
; CHECK-LABEL: not_udot:
; CHECK:       // %bb.0:
; CHECK-NEXT:    umull v1.8h, v2.8b, v1.8b
; CHECK-NEXT:    uaddw v0.4s, v0.4s, v1.4h
; CHECK-NEXT:    uaddw2 v0.4s, v0.4s, v1.8h
; CHECK-NEXT:    ret
  %u.wide = zext <8 x i8> %u to <8 x i32>
  %s.wide = zext <8 x i8> %s to <8 x i32>
  %mult = mul nuw nsw <8 x i32> %s.wide, %u.wide
  %partial.reduce = tail call <4 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> %acc, <8 x i32> %mult)
  ret <4 x i32> %partial.reduce
}

define <2 x i32> @not_udot_narrow(<2 x i32> %acc, <4 x i8> %u, <4 x i8> %s) {
; CHECK-LABEL: not_udot_narrow:
; CHECK:       // %bb.0:
; CHECK-NEXT:    bic v1.4h, #255, lsl #8
; CHECK-NEXT:    bic v2.4h, #255, lsl #8
; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT:    umull v3.4s, v2.4h, v1.4h
; CHECK-NEXT:    umlal v0.4s, v2.4h, v1.4h
; CHECK-NEXT:    ext v1.16b, v3.16b, v3.16b, #8
; CHECK-NEXT:    add v0.2s, v1.2s, v0.2s
; CHECK-NEXT:    ret
  %u.wide = zext <4 x i8> %u to <4 x i32>
  %s.wide = zext <4 x i8> %s to <4 x i32>
  %mult = mul nuw nsw <4 x i32> %s.wide, %u.wide
  %partial.reduce = tail call <2 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v16i32(<2 x i32> %acc, <4 x i32> %mult)
  ret <2 x i32> %partial.reduce
}
llvm/llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
