llvm/llvm/lib/MCA/HardwareUnits/RetireControlUnit.cpp

//===---------------------- RetireControlUnit.cpp ---------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
/// \file
///
/// This file simulates the hardware responsible for retiring instructions.
///
//===----------------------------------------------------------------------===//

#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
#include "llvm/Support/Debug.h"

#define DEBUG_TYPE …

namespace llvm {
namespace mca {

RetireControlUnit::RetireControlUnit(const MCSchedModel &SM)
    : … { … }

// Reserves a number of slots, and returns a new token.
unsigned RetireControlUnit::dispatch(const InstRef &IR) { … }

const RetireControlUnit::RUToken &RetireControlUnit::getCurrentToken() const { … }

unsigned RetireControlUnit::computeNextSlotIdx() const { … }

const RetireControlUnit::RUToken &RetireControlUnit::peekNextToken() const { … }

void RetireControlUnit::consumeCurrentToken() { … }

void RetireControlUnit::onInstructionExecuted(unsigned TokenID) { … }

#ifndef NDEBUG
void RetireControlUnit::dump() const {
  dbgs() << "Retire Unit: { Total ROB Entries =" << NumROBEntries
         << ", Available ROB entries=" << AvailableEntries << " }\n";
}
#endif

} // namespace mca
} // namespace llvm