llvm/llvm/lib/MCA/Instruction.cpp

//===--------------------- Instruction.cpp ----------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file defines abstractions used by the Pipeline to model register reads,
// register writes and instructions.
//
//===----------------------------------------------------------------------===//

#include "llvm/MCA/Instruction.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"

namespace llvm {
namespace mca {

void WriteState::writeStartEvent(unsigned IID, MCPhysReg RegID,
                                 unsigned Cycles) { … }

void ReadState::writeStartEvent(unsigned IID, MCPhysReg RegID,
                                unsigned Cycles) { … }

void WriteState::onInstructionIssued(unsigned IID) { … }

void WriteState::addUser(unsigned IID, ReadState *User, int ReadAdvance) { … }

void WriteState::addUser(unsigned IID, WriteState *User) { … }

void WriteState::cycleEvent() { … }

void ReadState::cycleEvent() { … }

#ifndef NDEBUG
void WriteState::dump() const {
  dbgs() << "{ OpIdx=" << WD->OpIndex << ", Lat=" << getLatency() << ", RegID "
         << getRegisterID() << ", Cycles Left=" << getCyclesLeft() << " }";
}
#endif

const CriticalDependency &Instruction::computeCriticalRegDep() { … }

void Instruction::reset() { … }

void Instruction::dispatch(unsigned RCUToken) { … }

void Instruction::execute(unsigned IID) { … }

void Instruction::forceExecuted() { … }

bool Instruction::updatePending() { … }

bool Instruction::updateDispatched() { … }

void Instruction::update() { … }

void Instruction::cycleEvent() { … }

} // namespace mca
} // namespace llvm