//===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // //===----------------------------------------------------------------------===// #include "AArch64TargetMachine.h" #include "AArch64.h" #include "AArch64MachineFunctionInfo.h" #include "AArch64MachineScheduler.h" #include "AArch64MacroFusion.h" #include "AArch64Subtarget.h" #include "AArch64TargetObjectFile.h" #include "AArch64TargetTransformInfo.h" #include "MCTargetDesc/AArch64MCTargetDesc.h" #include "TargetInfo/AArch64TargetInfo.h" #include "llvm/ADT/STLExtras.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/Analysis/ValueTracking.h" #include "llvm/CodeGen/CFIFixup.h" #include "llvm/CodeGen/CSEConfigBase.h" #include "llvm/CodeGen/GlobalISel/CSEInfo.h" #include "llvm/CodeGen/GlobalISel/IRTranslator.h" #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" #include "llvm/CodeGen/GlobalISel/Legalizer.h" #include "llvm/CodeGen/GlobalISel/LoadStoreOpt.h" #include "llvm/CodeGen/GlobalISel/Localizer.h" #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" #include "llvm/CodeGen/MIRParser/MIParser.h" #include "llvm/CodeGen/MachineScheduler.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/TargetInstrInfo.h" #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/IR/Attributes.h" #include "llvm/IR/Function.h" #include "llvm/InitializePasses.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCTargetOptions.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Pass.h" #include "llvm/Passes/PassBuilder.h" #include "llvm/Support/CodeGen.h" #include "llvm/Support/CommandLine.h" #include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetOptions.h" #include "llvm/TargetParser/Triple.h" #include "llvm/Transforms/CFGuard.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Vectorize/LoopIdiomVectorize.h" #include <memory> #include <optional> #include <string> usingnamespacellvm; static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp", cl::desc("Enable the CCMP formation pass"), cl::init(true), cl::Hidden); static cl::opt<bool> EnableCondBrTuning("aarch64-enable-cond-br-tune", cl::desc("Enable the conditional branch tuning pass"), cl::init(true), cl::Hidden); static cl::opt<bool> EnableAArch64CopyPropagation( "aarch64-enable-copy-propagation", cl::desc("Enable the copy propagation with AArch64 copy instr"), cl::init(true), cl::Hidden); static cl::opt<bool> EnableMCR("aarch64-enable-mcr", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden); static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress", cl::desc("Suppress STP for AArch64"), cl::init(true), cl::Hidden); static cl::opt<bool> EnableAdvSIMDScalar( "aarch64-enable-simd-scalar", cl::desc("Enable use of AdvSIMD scalar integer instructions"), cl::init(false), cl::Hidden); static cl::opt<bool> EnablePromoteConstant("aarch64-enable-promote-const", cl::desc("Enable the promote constant pass"), cl::init(true), cl::Hidden); static cl::opt<bool> EnableCollectLOH( "aarch64-enable-collect-loh", cl::desc("Enable the pass that emits the linker optimization hints (LOH)"), cl::init(true), cl::Hidden); static cl::opt<bool> EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitions and replaces stores to" " them with stores to the zero" " register"), cl::init(true)); static cl::opt<bool> EnableRedundantCopyElimination( "aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden); static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt", cl::desc("Enable the load/store pair" " optimization pass"), cl::init(true), cl::Hidden); static cl::opt<bool> EnableAtomicTidy( "aarch64-enable-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true)); static cl::opt<bool> EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(true)); static cl::opt<bool> EnableCondOpt("aarch64-enable-condopt", cl::desc("Enable the condition optimizer pass"), cl::init(true), cl::Hidden); static cl::opt<bool> EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(false)); static cl::opt<bool> EnableSelectOpt("aarch64-select-opt", cl::Hidden, cl::desc("Enable select to branch optimizations"), cl::init(true)); static cl::opt<bool> BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true), cl::desc("Relax out of range conditional branches")); static cl::opt<bool> EnableCompressJumpTables( "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true), cl::desc("Use smallest entry possible for jump tables")); // FIXME: Unify control over GlobalMerge. static cl::opt<cl::boolOrDefault> EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass")); static cl::opt<bool> EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true)); static cl::opt<int> EnableGlobalISelAtO( "aarch64-enable-global-isel-at-O", cl::Hidden, cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"), cl::init(0)); static cl::opt<bool> EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden, cl::desc("Enable SVE intrinsic opts"), cl::init(true)); static cl::opt<bool> EnableSMEPeepholeOpt("enable-aarch64-sme-peephole-opt", cl::init(true), cl::Hidden, cl::desc("Perform SME peephole optimization")); static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix", cl::init(true), cl::Hidden); static cl::opt<bool> EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden, cl::desc("Enable the AArch64 branch target pass"), cl::init(true)); static cl::opt<unsigned> SVEVectorBitsMaxOpt( "aarch64-sve-vector-bits-max", cl::desc("Assume SVE vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden); static cl::opt<unsigned> SVEVectorBitsMinOpt( "aarch64-sve-vector-bits-min", cl::desc("Assume SVE vector registers are at least this big, " "with zero meaning no minimum size is assumed."), cl::init(0), cl::Hidden); static cl::opt<bool> ForceStreaming( "force-streaming", cl::desc("Force the use of streaming code for all functions"), cl::init(false), cl::Hidden); static cl::opt<bool> ForceStreamingCompatible( "force-streaming-compatible", cl::desc("Force the use of streaming-compatible code for all functions"), cl::init(false), cl::Hidden); extern cl::opt<bool> EnableHomogeneousPrologEpilog; static cl::opt<bool> EnableGISelLoadStoreOptPreLegal( "aarch64-enable-gisel-ldst-prelegal", cl::desc("Enable GlobalISel's pre-legalizer load/store optimization pass"), cl::init(true), cl::Hidden); static cl::opt<bool> EnableGISelLoadStoreOptPostLegal( "aarch64-enable-gisel-ldst-postlegal", cl::desc("Enable GlobalISel's post-legalizer load/store optimization pass"), cl::init(false), cl::Hidden); static cl::opt<bool> EnableSinkFold("aarch64-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden); static cl::opt<bool> EnableMachinePipeliner("aarch64-enable-pipeliner", cl::desc("Enable Machine Pipeliner for AArch64"), cl::init(false), cl::Hidden); extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() { … } //===----------------------------------------------------------------------===// // AArch64 Lowering public interface. //===----------------------------------------------------------------------===// static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) { … } // Helper function to build a DataLayout string static std::string computeDataLayout(const Triple &TT, const MCTargetOptions &Options, bool LittleEndian) { … } static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU) { … } static Reloc::Model getEffectiveRelocModel(const Triple &TT, std::optional<Reloc::Model> RM) { … } static CodeModel::Model getEffectiveAArch64CodeModel(const Triple &TT, std::optional<CodeModel::Model> CM, bool JIT) { … } /// Create an AArch64 architecture model. /// AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional<Reloc::Model> RM, std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT, bool LittleEndian) : … { … } AArch64TargetMachine::~AArch64TargetMachine() = default; const AArch64Subtarget * AArch64TargetMachine::getSubtargetImpl(const Function &F) const { … } void AArch64leTargetMachine::anchor() { … } AArch64leTargetMachine::AArch64leTargetMachine( const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional<Reloc::Model> RM, std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT) : … { … } void AArch64beTargetMachine::anchor() { … } AArch64beTargetMachine::AArch64beTargetMachine( const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional<Reloc::Model> RM, std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT) : … { … } namespace { /// AArch64 Code Generator Pass Configuration Options. class AArch64PassConfig : public TargetPassConfig { … }; } // end anonymous namespace void AArch64TargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { … } TargetTransformInfo AArch64TargetMachine::getTargetTransformInfo(const Function &F) const { … } TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) { … } std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const { … } void AArch64PassConfig::addIRPasses() { … } // Pass Pipeline Configuration bool AArch64PassConfig::addPreISel() { … } void AArch64PassConfig::addCodeGenPrepare() { … } bool AArch64PassConfig::addInstSelector() { … } bool AArch64PassConfig::addIRTranslator() { … } void AArch64PassConfig::addPreLegalizeMachineIR() { … } bool AArch64PassConfig::addLegalizeMachineIR() { … } void AArch64PassConfig::addPreRegBankSelect() { … } bool AArch64PassConfig::addRegBankSelect() { … } bool AArch64PassConfig::addGlobalInstructionSelect() { … } void AArch64PassConfig::addMachineSSAOptimization() { … } bool AArch64PassConfig::addILPOpts() { … } void AArch64PassConfig::addPreRegAlloc() { … } void AArch64PassConfig::addPostRegAlloc() { … } void AArch64PassConfig::addPreSched2() { … } void AArch64PassConfig::addPreEmitPass() { … } void AArch64PassConfig::addPostBBSections() { … } void AArch64PassConfig::addPreEmitPass2() { … } bool AArch64PassConfig::addRegAssignAndRewriteOptimized() { … } MachineFunctionInfo *AArch64TargetMachine::createMachineFunctionInfo( BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const { … } yaml::MachineFunctionInfo * AArch64TargetMachine::createDefaultFuncInfoYAML() const { … } yaml::MachineFunctionInfo * AArch64TargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const { … } bool AArch64TargetMachine::parseMachineFunctionInfo( const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const { … }
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