//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // /// \file //===----------------------------------------------------------------------===// #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H #include "llvm/MC/MCInstrDesc.h" namespace llvm { // This needs to be kept in sync with the field bits in SIRegisterClass. enum SIRCFlags : uint8_t { … }; // enum SIRCFlagsr namespace SIEncodingFamily { // This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td // and the columns of the getMCOpcodeGen table. enum { … }; } namespace SIInstrFlags { // This needs to be kept in sync with the field bits in InstSI. enum : uint64_t { … }; // v_cmp_class_* etc. use a 10-bit mask for what operation is checked. // The result is true if any of these tests are true. enum ClassFlags : unsigned { … }; } namespace AMDGPU { enum OperandType : unsigned { … }; // Should be in sync with the OperandSemantics defined in SIRegisterInfo.td enum OperandSemantics : unsigned { … }; } // Input operand modifiers bit-masks // NEG and SEXT share same bit-mask because they can't be set simultaneously. namespace SISrcMods { enum : unsigned { … }; } namespace SIOutMods { enum : unsigned { … }; } namespace AMDGPU { namespace VGPRIndexMode { enum Id : unsigned { … }; enum EncBits : unsigned { … }; } // namespace VGPRIndexMode } // namespace AMDGPU namespace AMDGPUAsmVariants { enum : unsigned { … }; } // namespace AMDGPUAsmVariants namespace AMDGPU { namespace EncValues { // Encoding values of enum9/8/7 operands enum : unsigned { … }; } // namespace EncValues // Register codes as defined in the TableGen's HWEncoding field. namespace HWEncoding { enum : unsigned { … }; } // namespace HWEncoding namespace CPol { enum CPol { … }; } // namespace CPol namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns. enum Id { … }; enum Op { … }; enum StreamId : unsigned { … }; } // namespace SendMsg namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns. enum Id { … }; enum Offset : unsigned { … }; enum ModeRegisterMasks : uint32_t { … }; } // namespace Hwreg namespace MTBUFFormat { enum DataFormat : int64_t { … }; enum NumFormat : int64_t { … }; enum MergedFormat : int64_t { … }; enum UnifiedFormatCommon : int64_t { … }; } // namespace MTBUFFormat namespace UfmtGFX10 { enum UnifiedFormat : int64_t { … }; } // namespace UfmtGFX10 namespace UfmtGFX11 { enum UnifiedFormat : int64_t { … }; } // namespace UfmtGFX11 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32. enum Id : unsigned { … }; // clang-format off enum EncBits : unsigned { … }; // clang-format on } // namespace Swizzle namespace SDWA { enum SdwaSel : unsigned { … }; enum DstUnused : unsigned { … }; enum SDWA9EncValues : unsigned { … }; } // namespace SDWA namespace DPP { // clang-format off enum DppCtrl : unsigned { … }; // clang-format on enum DppFiMode { … }; } // namespace DPP namespace Exp { enum Target : unsigned { … }; } // namespace Exp namespace VOP3PEncoding { enum OpSel : uint64_t { … }; } // namespace VOP3PEncoding namespace ImplicitArg { // Implicit kernel argument offset for code object version 5. enum Offset_COV5 : unsigned { … }; } // namespace ImplicitArg namespace VirtRegFlag { // Virtual register flags used for various target specific handlings during // codegen. enum Register_Flag : uint8_t { … }; } // namespace VirtRegFlag } // namespace AMDGPU namespace AMDGPU { namespace Barrier { enum Type { … }; } // namespace Barrier } // namespace AMDGPU // clang-format off #define R_00B028_SPI_SHADER_PGM_RSRC1_PS … #define S_00B028_VGPRS(x) … #define S_00B028_SGPRS(x) … #define S_00B028_MEM_ORDERED(x) … #define G_00B028_MEM_ORDERED(x) … #define C_00B028_MEM_ORDERED … #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS … #define S_00B02C_EXTRA_LDS_SIZE(x) … #define R_00B128_SPI_SHADER_PGM_RSRC1_VS … #define S_00B128_MEM_ORDERED(x) … #define G_00B128_MEM_ORDERED(x) … #define C_00B128_MEM_ORDERED … #define R_00B228_SPI_SHADER_PGM_RSRC1_GS … #define S_00B228_WGP_MODE(x) … #define G_00B228_WGP_MODE(x) … #define C_00B228_WGP_MODE … #define S_00B228_MEM_ORDERED(x) … #define G_00B228_MEM_ORDERED(x) … #define C_00B228_MEM_ORDERED … #define R_00B328_SPI_SHADER_PGM_RSRC1_ES … #define R_00B428_SPI_SHADER_PGM_RSRC1_HS … #define S_00B428_WGP_MODE(x) … #define G_00B428_WGP_MODE(x) … #define C_00B428_WGP_MODE … #define S_00B428_MEM_ORDERED(x) … #define G_00B428_MEM_ORDERED(x) … #define C_00B428_MEM_ORDERED … #define R_00B528_SPI_SHADER_PGM_RSRC1_LS … #define R_00B84C_COMPUTE_PGM_RSRC2 … #define S_00B84C_SCRATCH_EN(x) … #define G_00B84C_SCRATCH_EN(x) … #define C_00B84C_SCRATCH_EN … #define S_00B84C_USER_SGPR(x) … #define G_00B84C_USER_SGPR(x) … #define C_00B84C_USER_SGPR … #define S_00B84C_TRAP_HANDLER(x) … #define G_00B84C_TRAP_HANDLER(x) … #define C_00B84C_TRAP_HANDLER … #define S_00B84C_TGID_X_EN(x) … #define G_00B84C_TGID_X_EN(x) … #define C_00B84C_TGID_X_EN … #define S_00B84C_TGID_Y_EN(x) … #define G_00B84C_TGID_Y_EN(x) … #define C_00B84C_TGID_Y_EN … #define S_00B84C_TGID_Z_EN(x) … #define G_00B84C_TGID_Z_EN(x) … #define C_00B84C_TGID_Z_EN … #define S_00B84C_TG_SIZE_EN(x) … #define G_00B84C_TG_SIZE_EN(x) … #define C_00B84C_TG_SIZE_EN … #define S_00B84C_TIDIG_COMP_CNT(x) … #define G_00B84C_TIDIG_COMP_CNT(x) … #define C_00B84C_TIDIG_COMP_CNT … /* CIK */ #define S_00B84C_EXCP_EN_MSB(x) … #define G_00B84C_EXCP_EN_MSB(x) … #define C_00B84C_EXCP_EN_MSB … /* */ #define S_00B84C_LDS_SIZE(x) … #define G_00B84C_LDS_SIZE(x) … #define C_00B84C_LDS_SIZE … #define S_00B84C_EXCP_EN(x) … #define G_00B84C_EXCP_EN(x) … #define C_00B84C_EXCP_EN … #define R_0286CC_SPI_PS_INPUT_ENA … #define R_0286D0_SPI_PS_INPUT_ADDR … #define R_00B848_COMPUTE_PGM_RSRC1 … #define S_00B848_VGPRS(x) … #define G_00B848_VGPRS(x) … #define C_00B848_VGPRS … #define S_00B848_SGPRS(x) … #define G_00B848_SGPRS(x) … #define C_00B848_SGPRS … #define S_00B848_PRIORITY(x) … #define G_00B848_PRIORITY(x) … #define C_00B848_PRIORITY … #define S_00B848_FLOAT_MODE(x) … #define G_00B848_FLOAT_MODE(x) … #define C_00B848_FLOAT_MODE … #define S_00B848_PRIV(x) … #define G_00B848_PRIV(x) … #define C_00B848_PRIV … #define S_00B848_DX10_CLAMP(x) … #define G_00B848_DX10_CLAMP(x) … #define C_00B848_DX10_CLAMP … #define S_00B848_RR_WG_MODE(x) … #define G_00B848_RR_WG_MODE(x) … #define C_00B848_RR_WG_MODE … #define S_00B848_DEBUG_MODE(x) … #define G_00B848_DEBUG_MODE(x) … #define C_00B848_DEBUG_MODE … #define S_00B848_IEEE_MODE(x) … #define G_00B848_IEEE_MODE(x) … #define C_00B848_IEEE_MODE … #define S_00B848_WGP_MODE(x) … #define G_00B848_WGP_MODE(x) … #define C_00B848_WGP_MODE … #define S_00B848_MEM_ORDERED(x) … #define G_00B848_MEM_ORDERED(x) … #define C_00B848_MEM_ORDERED … #define S_00B848_FWD_PROGRESS(x) … #define G_00B848_FWD_PROGRESS(x) … #define C_00B848_FWD_PROGRESS … // Helpers for setting FLOAT_MODE #define FP_ROUND_ROUND_TO_NEAREST … #define FP_ROUND_ROUND_TO_INF … #define FP_ROUND_ROUND_TO_NEGINF … #define FP_ROUND_ROUND_TO_ZERO … // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double // precision. #define FP_ROUND_MODE_SP(x) … #define FP_ROUND_MODE_DP(x) … #define FP_DENORM_FLUSH_IN_FLUSH_OUT … #define FP_DENORM_FLUSH_OUT … #define FP_DENORM_FLUSH_IN … #define FP_DENORM_FLUSH_NONE … // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double // precision. #define FP_DENORM_MODE_SP(x) … #define FP_DENORM_MODE_DP(x) … #define R_00B860_COMPUTE_TMPRING_SIZE … #define S_00B860_WAVESIZE_PreGFX11(x) … #define S_00B860_WAVESIZE_GFX11(x) … #define S_00B860_WAVESIZE_GFX12Plus(x) … #define R_0286E8_SPI_TMPRING_SIZE … #define S_0286E8_WAVESIZE_PreGFX11(x) … #define S_0286E8_WAVESIZE_GFX11(x) … #define S_0286E8_WAVESIZE_GFX12Plus(x) … #define R_028B54_VGT_SHADER_STAGES_EN … #define S_028B54_HS_W32_EN(x) … #define S_028B54_GS_W32_EN(x) … #define S_028B54_VS_W32_EN(x) … #define R_0286D8_SPI_PS_IN_CONTROL … #define S_0286D8_PS_W32_EN(x) … #define R_00B800_COMPUTE_DISPATCH_INITIATOR … #define S_00B800_CS_W32_EN(x) … #define R_SPILLED_SGPRS … #define R_SPILLED_VGPRS … // clang-format on } // End namespace llvm #endif
Codebase Browser
llvm