llvm/lib/Target/AMDGPU/R600GenInstrInfo.inc

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Instruction Enum Values and Descriptors                             *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
namespace llvm {

namespace R600 {
  enum { … };

} // end namespace R600
} // end namespace llvm
#endif // GET_INSTRINFO_ENUM

#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM
namespace llvm {

namespace R600 {
namespace Sched {
  enum { … };
} // end namespace Sched
} // end namespace R600
} // end namespace llvm
#endif // GET_INSTRINFO_SCHED_ENUM

#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
namespace llvm {

struct R600InstrTable {
  MCInstrDesc Insts[642];
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
  MCOperandInfo OperandInfo[462];
  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
  MCPhysReg ImplicitOps[1];
};

} // end namespace llvm
#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)

#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC
namespace llvm {

static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
static constexpr unsigned R600ImpOpBase = sizeof R600InstrTable::OperandInfo / (sizeof(MCPhysReg));

extern const R600InstrTable R600Descs = {
  {
    { 641,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #641 = XOR_INT
    { 640,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #640 = WHILE_LOOP_R600
    { 639,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #639 = WHILE_LOOP_EG
    { 638,	4,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	450,	0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // Inst #638 = VTX_READ_8_eg
    { 637,	4,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	450,	0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // Inst #637 = VTX_READ_8_cm
    { 636,	4,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	458,	0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // Inst #636 = VTX_READ_64_eg
    { 635,	4,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	458,	0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // Inst #635 = VTX_READ_64_cm
    { 634,	4,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	454,	0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // Inst #634 = VTX_READ_32_eg
    { 633,	4,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	454,	0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // Inst #633 = VTX_READ_32_cm
    { 632,	4,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	450,	0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // Inst #632 = VTX_READ_16_eg
    { 631,	4,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	450,	0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // Inst #631 = VTX_READ_16_cm
    { 630,	4,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	446,	0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // Inst #630 = VTX_READ_128_eg
    { 629,	4,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	446,	0|(1ULL<<MCID::MayLoad), 0x1000ULL },  // Inst #629 = VTX_READ_128_cm
    { 628,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #628 = UINT_TO_FLT_r600
    { 627,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #627 = UINT_TO_FLT_eg
    { 626,	14,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #626 = TRUNC
    { 625,	4,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	446,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x1000ULL },  // Inst #625 = TEX_VTX_TEXBUF
    { 624,	4,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	446,	0, 0x1000ULL },  // Inst #624 = TEX_VTX_CONSTBUF
    { 623,	19,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	427,	0, 0x2000ULL },  // Inst #623 = TEX_SET_GRADIENTS_V
    { 622,	19,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	427,	0, 0x2000ULL },  // Inst #622 = TEX_SET_GRADIENTS_H
    { 621,	19,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	427,	0, 0x2000ULL },  // Inst #621 = TEX_SAMPLE_LB
    { 620,	19,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	427,	0, 0x2000ULL },  // Inst #620 = TEX_SAMPLE_L
    { 619,	19,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	427,	0, 0x2000ULL },  // Inst #619 = TEX_SAMPLE_G
    { 618,	19,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	427,	0, 0x2000ULL },  // Inst #618 = TEX_SAMPLE_C_LB
    { 617,	19,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	427,	0, 0x2000ULL },  // Inst #617 = TEX_SAMPLE_C_L
    { 616,	19,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	427,	0, 0x2000ULL },  // Inst #616 = TEX_SAMPLE_C_G
    { 615,	19,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	427,	0, 0x2000ULL },  // Inst #615 = TEX_SAMPLE_C
    { 614,	19,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	427,	0, 0x2000ULL },  // Inst #614 = TEX_SAMPLE
    { 613,	19,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	427,	0, 0x2000ULL },  // Inst #613 = TEX_LDPTR
    { 612,	19,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	427,	0, 0x2000ULL },  // Inst #612 = TEX_LD
    { 611,	19,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	427,	0, 0x2000ULL },  // Inst #611 = TEX_GET_TEXTURE_RESINFO
    { 610,	19,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	427,	0, 0x2000ULL },  // Inst #610 = TEX_GET_GRADIENTS_V
    { 609,	19,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	427,	0, 0x2000ULL },  // Inst #609 = TEX_GET_GRADIENTS_H
    { 608,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #608 = SUB_INT
    { 607,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #607 = SUBB_UINT
    { 606,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #606 = SNE
    { 605,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4610ULL },  // Inst #605 = SIN_r700
    { 604,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4610ULL },  // Inst #604 = SIN_r600
    { 603,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4610ULL },  // Inst #603 = SIN_eg
    { 602,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4650ULL },  // Inst #602 = SIN_cm
    { 601,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #601 = SGT
    { 600,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #600 = SGE
    { 599,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #599 = SETNE_INT
    { 598,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #598 = SETNE_DX10
    { 597,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #597 = SETGT_UINT
    { 596,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #596 = SETGT_INT
    { 595,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #595 = SETGT_DX10
    { 594,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #594 = SETGE_UINT
    { 593,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #593 = SETGE_INT
    { 592,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #592 = SETGE_DX10
    { 591,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #591 = SETE_INT
    { 590,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #590 = SETE_DX10
    { 589,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #589 = SETE
    { 588,	14,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #588 = RNDNE
    { 587,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #587 = RECIP_UINT_r600
    { 586,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #586 = RECIP_UINT_eg
    { 585,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #585 = RECIP_IEEE_r600
    { 584,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #584 = RECIP_IEEE_eg
    { 583,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4640ULL },  // Inst #583 = RECIP_IEEE_cm
    { 582,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #582 = RECIP_CLAMPED_r600
    { 581,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #581 = RECIP_CLAMPED_eg
    { 580,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4640ULL },  // Inst #580 = RECIP_CLAMPED_cm
    { 579,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #579 = RECIPSQRT_IEEE_r600
    { 578,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #578 = RECIPSQRT_IEEE_eg
    { 577,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4640ULL },  // Inst #577 = RECIPSQRT_IEEE_cm
    { 576,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #576 = RECIPSQRT_CLAMPED_r600
    { 575,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #575 = RECIPSQRT_CLAMPED_eg
    { 574,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4640ULL },  // Inst #574 = RECIPSQRT_CLAMPED_cm
    { 573,	3,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	424,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL },  // Inst #573 = RAT_WRITE_CACHELESS_64_eg
    { 572,	3,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	421,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL },  // Inst #572 = RAT_WRITE_CACHELESS_32_eg
    { 571,	3,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	418,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL },  // Inst #571 = RAT_WRITE_CACHELESS_128_eg
    { 570,	4,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	414,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #570 = RAT_STORE_TYPED_eg
    { 569,	4,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	414,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #569 = RAT_STORE_TYPED_cm
    { 568,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	412,	0|(1ULL<<MCID::MayStore), 0x20000ULL },  // Inst #568 = RAT_STORE_DWORD64
    { 567,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	410,	0|(1ULL<<MCID::MayStore), 0x20000ULL },  // Inst #567 = RAT_STORE_DWORD32
    { 566,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	408,	0|(1ULL<<MCID::MayStore), 0x20000ULL },  // Inst #566 = RAT_STORE_DWORD128
    { 565,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	408,	0|(1ULL<<MCID::MayStore), 0x20000ULL },  // Inst #565 = RAT_MSKOR
    { 564,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #564 = RAT_ATOMIC_XOR_RTN
    { 563,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #563 = RAT_ATOMIC_XOR_NORET
    { 562,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #562 = RAT_ATOMIC_XCHG_INT_RTN
    { 561,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #561 = RAT_ATOMIC_XCHG_INT_NORET
    { 560,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #560 = RAT_ATOMIC_SUB_RTN
    { 559,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #559 = RAT_ATOMIC_SUB_NORET
    { 558,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #558 = RAT_ATOMIC_RSUB_RTN
    { 557,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #557 = RAT_ATOMIC_RSUB_NORET
    { 556,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #556 = RAT_ATOMIC_OR_RTN
    { 555,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #555 = RAT_ATOMIC_OR_NORET
    { 554,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #554 = RAT_ATOMIC_MIN_UINT_RTN
    { 553,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #553 = RAT_ATOMIC_MIN_UINT_NORET
    { 552,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #552 = RAT_ATOMIC_MIN_INT_RTN
    { 551,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #551 = RAT_ATOMIC_MIN_INT_NORET
    { 550,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #550 = RAT_ATOMIC_MAX_UINT_RTN
    { 549,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #549 = RAT_ATOMIC_MAX_UINT_NORET
    { 548,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #548 = RAT_ATOMIC_MAX_INT_RTN
    { 547,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #547 = RAT_ATOMIC_MAX_INT_NORET
    { 546,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #546 = RAT_ATOMIC_INC_UINT_RTN
    { 545,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #545 = RAT_ATOMIC_INC_UINT_NORET
    { 544,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #544 = RAT_ATOMIC_DEC_UINT_RTN
    { 543,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #543 = RAT_ATOMIC_DEC_UINT_NORET
    { 542,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #542 = RAT_ATOMIC_CMPXCHG_INT_RTN
    { 541,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #541 = RAT_ATOMIC_CMPXCHG_INT_NORET
    { 540,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #540 = RAT_ATOMIC_AND_RTN
    { 539,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #539 = RAT_ATOMIC_AND_NORET
    { 538,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #538 = RAT_ATOMIC_ADD_RTN
    { 537,	3,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	405,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #537 = RAT_ATOMIC_ADD_NORET
    { 536,	9,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	333,	0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #536 = R600_ExportSwz
    { 535,	7,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	326,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #535 = R600_ExportBuf
    { 534,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #534 = PRED_SETNE_INT
    { 533,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #533 = PRED_SETNE
    { 532,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #532 = PRED_SETGT_INT
    { 531,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #531 = PRED_SETGT
    { 530,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #530 = PRED_SETGE_INT
    { 529,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #529 = PRED_SETGE
    { 528,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #528 = PRED_SETE_INT
    { 527,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #527 = PRED_SETE
    { 526,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	21,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #526 = POP_R600
    { 525,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	21,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #525 = POP_EG
    { 524,	0,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #524 = PAD
    { 523,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #523 = OR_INT
    { 522,	14,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #522 = NOT_INT
    { 521,	21,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #521 = MUL_UINT24_eg
    { 520,	19,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #520 = MUL_LIT_r600
    { 519,	19,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #519 = MUL_LIT_eg
    { 518,	21,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #518 = MUL_INT24_cm
    { 517,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #517 = MUL_IEEE
    { 516,	21,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #516 = MULLO_UINT_r600
    { 515,	21,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #515 = MULLO_UINT_eg
    { 514,	21,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a40ULL },  // Inst #514 = MULLO_UINT_cm
    { 513,	21,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #513 = MULLO_INT_r600
    { 512,	21,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #512 = MULLO_INT_eg
    { 511,	21,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a40ULL },  // Inst #511 = MULLO_INT_cm
    { 510,	21,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #510 = MULHI_UINT_r600
    { 509,	21,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #509 = MULHI_UINT_eg
    { 508,	21,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a40ULL },  // Inst #508 = MULHI_UINT_cm24
    { 507,	21,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a40ULL },  // Inst #507 = MULHI_UINT_cm
    { 506,	21,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #506 = MULHI_UINT24_eg
    { 505,	21,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #505 = MULHI_INT_r600
    { 504,	21,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #504 = MULHI_INT_eg
    { 503,	21,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a40ULL },  // Inst #503 = MULHI_INT_cm24
    { 502,	21,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a40ULL },  // Inst #502 = MULHI_INT_cm
    { 501,	19,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #501 = MULADD_r600
    { 500,	19,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #500 = MULADD_eg
    { 499,	19,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #499 = MULADD_UINT24_eg
    { 498,	19,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #498 = MULADD_INT24_cm
    { 497,	19,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #497 = MULADD_IEEE_r600
    { 496,	19,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #496 = MULADD_IEEE_eg
    { 495,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #495 = MUL
    { 494,	14,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4600ULL },  // Inst #494 = MOVA_INT_eg
    { 493,	14,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #493 = MOV
    { 492,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #492 = MIN_UINT
    { 491,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #491 = MIN_INT
    { 490,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #490 = MIN_DX10
    { 489,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #489 = MIN
    { 488,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #488 = MAX_UINT
    { 487,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #487 = MAX_INT
    { 486,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #486 = MAX_DX10
    { 485,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #485 = MAX
    { 484,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #484 = LSHR_r600
    { 483,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #483 = LSHR_eg
    { 482,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #482 = LSHL_r600
    { 481,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #481 = LSHL_eg
    { 480,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #480 = LOOP_BREAK_R600
    { 479,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #479 = LOOP_BREAK_EG
    { 478,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #478 = LOG_IEEE_r600
    { 477,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #477 = LOG_IEEE_eg
    { 476,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4640ULL },  // Inst #476 = LOG_IEEE_cm
    { 475,	14,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #475 = LOG_CLAMPED_r600
    { 474,	14,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #474 = LOG_CLAMPED_eg
    { 473,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	13,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #473 = LITERALS
    { 472,	10,	1,	0,	5,	0,	0,	R600ImpOpBase + 0,	363,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // Inst #472 = LDS_XOR_RET
    { 471,	9,	0,	0,	5,	0,	0,	R600ImpOpBase + 0,	354,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // Inst #471 = LDS_XOR
    { 470,	10,	1,	0,	5,	0,	0,	R600ImpOpBase + 0,	363,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // Inst #470 = LDS_WRXCHG_RET
    { 469,	9,	0,	0,	5,	0,	0,	R600ImpOpBase + 0,	354,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // Inst #469 = LDS_WRXCHG
    { 468,	9,	0,	0,	5,	0,	0,	R600ImpOpBase + 0,	354,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL },  // Inst #468 = LDS_WRITE
    { 467,	7,	1,	0,	5,	0,	0,	R600ImpOpBase + 0,	373,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL },  // Inst #467 = LDS_USHORT_READ_RET
    { 466,	7,	1,	0,	5,	0,	0,	R600ImpOpBase + 0,	373,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL },  // Inst #466 = LDS_UBYTE_READ_RET
    { 465,	10,	1,	0,	5,	0,	0,	R600ImpOpBase + 0,	363,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // Inst #465 = LDS_SUB_RET
    { 464,	9,	0,	0,	5,	0,	0,	R600ImpOpBase + 0,	354,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // Inst #464 = LDS_SUB
    { 463,	9,	0,	0,	5,	0,	0,	R600ImpOpBase + 0,	354,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL },  // Inst #463 = LDS_SHORT_WRITE
    { 462,	7,	1,	0,	5,	0,	0,	R600ImpOpBase + 0,	373,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL },  // Inst #462 = LDS_SHORT_READ_RET
    { 461,	7,	1,	0,	5,	0,	0,	R600ImpOpBase + 0,	373,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL },  // Inst #461 = LDS_READ_RET
    { 460,	10,	1,	0,	5,	0,	0,	R600ImpOpBase + 0,	363,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // Inst #460 = LDS_OR_RET
    { 459,	9,	0,	0,	5,	0,	0,	R600ImpOpBase + 0,	354,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // Inst #459 = LDS_OR
    { 458,	10,	1,	0,	5,	0,	0,	R600ImpOpBase + 0,	363,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // Inst #458 = LDS_MIN_UINT_RET
    { 457,	9,	0,	0,	5,	0,	0,	R600ImpOpBase + 0,	354,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // Inst #457 = LDS_MIN_UINT
    { 456,	10,	1,	0,	5,	0,	0,	R600ImpOpBase + 0,	363,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // Inst #456 = LDS_MIN_INT_RET
    { 455,	9,	0,	0,	5,	0,	0,	R600ImpOpBase + 0,	354,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // Inst #455 = LDS_MIN_INT
    { 454,	10,	1,	0,	5,	0,	0,	R600ImpOpBase + 0,	363,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // Inst #454 = LDS_MAX_UINT_RET
    { 453,	9,	0,	0,	5,	0,	0,	R600ImpOpBase + 0,	354,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // Inst #453 = LDS_MAX_UINT
    { 452,	10,	1,	0,	5,	0,	0,	R600ImpOpBase + 0,	363,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // Inst #452 = LDS_MAX_INT_RET
    { 451,	9,	0,	0,	5,	0,	0,	R600ImpOpBase + 0,	354,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // Inst #451 = LDS_MAX_INT
    { 450,	13,	1,	0,	5,	0,	0,	R600ImpOpBase + 0,	392,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x44200ULL },  // Inst #450 = LDS_CMPST_RET
    { 449,	12,	0,	0,	5,	0,	0,	R600ImpOpBase + 0,	380,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44200ULL },  // Inst #449 = LDS_CMPST
    { 448,	9,	0,	0,	5,	0,	0,	R600ImpOpBase + 0,	354,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL },  // Inst #448 = LDS_BYTE_WRITE
    { 447,	7,	1,	0,	5,	0,	0,	R600ImpOpBase + 0,	373,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL },  // Inst #447 = LDS_BYTE_READ_RET
    { 446,	10,	1,	0,	5,	0,	0,	R600ImpOpBase + 0,	363,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // Inst #446 = LDS_AND_RET
    { 445,	9,	0,	0,	5,	0,	0,	R600ImpOpBase + 0,	354,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // Inst #445 = LDS_AND
    { 444,	10,	1,	0,	5,	0,	0,	R600ImpOpBase + 0,	363,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL },  // Inst #444 = LDS_ADD_RET
    { 443,	9,	0,	0,	5,	0,	0,	R600ImpOpBase + 0,	354,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL },  // Inst #443 = LDS_ADD
    { 442,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4a00ULL },  // Inst #442 = KILLGT
    { 441,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #441 = INT_TO_FLT_r600
    { 440,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #440 = INT_TO_FLT_eg
    { 439,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #439 = INTERP_ZW
    { 438,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #438 = INTERP_XY
    { 437,	2,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	352,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #437 = INTERP_VEC_LOAD
    { 436,	5,	2,	0,	1,	0,	0,	R600ImpOpBase + 0,	347,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #436 = INTERP_PAIR_ZW
    { 435,	5,	2,	0,	1,	0,	0,	R600ImpOpBase + 0,	342,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #435 = INTERP_PAIR_XY
    { 434,	14,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #434 = INTERP_LOAD_P0
    { 433,	0,	0,	0,	3,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4000ULL },  // Inst #433 = GROUP_BARRIER
    { 432,	14,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #432 = FRACT
    { 431,	19,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #431 = FMA_eg
    { 430,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #430 = FLT_TO_UINT_r600
    { 429,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #429 = FLT_TO_UINT_eg
    { 428,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #428 = FLT_TO_INT_r600
    { 427,	14,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #427 = FLT_TO_INT_eg
    { 426,	14,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #426 = FLT32_TO_FLT16
    { 425,	14,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #425 = FLT16_TO_FLT32
    { 424,	14,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #424 = FLOOR
    { 423,	14,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #423 = FFBL_INT
    { 422,	14,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #422 = FFBH_UINT
    { 421,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #421 = FETCH_CLAUSE
    { 420,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #420 = EXP_IEEE_r600
    { 419,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #419 = EXP_IEEE_eg
    { 418,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4640ULL },  // Inst #418 = EXP_IEEE_cm
    { 417,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #417 = END_LOOP_R600
    { 416,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #416 = END_LOOP_EG
    { 415,	9,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	333,	0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #415 = EG_ExportSwz
    { 414,	7,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	326,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL },  // Inst #414 = EG_ExportBuf
    { 413,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #413 = DOT4_r600
    { 412,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #412 = DOT4_eg
    { 411,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #411 = CUBE_r600_real
    { 410,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #410 = CUBE_eg_real
    { 409,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4610ULL },  // Inst #409 = COS_r700
    { 408,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4610ULL },  // Inst #408 = COS_r600
    { 407,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4610ULL },  // Inst #407 = COS_eg
    { 406,	14,	1,	0,	4,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4650ULL },  // Inst #406 = COS_cm
    { 405,	19,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #405 = CNDGT_r600
    { 404,	19,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #404 = CNDGT_eg
    { 403,	19,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #403 = CNDGT_INT
    { 402,	19,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #402 = CNDGE_r600
    { 401,	19,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #401 = CNDGE_eg
    { 400,	19,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #400 = CNDGE_INT
    { 399,	19,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #399 = CNDE_r600
    { 398,	19,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #398 = CNDE_eg
    { 397,	19,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #397 = CNDE_INT
    { 396,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	21,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #396 = CF_VC_R600
    { 395,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	21,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #395 = CF_VC_EG
    { 394,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	21,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #394 = CF_TC_R600
    { 393,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	21,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #393 = CF_TC_EG
    { 392,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #392 = CF_PUSH_ELSE_R600
    { 391,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	21,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #391 = CF_PUSH_EG
    { 390,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	21,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #390 = CF_JUMP_R600
    { 389,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	21,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #389 = CF_JUMP_EG
    { 388,	0,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #388 = CF_END_R600
    { 387,	0,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #387 = CF_END_EG
    { 386,	0,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #386 = CF_END_CM
    { 385,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	21,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #385 = CF_ELSE_R600
    { 384,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	21,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #384 = CF_ELSE_EG
    { 383,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #383 = CF_CONTINUE_R600
    { 382,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #382 = CF_CONTINUE_EG
    { 381,	0,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #381 = CF_CALL_FS_R600
    { 380,	0,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #380 = CF_CALL_FS_EG
    { 379,	9,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	317,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #379 = CF_ALU_PUSH_BEFORE
    { 378,	9,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	317,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #378 = CF_ALU_POP_AFTER
    { 377,	9,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	317,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #377 = CF_ALU_ELSE_AFTER
    { 376,	9,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	317,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #376 = CF_ALU_CONTINUE
    { 375,	9,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	317,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #375 = CF_ALU_BREAK
    { 374,	9,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	317,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #374 = CF_ALU
    { 373,	14,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #373 = CEIL
    { 372,	19,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #372 = BIT_ALIGN_INT_eg
    { 371,	21,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #371 = BFM_INT_eg
    { 370,	19,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #370 = BFI_INT_eg
    { 369,	19,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #369 = BFE_UINT_eg
    { 368,	19,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	298,	0|(1ULL<<MCID::Predicable), 0x4220ULL },  // Inst #368 = BFE_INT_eg
    { 367,	14,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	284,	0|(1ULL<<MCID::Predicable), 0x4600ULL },  // Inst #367 = BCNT_INT
    { 366,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #366 = ASHR_r600
    { 365,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #365 = ASHR_eg
    { 364,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #364 = AND_INT
    { 363,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #363 = ALU_CLAUSE
    { 362,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #362 = ADD_INT
    { 361,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #361 = ADDC_UINT
    { 360,	21,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	263,	0|(1ULL<<MCID::Predicable), 0x4a00ULL },  // Inst #360 = ADD
    { 359,	0,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #359 = WHILELOOP
    { 358,	7,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	256,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL },  // Inst #358 = TXD_SHADOW
    { 357,	7,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	256,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL },  // Inst #357 = TXD
    { 356,	0,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #356 = RETURN
    { 355,	0,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #355 = RETDYN
    { 354,	4,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	252,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000000000000000ULL },  // Inst #354 = R600_RegisterStore
    { 353,	4,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	252,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8000000000000000ULL },  // Inst #353 = R600_RegisterLoad
    { 352,	4,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	248,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #352 = R600_INSERT_ELT_V4
    { 351,	4,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	244,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #351 = R600_INSERT_ELT_V2
    { 350,	3,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	241,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #350 = R600_EXTRACT_ELT_V4
    { 349,	3,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	238,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #349 = R600_EXTRACT_ELT_V2
    { 348,	4,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	234,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL },  // Inst #348 = PRED_X
    { 347,	2,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	157,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #347 = MOV_IMM_I32
    { 346,	2,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	157,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #346 = MOV_IMM_GLOBAL_ADDR
    { 345,	2,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	157,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #345 = MOV_IMM_F32
    { 344,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	156,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #344 = MASK_WRITE
    { 343,	2,	0,	0,	3,	0,	0,	R600ImpOpBase + 0,	232,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #343 = JUMP_COND
    { 342,	1,	0,	0,	3,	0,	0,	R600ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #342 = JUMP
    { 341,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	156,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #341 = IF_PREDICATE_SET
    { 340,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	156,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #340 = IF_LOGICALZ_i32
    { 339,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	156,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #339 = IF_LOGICALZ_f32
    { 338,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	156,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #338 = IF_LOGICALNZ_i32
    { 337,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	156,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #337 = IF_LOGICALNZ_f32
    { 336,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	154,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #336 = IFC_i32
    { 335,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	154,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #335 = IFC_f32
    { 334,	0,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #334 = FUNC
    { 333,	2,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	154,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #333 = FNEG_R600
    { 332,	2,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	154,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #332 = FABS_R600
    { 331,	0,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #331 = ENDSWITCH
    { 330,	0,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #330 = ENDMAIN
    { 329,	0,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #329 = ENDLOOP
    { 328,	0,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #328 = ENDIF
    { 327,	0,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #327 = ENDFUNC
    { 326,	0,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #326 = END
    { 325,	0,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #325 = ELSE
    { 324,	0,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #324 = DUMMY_CHAIN
    { 323,	71,	1,	0,	3,	0,	0,	R600ImpOpBase + 0,	161,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL },  // Inst #323 = DOT_4
    { 322,	0,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #322 = DEFAULT
    { 321,	2,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	159,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #321 = CUBE_r600_pseudo
    { 320,	2,	1,	0,	2,	0,	0,	R600ImpOpBase + 0,	159,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #320 = CUBE_eg_pseudo
    { 319,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	156,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #319 = CONTINUE_LOGICALZ_i32
    { 318,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	156,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #318 = CONTINUE_LOGICALZ_f32
    { 317,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	156,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #317 = CONTINUE_LOGICALNZ_i32
    { 316,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	156,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #316 = CONTINUE_LOGICALNZ_f32
    { 315,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	154,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #315 = CONTINUEC_i32
    { 314,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	154,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #314 = CONTINUEC_f32
    { 313,	0,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #313 = CONTINUE
    { 312,	2,	1,	0,	1,	0,	0,	R600ImpOpBase + 0,	157,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // Inst #312 = CONST_COPY
    { 311,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	156,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #311 = BREAK_LOGICALZ_i32
    { 310,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	156,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #310 = BREAK_LOGICALZ_f32
    { 309,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	156,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #309 = BREAK_LOGICALNZ_i32
    { 308,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	156,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #308 = BREAK_LOGICALNZ_f32
    { 307,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	154,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #307 = BREAKC_i32
    { 306,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	154,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #306 = BREAKC_f32
    { 305,	0,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #305 = BREAK
    { 304,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #304 = BRANCH_COND_i32
    { 303,	2,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #303 = BRANCH_COND_f32
    { 302,	1,	0,	0,	1,	0,	0,	R600ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #302 = BRANCH
    { 301,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #301 = G_UBFX
    { 300,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #300 = G_SBFX
    { 299,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #299 = G_VECREDUCE_UMIN
    { 298,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #298 = G_VECREDUCE_UMAX
    { 297,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #297 = G_VECREDUCE_SMIN
    { 296,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #296 = G_VECREDUCE_SMAX
    { 295,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #295 = G_VECREDUCE_XOR
    { 294,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #294 = G_VECREDUCE_OR
    { 293,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #293 = G_VECREDUCE_AND
    { 292,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #292 = G_VECREDUCE_MUL
    { 291,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #291 = G_VECREDUCE_ADD
    { 290,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #290 = G_VECREDUCE_FMINIMUM
    { 289,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #289 = G_VECREDUCE_FMAXIMUM
    { 288,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #288 = G_VECREDUCE_FMIN
    { 287,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #287 = G_VECREDUCE_FMAX
    { 286,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #286 = G_VECREDUCE_FMUL
    { 285,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #285 = G_VECREDUCE_FADD
    { 284,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #284 = G_VECREDUCE_SEQ_FMUL
    { 283,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #283 = G_VECREDUCE_SEQ_FADD
    { 282,	1,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #282 = G_UBSANTRAP
    { 281,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #281 = G_DEBUGTRAP
    { 280,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #280 = G_TRAP
    { 279,	3,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #279 = G_BZERO
    { 278,	4,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #278 = G_MEMSET
    { 277,	4,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #277 = G_MEMMOVE
    { 276,	3,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #276 = G_MEMCPY_INLINE
    { 275,	4,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #275 = G_MEMCPY
    { 274,	2,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	142,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #274 = G_WRITE_REGISTER
    { 273,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #273 = G_READ_REGISTER
    { 272,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #272 = G_STRICT_FLDEXP
    { 271,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #271 = G_STRICT_FSQRT
    { 270,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #270 = G_STRICT_FMA
    { 269,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #269 = G_STRICT_FREM
    { 268,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #268 = G_STRICT_FDIV
    { 267,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #267 = G_STRICT_FMUL
    { 266,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #266 = G_STRICT_FSUB
    { 265,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #265 = G_STRICT_FADD
    { 264,	1,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #264 = G_STACKRESTORE
    { 263,	1,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #263 = G_STACKSAVE
    { 262,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #262 = G_DYN_STACKALLOC
    { 261,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #261 = G_JUMP_TABLE
    { 260,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #260 = G_BLOCK_ADDR
    { 259,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #259 = G_ADDRSPACE_CAST
    { 258,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #258 = G_FNEARBYINT
    { 257,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #257 = G_FRINT
    { 256,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #256 = G_FFLOOR
    { 255,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #255 = G_FSQRT
    { 254,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #254 = G_FTANH
    { 253,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #253 = G_FSINH
    { 252,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #252 = G_FCOSH
    { 251,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #251 = G_FATAN2
    { 250,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #250 = G_FATAN
    { 249,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #249 = G_FASIN
    { 248,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #248 = G_FACOS
    { 247,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #247 = G_FTAN
    { 246,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #246 = G_FSIN
    { 245,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #245 = G_FCOS
    { 244,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #244 = G_FCEIL
    { 243,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #243 = G_BITREVERSE
    { 242,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #242 = G_BSWAP
    { 241,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #241 = G_CTPOP
    { 240,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #240 = G_CTLZ_ZERO_UNDEF
    { 239,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #239 = G_CTLZ
    { 238,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #238 = G_CTTZ_ZERO_UNDEF
    { 237,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #237 = G_CTTZ
    { 236,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	138,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #236 = G_VECTOR_COMPRESS
    { 235,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #235 = G_SPLAT_VECTOR
    { 234,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	134,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #234 = G_SHUFFLE_VECTOR
    { 233,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #233 = G_EXTRACT_VECTOR_ELT
    { 232,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	127,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #232 = G_INSERT_VECTOR_ELT
    { 231,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #231 = G_EXTRACT_SUBVECTOR
    { 230,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #230 = G_INSERT_SUBVECTOR
    { 229,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #229 = G_VSCALE
    { 228,	3,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	124,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #228 = G_BRJT
    { 227,	1,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #227 = G_BR
    { 226,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #226 = G_LLROUND
    { 225,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #225 = G_LROUND
    { 224,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #224 = G_ABS
    { 223,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #223 = G_UMAX
    { 222,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #222 = G_UMIN
    { 221,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #221 = G_SMAX
    { 220,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #220 = G_SMIN
    { 219,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #219 = G_PTRMASK
    { 218,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #218 = G_PTR_ADD
    { 217,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #217 = G_RESET_FPMODE
    { 216,	1,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #216 = G_SET_FPMODE
    { 215,	1,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #215 = G_GET_FPMODE
    { 214,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #214 = G_RESET_FPENV
    { 213,	1,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #213 = G_SET_FPENV
    { 212,	1,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #212 = G_GET_FPENV
    { 211,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #211 = G_FMAXIMUM
    { 210,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #210 = G_FMINIMUM
    { 209,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #209 = G_FMAXNUM_IEEE
    { 208,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #208 = G_FMINNUM_IEEE
    { 207,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #207 = G_FMAXNUM
    { 206,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #206 = G_FMINNUM
    { 205,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #205 = G_FCANONICALIZE
    { 204,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #204 = G_IS_FPCLASS
    { 203,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #203 = G_FCOPYSIGN
    { 202,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #202 = G_FABS
    { 201,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #201 = G_FPTOUI_SAT
    { 200,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #200 = G_FPTOSI_SAT
    { 199,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #199 = G_UITOFP
    { 198,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #198 = G_SITOFP
    { 197,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #197 = G_FPTOUI
    { 196,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #196 = G_FPTOSI
    { 195,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #195 = G_FPTRUNC
    { 194,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #194 = G_FPEXT
    { 193,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #193 = G_FNEG
    { 192,	3,	2,	0,	0,	0,	0,	R600ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #192 = G_FFREXP
    { 191,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #191 = G_FLDEXP
    { 190,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #190 = G_FLOG10
    { 189,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #189 = G_FLOG2
    { 188,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #188 = G_FLOG
    { 187,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #187 = G_FEXP10
    { 186,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #186 = G_FEXP2
    { 185,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #185 = G_FEXP
    { 184,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #184 = G_FPOWI
    { 183,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #183 = G_FPOW
    { 182,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #182 = G_FREM
    { 181,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #181 = G_FDIV
    { 180,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #180 = G_FMAD
    { 179,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #179 = G_FMA
    { 178,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #178 = G_FMUL
    { 177,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #177 = G_FSUB
    { 176,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #176 = G_FADD
    { 175,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #175 = G_UDIVFIXSAT
    { 174,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #174 = G_SDIVFIXSAT
    { 173,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #173 = G_UDIVFIX
    { 172,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #172 = G_SDIVFIX
    { 171,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #171 = G_UMULFIXSAT
    { 170,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #170 = G_SMULFIXSAT
    { 169,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #169 = G_UMULFIX
    { 168,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #168 = G_SMULFIX
    { 167,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #167 = G_SSHLSAT
    { 166,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #166 = G_USHLSAT
    { 165,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #165 = G_SSUBSAT
    { 164,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #164 = G_USUBSAT
    { 163,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #163 = G_SADDSAT
    { 162,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #162 = G_UADDSAT
    { 161,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #161 = G_SMULH
    { 160,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #160 = G_UMULH
    { 159,	4,	2,	0,	0,	0,	0,	R600ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #159 = G_SMULO
    { 158,	4,	2,	0,	0,	0,	0,	R600ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #158 = G_UMULO
    { 157,	5,	2,	0,	0,	0,	0,	R600ImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #157 = G_SSUBE
    { 156,	4,	2,	0,	0,	0,	0,	R600ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #156 = G_SSUBO
    { 155,	5,	2,	0,	0,	0,	0,	R600ImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #155 = G_SADDE
    { 154,	4,	2,	0,	0,	0,	0,	R600ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #154 = G_SADDO
    { 153,	5,	2,	0,	0,	0,	0,	R600ImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #153 = G_USUBE
    { 152,	4,	2,	0,	0,	0,	0,	R600ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #152 = G_USUBO
    { 151,	5,	2,	0,	0,	0,	0,	R600ImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #151 = G_UADDE
    { 150,	4,	2,	0,	0,	0,	0,	R600ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #150 = G_UADDO
    { 149,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #149 = G_SELECT
    { 148,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #148 = G_UCMP
    { 147,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #147 = G_SCMP
    { 146,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #146 = G_FCMP
    { 145,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #145 = G_ICMP
    { 144,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #144 = G_ROTL
    { 143,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #143 = G_ROTR
    { 142,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #142 = G_FSHR
    { 141,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #141 = G_FSHL
    { 140,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #140 = G_ASHR
    { 139,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #139 = G_LSHR
    { 138,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #138 = G_SHL
    { 137,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #137 = G_ZEXT
    { 136,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #136 = G_SEXT_INREG
    { 135,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #135 = G_SEXT
    { 134,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #134 = G_VAARG
    { 133,	1,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #133 = G_VASTART
    { 132,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #132 = G_FCONSTANT
    { 131,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #131 = G_CONSTANT
    { 130,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #130 = G_TRUNC
    { 129,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #129 = G_ANYEXT
    { 128,	1,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #128 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
    { 127,	1,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #127 = G_INTRINSIC_CONVERGENT
    { 126,	1,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #126 = G_INTRINSIC_W_SIDE_EFFECTS
    { 125,	1,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #125 = G_INTRINSIC
    { 124,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #124 = G_INVOKE_REGION_START
    { 123,	1,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #123 = G_BRINDIRECT
    { 122,	2,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #122 = G_BRCOND
    { 121,	4,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	94,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #121 = G_PREFETCH
    { 120,	2,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	21,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #120 = G_FENCE
    { 119,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #119 = G_ATOMICRMW_USUB_SAT
    { 118,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #118 = G_ATOMICRMW_USUB_COND
    { 117,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #117 = G_ATOMICRMW_UDEC_WRAP
    { 116,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #116 = G_ATOMICRMW_UINC_WRAP
    { 115,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #115 = G_ATOMICRMW_FMIN
    { 114,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #114 = G_ATOMICRMW_FMAX
    { 113,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #113 = G_ATOMICRMW_FSUB
    { 112,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #112 = G_ATOMICRMW_FADD
    { 111,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #111 = G_ATOMICRMW_UMIN
    { 110,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #110 = G_ATOMICRMW_UMAX
    { 109,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #109 = G_ATOMICRMW_MIN
    { 108,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #108 = G_ATOMICRMW_MAX
    { 107,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #107 = G_ATOMICRMW_XOR
    { 106,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #106 = G_ATOMICRMW_OR
    { 105,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #105 = G_ATOMICRMW_NAND
    { 104,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #104 = G_ATOMICRMW_AND
    { 103,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #103 = G_ATOMICRMW_SUB
    { 102,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #102 = G_ATOMICRMW_ADD
    { 101,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #101 = G_ATOMICRMW_XCHG
    { 100,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #100 = G_ATOMIC_CMPXCHG
    { 99,	5,	2,	0,	0,	0,	0,	R600ImpOpBase + 0,	82,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #99 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
    { 98,	5,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	77,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #98 = G_INDEXED_STORE
    { 97,	2,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #97 = G_STORE
    { 96,	5,	2,	0,	0,	0,	0,	R600ImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #96 = G_INDEXED_ZEXTLOAD
    { 95,	5,	2,	0,	0,	0,	0,	R600ImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #95 = G_INDEXED_SEXTLOAD
    { 94,	5,	2,	0,	0,	0,	0,	R600ImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #94 = G_INDEXED_LOAD
    { 93,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #93 = G_ZEXTLOAD
    { 92,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #92 = G_SEXTLOAD
    { 91,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #91 = G_LOAD
    { 90,	1,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #90 = G_READSTEADYCOUNTER
    { 89,	1,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #89 = G_READCYCLECOUNTER
    { 88,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #88 = G_INTRINSIC_ROUNDEVEN
    { 87,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #87 = G_INTRINSIC_LLRINT
    { 86,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #86 = G_INTRINSIC_LRINT
    { 85,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #85 = G_INTRINSIC_ROUND
    { 84,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #84 = G_INTRINSIC_TRUNC
    { 83,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #83 = G_INTRINSIC_FPTRUNC_ROUND
    { 82,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #82 = G_CONSTANT_FOLD_BARRIER
    { 81,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #81 = G_FREEZE
    { 80,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #80 = G_BITCAST
    { 79,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #79 = G_INTTOPTR
    { 78,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #78 = G_PTRTOINT
    { 77,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #77 = G_CONCAT_VECTORS
    { 76,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #76 = G_BUILD_VECTOR_TRUNC
    { 75,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #75 = G_BUILD_VECTOR
    { 74,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #74 = G_MERGE_VALUES
    { 73,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #73 = G_INSERT
    { 72,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #72 = G_UNMERGE_VALUES
    { 71,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #71 = G_EXTRACT
    { 70,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #70 = G_CONSTANT_POOL
    { 69,	5,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	53,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #69 = G_PTRAUTH_GLOBAL_VALUE
    { 68,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #68 = G_GLOBAL_VALUE
    { 67,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #67 = G_FRAME_INDEX
    { 66,	1,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #66 = G_PHI
    { 65,	1,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #65 = G_IMPLICIT_DEF
    { 64,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #64 = G_XOR
    { 63,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #63 = G_OR
    { 62,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #62 = G_AND
    { 61,	4,	2,	0,	0,	0,	0,	R600ImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #61 = G_UDIVREM
    { 60,	4,	2,	0,	0,	0,	0,	R600ImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #60 = G_SDIVREM
    { 59,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #59 = G_UREM
    { 58,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #58 = G_SREM
    { 57,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #57 = G_UDIV
    { 56,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #56 = G_SDIV
    { 55,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #55 = G_MUL
    { 54,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #54 = G_SUB
    { 53,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #53 = G_ADD
    { 52,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #52 = G_ASSERT_ALIGN
    { 51,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #51 = G_ASSERT_ZEXT
    { 50,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #50 = G_ASSERT_SEXT
    { 49,	1,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #49 = CONVERGENCECTRL_GLUE
    { 48,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #48 = CONVERGENCECTRL_LOOP
    { 47,	1,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #47 = CONVERGENCECTRL_ANCHOR
    { 46,	1,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #46 = CONVERGENCECTRL_ENTRY
    { 45,	1,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // Inst #45 = JUMP_TABLE_DEBUG_INFO
    { 44,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #44 = MEMBARRIER
    { 43,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #43 = FAKE_USE
    { 42,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #42 = ICALL_BRANCH_FUNNEL
    { 41,	3,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	37,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #41 = PATCHABLE_TYPED_EVENT_CALL
    { 40,	2,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	35,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #40 = PATCHABLE_EVENT_CALL
    { 39,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #39 = PATCHABLE_TAIL_CALL
    { 38,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #38 = PATCHABLE_FUNCTION_EXIT
    { 37,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #37 = PATCHABLE_RET
    { 36,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #36 = PATCHABLE_FUNCTION_ENTER
    { 35,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #35 = PATCHABLE_OP
    { 34,	1,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #34 = FAULTING_OP
    { 33,	2,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	33,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #33 = LOCAL_ESCAPE
    { 32,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #32 = STATEPOINT
    { 31,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	30,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #31 = PREALLOCATED_ARG
    { 30,	1,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #30 = PREALLOCATED_SETUP
    { 29,	1,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	29,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL },  // Inst #29 = LOAD_STACK_GUARD
    { 28,	6,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	23,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #28 = PATCHPOINT
    { 27,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #27 = FENTRY_CALL
    { 26,	2,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #26 = STACKMAP
    { 25,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	19,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // Inst #25 = ARITH_FENCE
    { 24,	4,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	15,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #24 = PSEUDO_PROBE
    { 23,	1,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // Inst #23 = LIFETIME_END
    { 22,	1,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // Inst #22 = LIFETIME_START
    { 21,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #21 = BUNDLE
    { 20,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // Inst #20 = COPY
    { 19,	2,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // Inst #19 = REG_SEQUENCE
    { 18,	1,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // Inst #18 = DBG_LABEL
    { 17,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #17 = DBG_PHI
    { 16,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #16 = DBG_INSTR_REF
    { 15,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #15 = DBG_VALUE_LIST
    { 14,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #14 = DBG_VALUE
    { 13,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // Inst #13 = COPY_TO_REGCLASS
    { 12,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	9,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #12 = SUBREG_TO_REG
    { 11,	1,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #11 = INIT_UNDEF
    { 10,	1,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // Inst #10 = IMPLICIT_DEF
    { 9,	4,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	5,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #9 = INSERT_SUBREG
    { 8,	3,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #8 = EXTRACT_SUBREG
    { 7,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #7 = KILL
    { 6,	1,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL },  // Inst #6 = ANNOTATION_LABEL
    { 5,	1,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL },  // Inst #5 = GC_LABEL
    { 4,	1,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL },  // Inst #4 = EH_LABEL
    { 3,	1,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL },  // Inst #3 = CFI_INSTRUCTION
    { 2,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #2 = INLINEASM_BR
    { 1,	0,	0,	0,	0,	0,	0,	R600ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #1 = INLINEASM
    { 0,	1,	1,	0,	0,	0,	0,	R600ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #0 = PHI
  }, {
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 1 */
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
    /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
    /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 152 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 154 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 156 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 157 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 159 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 161 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 232 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 234 */ { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 238 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 241 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 244 */ { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 248 */ { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 252 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 256 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 263 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 284 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 298 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 317 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 326 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 333 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 342 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 347 */ { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 352 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 354 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 363 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 373 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 380 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 392 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 405 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 408 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 410 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 412 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 414 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 418 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 421 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 424 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 427 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 446 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 450 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 454 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 458 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
  }, {
    /* 0 */
  }
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char R600InstrNameData[] = {
  /* 0 */ "CF_TC_R600\0"
  /* 11 */ "CF_VC_R600\0"
  /* 22 */ "CF_END_R600\0"
  /* 34 */ "CF_ELSE_R600\0"
  /* 47 */ "CF_PUSH_ELSE_R600\0"
  /* 65 */ "CF_CONTINUE_R600\0"
  /* 82 */ "FNEG_R600\0"
  /* 92 */ "LOOP_BREAK_R600\0"
  /* 108 */ "CF_JUMP_R600\0"
  /* 121 */ "END_LOOP_R600\0"
  /* 135 */ "WHILE_LOOP_R600\0"
  /* 151 */ "POP_R600\0"
  /* 160 */ "FABS_R600\0"
  /* 170 */ "CF_CALL_FS_R600\0"
  /* 186 */ "DOT4_r600\0"
  /* 196 */ "MULADD_r600\0"
  /* 208 */ "LOG_CLAMPED_r600\0"
  /* 225 */ "RECIP_CLAMPED_r600\0"
  /* 244 */ "RECIPSQRT_CLAMPED_r600\0"
  /* 267 */ "CNDE_r600\0"
  /* 277 */ "MULADD_IEEE_r600\0"
  /* 294 */ "LOG_IEEE_r600\0"
  /* 308 */ "RECIP_IEEE_r600\0"
  /* 324 */ "EXP_IEEE_r600\0"
  /* 338 */ "RECIPSQRT_IEEE_r600\0"
  /* 358 */ "CNDGE_r600\0"
  /* 369 */ "LSHL_r600\0"
  /* 379 */ "SIN_r600\0"
  /* 388 */ "ASHR_r600\0"
  /* 398 */ "LSHR_r600\0"
  /* 408 */ "COS_r600\0"
  /* 417 */ "CNDGT_r600\0"
  /* 428 */ "MUL_LIT_r600\0"
  /* 441 */ "UINT_TO_FLT_r600\0"
  /* 458 */ "MULHI_UINT_r600\0"
  /* 474 */ "MULLO_UINT_r600\0"
  /* 490 */ "FLT_TO_UINT_r600\0"
  /* 507 */ "RECIP_UINT_r600\0"
  /* 523 */ "MULHI_INT_r600\0"
  /* 538 */ "MULLO_INT_r600\0"
  /* 553 */ "FLT_TO_INT_r600\0"
  /* 569 */ "SIN_r700\0"
  /* 578 */ "COS_r700\0"
  /* 587 */ "G_FLOG10\0"
  /* 596 */ "G_FEXP10\0"
  /* 605 */ "SETGE_DX10\0"
  /* 616 */ "SETNE_DX10\0"
  /* 627 */ "SETE_DX10\0"
  /* 637 */ "MIN_DX10\0"
  /* 646 */ "SETGT_DX10\0"
  /* 657 */ "MAX_DX10\0"
  /* 666 */ "INTERP_LOAD_P0\0"
  /* 681 */ "RAT_STORE_DWORD32\0"
  /* 699 */ "MOV_IMM_F32\0"
  /* 711 */ "MOV_IMM_I32\0"
  /* 723 */ "FLT16_TO_FLT32\0"
  /* 738 */ "CONTINUEC_f32\0"
  /* 752 */ "IFC_f32\0"
  /* 760 */ "BREAKC_f32\0"
  /* 771 */ "BRANCH_COND_f32\0"
  /* 787 */ "CONTINUE_LOGICALZ_f32\0"
  /* 809 */ "IF_LOGICALZ_f32\0"
  /* 825 */ "BREAK_LOGICALZ_f32\0"
  /* 844 */ "CONTINUE_LOGICALNZ_f32\0"
  /* 867 */ "IF_LOGICALNZ_f32\0"
  /* 884 */ "BREAK_LOGICALNZ_f32\0"
  /* 904 */ "CONTINUEC_i32\0"
  /* 918 */ "IFC_i32\0"
  /* 926 */ "BREAKC_i32\0"
  /* 937 */ "BRANCH_COND_i32\0"
  /* 953 */ "CONTINUE_LOGICALZ_i32\0"
  /* 975 */ "IF_LOGICALZ_i32\0"
  /* 991 */ "BREAK_LOGICALZ_i32\0"
  /* 1010 */ "CONTINUE_LOGICALNZ_i32\0"
  /* 1033 */ "IF_LOGICALNZ_i32\0"
  /* 1050 */ "BREAK_LOGICALNZ_i32\0"
  /* 1070 */ "G_FLOG2\0"
  /* 1078 */ "G_FATAN2\0"
  /* 1087 */ "G_FEXP2\0"
  /* 1095 */ "R600_EXTRACT_ELT_V2\0"
  /* 1115 */ "R600_INSERT_ELT_V2\0"
  /* 1134 */ "MULHI_UINT_cm24\0"
  /* 1150 */ "MULHI_INT_cm24\0"
  /* 1165 */ "RAT_STORE_DWORD64\0"
  /* 1183 */ "R600_EXTRACT_ELT_V4\0"
  /* 1203 */ "R600_INSERT_ELT_V4\0"
  /* 1222 */ "DOT_4\0"
  /* 1228 */ "FLT32_TO_FLT16\0"
  /* 1243 */ "RAT_STORE_DWORD128\0"
  /* 1262 */ "G_FMA\0"
  /* 1268 */ "G_STRICT_FMA\0"
  /* 1281 */ "TEX_SAMPLE_C_LB\0"
  /* 1297 */ "TEX_SAMPLE_LB\0"
  /* 1311 */ "G_FSUB\0"
  /* 1318 */ "G_STRICT_FSUB\0"
  /* 1332 */ "G_ATOMICRMW_FSUB\0"
  /* 1349 */ "G_SUB\0"
  /* 1355 */ "LDS_SUB\0"
  /* 1363 */ "G_ATOMICRMW_SUB\0"
  /* 1379 */ "G_INTRINSIC\0"
  /* 1391 */ "ENDFUNC\0"
  /* 1399 */ "G_FPTRUNC\0"
  /* 1409 */ "G_INTRINSIC_TRUNC\0"
  /* 1427 */ "G_TRUNC\0"
  /* 1435 */ "G_BUILD_VECTOR_TRUNC\0"
  /* 1456 */ "G_DYN_STACKALLOC\0"
  /* 1473 */ "TEX_SAMPLE_C\0"
  /* 1486 */ "G_FMAD\0"
  /* 1493 */ "G_INDEXED_SEXTLOAD\0"
  /* 1512 */ "G_SEXTLOAD\0"
  /* 1523 */ "G_INDEXED_ZEXTLOAD\0"
  /* 1542 */ "G_ZEXTLOAD\0"
  /* 1553 */ "INTERP_VEC_LOAD\0"
  /* 1569 */ "G_INDEXED_LOAD\0"
  /* 1584 */ "G_LOAD\0"
  /* 1591 */ "PAD\0"
  /* 1595 */ "G_VECREDUCE_FADD\0"
  /* 1612 */ "G_FADD\0"
  /* 1619 */ "G_VECREDUCE_SEQ_FADD\0"
  /* 1640 */ "G_STRICT_FADD\0"
  /* 1654 */ "G_ATOMICRMW_FADD\0"
  /* 1671 */ "G_VECREDUCE_ADD\0"
  /* 1687 */ "G_ADD\0"
  /* 1693 */ "G_PTR_ADD\0"
  /* 1703 */ "LDS_ADD\0"
  /* 1711 */ "G_ATOMICRMW_ADD\0"
  /* 1727 */ "TEX_LD\0"
  /* 1734 */ "G_ATOMICRMW_NAND\0"
  /* 1751 */ "G_VECREDUCE_AND\0"
  /* 1767 */ "G_AND\0"
  /* 1773 */ "LDS_AND\0"
  /* 1781 */ "G_ATOMICRMW_AND\0"
  /* 1797 */ "LIFETIME_END\0"
  /* 1810 */ "G_BRCOND\0"
  /* 1819 */ "G_ATOMICRMW_USUB_COND\0"
  /* 1841 */ "JUMP_COND\0"
  /* 1851 */ "G_LLROUND\0"
  /* 1861 */ "G_LROUND\0"
  /* 1870 */ "G_INTRINSIC_ROUND\0"
  /* 1888 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
  /* 1914 */ "LOAD_STACK_GUARD\0"
  /* 1931 */ "TXD\0"
  /* 1935 */ "PSEUDO_PROBE\0"
  /* 1948 */ "G_SSUBE\0"
  /* 1956 */ "G_USUBE\0"
  /* 1964 */ "G_FENCE\0"
  /* 1972 */ "ARITH_FENCE\0"
  /* 1984 */ "REG_SEQUENCE\0"
  /* 1997 */ "G_SADDE\0"
  /* 2005 */ "G_UADDE\0"
  /* 2013 */ "G_GET_FPMODE\0"
  /* 2026 */ "G_RESET_FPMODE\0"
  /* 2041 */ "G_SET_FPMODE\0"
  /* 2054 */ "MUL_IEEE\0"
  /* 2063 */ "G_FMINNUM_IEEE\0"
  /* 2078 */ "G_FMAXNUM_IEEE\0"
  /* 2093 */ "SGE\0"
  /* 2097 */ "PRED_SETGE\0"
  /* 2108 */ "G_VSCALE\0"
  /* 2117 */ "G_JUMP_TABLE\0"
  /* 2130 */ "BUNDLE\0"
  /* 2137 */ "TEX_SAMPLE\0"
  /* 2148 */ "RNDNE\0"
  /* 2154 */ "G_MEMCPY_INLINE\0"
  /* 2170 */ "SNE\0"
  /* 2174 */ "PRED_SETNE\0"
  /* 2185 */ "LOCAL_ESCAPE\0"
  /* 2198 */ "CF_ALU_PUSH_BEFORE\0"
  /* 2217 */ "G_STACKRESTORE\0"
  /* 2232 */ "G_INDEXED_STORE\0"
  /* 2248 */ "G_STORE\0"
  /* 2256 */ "ELSE\0"
  /* 2261 */ "G_BITREVERSE\0"
  /* 2274 */ "FETCH_CLAUSE\0"
  /* 2287 */ "ALU_CLAUSE\0"
  /* 2298 */ "FAKE_USE\0"
  /* 2307 */ "PRED_SETE\0"
  /* 2317 */ "LDS_BYTE_WRITE\0"
  /* 2332 */ "MASK_WRITE\0"
  /* 2343 */ "LDS_WRITE\0"
  /* 2353 */ "LDS_SHORT_WRITE\0"
  /* 2369 */ "DBG_VALUE\0"
  /* 2379 */ "G_GLOBAL_VALUE\0"
  /* 2394 */ "G_PTRAUTH_GLOBAL_VALUE\0"
  /* 2417 */ "CONVERGENCECTRL_GLUE\0"
  /* 2438 */ "CF_ALU_CONTINUE\0"
  /* 2454 */ "G_STACKSAVE\0"
  /* 2466 */ "G_MEMMOVE\0"
  /* 2476 */ "G_FREEZE\0"
  /* 2485 */ "G_FCANONICALIZE\0"
  /* 2501 */ "G_CTLZ_ZERO_UNDEF\0"
  /* 2519 */ "G_CTTZ_ZERO_UNDEF\0"
  /* 2537 */ "INIT_UNDEF\0"
  /* 2548 */ "G_IMPLICIT_DEF\0"
  /* 2563 */ "DBG_INSTR_REF\0"
  /* 2577 */ "ENDIF\0"
  /* 2583 */ "TEX_VTX_CONSTBUF\0"
  /* 2600 */ "TEX_VTX_TEXBUF\0"
  /* 2615 */ "G_FNEG\0"
  /* 2622 */ "EXTRACT_SUBREG\0"
  /* 2637 */ "INSERT_SUBREG\0"
  /* 2651 */ "G_SEXT_INREG\0"
  /* 2664 */ "SUBREG_TO_REG\0"
  /* 2678 */ "CF_TC_EG\0"
  /* 2687 */ "CF_VC_EG\0"
  /* 2696 */ "CF_END_EG\0"
  /* 2706 */ "CF_ELSE_EG\0"
  /* 2717 */ "CF_CONTINUE_EG\0"
  /* 2732 */ "CF_PUSH_EG\0"
  /* 2743 */ "LOOP_BREAK_EG\0"
  /* 2757 */ "CF_JUMP_EG\0"
  /* 2768 */ "END_LOOP_EG\0"
  /* 2780 */ "WHILE_LOOP_EG\0"
  /* 2794 */ "POP_EG\0"
  /* 2801 */ "CF_CALL_FS_EG\0"
  /* 2815 */ "G_ATOMIC_CMPXCHG\0"
  /* 2832 */ "LDS_WRXCHG\0"
  /* 2843 */ "G_ATOMICRMW_XCHG\0"
  /* 2860 */ "G_FLOG\0"
  /* 2867 */ "G_VAARG\0"
  /* 2875 */ "PREALLOCATED_ARG\0"
  /* 2892 */ "TEX_SAMPLE_C_G\0"
  /* 2907 */ "TEX_SAMPLE_G\0"
  /* 2920 */ "BRANCH\0"
  /* 2927 */ "G_PREFETCH\0"
  /* 2938 */ "ENDSWITCH\0"
  /* 2948 */ "G_SMULH\0"
  /* 2956 */ "G_UMULH\0"
  /* 2964 */ "G_FTANH\0"
  /* 2972 */ "G_FSINH\0"
  /* 2980 */ "G_FCOSH\0"
  /* 2988 */ "TEX_GET_GRADIENTS_H\0"
  /* 3008 */ "TEX_SET_GRADIENTS_H\0"
  /* 3028 */ "DBG_PHI\0"
  /* 3036 */ "G_FPTOSI\0"
  /* 3045 */ "G_FPTOUI\0"
  /* 3054 */ "G_FPOWI\0"
  /* 3062 */ "CF_ALU_BREAK\0"
  /* 3075 */ "G_PTRMASK\0"
  /* 3085 */ "GC_LABEL\0"
  /* 3094 */ "DBG_LABEL\0"
  /* 3104 */ "EH_LABEL\0"
  /* 3113 */ "ANNOTATION_LABEL\0"
  /* 3130 */ "ICALL_BRANCH_FUNNEL\0"
  /* 3150 */ "G_FSHL\0"
  /* 3157 */ "G_SHL\0"
  /* 3163 */ "G_FCEIL\0"
  /* 3171 */ "PATCHABLE_TAIL_CALL\0"
  /* 3191 */ "PATCHABLE_TYPED_EVENT_CALL\0"
  /* 3218 */ "PATCHABLE_EVENT_CALL\0"
  /* 3239 */ "FENTRY_CALL\0"
  /* 3251 */ "KILL\0"
  /* 3256 */ "G_CONSTANT_POOL\0"
  /* 3272 */ "G_ROTL\0"
  /* 3279 */ "G_VECREDUCE_FMUL\0"
  /* 3296 */ "G_FMUL\0"
  /* 3303 */ "G_VECREDUCE_SEQ_FMUL\0"
  /* 3324 */ "G_STRICT_FMUL\0"
  /* 3338 */ "G_VECREDUCE_MUL\0"
  /* 3354 */ "G_MUL\0"
  /* 3360 */ "TEX_SAMPLE_C_L\0"
  /* 3375 */ "TEX_SAMPLE_L\0"
  /* 3388 */ "CF_END_CM\0"
  /* 3398 */ "G_FREM\0"
  /* 3405 */ "G_STRICT_FREM\0"
  /* 3419 */ "G_SREM\0"
  /* 3426 */ "G_UREM\0"
  /* 3433 */ "G_SDIVREM\0"
  /* 3443 */ "G_UDIVREM\0"
  /* 3453 */ "INLINEASM\0"
  /* 3463 */ "G_VECREDUCE_FMINIMUM\0"
  /* 3484 */ "G_FMINIMUM\0"
  /* 3495 */ "G_VECREDUCE_FMAXIMUM\0"
  /* 3516 */ "G_FMAXIMUM\0"
  /* 3527 */ "G_FMINNUM\0"
  /* 3537 */ "G_FMAXNUM\0"
  /* 3547 */ "G_FATAN\0"
  /* 3555 */ "G_FTAN\0"
  /* 3562 */ "G_INTRINSIC_ROUNDEVEN\0"
  /* 3584 */ "G_ASSERT_ALIGN\0"
  /* 3599 */ "G_FCOPYSIGN\0"
  /* 3611 */ "DUMMY_CHAIN\0"
  /* 3623 */ "ENDMAIN\0"
  /* 3631 */ "G_VECREDUCE_FMIN\0"
  /* 3648 */ "G_ATOMICRMW_FMIN\0"
  /* 3665 */ "G_VECREDUCE_SMIN\0"
  /* 3682 */ "G_SMIN\0"
  /* 3689 */ "G_VECREDUCE_UMIN\0"
  /* 3706 */ "G_UMIN\0"
  /* 3713 */ "G_ATOMICRMW_UMIN\0"
  /* 3730 */ "G_ATOMICRMW_MIN\0"
  /* 3746 */ "G_FASIN\0"
  /* 3754 */ "G_FSIN\0"
  /* 3761 */ "CFI_INSTRUCTION\0"
  /* 3777 */ "RETURN\0"
  /* 3784 */ "RAT_ATOMIC_RSUB_RTN\0"
  /* 3804 */ "RAT_ATOMIC_SUB_RTN\0"
  /* 3823 */ "RAT_ATOMIC_ADD_RTN\0"
  /* 3842 */ "RAT_ATOMIC_AND_RTN\0"
  /* 3861 */ "RAT_ATOMIC_XOR_RTN\0"
  /* 3880 */ "RAT_ATOMIC_OR_RTN\0"
  /* 3898 */ "RAT_ATOMIC_DEC_UINT_RTN\0"
  /* 3922 */ "RAT_ATOMIC_INC_UINT_RTN\0"
  /* 3946 */ "RAT_ATOMIC_MIN_UINT_RTN\0"
  /* 3970 */ "RAT_ATOMIC_MAX_UINT_RTN\0"
  /* 3994 */ "RAT_ATOMIC_CMPXCHG_INT_RTN\0"
  /* 4021 */ "RAT_ATOMIC_XCHG_INT_RTN\0"
  /* 4045 */ "RAT_ATOMIC_MIN_INT_RTN\0"
  /* 4068 */ "RAT_ATOMIC_MAX_INT_RTN\0"
  /* 4091 */ "RETDYN\0"
  /* 4098 */ "G_SSUBO\0"
  /* 4106 */ "G_USUBO\0"
  /* 4114 */ "G_SADDO\0"
  /* 4122 */ "G_UADDO\0"
  /* 4130 */ "TEX_GET_TEXTURE_RESINFO\0"
  /* 4154 */ "JUMP_TABLE_DEBUG_INFO\0"
  /* 4176 */ "G_SMULO\0"
  /* 4184 */ "G_UMULO\0"
  /* 4192 */ "G_BZERO\0"
  /* 4200 */ "STACKMAP\0"
  /* 4209 */ "G_DEBUGTRAP\0"
  /* 4221 */ "G_UBSANTRAP\0"
  /* 4233 */ "G_TRAP\0"
  /* 4240 */ "G_ATOMICRMW_UDEC_WRAP\0"
  /* 4262 */ "G_ATOMICRMW_UINC_WRAP\0"
  /* 4284 */ "G_BSWAP\0"
  /* 4292 */ "G_SITOFP\0"
  /* 4301 */ "G_UITOFP\0"
  /* 4310 */ "G_FCMP\0"
  /* 4317 */ "G_ICMP\0"
  /* 4324 */ "G_SCMP\0"
  /* 4331 */ "G_UCMP\0"
  /* 4338 */ "JUMP\0"
  /* 4343 */ "ENDLOOP\0"
  /* 4351 */ "WHILELOOP\0"
  /* 4361 */ "CONVERGENCECTRL_LOOP\0"
  /* 4382 */ "G_CTPOP\0"
  /* 4390 */ "PATCHABLE_OP\0"
  /* 4403 */ "FAULTING_OP\0"
  /* 4415 */ "PREALLOCATED_SETUP\0"
  /* 4434 */ "G_FLDEXP\0"
  /* 4443 */ "G_STRICT_FLDEXP\0"
  /* 4459 */ "G_FEXP\0"
  /* 4466 */ "G_FFREXP\0"
  /* 4475 */ "G_BR\0"
  /* 4480 */ "INLINEASM_BR\0"
  /* 4493 */ "G_BLOCK_ADDR\0"
  /* 4506 */ "MOV_IMM_GLOBAL_ADDR\0"
  /* 4526 */ "MEMBARRIER\0"
  /* 4537 */ "G_CONSTANT_FOLD_BARRIER\0"
  /* 4561 */ "GROUP_BARRIER\0"
  /* 4575 */ "CF_ALU_ELSE_AFTER\0"
  /* 4593 */ "CF_ALU_POP_AFTER\0"
  /* 4610 */ "PATCHABLE_FUNCTION_ENTER\0"
  /* 4635 */ "G_READCYCLECOUNTER\0"
  /* 4654 */ "G_READSTEADYCOUNTER\0"
  /* 4674 */ "G_READ_REGISTER\0"
  /* 4690 */ "G_WRITE_REGISTER\0"
  /* 4707 */ "G_ASHR\0"
  /* 4714 */ "G_FSHR\0"
  /* 4721 */ "G_LSHR\0"
  /* 4728 */ "CONVERGENCECTRL_ANCHOR\0"
  /* 4751 */ "RAT_MSKOR\0"
  /* 4761 */ "G_FFLOOR\0"
  /* 4770 */ "G_EXTRACT_SUBVECTOR\0"
  /* 4790 */ "G_INSERT_SUBVECTOR\0"
  /* 4809 */ "G_BUILD_VECTOR\0"
  /* 4824 */ "G_SHUFFLE_VECTOR\0"
  /* 4841 */ "G_SPLAT_VECTOR\0"
  /* 4856 */ "G_VECREDUCE_XOR\0"
  /* 4872 */ "G_XOR\0"
  /* 4878 */ "LDS_XOR\0"
  /* 4886 */ "G_ATOMICRMW_XOR\0"
  /* 4902 */ "G_VECREDUCE_OR\0"
  /* 4917 */ "G_OR\0"
  /* 4922 */ "LDS_OR\0"
  /* 4929 */ "G_ATOMICRMW_OR\0"
  /* 4944 */ "G_ROTR\0"
  /* 4951 */ "TEX_LDPTR\0"
  /* 4961 */ "G_INTTOPTR\0"
  /* 4972 */ "G_FABS\0"
  /* 4979 */ "G_ABS\0"
  /* 4985 */ "G_UNMERGE_VALUES\0"
  /* 5002 */ "G_MERGE_VALUES\0"
  /* 5017 */ "LITERALS\0"
  /* 5026 */ "G_FACOS\0"
  /* 5034 */ "G_FCOS\0"
  /* 5041 */ "G_CONCAT_VECTORS\0"
  /* 5058 */ "COPY_TO_REGCLASS\0"
  /* 5075 */ "G_IS_FPCLASS\0"
  /* 5088 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
  /* 5118 */ "G_VECTOR_COMPRESS\0"
  /* 5136 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
  /* 5163 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
  /* 5201 */ "G_SSUBSAT\0"
  /* 5211 */ "G_USUBSAT\0"
  /* 5221 */ "G_SADDSAT\0"
  /* 5231 */ "G_UADDSAT\0"
  /* 5241 */ "G_SSHLSAT\0"
  /* 5251 */ "G_USHLSAT\0"
  /* 5261 */ "G_SMULFIXSAT\0"
  /* 5274 */ "G_UMULFIXSAT\0"
  /* 5287 */ "G_SDIVFIXSAT\0"
  /* 5300 */ "G_UDIVFIXSAT\0"
  /* 5313 */ "G_ATOMICRMW_USUB_SAT\0"
  /* 5334 */ "G_FPTOSI_SAT\0"
  /* 5347 */ "G_FPTOUI_SAT\0"
  /* 5360 */ "FRACT\0"
  /* 5366 */ "G_EXTRACT\0"
  /* 5376 */ "G_SELECT\0"
  /* 5385 */ "G_BRINDIRECT\0"
  /* 5398 */ "RAT_ATOMIC_RSUB_NORET\0"
  /* 5420 */ "RAT_ATOMIC_SUB_NORET\0"
  /* 5441 */ "RAT_ATOMIC_ADD_NORET\0"
  /* 5462 */ "RAT_ATOMIC_AND_NORET\0"
  /* 5483 */ "RAT_ATOMIC_XOR_NORET\0"
  /* 5504 */ "RAT_ATOMIC_OR_NORET\0"
  /* 5524 */ "RAT_ATOMIC_DEC_UINT_NORET\0"
  /* 5550 */ "RAT_ATOMIC_INC_UINT_NORET\0"
  /* 5576 */ "RAT_ATOMIC_MIN_UINT_NORET\0"
  /* 5602 */ "RAT_ATOMIC_MAX_UINT_NORET\0"
  /* 5628 */ "RAT_ATOMIC_CMPXCHG_INT_NORET\0"
  /* 5657 */ "RAT_ATOMIC_XCHG_INT_NORET\0"
  /* 5683 */ "RAT_ATOMIC_MIN_INT_NORET\0"
  /* 5708 */ "RAT_ATOMIC_MAX_INT_NORET\0"
  /* 5733 */ "LDS_SUB_RET\0"
  /* 5745 */ "LDS_UBYTE_READ_RET\0"
  /* 5764 */ "LDS_BYTE_READ_RET\0"
  /* 5782 */ "LDS_READ_RET\0"
  /* 5795 */ "LDS_USHORT_READ_RET\0"
  /* 5815 */ "LDS_SHORT_READ_RET\0"
  /* 5834 */ "LDS_ADD_RET\0"
  /* 5846 */ "LDS_AND_RET\0"
  /* 5858 */ "PATCHABLE_RET\0"
  /* 5872 */ "LDS_WRXCHG_RET\0"
  /* 5887 */ "LDS_XOR_RET\0"
  /* 5899 */ "LDS_OR_RET\0"
  /* 5910 */ "LDS_MIN_UINT_RET\0"
  /* 5927 */ "LDS_MAX_UINT_RET\0"
  /* 5944 */ "LDS_MIN_INT_RET\0"
  /* 5960 */ "LDS_MAX_INT_RET\0"
  /* 5976 */ "LDS_CMPST_RET\0"
  /* 5990 */ "G_MEMSET\0"
  /* 5999 */ "IF_PREDICATE_SET\0"
  /* 6016 */ "KILLGT\0"
  /* 6023 */ "SGT\0"
  /* 6027 */ "PRED_SETGT\0"
  /* 6038 */ "PATCHABLE_FUNCTION_EXIT\0"
  /* 6062 */ "G_BRJT\0"
  /* 6069 */ "G_EXTRACT_VECTOR_ELT\0"
  /* 6090 */ "G_INSERT_VECTOR_ELT\0"
  /* 6110 */ "DEFAULT\0"
  /* 6118 */ "G_FCONSTANT\0"
  /* 6130 */ "G_CONSTANT\0"
  /* 6141 */ "G_INTRINSIC_CONVERGENT\0"
  /* 6164 */ "STATEPOINT\0"
  /* 6175 */ "PATCHPOINT\0"
  /* 6186 */ "G_PTRTOINT\0"
  /* 6197 */ "G_FRINT\0"
  /* 6205 */ "G_INTRINSIC_LLRINT\0"
  /* 6224 */ "G_INTRINSIC_LRINT\0"
  /* 6242 */ "SUBB_UINT\0"
  /* 6252 */ "ADDC_UINT\0"
  /* 6262 */ "SETGE_UINT\0"
  /* 6273 */ "FFBH_UINT\0"
  /* 6283 */ "LDS_MIN_UINT\0"
  /* 6296 */ "SETGT_UINT\0"
  /* 6307 */ "LDS_MAX_UINT\0"
  /* 6320 */ "G_FNEARBYINT\0"
  /* 6333 */ "SUB_INT\0"
  /* 6341 */ "ADD_INT\0"
  /* 6349 */ "AND_INT\0"
  /* 6357 */ "CNDE_INT\0"
  /* 6366 */ "CNDGE_INT\0"
  /* 6376 */ "PRED_SETGE_INT\0"
  /* 6391 */ "PRED_SETNE_INT\0"
  /* 6406 */ "PRED_SETE_INT\0"
  /* 6420 */ "FFBL_INT\0"
  /* 6429 */ "LDS_MIN_INT\0"
  /* 6441 */ "XOR_INT\0"
  /* 6449 */ "CNDGT_INT\0"
  /* 6459 */ "PRED_SETGT_INT\0"
  /* 6474 */ "BCNT_INT\0"
  /* 6483 */ "NOT_INT\0"
  /* 6491 */ "LDS_MAX_INT\0"
  /* 6503 */ "G_VASTART\0"
  /* 6513 */ "LIFETIME_START\0"
  /* 6528 */ "G_INVOKE_REGION_START\0"
  /* 6550 */ "G_INSERT\0"
  /* 6559 */ "G_FSQRT\0"
  /* 6567 */ "G_STRICT_FSQRT\0"
  /* 6582 */ "G_BITCAST\0"
  /* 6592 */ "G_ADDRSPACE_CAST\0"
  /* 6609 */ "DBG_VALUE_LIST\0"
  /* 6624 */ "LDS_CMPST\0"
  /* 6634 */ "G_FPEXT\0"
  /* 6642 */ "G_SEXT\0"
  /* 6649 */ "G_ASSERT_SEXT\0"
  /* 6663 */ "G_ANYEXT\0"
  /* 6672 */ "G_ZEXT\0"
  /* 6679 */ "G_ASSERT_ZEXT\0"
  /* 6693 */ "CF_ALU\0"
  /* 6700 */ "G_FDIV\0"
  /* 6707 */ "G_STRICT_FDIV\0"
  /* 6721 */ "G_SDIV\0"
  /* 6728 */ "G_UDIV\0"
  /* 6735 */ "G_GET_FPENV\0"
  /* 6747 */ "G_RESET_FPENV\0"
  /* 6761 */ "G_SET_FPENV\0"
  /* 6773 */ "MOV\0"
  /* 6777 */ "TEX_GET_GRADIENTS_V\0"
  /* 6797 */ "TEX_SET_GRADIENTS_V\0"
  /* 6817 */ "TXD_SHADOW\0"
  /* 6828 */ "G_FPOW\0"
  /* 6835 */ "INTERP_ZW\0"
  /* 6845 */ "INTERP_PAIR_ZW\0"
  /* 6860 */ "G_VECREDUCE_FMAX\0"
  /* 6877 */ "G_ATOMICRMW_FMAX\0"
  /* 6894 */ "G_VECREDUCE_SMAX\0"
  /* 6911 */ "G_SMAX\0"
  /* 6918 */ "G_VECREDUCE_UMAX\0"
  /* 6935 */ "G_UMAX\0"
  /* 6942 */ "G_ATOMICRMW_UMAX\0"
  /* 6959 */ "G_ATOMICRMW_MAX\0"
  /* 6975 */ "G_FRAME_INDEX\0"
  /* 6989 */ "G_SBFX\0"
  /* 6996 */ "G_UBFX\0"
  /* 7003 */ "G_SMULFIX\0"
  /* 7013 */ "G_UMULFIX\0"
  /* 7023 */ "G_SDIVFIX\0"
  /* 7033 */ "G_UDIVFIX\0"
  /* 7043 */ "PRED_X\0"
  /* 7050 */ "G_MEMCPY\0"
  /* 7059 */ "CONST_COPY\0"
  /* 7070 */ "CONVERGENCECTRL_ENTRY\0"
  /* 7092 */ "INTERP_XY\0"
  /* 7102 */ "INTERP_PAIR_XY\0"
  /* 7117 */ "G_CTLZ\0"
  /* 7124 */ "G_CTTZ\0"
  /* 7131 */ "R600_RegisterLoad\0"
  /* 7149 */ "R600_RegisterStore\0"
  /* 7168 */ "R600_ExportBuf\0"
  /* 7183 */ "EG_ExportBuf\0"
  /* 7196 */ "VTX_READ_32_eg\0"
  /* 7211 */ "RAT_WRITE_CACHELESS_32_eg\0"
  /* 7237 */ "MULADD_UINT24_eg\0"
  /* 7254 */ "MULHI_UINT24_eg\0"
  /* 7270 */ "MUL_UINT24_eg\0"
  /* 7284 */ "VTX_READ_64_eg\0"
  /* 7299 */ "RAT_WRITE_CACHELESS_64_eg\0"
  /* 7325 */ "DOT4_eg\0"
  /* 7333 */ "VTX_READ_16_eg\0"
  /* 7348 */ "VTX_READ_128_eg\0"
  /* 7364 */ "RAT_WRITE_CACHELESS_128_eg\0"
  /* 7391 */ "VTX_READ_8_eg\0"
  /* 7405 */ "FMA_eg\0"
  /* 7412 */ "MULADD_eg\0"
  /* 7422 */ "LOG_CLAMPED_eg\0"
  /* 7437 */ "RECIP_CLAMPED_eg\0"
  /* 7454 */ "RECIPSQRT_CLAMPED_eg\0"
  /* 7475 */ "RAT_STORE_TYPED_eg\0"
  /* 7494 */ "CNDE_eg\0"
  /* 7502 */ "MULADD_IEEE_eg\0"
  /* 7517 */ "LOG_IEEE_eg\0"
  /* 7529 */ "RECIP_IEEE_eg\0"
  /* 7543 */ "EXP_IEEE_eg\0"
  /* 7555 */ "RECIPSQRT_IEEE_eg\0"
  /* 7573 */ "CNDGE_eg\0"
  /* 7582 */ "LSHL_eg\0"
  /* 7590 */ "SIN_eg\0"
  /* 7597 */ "ASHR_eg\0"
  /* 7605 */ "LSHR_eg\0"
  /* 7613 */ "COS_eg\0"
  /* 7620 */ "CNDGT_eg\0"
  /* 7629 */ "MUL_LIT_eg\0"
  /* 7640 */ "UINT_TO_FLT_eg\0"
  /* 7655 */ "BFE_UINT_eg\0"
  /* 7667 */ "MULHI_UINT_eg\0"
  /* 7681 */ "MULLO_UINT_eg\0"
  /* 7695 */ "FLT_TO_UINT_eg\0"
  /* 7710 */ "RECIP_UINT_eg\0"
  /* 7724 */ "MOVA_INT_eg\0"
  /* 7736 */ "BFE_INT_eg\0"
  /* 7747 */ "BFI_INT_eg\0"
  /* 7758 */ "MULHI_INT_eg\0"
  /* 7771 */ "BFM_INT_eg\0"
  /* 7782 */ "BIT_ALIGN_INT_eg\0"
  /* 7799 */ "MULLO_INT_eg\0"
  /* 7812 */ "FLT_TO_INT_eg\0"
  /* 7826 */ "CUBE_r600_real\0"
  /* 7841 */ "CUBE_eg_real\0"
  /* 7854 */ "VTX_READ_32_cm\0"
  /* 7869 */ "MULADD_INT24_cm\0"
  /* 7885 */ "MUL_INT24_cm\0"
  /* 7898 */ "VTX_READ_64_cm\0"
  /* 7913 */ "VTX_READ_16_cm\0"
  /* 7928 */ "VTX_READ_128_cm\0"
  /* 7944 */ "VTX_READ_8_cm\0"
  /* 7958 */ "RECIP_CLAMPED_cm\0"
  /* 7975 */ "RECIPSQRT_CLAMPED_cm\0"
  /* 7996 */ "RAT_STORE_TYPED_cm\0"
  /* 8015 */ "LOG_IEEE_cm\0"
  /* 8027 */ "RECIP_IEEE_cm\0"
  /* 8041 */ "EXP_IEEE_cm\0"
  /* 8053 */ "RECIPSQRT_IEEE_cm\0"
  /* 8071 */ "SIN_cm\0"
  /* 8078 */ "COS_cm\0"
  /* 8085 */ "MULHI_UINT_cm\0"
  /* 8099 */ "MULLO_UINT_cm\0"
  /* 8113 */ "MULHI_INT_cm\0"
  /* 8126 */ "MULLO_INT_cm\0"
  /* 8139 */ "CUBE_r600_pseudo\0"
  /* 8156 */ "CUBE_eg_pseudo\0"
  /* 8171 */ "R600_ExportSwz\0"
  /* 8186 */ "EG_ExportSwz\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const unsigned R600InstrNameIndices[] = {
    3032U, 3453U, 4480U, 3761U, 3104U, 3085U, 3113U, 3251U, 
    2622U, 2637U, 2550U, 2537U, 2664U, 5058U, 2369U, 6609U, 
    2563U, 3028U, 3094U, 1984U, 7065U, 2130U, 6513U, 1797U, 
    1935U, 1972U, 4200U, 3239U, 6175U, 1914U, 4415U, 2875U, 
    6164U, 2185U, 4403U, 4390U, 4610U, 5858U, 6038U, 3171U, 
    3218U, 3191U, 3130U, 2298U, 4526U, 4154U, 7070U, 4728U, 
    4361U, 2417U, 6649U, 6679U, 3584U, 1687U, 1349U, 3354U, 
    6721U, 6728U, 3419U, 3426U, 3433U, 3443U, 1767U, 4917U, 
    4872U, 2548U, 3030U, 6975U, 2379U, 2394U, 3256U, 5366U, 
    4985U, 6550U, 5002U, 4809U, 1435U, 5041U, 6186U, 4961U, 
    6582U, 2476U, 4537U, 1888U, 1409U, 1870U, 6224U, 6205U, 
    3562U, 4635U, 4654U, 1584U, 1512U, 1542U, 1569U, 1493U, 
    1523U, 2248U, 2232U, 5088U, 2815U, 2843U, 1711U, 1363U, 
    1781U, 1734U, 4929U, 4886U, 6959U, 3730U, 6942U, 3713U, 
    1654U, 1332U, 6877U, 3648U, 4262U, 4240U, 1819U, 5313U, 
    1964U, 2927U, 1810U, 5385U, 6528U, 1379U, 5136U, 6141U, 
    5163U, 6663U, 1427U, 6130U, 6118U, 6503U, 2867U, 6642U, 
    2651U, 6672U, 3157U, 4721U, 4707U, 3150U, 4714U, 4944U, 
    3272U, 4317U, 4310U, 4324U, 4331U, 5376U, 4122U, 2005U, 
    4106U, 1956U, 4114U, 1997U, 4098U, 1948U, 4184U, 4176U, 
    2956U, 2948U, 5231U, 5221U, 5211U, 5201U, 5251U, 5241U, 
    7003U, 7013U, 5261U, 5274U, 7023U, 7033U, 5287U, 5300U, 
    1612U, 1311U, 3296U, 1262U, 1486U, 6700U, 3398U, 6828U, 
    3054U, 4459U, 1087U, 596U, 2860U, 1070U, 587U, 4434U, 
    4466U, 2615U, 6634U, 1399U, 3036U, 3045U, 4292U, 4301U, 
    5334U, 5347U, 4972U, 3599U, 5075U, 2485U, 3527U, 3537U, 
    2063U, 2078U, 3484U, 3516U, 6735U, 6761U, 6747U, 2013U, 
    2041U, 2026U, 1693U, 3075U, 3682U, 6911U, 3706U, 6935U, 
    4979U, 1861U, 1851U, 4475U, 6062U, 2108U, 4790U, 4770U, 
    6090U, 6069U, 4824U, 4841U, 5118U, 7124U, 2519U, 7117U, 
    2501U, 4382U, 4284U, 2261U, 3163U, 5034U, 3754U, 3555U, 
    5026U, 3746U, 3547U, 1078U, 2980U, 2972U, 2964U, 6559U, 
    4761U, 6197U, 6320U, 6592U, 4493U, 2117U, 1456U, 2454U, 
    2217U, 1640U, 1318U, 3324U, 6707U, 3405U, 1268U, 6567U, 
    4443U, 4674U, 4690U, 7050U, 2154U, 2466U, 5990U, 4192U, 
    4233U, 4209U, 4221U, 1619U, 3303U, 1595U, 3279U, 6860U, 
    3631U, 3495U, 3463U, 1671U, 3338U, 1751U, 4902U, 4856U, 
    6894U, 3665U, 6918U, 3689U, 6989U, 6996U, 2920U, 771U, 
    937U, 3069U, 760U, 926U, 884U, 1050U, 825U, 991U, 
    7059U, 2445U, 738U, 904U, 844U, 1010U, 787U, 953U, 
    8156U, 8139U, 6110U, 1222U, 3611U, 2256U, 1806U, 1391U, 
    2577U, 4343U, 3623U, 2938U, 160U, 82U, 1394U, 752U, 
    918U, 867U, 1033U, 809U, 975U, 5999U, 4338U, 1841U, 
    2332U, 699U, 4506U, 711U, 7043U, 1095U, 1183U, 1115U, 
    1203U, 7131U, 7149U, 4091U, 3777U, 1931U, 6817U, 4351U, 
    1608U, 6252U, 6341U, 2287U, 6349U, 7597U, 388U, 6474U, 
    7736U, 7655U, 7747U, 7771U, 7782U, 3166U, 6693U, 3062U, 
    2438U, 4575U, 4593U, 2198U, 2801U, 170U, 2717U, 65U, 
    2706U, 34U, 3388U, 2696U, 22U, 2757U, 108U, 2732U, 
    47U, 2678U, 0U, 2687U, 11U, 6357U, 7494U, 267U, 
    6366U, 7573U, 358U, 6449U, 7620U, 417U, 8078U, 7613U, 
    408U, 578U, 7841U, 7826U, 7325U, 186U, 7183U, 8186U, 
    2768U, 121U, 8041U, 7543U, 324U, 2274U, 6273U, 6420U, 
    4764U, 723U, 1228U, 7812U, 553U, 7695U, 490U, 7405U, 
    5360U, 4561U, 666U, 7102U, 6845U, 1553U, 7092U, 6835U, 
    7641U, 442U, 6016U, 1703U, 5834U, 1773U, 5846U, 5764U, 
    2317U, 6624U, 5976U, 6491U, 5960U, 6307U, 5927U, 6429U, 
    5944U, 6283U, 5910U, 4922U, 5899U, 5782U, 5815U, 2353U, 
    1355U, 5733U, 5745U, 5795U, 2343U, 2832U, 5872U, 4878U, 
    5887U, 5017U, 7422U, 208U, 8015U, 7517U, 294U, 2743U, 
    92U, 7582U, 369U, 7605U, 398U, 6873U, 657U, 6495U, 
    6311U, 3644U, 637U, 6433U, 6287U, 6773U, 7724U, 3292U, 
    7502U, 277U, 7869U, 7237U, 7412U, 196U, 8113U, 1150U, 
    7758U, 523U, 7254U, 8085U, 1134U, 7667U, 458U, 8126U, 
    7799U, 538U, 8099U, 7681U, 474U, 2054U, 7885U, 7629U, 
    428U, 7270U, 6483U, 6442U, 1591U, 2794U, 151U, 2307U, 
    6406U, 2097U, 6376U, 6027U, 6459U, 2174U, 6391U, 7168U, 
    8171U, 5441U, 3823U, 5462U, 3842U, 5628U, 3994U, 5524U, 
    3898U, 5550U, 3922U, 5708U, 4068U, 5602U, 3970U, 5683U, 
    4045U, 5576U, 3946U, 5504U, 3880U, 5398U, 3784U, 5420U, 
    3804U, 5657U, 4021U, 5483U, 3861U, 4751U, 1243U, 681U, 
    1165U, 7996U, 7475U, 7364U, 7211U, 7299U, 7975U, 7454U, 
    244U, 8053U, 7555U, 338U, 7958U, 7437U, 225U, 8027U, 
    7529U, 308U, 7710U, 507U, 2148U, 2312U, 627U, 6411U, 
    605U, 6381U, 6262U, 646U, 6464U, 6296U, 616U, 6396U, 
    2093U, 6023U, 8071U, 7590U, 379U, 569U, 2170U, 6242U, 
    6333U, 2988U, 6777U, 4130U, 1727U, 4951U, 2137U, 1473U, 
    2892U, 3360U, 1281U, 2907U, 3375U, 1297U, 3008U, 6797U, 
    2583U, 2600U, 1403U, 7640U, 441U, 7928U, 7348U, 7913U, 
    7333U, 7854U, 7196U, 7898U, 7284U, 7944U, 7391U, 2780U, 
    135U, 6441U, 
};

static inline void InitR600MCInstrInfo(MCInstrInfo *II) {
  II->InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 642);
}

} // end namespace llvm
#endif // GET_INSTRINFO_MC_DESC

#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER
namespace llvm {
struct R600GenInstrInfo : public TargetInstrInfo {
  explicit R600GenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
  ~R600GenInstrInfo() override = default;

};
} // end namespace llvm
#endif // GET_INSTRINFO_HEADER

#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS


#endif // GET_INSTRINFO_HELPER_DECLS

#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS

#endif // GET_INSTRINFO_HELPERS

#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR
namespace llvm {
extern const R600InstrTable R600Descs;
extern const unsigned R600InstrNameIndices[];
extern const char R600InstrNameData[];
R600GenInstrInfo::R600GenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
  InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 642);
}
} // end namespace llvm
#endif // GET_INSTRINFO_CTOR_DTOR

#ifdef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_OPERAND_ENUM
namespace llvm {
namespace R600 {
namespace OpName {
enum { … };
} // end namespace OpName
} // end namespace R600
} // end namespace llvm
#endif //GET_INSTRINFO_OPERAND_ENUM

#ifdef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_NAMED_OPS
namespace llvm {
namespace R600 {
LLVM_READONLY
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
  static const int16_t OperandMap [][107] = {
{0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
{0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 7, 8, -1, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
{0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 10, 11, -1, 12, 7, -1, 8, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
{0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, -1, -1, -1, -1, -1, 4, 5, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
{0, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 4, 5, -1, 6, 7, 8, 9, -1, 10, 15, 16, 17, 18, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
{0, 5, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 6, 7, 8, 9, -1, -1, -1, -1, -1, 10, 11, 12, 13, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
{0, 7, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
{0, -1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
{0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
{-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 6, 7, -1, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
{-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 9, 10, -1, 11, 6, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, },
};
  switch(Opcode) {
  case R600::CUBE_eg_pseudo:
  case R600::CUBE_r600_pseudo:
    return OperandMap[0][NamedIdx];
  case R600::LDS_ADD_RET:
  case R600::LDS_AND_RET:
  case R600::LDS_MAX_INT_RET:
  case R600::LDS_MAX_UINT_RET:
  case R600::LDS_MIN_INT_RET:
  case R600::LDS_MIN_UINT_RET:
  case R600::LDS_OR_RET:
  case R600::LDS_SUB_RET:
  case R600::LDS_WRXCHG_RET:
  case R600::LDS_XOR_RET:
    return OperandMap[1][NamedIdx];
  case R600::LDS_CMPST_RET:
    return OperandMap[2][NamedIdx];
  case R600::LDS_BYTE_READ_RET:
  case R600::LDS_READ_RET:
  case R600::LDS_SHORT_READ_RET:
  case R600::LDS_UBYTE_READ_RET:
  case R600::LDS_USHORT_READ_RET:
    return OperandMap[3][NamedIdx];
  case R600::BFE_INT_eg:
  case R600::BFE_UINT_eg:
  case R600::BFI_INT_eg:
  case R600::BIT_ALIGN_INT_eg:
  case R600::CNDE_INT:
  case R600::CNDE_eg:
  case R600::CNDE_r600:
  case R600::CNDGE_INT:
  case R600::CNDGE_eg:
  case R600::CNDGE_r600:
  case R600::CNDGT_INT:
  case R600::CNDGT_eg:
  case R600::CNDGT_r600:
  case R600::FMA_eg:
  case R600::MULADD_IEEE_eg:
  case R600::MULADD_IEEE_r600:
  case R600::MULADD_INT24_cm:
  case R600::MULADD_UINT24_eg:
  case R600::MULADD_eg:
  case R600::MULADD_r600:
  case R600::MUL_LIT_eg:
  case R600::MUL_LIT_r600:
    return OperandMap[4][NamedIdx];
  case R600::BCNT_INT:
  case R600::CEIL:
  case R600::COS_cm:
  case R600::COS_eg:
  case R600::COS_r600:
  case R600::COS_r700:
  case R600::EXP_IEEE_cm:
  case R600::EXP_IEEE_eg:
  case R600::EXP_IEEE_r600:
  case R600::FFBH_UINT:
  case R600::FFBL_INT:
  case R600::FLOOR:
  case R600::FLT16_TO_FLT32:
  case R600::FLT32_TO_FLT16:
  case R600::FLT_TO_INT_eg:
  case R600::FLT_TO_INT_r600:
  case R600::FLT_TO_UINT_eg:
  case R600::FLT_TO_UINT_r600:
  case R600::FRACT:
  case R600::INTERP_LOAD_P0:
  case R600::INT_TO_FLT_eg:
  case R600::INT_TO_FLT_r600:
  case R600::LOG_CLAMPED_eg:
  case R600::LOG_CLAMPED_r600:
  case R600::LOG_IEEE_cm:
  case R600::LOG_IEEE_eg:
  case R600::LOG_IEEE_r600:
  case R600::MOV:
  case R600::MOVA_INT_eg:
  case R600::NOT_INT:
  case R600::RECIPSQRT_CLAMPED_cm:
  case R600::RECIPSQRT_CLAMPED_eg:
  case R600::RECIPSQRT_CLAMPED_r600:
  case R600::RECIPSQRT_IEEE_cm:
  case R600::RECIPSQRT_IEEE_eg:
  case R600::RECIPSQRT_IEEE_r600:
  case R600::RECIP_CLAMPED_cm:
  case R600::RECIP_CLAMPED_eg:
  case R600::RECIP_CLAMPED_r600:
  case R600::RECIP_IEEE_cm:
  case R600::RECIP_IEEE_eg:
  case R600::RECIP_IEEE_r600:
  case R600::RECIP_UINT_eg:
  case R600::RECIP_UINT_r600:
  case R600::RNDNE:
  case R600::SIN_cm:
  case R600::SIN_eg:
  case R600::SIN_r600:
  case R600::SIN_r700:
  case R600::TRUNC:
  case R600::UINT_TO_FLT_eg:
  case R600::UINT_TO_FLT_r600:
    return OperandMap[5][NamedIdx];
  case R600::ADD:
  case R600::ADDC_UINT:
  case R600::ADD_INT:
  case R600::AND_INT:
  case R600::ASHR_eg:
  case R600::ASHR_r600:
  case R600::BFM_INT_eg:
  case R600::CUBE_eg_real:
  case R600::CUBE_r600_real:
  case R600::DOT4_eg:
  case R600::DOT4_r600:
  case R600::INTERP_XY:
  case R600::INTERP_ZW:
  case R600::KILLGT:
  case R600::LSHL_eg:
  case R600::LSHL_r600:
  case R600::LSHR_eg:
  case R600::LSHR_r600:
  case R600::MAX:
  case R600::MAX_DX10:
  case R600::MAX_INT:
  case R600::MAX_UINT:
  case R600::MIN:
  case R600::MIN_DX10:
  case R600::MIN_INT:
  case R600::MIN_UINT:
  case R600::MUL:
  case R600::MULHI_INT_cm:
  case R600::MULHI_INT_cm24:
  case R600::MULHI_INT_eg:
  case R600::MULHI_INT_r600:
  case R600::MULHI_UINT24_eg:
  case R600::MULHI_UINT_cm:
  case R600::MULHI_UINT_cm24:
  case R600::MULHI_UINT_eg:
  case R600::MULHI_UINT_r600:
  case R600::MULLO_INT_cm:
  case R600::MULLO_INT_eg:
  case R600::MULLO_INT_r600:
  case R600::MULLO_UINT_cm:
  case R600::MULLO_UINT_eg:
  case R600::MULLO_UINT_r600:
  case R600::MUL_IEEE:
  case R600::MUL_INT24_cm:
  case R600::MUL_UINT24_eg:
  case R600::OR_INT:
  case R600::PRED_SETE:
  case R600::PRED_SETE_INT:
  case R600::PRED_SETGE:
  case R600::PRED_SETGE_INT:
  case R600::PRED_SETGT:
  case R600::PRED_SETGT_INT:
  case R600::PRED_SETNE:
  case R600::PRED_SETNE_INT:
  case R600::SETE:
  case R600::SETE_DX10:
  case R600::SETE_INT:
  case R600::SETGE_DX10:
  case R600::SETGE_INT:
  case R600::SETGE_UINT:
  case R600::SETGT_DX10:
  case R600::SETGT_INT:
  case R600::SETGT_UINT:
  case R600::SETNE_DX10:
  case R600::SETNE_INT:
  case R600::SGE:
  case R600::SGT:
  case R600::SNE:
  case R600::SUBB_UINT:
  case R600::SUB_INT:
  case R600::XOR_INT:
    return OperandMap[6][NamedIdx];
  case R600::DOT_4:
    return OperandMap[7][NamedIdx];
  case R600::R600_RegisterLoad:
    return OperandMap[8][NamedIdx];
  case R600::LDS_ADD:
  case R600::LDS_AND:
  case R600::LDS_BYTE_WRITE:
  case R600::LDS_MAX_INT:
  case R600::LDS_MAX_UINT:
  case R600::LDS_MIN_INT:
  case R600::LDS_MIN_UINT:
  case R600::LDS_OR:
  case R600::LDS_SHORT_WRITE:
  case R600::LDS_SUB:
  case R600::LDS_WRITE:
  case R600::LDS_WRXCHG:
  case R600::LDS_XOR:
    return OperandMap[9][NamedIdx];
  case R600::LDS_CMPST:
    return OperandMap[10][NamedIdx];
  case R600::R600_RegisterStore:
    return OperandMap[11][NamedIdx];
  case R600::CF_ALU:
  case R600::CF_ALU_BREAK:
  case R600::CF_ALU_CONTINUE:
  case R600::CF_ALU_ELSE_AFTER:
  case R600::CF_ALU_POP_AFTER:
  case R600::CF_ALU_PUSH_BEFORE:
    return OperandMap[12][NamedIdx];
  default: return -1;
  }
}
} // end namespace R600
} // end namespace llvm
#endif //GET_INSTRINFO_NAMED_OPS

#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
namespace llvm {
namespace R600 {
namespace OpTypes {
enum OperandType {
  ABS = 0,
  BANK_SWIZZLE = 1,
  CLAMP = 2,
  CT = 3,
  FRAMEri = 4,
  InstFlag = 5,
  KCACHE = 6,
  LAST = 7,
  LITERAL = 8,
  MEMrr = 9,
  MEMxi = 10,
  NEG = 11,
  OMOD = 12,
  R600_Pred = 13,
  REL = 14,
  RSel = 15,
  SEL = 16,
  UEM = 17,
  UP = 18,
  WRITE = 19,
  brtarget = 20,
  f32imm = 21,
  f64imm = 22,
  i1imm = 23,
  i1imm_0 = 24,
  i8imm = 25,
  i16imm = 26,
  i32imm = 27,
  i64imm = 28,
  ptype0 = 29,
  ptype1 = 30,
  ptype2 = 31,
  ptype3 = 32,
  ptype4 = 33,
  ptype5 = 34,
  s16imm = 35,
  type0 = 36,
  type1 = 37,
  type2 = 38,
  type3 = 39,
  type4 = 40,
  type5 = 41,
  u16imm = 42,
  untyped_imm_0 = 43,
  R600_Addr = 44,
  R600_Addr_W = 45,
  R600_Addr_Y = 46,
  R600_Addr_Z = 47,
  R600_ArrayBase = 48,
  R600_KC0 = 49,
  R600_KC0_W = 50,
  R600_KC0_X = 51,
  R600_KC0_Y = 52,
  R600_KC0_Z = 53,
  R600_KC1 = 54,
  R600_KC1_W = 55,
  R600_KC1_X = 56,
  R600_KC1_Y = 57,
  R600_KC1_Z = 58,
  R600_LDS_SRC_REG = 59,
  R600_Predicate = 60,
  R600_Predicate_Bit = 61,
  R600_Reg32 = 62,
  R600_Reg64 = 63,
  R600_Reg64Vertical = 64,
  R600_Reg128 = 65,
  R600_Reg128Vertical = 66,
  R600_TReg32 = 67,
  R600_TReg32_W = 68,
  R600_TReg32_X = 69,
  R600_TReg32_Y = 70,
  R600_TReg32_Z = 71,
  OPERAND_TYPE_LIST_END
};
} // end namespace OpTypes
} // end namespace R600
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM

#ifdef GET_INSTRINFO_OPERAND_TYPE
#undef GET_INSTRINFO_OPERAND_TYPE
namespace llvm {
namespace R600 {
LLVM_READONLY
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
  static const uint16_t Offsets[] = {
    /* PHI */
    0,
    /* INLINEASM */
    1,
    /* INLINEASM_BR */
    1,
    /* CFI_INSTRUCTION */
    1,
    /* EH_LABEL */
    2,
    /* GC_LABEL */
    3,
    /* ANNOTATION_LABEL */
    4,
    /* KILL */
    5,
    /* EXTRACT_SUBREG */
    5,
    /* INSERT_SUBREG */
    8,
    /* IMPLICIT_DEF */
    12,
    /* INIT_UNDEF */
    13,
    /* SUBREG_TO_REG */
    14,
    /* COPY_TO_REGCLASS */
    18,
    /* DBG_VALUE */
    21,
    /* DBG_VALUE_LIST */
    21,
    /* DBG_INSTR_REF */
    21,
    /* DBG_PHI */
    21,
    /* DBG_LABEL */
    21,
    /* REG_SEQUENCE */
    22,
    /* COPY */
    24,
    /* BUNDLE */
    26,
    /* LIFETIME_START */
    26,
    /* LIFETIME_END */
    27,
    /* PSEUDO_PROBE */
    28,
    /* ARITH_FENCE */
    32,
    /* STACKMAP */
    34,
    /* FENTRY_CALL */
    36,
    /* PATCHPOINT */
    36,
    /* LOAD_STACK_GUARD */
    42,
    /* PREALLOCATED_SETUP */
    43,
    /* PREALLOCATED_ARG */
    44,
    /* STATEPOINT */
    47,
    /* LOCAL_ESCAPE */
    47,
    /* FAULTING_OP */
    49,
    /* PATCHABLE_OP */
    50,
    /* PATCHABLE_FUNCTION_ENTER */
    50,
    /* PATCHABLE_RET */
    50,
    /* PATCHABLE_FUNCTION_EXIT */
    50,
    /* PATCHABLE_TAIL_CALL */
    50,
    /* PATCHABLE_EVENT_CALL */
    50,
    /* PATCHABLE_TYPED_EVENT_CALL */
    52,
    /* ICALL_BRANCH_FUNNEL */
    55,
    /* FAKE_USE */
    55,
    /* MEMBARRIER */
    55,
    /* JUMP_TABLE_DEBUG_INFO */
    55,
    /* CONVERGENCECTRL_ENTRY */
    56,
    /* CONVERGENCECTRL_ANCHOR */
    57,
    /* CONVERGENCECTRL_LOOP */
    58,
    /* CONVERGENCECTRL_GLUE */
    60,
    /* G_ASSERT_SEXT */
    61,
    /* G_ASSERT_ZEXT */
    64,
    /* G_ASSERT_ALIGN */
    67,
    /* G_ADD */
    70,
    /* G_SUB */
    73,
    /* G_MUL */
    76,
    /* G_SDIV */
    79,
    /* G_UDIV */
    82,
    /* G_SREM */
    85,
    /* G_UREM */
    88,
    /* G_SDIVREM */
    91,
    /* G_UDIVREM */
    95,
    /* G_AND */
    99,
    /* G_OR */
    102,
    /* G_XOR */
    105,
    /* G_IMPLICIT_DEF */
    108,
    /* G_PHI */
    109,
    /* G_FRAME_INDEX */
    110,
    /* G_GLOBAL_VALUE */
    112,
    /* G_PTRAUTH_GLOBAL_VALUE */
    114,
    /* G_CONSTANT_POOL */
    119,
    /* G_EXTRACT */
    121,
    /* G_UNMERGE_VALUES */
    124,
    /* G_INSERT */
    126,
    /* G_MERGE_VALUES */
    130,
    /* G_BUILD_VECTOR */
    132,
    /* G_BUILD_VECTOR_TRUNC */
    134,
    /* G_CONCAT_VECTORS */
    136,
    /* G_PTRTOINT */
    138,
    /* G_INTTOPTR */
    140,
    /* G_BITCAST */
    142,
    /* G_FREEZE */
    144,
    /* G_CONSTANT_FOLD_BARRIER */
    146,
    /* G_INTRINSIC_FPTRUNC_ROUND */
    148,
    /* G_INTRINSIC_TRUNC */
    151,
    /* G_INTRINSIC_ROUND */
    153,
    /* G_INTRINSIC_LRINT */
    155,
    /* G_INTRINSIC_LLRINT */
    157,
    /* G_INTRINSIC_ROUNDEVEN */
    159,
    /* G_READCYCLECOUNTER */
    161,
    /* G_READSTEADYCOUNTER */
    162,
    /* G_LOAD */
    163,
    /* G_SEXTLOAD */
    165,
    /* G_ZEXTLOAD */
    167,
    /* G_INDEXED_LOAD */
    169,
    /* G_INDEXED_SEXTLOAD */
    174,
    /* G_INDEXED_ZEXTLOAD */
    179,
    /* G_STORE */
    184,
    /* G_INDEXED_STORE */
    186,
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    191,
    /* G_ATOMIC_CMPXCHG */
    196,
    /* G_ATOMICRMW_XCHG */
    200,
    /* G_ATOMICRMW_ADD */
    203,
    /* G_ATOMICRMW_SUB */
    206,
    /* G_ATOMICRMW_AND */
    209,
    /* G_ATOMICRMW_NAND */
    212,
    /* G_ATOMICRMW_OR */
    215,
    /* G_ATOMICRMW_XOR */
    218,
    /* G_ATOMICRMW_MAX */
    221,
    /* G_ATOMICRMW_MIN */
    224,
    /* G_ATOMICRMW_UMAX */
    227,
    /* G_ATOMICRMW_UMIN */
    230,
    /* G_ATOMICRMW_FADD */
    233,
    /* G_ATOMICRMW_FSUB */
    236,
    /* G_ATOMICRMW_FMAX */
    239,
    /* G_ATOMICRMW_FMIN */
    242,
    /* G_ATOMICRMW_UINC_WRAP */
    245,
    /* G_ATOMICRMW_UDEC_WRAP */
    248,
    /* G_ATOMICRMW_USUB_COND */
    251,
    /* G_ATOMICRMW_USUB_SAT */
    254,
    /* G_FENCE */
    257,
    /* G_PREFETCH */
    259,
    /* G_BRCOND */
    263,
    /* G_BRINDIRECT */
    265,
    /* G_INVOKE_REGION_START */
    266,
    /* G_INTRINSIC */
    266,
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    267,
    /* G_INTRINSIC_CONVERGENT */
    268,
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    269,
    /* G_ANYEXT */
    270,
    /* G_TRUNC */
    272,
    /* G_CONSTANT */
    274,
    /* G_FCONSTANT */
    276,
    /* G_VASTART */
    278,
    /* G_VAARG */
    279,
    /* G_SEXT */
    282,
    /* G_SEXT_INREG */
    284,
    /* G_ZEXT */
    287,
    /* G_SHL */
    289,
    /* G_LSHR */
    292,
    /* G_ASHR */
    295,
    /* G_FSHL */
    298,
    /* G_FSHR */
    302,
    /* G_ROTR */
    306,
    /* G_ROTL */
    309,
    /* G_ICMP */
    312,
    /* G_FCMP */
    316,
    /* G_SCMP */
    320,
    /* G_UCMP */
    323,
    /* G_SELECT */
    326,
    /* G_UADDO */
    330,
    /* G_UADDE */
    334,
    /* G_USUBO */
    339,
    /* G_USUBE */
    343,
    /* G_SADDO */
    348,
    /* G_SADDE */
    352,
    /* G_SSUBO */
    357,
    /* G_SSUBE */
    361,
    /* G_UMULO */
    366,
    /* G_SMULO */
    370,
    /* G_UMULH */
    374,
    /* G_SMULH */
    377,
    /* G_UADDSAT */
    380,
    /* G_SADDSAT */
    383,
    /* G_USUBSAT */
    386,
    /* G_SSUBSAT */
    389,
    /* G_USHLSAT */
    392,
    /* G_SSHLSAT */
    395,
    /* G_SMULFIX */
    398,
    /* G_UMULFIX */
    402,
    /* G_SMULFIXSAT */
    406,
    /* G_UMULFIXSAT */
    410,
    /* G_SDIVFIX */
    414,
    /* G_UDIVFIX */
    418,
    /* G_SDIVFIXSAT */
    422,
    /* G_UDIVFIXSAT */
    426,
    /* G_FADD */
    430,
    /* G_FSUB */
    433,
    /* G_FMUL */
    436,
    /* G_FMA */
    439,
    /* G_FMAD */
    443,
    /* G_FDIV */
    447,
    /* G_FREM */
    450,
    /* G_FPOW */
    453,
    /* G_FPOWI */
    456,
    /* G_FEXP */
    459,
    /* G_FEXP2 */
    461,
    /* G_FEXP10 */
    463,
    /* G_FLOG */
    465,
    /* G_FLOG2 */
    467,
    /* G_FLOG10 */
    469,
    /* G_FLDEXP */
    471,
    /* G_FFREXP */
    474,
    /* G_FNEG */
    477,
    /* G_FPEXT */
    479,
    /* G_FPTRUNC */
    481,
    /* G_FPTOSI */
    483,
    /* G_FPTOUI */
    485,
    /* G_SITOFP */
    487,
    /* G_UITOFP */
    489,
    /* G_FPTOSI_SAT */
    491,
    /* G_FPTOUI_SAT */
    493,
    /* G_FABS */
    495,
    /* G_FCOPYSIGN */
    497,
    /* G_IS_FPCLASS */
    500,
    /* G_FCANONICALIZE */
    503,
    /* G_FMINNUM */
    505,
    /* G_FMAXNUM */
    508,
    /* G_FMINNUM_IEEE */
    511,
    /* G_FMAXNUM_IEEE */
    514,
    /* G_FMINIMUM */
    517,
    /* G_FMAXIMUM */
    520,
    /* G_GET_FPENV */
    523,
    /* G_SET_FPENV */
    524,
    /* G_RESET_FPENV */
    525,
    /* G_GET_FPMODE */
    525,
    /* G_SET_FPMODE */
    526,
    /* G_RESET_FPMODE */
    527,
    /* G_PTR_ADD */
    527,
    /* G_PTRMASK */
    530,
    /* G_SMIN */
    533,
    /* G_SMAX */
    536,
    /* G_UMIN */
    539,
    /* G_UMAX */
    542,
    /* G_ABS */
    545,
    /* G_LROUND */
    547,
    /* G_LLROUND */
    549,
    /* G_BR */
    551,
    /* G_BRJT */
    552,
    /* G_VSCALE */
    555,
    /* G_INSERT_SUBVECTOR */
    557,
    /* G_EXTRACT_SUBVECTOR */
    561,
    /* G_INSERT_VECTOR_ELT */
    564,
    /* G_EXTRACT_VECTOR_ELT */
    568,
    /* G_SHUFFLE_VECTOR */
    571,
    /* G_SPLAT_VECTOR */
    575,
    /* G_VECTOR_COMPRESS */
    577,
    /* G_CTTZ */
    581,
    /* G_CTTZ_ZERO_UNDEF */
    583,
    /* G_CTLZ */
    585,
    /* G_CTLZ_ZERO_UNDEF */
    587,
    /* G_CTPOP */
    589,
    /* G_BSWAP */
    591,
    /* G_BITREVERSE */
    593,
    /* G_FCEIL */
    595,
    /* G_FCOS */
    597,
    /* G_FSIN */
    599,
    /* G_FTAN */
    601,
    /* G_FACOS */
    603,
    /* G_FASIN */
    605,
    /* G_FATAN */
    607,
    /* G_FATAN2 */
    609,
    /* G_FCOSH */
    612,
    /* G_FSINH */
    614,
    /* G_FTANH */
    616,
    /* G_FSQRT */
    618,
    /* G_FFLOOR */
    620,
    /* G_FRINT */
    622,
    /* G_FNEARBYINT */
    624,
    /* G_ADDRSPACE_CAST */
    626,
    /* G_BLOCK_ADDR */
    628,
    /* G_JUMP_TABLE */
    630,
    /* G_DYN_STACKALLOC */
    632,
    /* G_STACKSAVE */
    635,
    /* G_STACKRESTORE */
    636,
    /* G_STRICT_FADD */
    637,
    /* G_STRICT_FSUB */
    640,
    /* G_STRICT_FMUL */
    643,
    /* G_STRICT_FDIV */
    646,
    /* G_STRICT_FREM */
    649,
    /* G_STRICT_FMA */
    652,
    /* G_STRICT_FSQRT */
    656,
    /* G_STRICT_FLDEXP */
    658,
    /* G_READ_REGISTER */
    661,
    /* G_WRITE_REGISTER */
    663,
    /* G_MEMCPY */
    665,
    /* G_MEMCPY_INLINE */
    669,
    /* G_MEMMOVE */
    672,
    /* G_MEMSET */
    676,
    /* G_BZERO */
    680,
    /* G_TRAP */
    683,
    /* G_DEBUGTRAP */
    683,
    /* G_UBSANTRAP */
    683,
    /* G_VECREDUCE_SEQ_FADD */
    684,
    /* G_VECREDUCE_SEQ_FMUL */
    687,
    /* G_VECREDUCE_FADD */
    690,
    /* G_VECREDUCE_FMUL */
    692,
    /* G_VECREDUCE_FMAX */
    694,
    /* G_VECREDUCE_FMIN */
    696,
    /* G_VECREDUCE_FMAXIMUM */
    698,
    /* G_VECREDUCE_FMINIMUM */
    700,
    /* G_VECREDUCE_ADD */
    702,
    /* G_VECREDUCE_MUL */
    704,
    /* G_VECREDUCE_AND */
    706,
    /* G_VECREDUCE_OR */
    708,
    /* G_VECREDUCE_XOR */
    710,
    /* G_VECREDUCE_SMAX */
    712,
    /* G_VECREDUCE_SMIN */
    714,
    /* G_VECREDUCE_UMAX */
    716,
    /* G_VECREDUCE_UMIN */
    718,
    /* G_SBFX */
    720,
    /* G_UBFX */
    724,
    /* BRANCH */
    728,
    /* BRANCH_COND_f32 */
    729,
    /* BRANCH_COND_i32 */
    731,
    /* BREAK */
    733,
    /* BREAKC_f32 */
    733,
    /* BREAKC_i32 */
    735,
    /* BREAK_LOGICALNZ_f32 */
    737,
    /* BREAK_LOGICALNZ_i32 */
    738,
    /* BREAK_LOGICALZ_f32 */
    739,
    /* BREAK_LOGICALZ_i32 */
    740,
    /* CONST_COPY */
    741,
    /* CONTINUE */
    743,
    /* CONTINUEC_f32 */
    743,
    /* CONTINUEC_i32 */
    745,
    /* CONTINUE_LOGICALNZ_f32 */
    747,
    /* CONTINUE_LOGICALNZ_i32 */
    748,
    /* CONTINUE_LOGICALZ_f32 */
    749,
    /* CONTINUE_LOGICALZ_i32 */
    750,
    /* CUBE_eg_pseudo */
    751,
    /* CUBE_r600_pseudo */
    753,
    /* DEFAULT */
    755,
    /* DOT_4 */
    755,
    /* DUMMY_CHAIN */
    826,
    /* ELSE */
    826,
    /* END */
    826,
    /* ENDFUNC */
    826,
    /* ENDIF */
    826,
    /* ENDLOOP */
    826,
    /* ENDMAIN */
    826,
    /* ENDSWITCH */
    826,
    /* FABS_R600 */
    826,
    /* FNEG_R600 */
    828,
    /* FUNC */
    830,
    /* IFC_f32 */
    830,
    /* IFC_i32 */
    832,
    /* IF_LOGICALNZ_f32 */
    834,
    /* IF_LOGICALNZ_i32 */
    835,
    /* IF_LOGICALZ_f32 */
    836,
    /* IF_LOGICALZ_i32 */
    837,
    /* IF_PREDICATE_SET */
    838,
    /* JUMP */
    839,
    /* JUMP_COND */
    840,
    /* MASK_WRITE */
    842,
    /* MOV_IMM_F32 */
    843,
    /* MOV_IMM_GLOBAL_ADDR */
    845,
    /* MOV_IMM_I32 */
    847,
    /* PRED_X */
    849,
    /* R600_EXTRACT_ELT_V2 */
    853,
    /* R600_EXTRACT_ELT_V4 */
    856,
    /* R600_INSERT_ELT_V2 */
    859,
    /* R600_INSERT_ELT_V4 */
    863,
    /* R600_RegisterLoad */
    867,
    /* R600_RegisterStore */
    871,
    /* RETDYN */
    875,
    /* RETURN */
    875,
    /* TXD */
    875,
    /* TXD_SHADOW */
    882,
    /* WHILELOOP */
    889,
    /* ADD */
    889,
    /* ADDC_UINT */
    910,
    /* ADD_INT */
    931,
    /* ALU_CLAUSE */
    952,
    /* AND_INT */
    953,
    /* ASHR_eg */
    974,
    /* ASHR_r600 */
    995,
    /* BCNT_INT */
    1016,
    /* BFE_INT_eg */
    1030,
    /* BFE_UINT_eg */
    1049,
    /* BFI_INT_eg */
    1068,
    /* BFM_INT_eg */
    1087,
    /* BIT_ALIGN_INT_eg */
    1108,
    /* CEIL */
    1127,
    /* CF_ALU */
    1141,
    /* CF_ALU_BREAK */
    1150,
    /* CF_ALU_CONTINUE */
    1159,
    /* CF_ALU_ELSE_AFTER */
    1168,
    /* CF_ALU_POP_AFTER */
    1177,
    /* CF_ALU_PUSH_BEFORE */
    1186,
    /* CF_CALL_FS_EG */
    1195,
    /* CF_CALL_FS_R600 */
    1195,
    /* CF_CONTINUE_EG */
    1195,
    /* CF_CONTINUE_R600 */
    1196,
    /* CF_ELSE_EG */
    1197,
    /* CF_ELSE_R600 */
    1199,
    /* CF_END_CM */
    1201,
    /* CF_END_EG */
    1201,
    /* CF_END_R600 */
    1201,
    /* CF_JUMP_EG */
    1201,
    /* CF_JUMP_R600 */
    1203,
    /* CF_PUSH_EG */
    1205,
    /* CF_PUSH_ELSE_R600 */
    1207,
    /* CF_TC_EG */
    1208,
    /* CF_TC_R600 */
    1210,
    /* CF_VC_EG */
    1212,
    /* CF_VC_R600 */
    1214,
    /* CNDE_INT */
    1216,
    /* CNDE_eg */
    1235,
    /* CNDE_r600 */
    1254,
    /* CNDGE_INT */
    1273,
    /* CNDGE_eg */
    1292,
    /* CNDGE_r600 */
    1311,
    /* CNDGT_INT */
    1330,
    /* CNDGT_eg */
    1349,
    /* CNDGT_r600 */
    1368,
    /* COS_cm */
    1387,
    /* COS_eg */
    1401,
    /* COS_r600 */
    1415,
    /* COS_r700 */
    1429,
    /* CUBE_eg_real */
    1443,
    /* CUBE_r600_real */
    1464,
    /* DOT4_eg */
    1485,
    /* DOT4_r600 */
    1506,
    /* EG_ExportBuf */
    1527,
    /* EG_ExportSwz */
    1534,
    /* END_LOOP_EG */
    1543,
    /* END_LOOP_R600 */
    1544,
    /* EXP_IEEE_cm */
    1545,
    /* EXP_IEEE_eg */
    1559,
    /* EXP_IEEE_r600 */
    1573,
    /* FETCH_CLAUSE */
    1587,
    /* FFBH_UINT */
    1588,
    /* FFBL_INT */
    1602,
    /* FLOOR */
    1616,
    /* FLT16_TO_FLT32 */
    1630,
    /* FLT32_TO_FLT16 */
    1644,
    /* FLT_TO_INT_eg */
    1658,
    /* FLT_TO_INT_r600 */
    1672,
    /* FLT_TO_UINT_eg */
    1686,
    /* FLT_TO_UINT_r600 */
    1700,
    /* FMA_eg */
    1714,
    /* FRACT */
    1733,
    /* GROUP_BARRIER */
    1747,
    /* INTERP_LOAD_P0 */
    1747,
    /* INTERP_PAIR_XY */
    1761,
    /* INTERP_PAIR_ZW */
    1766,
    /* INTERP_VEC_LOAD */
    1771,
    /* INTERP_XY */
    1773,
    /* INTERP_ZW */
    1794,
    /* INT_TO_FLT_eg */
    1815,
    /* INT_TO_FLT_r600 */
    1829,
    /* KILLGT */
    1843,
    /* LDS_ADD */
    1864,
    /* LDS_ADD_RET */
    1873,
    /* LDS_AND */
    1883,
    /* LDS_AND_RET */
    1892,
    /* LDS_BYTE_READ_RET */
    1902,
    /* LDS_BYTE_WRITE */
    1909,
    /* LDS_CMPST */
    1918,
    /* LDS_CMPST_RET */
    1930,
    /* LDS_MAX_INT */
    1943,
    /* LDS_MAX_INT_RET */
    1952,
    /* LDS_MAX_UINT */
    1962,
    /* LDS_MAX_UINT_RET */
    1971,
    /* LDS_MIN_INT */
    1981,
    /* LDS_MIN_INT_RET */
    1990,
    /* LDS_MIN_UINT */
    2000,
    /* LDS_MIN_UINT_RET */
    2009,
    /* LDS_OR */
    2019,
    /* LDS_OR_RET */
    2028,
    /* LDS_READ_RET */
    2038,
    /* LDS_SHORT_READ_RET */
    2045,
    /* LDS_SHORT_WRITE */
    2052,
    /* LDS_SUB */
    2061,
    /* LDS_SUB_RET */
    2070,
    /* LDS_UBYTE_READ_RET */
    2080,
    /* LDS_USHORT_READ_RET */
    2087,
    /* LDS_WRITE */
    2094,
    /* LDS_WRXCHG */
    2103,
    /* LDS_WRXCHG_RET */
    2112,
    /* LDS_XOR */
    2122,
    /* LDS_XOR_RET */
    2131,
    /* LITERALS */
    2141,
    /* LOG_CLAMPED_eg */
    2143,
    /* LOG_CLAMPED_r600 */
    2157,
    /* LOG_IEEE_cm */
    2171,
    /* LOG_IEEE_eg */
    2185,
    /* LOG_IEEE_r600 */
    2199,
    /* LOOP_BREAK_EG */
    2213,
    /* LOOP_BREAK_R600 */
    2214,
    /* LSHL_eg */
    2215,
    /* LSHL_r600 */
    2236,
    /* LSHR_eg */
    2257,
    /* LSHR_r600 */
    2278,
    /* MAX */
    2299,
    /* MAX_DX10 */
    2320,
    /* MAX_INT */
    2341,
    /* MAX_UINT */
    2362,
    /* MIN */
    2383,
    /* MIN_DX10 */
    2404,
    /* MIN_INT */
    2425,
    /* MIN_UINT */
    2446,
    /* MOV */
    2467,
    /* MOVA_INT_eg */
    2481,
    /* MUL */
    2495,
    /* MULADD_IEEE_eg */
    2516,
    /* MULADD_IEEE_r600 */
    2535,
    /* MULADD_INT24_cm */
    2554,
    /* MULADD_UINT24_eg */
    2573,
    /* MULADD_eg */
    2592,
    /* MULADD_r600 */
    2611,
    /* MULHI_INT_cm */
    2630,
    /* MULHI_INT_cm24 */
    2651,
    /* MULHI_INT_eg */
    2672,
    /* MULHI_INT_r600 */
    2693,
    /* MULHI_UINT24_eg */
    2714,
    /* MULHI_UINT_cm */
    2735,
    /* MULHI_UINT_cm24 */
    2756,
    /* MULHI_UINT_eg */
    2777,
    /* MULHI_UINT_r600 */
    2798,
    /* MULLO_INT_cm */
    2819,
    /* MULLO_INT_eg */
    2840,
    /* MULLO_INT_r600 */
    2861,
    /* MULLO_UINT_cm */
    2882,
    /* MULLO_UINT_eg */
    2903,
    /* MULLO_UINT_r600 */
    2924,
    /* MUL_IEEE */
    2945,
    /* MUL_INT24_cm */
    2966,
    /* MUL_LIT_eg */
    2987,
    /* MUL_LIT_r600 */
    3006,
    /* MUL_UINT24_eg */
    3025,
    /* NOT_INT */
    3046,
    /* OR_INT */
    3060,
    /* PAD */
    3081,
    /* POP_EG */
    3081,
    /* POP_R600 */
    3083,
    /* PRED_SETE */
    3085,
    /* PRED_SETE_INT */
    3106,
    /* PRED_SETGE */
    3127,
    /* PRED_SETGE_INT */
    3148,
    /* PRED_SETGT */
    3169,
    /* PRED_SETGT_INT */
    3190,
    /* PRED_SETNE */
    3211,
    /* PRED_SETNE_INT */
    3232,
    /* R600_ExportBuf */
    3253,
    /* R600_ExportSwz */
    3260,
    /* RAT_ATOMIC_ADD_NORET */
    3269,
    /* RAT_ATOMIC_ADD_RTN */
    3272,
    /* RAT_ATOMIC_AND_NORET */
    3275,
    /* RAT_ATOMIC_AND_RTN */
    3278,
    /* RAT_ATOMIC_CMPXCHG_INT_NORET */
    3281,
    /* RAT_ATOMIC_CMPXCHG_INT_RTN */
    3284,
    /* RAT_ATOMIC_DEC_UINT_NORET */
    3287,
    /* RAT_ATOMIC_DEC_UINT_RTN */
    3290,
    /* RAT_ATOMIC_INC_UINT_NORET */
    3293,
    /* RAT_ATOMIC_INC_UINT_RTN */
    3296,
    /* RAT_ATOMIC_MAX_INT_NORET */
    3299,
    /* RAT_ATOMIC_MAX_INT_RTN */
    3302,
    /* RAT_ATOMIC_MAX_UINT_NORET */
    3305,
    /* RAT_ATOMIC_MAX_UINT_RTN */
    3308,
    /* RAT_ATOMIC_MIN_INT_NORET */
    3311,
    /* RAT_ATOMIC_MIN_INT_RTN */
    3314,
    /* RAT_ATOMIC_MIN_UINT_NORET */
    3317,
    /* RAT_ATOMIC_MIN_UINT_RTN */
    3320,
    /* RAT_ATOMIC_OR_NORET */
    3323,
    /* RAT_ATOMIC_OR_RTN */
    3326,
    /* RAT_ATOMIC_RSUB_NORET */
    3329,
    /* RAT_ATOMIC_RSUB_RTN */
    3332,
    /* RAT_ATOMIC_SUB_NORET */
    3335,
    /* RAT_ATOMIC_SUB_RTN */
    3338,
    /* RAT_ATOMIC_XCHG_INT_NORET */
    3341,
    /* RAT_ATOMIC_XCHG_INT_RTN */
    3344,
    /* RAT_ATOMIC_XOR_NORET */
    3347,
    /* RAT_ATOMIC_XOR_RTN */
    3350,
    /* RAT_MSKOR */
    3353,
    /* RAT_STORE_DWORD128 */
    3355,
    /* RAT_STORE_DWORD32 */
    3357,
    /* RAT_STORE_DWORD64 */
    3359,
    /* RAT_STORE_TYPED_cm */
    3361,
    /* RAT_STORE_TYPED_eg */
    3365,
    /* RAT_WRITE_CACHELESS_128_eg */
    3369,
    /* RAT_WRITE_CACHELESS_32_eg */
    3372,
    /* RAT_WRITE_CACHELESS_64_eg */
    3375,
    /* RECIPSQRT_CLAMPED_cm */
    3378,
    /* RECIPSQRT_CLAMPED_eg */
    3392,
    /* RECIPSQRT_CLAMPED_r600 */
    3406,
    /* RECIPSQRT_IEEE_cm */
    3420,
    /* RECIPSQRT_IEEE_eg */
    3434,
    /* RECIPSQRT_IEEE_r600 */
    3448,
    /* RECIP_CLAMPED_cm */
    3462,
    /* RECIP_CLAMPED_eg */
    3476,
    /* RECIP_CLAMPED_r600 */
    3490,
    /* RECIP_IEEE_cm */
    3504,
    /* RECIP_IEEE_eg */
    3518,
    /* RECIP_IEEE_r600 */
    3532,
    /* RECIP_UINT_eg */
    3546,
    /* RECIP_UINT_r600 */
    3560,
    /* RNDNE */
    3574,
    /* SETE */
    3588,
    /* SETE_DX10 */
    3609,
    /* SETE_INT */
    3630,
    /* SETGE_DX10 */
    3651,
    /* SETGE_INT */
    3672,
    /* SETGE_UINT */
    3693,
    /* SETGT_DX10 */
    3714,
    /* SETGT_INT */
    3735,
    /* SETGT_UINT */
    3756,
    /* SETNE_DX10 */
    3777,
    /* SETNE_INT */
    3798,
    /* SGE */
    3819,
    /* SGT */
    3840,
    /* SIN_cm */
    3861,
    /* SIN_eg */
    3875,
    /* SIN_r600 */
    3889,
    /* SIN_r700 */
    3903,
    /* SNE */
    3917,
    /* SUBB_UINT */
    3938,
    /* SUB_INT */
    3959,
    /* TEX_GET_GRADIENTS_H */
    3980,
    /* TEX_GET_GRADIENTS_V */
    3999,
    /* TEX_GET_TEXTURE_RESINFO */
    4018,
    /* TEX_LD */
    4037,
    /* TEX_LDPTR */
    4056,
    /* TEX_SAMPLE */
    4075,
    /* TEX_SAMPLE_C */
    4094,
    /* TEX_SAMPLE_C_G */
    4113,
    /* TEX_SAMPLE_C_L */
    4132,
    /* TEX_SAMPLE_C_LB */
    4151,
    /* TEX_SAMPLE_G */
    4170,
    /* TEX_SAMPLE_L */
    4189,
    /* TEX_SAMPLE_LB */
    4208,
    /* TEX_SET_GRADIENTS_H */
    4227,
    /* TEX_SET_GRADIENTS_V */
    4246,
    /* TEX_VTX_CONSTBUF */
    4265,
    /* TEX_VTX_TEXBUF */
    4269,
    /* TRUNC */
    4273,
    /* UINT_TO_FLT_eg */
    4287,
    /* UINT_TO_FLT_r600 */
    4301,
    /* VTX_READ_128_cm */
    4315,
    /* VTX_READ_128_eg */
    4319,
    /* VTX_READ_16_cm */
    4323,
    /* VTX_READ_16_eg */
    4327,
    /* VTX_READ_32_cm */
    4331,
    /* VTX_READ_32_eg */
    4335,
    /* VTX_READ_64_cm */
    4339,
    /* VTX_READ_64_eg */
    4343,
    /* VTX_READ_8_cm */
    4347,
    /* VTX_READ_8_eg */
    4351,
    /* WHILE_LOOP_EG */
    4355,
    /* WHILE_LOOP_R600 */
    4356,
    /* XOR_INT */
    4357,
  };

  using namespace OpTypes;
  static const int8_t OpcodeOperandTypes[] = {
    
    /* PHI */
    -1, 
    /* INLINEASM */
    /* INLINEASM_BR */
    /* CFI_INSTRUCTION */
    i32imm, 
    /* EH_LABEL */
    i32imm, 
    /* GC_LABEL */
    i32imm, 
    /* ANNOTATION_LABEL */
    i32imm, 
    /* KILL */
    /* EXTRACT_SUBREG */
    -1, -1, i32imm, 
    /* INSERT_SUBREG */
    -1, -1, -1, i32imm, 
    /* IMPLICIT_DEF */
    -1, 
    /* INIT_UNDEF */
    -1, 
    /* SUBREG_TO_REG */
    -1, -1, -1, i32imm, 
    /* COPY_TO_REGCLASS */
    -1, -1, i32imm, 
    /* DBG_VALUE */
    /* DBG_VALUE_LIST */
    /* DBG_INSTR_REF */
    /* DBG_PHI */
    /* DBG_LABEL */
    -1, 
    /* REG_SEQUENCE */
    -1, -1, 
    /* COPY */
    -1, -1, 
    /* BUNDLE */
    /* LIFETIME_START */
    i32imm, 
    /* LIFETIME_END */
    i32imm, 
    /* PSEUDO_PROBE */
    i64imm, i64imm, i8imm, i32imm, 
    /* ARITH_FENCE */
    -1, -1, 
    /* STACKMAP */
    i64imm, i32imm, 
    /* FENTRY_CALL */
    /* PATCHPOINT */
    -1, i64imm, i32imm, -1, i32imm, i32imm, 
    /* LOAD_STACK_GUARD */
    -1, 
    /* PREALLOCATED_SETUP */
    i32imm, 
    /* PREALLOCATED_ARG */
    -1, i32imm, i32imm, 
    /* STATEPOINT */
    /* LOCAL_ESCAPE */
    -1, i32imm, 
    /* FAULTING_OP */
    -1, 
    /* PATCHABLE_OP */
    /* PATCHABLE_FUNCTION_ENTER */
    /* PATCHABLE_RET */
    /* PATCHABLE_FUNCTION_EXIT */
    /* PATCHABLE_TAIL_CALL */
    /* PATCHABLE_EVENT_CALL */
    -1, -1, 
    /* PATCHABLE_TYPED_EVENT_CALL */
    -1, -1, -1, 
    /* ICALL_BRANCH_FUNNEL */
    /* FAKE_USE */
    /* MEMBARRIER */
    /* JUMP_TABLE_DEBUG_INFO */
    i64imm, 
    /* CONVERGENCECTRL_ENTRY */
    -1, 
    /* CONVERGENCECTRL_ANCHOR */
    -1, 
    /* CONVERGENCECTRL_LOOP */
    -1, -1, 
    /* CONVERGENCECTRL_GLUE */
    -1, 
    /* G_ASSERT_SEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ZEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ALIGN */
    type0, type0, untyped_imm_0, 
    /* G_ADD */
    type0, type0, type0, 
    /* G_SUB */
    type0, type0, type0, 
    /* G_MUL */
    type0, type0, type0, 
    /* G_SDIV */
    type0, type0, type0, 
    /* G_UDIV */
    type0, type0, type0, 
    /* G_SREM */
    type0, type0, type0, 
    /* G_UREM */
    type0, type0, type0, 
    /* G_SDIVREM */
    type0, type0, type0, type0, 
    /* G_UDIVREM */
    type0, type0, type0, type0, 
    /* G_AND */
    type0, type0, type0, 
    /* G_OR */
    type0, type0, type0, 
    /* G_XOR */
    type0, type0, type0, 
    /* G_IMPLICIT_DEF */
    type0, 
    /* G_PHI */
    type0, 
    /* G_FRAME_INDEX */
    type0, -1, 
    /* G_GLOBAL_VALUE */
    type0, -1, 
    /* G_PTRAUTH_GLOBAL_VALUE */
    type0, -1, i32imm, type1, i64imm, 
    /* G_CONSTANT_POOL */
    type0, -1, 
    /* G_EXTRACT */
    type0, type1, untyped_imm_0, 
    /* G_UNMERGE_VALUES */
    type0, type1, 
    /* G_INSERT */
    type0, type0, type1, untyped_imm_0, 
    /* G_MERGE_VALUES */
    type0, type1, 
    /* G_BUILD_VECTOR */
    type0, type1, 
    /* G_BUILD_VECTOR_TRUNC */
    type0, type1, 
    /* G_CONCAT_VECTORS */
    type0, type1, 
    /* G_PTRTOINT */
    type0, type1, 
    /* G_INTTOPTR */
    type0, type1, 
    /* G_BITCAST */
    type0, type1, 
    /* G_FREEZE */
    type0, type0, 
    /* G_CONSTANT_FOLD_BARRIER */
    type0, type0, 
    /* G_INTRINSIC_FPTRUNC_ROUND */
    type0, type1, i32imm, 
    /* G_INTRINSIC_TRUNC */
    type0, type0, 
    /* G_INTRINSIC_ROUND */
    type0, type0, 
    /* G_INTRINSIC_LRINT */
    type0, type1, 
    /* G_INTRINSIC_LLRINT */
    type0, type1, 
    /* G_INTRINSIC_ROUNDEVEN */
    type0, type0, 
    /* G_READCYCLECOUNTER */
    type0, 
    /* G_READSTEADYCOUNTER */
    type0, 
    /* G_LOAD */
    type0, ptype1, 
    /* G_SEXTLOAD */
    type0, ptype1, 
    /* G_ZEXTLOAD */
    type0, ptype1, 
    /* G_INDEXED_LOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_SEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_ZEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_STORE */
    type0, ptype1, 
    /* G_INDEXED_STORE */
    ptype0, type1, ptype0, ptype2, -1, 
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    type0, type1, type2, type0, type0, 
    /* G_ATOMIC_CMPXCHG */
    type0, ptype1, type0, type0, 
    /* G_ATOMICRMW_XCHG */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_ADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_SUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_AND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_NAND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_OR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_XOR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FSUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UINC_WRAP */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UDEC_WRAP */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_USUB_COND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_USUB_SAT */
    type0, ptype1, type0, 
    /* G_FENCE */
    i32imm, i32imm, 
    /* G_PREFETCH */
    ptype0, i32imm, i32imm, i32imm, 
    /* G_BRCOND */
    type0, -1, 
    /* G_BRINDIRECT */
    type0, 
    /* G_INVOKE_REGION_START */
    /* G_INTRINSIC */
    -1, 
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    -1, 
    /* G_INTRINSIC_CONVERGENT */
    -1, 
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    -1, 
    /* G_ANYEXT */
    type0, type1, 
    /* G_TRUNC */
    type0, type1, 
    /* G_CONSTANT */
    type0, -1, 
    /* G_FCONSTANT */
    type0, -1, 
    /* G_VASTART */
    type0, 
    /* G_VAARG */
    type0, type1, -1, 
    /* G_SEXT */
    type0, type1, 
    /* G_SEXT_INREG */
    type0, type0, untyped_imm_0, 
    /* G_ZEXT */
    type0, type1, 
    /* G_SHL */
    type0, type0, type1, 
    /* G_LSHR */
    type0, type0, type1, 
    /* G_ASHR */
    type0, type0, type1, 
    /* G_FSHL */
    type0, type0, type0, type1, 
    /* G_FSHR */
    type0, type0, type0, type1, 
    /* G_ROTR */
    type0, type0, type1, 
    /* G_ROTL */
    type0, type0, type1, 
    /* G_ICMP */
    type0, -1, type1, type1, 
    /* G_FCMP */
    type0, -1, type1, type1, 
    /* G_SCMP */
    type0, type1, type1, 
    /* G_UCMP */
    type0, type1, type1, 
    /* G_SELECT */
    type0, type1, type0, type0, 
    /* G_UADDO */
    type0, type1, type0, type0, 
    /* G_UADDE */
    type0, type1, type0, type0, type1, 
    /* G_USUBO */
    type0, type1, type0, type0, 
    /* G_USUBE */
    type0, type1, type0, type0, type1, 
    /* G_SADDO */
    type0, type1, type0, type0, 
    /* G_SADDE */
    type0, type1, type0, type0, type1, 
    /* G_SSUBO */
    type0, type1, type0, type0, 
    /* G_SSUBE */
    type0, type1, type0, type0, type1, 
    /* G_UMULO */
    type0, type1, type0, type0, 
    /* G_SMULO */
    type0, type1, type0, type0, 
    /* G_UMULH */
    type0, type0, type0, 
    /* G_SMULH */
    type0, type0, type0, 
    /* G_UADDSAT */
    type0, type0, type0, 
    /* G_SADDSAT */
    type0, type0, type0, 
    /* G_USUBSAT */
    type0, type0, type0, 
    /* G_SSUBSAT */
    type0, type0, type0, 
    /* G_USHLSAT */
    type0, type0, type1, 
    /* G_SSHLSAT */
    type0, type0, type1, 
    /* G_SMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_FADD */
    type0, type0, type0, 
    /* G_FSUB */
    type0, type0, type0, 
    /* G_FMUL */
    type0, type0, type0, 
    /* G_FMA */
    type0, type0, type0, type0, 
    /* G_FMAD */
    type0, type0, type0, type0, 
    /* G_FDIV */
    type0, type0, type0, 
    /* G_FREM */
    type0, type0, type0, 
    /* G_FPOW */
    type0, type0, type0, 
    /* G_FPOWI */
    type0, type0, type1, 
    /* G_FEXP */
    type0, type0, 
    /* G_FEXP2 */
    type0, type0, 
    /* G_FEXP10 */
    type0, type0, 
    /* G_FLOG */
    type0, type0, 
    /* G_FLOG2 */
    type0, type0, 
    /* G_FLOG10 */
    type0, type0, 
    /* G_FLDEXP */
    type0, type0, type1, 
    /* G_FFREXP */
    type0, type1, type0, 
    /* G_FNEG */
    type0, type0, 
    /* G_FPEXT */
    type0, type1, 
    /* G_FPTRUNC */
    type0, type1, 
    /* G_FPTOSI */
    type0, type1, 
    /* G_FPTOUI */
    type0, type1, 
    /* G_SITOFP */
    type0, type1, 
    /* G_UITOFP */
    type0, type1, 
    /* G_FPTOSI_SAT */
    type0, type1, 
    /* G_FPTOUI_SAT */
    type0, type1, 
    /* G_FABS */
    type0, type0, 
    /* G_FCOPYSIGN */
    type0, type0, type1, 
    /* G_IS_FPCLASS */
    type0, type1, -1, 
    /* G_FCANONICALIZE */
    type0, type0, 
    /* G_FMINNUM */
    type0, type0, type0, 
    /* G_FMAXNUM */
    type0, type0, type0, 
    /* G_FMINNUM_IEEE */
    type0, type0, type0, 
    /* G_FMAXNUM_IEEE */
    type0, type0, type0, 
    /* G_FMINIMUM */
    type0, type0, type0, 
    /* G_FMAXIMUM */
    type0, type0, type0, 
    /* G_GET_FPENV */
    type0, 
    /* G_SET_FPENV */
    type0, 
    /* G_RESET_FPENV */
    /* G_GET_FPMODE */
    type0, 
    /* G_SET_FPMODE */
    type0, 
    /* G_RESET_FPMODE */
    /* G_PTR_ADD */
    ptype0, ptype0, type1, 
    /* G_PTRMASK */
    ptype0, ptype0, type1, 
    /* G_SMIN */
    type0, type0, type0, 
    /* G_SMAX */
    type0, type0, type0, 
    /* G_UMIN */
    type0, type0, type0, 
    /* G_UMAX */
    type0, type0, type0, 
    /* G_ABS */
    type0, type0, 
    /* G_LROUND */
    type0, type1, 
    /* G_LLROUND */
    type0, type1, 
    /* G_BR */
    -1, 
    /* G_BRJT */
    ptype0, -1, type1, 
    /* G_VSCALE */
    type0, -1, 
    /* G_INSERT_SUBVECTOR */
    type0, type0, type1, untyped_imm_0, 
    /* G_EXTRACT_SUBVECTOR */
    type0, type1, untyped_imm_0, 
    /* G_INSERT_VECTOR_ELT */
    type0, type0, type1, type2, 
    /* G_EXTRACT_VECTOR_ELT */
    type0, type1, type2, 
    /* G_SHUFFLE_VECTOR */
    type0, type1, type1, -1, 
    /* G_SPLAT_VECTOR */
    type0, type1, 
    /* G_VECTOR_COMPRESS */
    type0, type0, type1, type0, 
    /* G_CTTZ */
    type0, type1, 
    /* G_CTTZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTLZ */
    type0, type1, 
    /* G_CTLZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTPOP */
    type0, type1, 
    /* G_BSWAP */
    type0, type0, 
    /* G_BITREVERSE */
    type0, type0, 
    /* G_FCEIL */
    type0, type0, 
    /* G_FCOS */
    type0, type0, 
    /* G_FSIN */
    type0, type0, 
    /* G_FTAN */
    type0, type0, 
    /* G_FACOS */
    type0, type0, 
    /* G_FASIN */
    type0, type0, 
    /* G_FATAN */
    type0, type0, 
    /* G_FATAN2 */
    type0, type0, type0, 
    /* G_FCOSH */
    type0, type0, 
    /* G_FSINH */
    type0, type0, 
    /* G_FTANH */
    type0, type0, 
    /* G_FSQRT */
    type0, type0, 
    /* G_FFLOOR */
    type0, type0, 
    /* G_FRINT */
    type0, type0, 
    /* G_FNEARBYINT */
    type0, type0, 
    /* G_ADDRSPACE_CAST */
    type0, type1, 
    /* G_BLOCK_ADDR */
    type0, -1, 
    /* G_JUMP_TABLE */
    type0, -1, 
    /* G_DYN_STACKALLOC */
    ptype0, type1, i32imm, 
    /* G_STACKSAVE */
    ptype0, 
    /* G_STACKRESTORE */
    ptype0, 
    /* G_STRICT_FADD */
    type0, type0, type0, 
    /* G_STRICT_FSUB */
    type0, type0, type0, 
    /* G_STRICT_FMUL */
    type0, type0, type0, 
    /* G_STRICT_FDIV */
    type0, type0, type0, 
    /* G_STRICT_FREM */
    type0, type0, type0, 
    /* G_STRICT_FMA */
    type0, type0, type0, type0, 
    /* G_STRICT_FSQRT */
    type0, type0, 
    /* G_STRICT_FLDEXP */
    type0, type0, type1, 
    /* G_READ_REGISTER */
    type0, -1, 
    /* G_WRITE_REGISTER */
    -1, type0, 
    /* G_MEMCPY */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMCPY_INLINE */
    ptype0, ptype1, type2, 
    /* G_MEMMOVE */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMSET */
    ptype0, type1, type2, untyped_imm_0, 
    /* G_BZERO */
    ptype0, type1, untyped_imm_0, 
    /* G_TRAP */
    /* G_DEBUGTRAP */
    /* G_UBSANTRAP */
    i8imm, 
    /* G_VECREDUCE_SEQ_FADD */
    type0, type1, type2, 
    /* G_VECREDUCE_SEQ_FMUL */
    type0, type1, type2, 
    /* G_VECREDUCE_FADD */
    type0, type1, 
    /* G_VECREDUCE_FMUL */
    type0, type1, 
    /* G_VECREDUCE_FMAX */
    type0, type1, 
    /* G_VECREDUCE_FMIN */
    type0, type1, 
    /* G_VECREDUCE_FMAXIMUM */
    type0, type1, 
    /* G_VECREDUCE_FMINIMUM */
    type0, type1, 
    /* G_VECREDUCE_ADD */
    type0, type1, 
    /* G_VECREDUCE_MUL */
    type0, type1, 
    /* G_VECREDUCE_AND */
    type0, type1, 
    /* G_VECREDUCE_OR */
    type0, type1, 
    /* G_VECREDUCE_XOR */
    type0, type1, 
    /* G_VECREDUCE_SMAX */
    type0, type1, 
    /* G_VECREDUCE_SMIN */
    type0, type1, 
    /* G_VECREDUCE_UMAX */
    type0, type1, 
    /* G_VECREDUCE_UMIN */
    type0, type1, 
    /* G_SBFX */
    type0, type0, type1, type1, 
    /* G_UBFX */
    type0, type0, type1, type1, 
    /* BRANCH */
    brtarget, 
    /* BRANCH_COND_f32 */
    brtarget, R600_Reg32, 
    /* BRANCH_COND_i32 */
    brtarget, R600_Reg32, 
    /* BREAK */
    /* BREAKC_f32 */
    R600_Reg32, R600_Reg32, 
    /* BREAKC_i32 */
    R600_Reg32, R600_Reg32, 
    /* BREAK_LOGICALNZ_f32 */
    R600_Reg32, 
    /* BREAK_LOGICALNZ_i32 */
    R600_Reg32, 
    /* BREAK_LOGICALZ_f32 */
    R600_Reg32, 
    /* BREAK_LOGICALZ_i32 */
    R600_Reg32, 
    /* CONST_COPY */
    R600_Reg32, i32imm, 
    /* CONTINUE */
    /* CONTINUEC_f32 */
    R600_Reg32, R600_Reg32, 
    /* CONTINUEC_i32 */
    R600_Reg32, R600_Reg32, 
    /* CONTINUE_LOGICALNZ_f32 */
    R600_Reg32, 
    /* CONTINUE_LOGICALNZ_i32 */
    R600_Reg32, 
    /* CONTINUE_LOGICALZ_f32 */
    R600_Reg32, 
    /* CONTINUE_LOGICALZ_i32 */
    R600_Reg32, 
    /* CUBE_eg_pseudo */
    R600_Reg128, R600_Reg128, 
    /* CUBE_r600_pseudo */
    R600_Reg128, R600_Reg128, 
    /* DEFAULT */
    /* DOT_4 */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_TReg32_X, NEG, REL, ABS, SEL, R600_TReg32_X, NEG, REL, ABS, SEL, R600_Predicate, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_TReg32_Y, NEG, REL, ABS, SEL, R600_TReg32_Y, NEG, REL, ABS, SEL, R600_Predicate, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_TReg32_Z, NEG, REL, ABS, SEL, R600_TReg32_Z, NEG, REL, ABS, SEL, R600_Predicate, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_TReg32_W, NEG, REL, ABS, SEL, R600_TReg32_W, NEG, REL, ABS, SEL, R600_Predicate, LITERAL, LITERAL, 
    /* DUMMY_CHAIN */
    /* ELSE */
    /* END */
    /* ENDFUNC */
    /* ENDIF */
    /* ENDLOOP */
    /* ENDMAIN */
    /* ENDSWITCH */
    /* FABS_R600 */
    R600_Reg32, R600_Reg32, 
    /* FNEG_R600 */
    R600_Reg32, R600_Reg32, 
    /* FUNC */
    /* IFC_f32 */
    R600_Reg32, R600_Reg32, 
    /* IFC_i32 */
    R600_Reg32, R600_Reg32, 
    /* IF_LOGICALNZ_f32 */
    R600_Reg32, 
    /* IF_LOGICALNZ_i32 */
    R600_Reg32, 
    /* IF_LOGICALZ_f32 */
    R600_Reg32, 
    /* IF_LOGICALZ_i32 */
    R600_Reg32, 
    /* IF_PREDICATE_SET */
    R600_Reg32, 
    /* JUMP */
    brtarget, 
    /* JUMP_COND */
    brtarget, R600_Predicate_Bit, 
    /* MASK_WRITE */
    R600_Reg32, 
    /* MOV_IMM_F32 */
    R600_Reg32, f32imm, 
    /* MOV_IMM_GLOBAL_ADDR */
    R600_Reg32, i32imm, 
    /* MOV_IMM_I32 */
    R600_Reg32, i32imm, 
    /* PRED_X */
    R600_Predicate_Bit, R600_Reg32, i32imm, i32imm, 
    /* R600_EXTRACT_ELT_V2 */
    R600_Reg32, R600_Reg64Vertical, R600_Reg32, 
    /* R600_EXTRACT_ELT_V4 */
    R600_Reg32, R600_Reg128Vertical, R600_Reg32, 
    /* R600_INSERT_ELT_V2 */
    R600_Reg64Vertical, R600_Reg64Vertical, R600_Reg32, R600_Reg32, 
    /* R600_INSERT_ELT_V4 */
    R600_Reg128Vertical, R600_Reg128Vertical, R600_Reg32, R600_Reg32, 
    /* R600_RegisterLoad */
    R600_Reg32, R600_Reg32, i32imm, i32imm, 
    /* R600_RegisterStore */
    R600_Reg32, R600_Reg32, i32imm, i32imm, 
    /* RETDYN */
    /* RETURN */
    /* TXD */
    R600_Reg128, R600_Reg128, R600_Reg128, R600_Reg128, i32imm, i32imm, i32imm, 
    /* TXD_SHADOW */
    R600_Reg128, R600_Reg128, R600_Reg128, R600_Reg128, i32imm, i32imm, i32imm, 
    /* WHILELOOP */
    /* ADD */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* ADDC_UINT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* ADD_INT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* ALU_CLAUSE */
    i32imm, 
    /* AND_INT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* ASHR_eg */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* ASHR_r600 */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* BCNT_INT */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* BFE_INT_eg */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* BFE_UINT_eg */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* BFI_INT_eg */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* BFM_INT_eg */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* BIT_ALIGN_INT_eg */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* CEIL */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* CF_ALU */
    i32imm, i32imm, i32imm, KCACHE, KCACHE, i32imm, i32imm, i32imm, i32imm, 
    /* CF_ALU_BREAK */
    i32imm, i32imm, i32imm, KCACHE, KCACHE, i32imm, i32imm, i32imm, i32imm, 
    /* CF_ALU_CONTINUE */
    i32imm, i32imm, i32imm, KCACHE, KCACHE, i32imm, i32imm, i32imm, i32imm, 
    /* CF_ALU_ELSE_AFTER */
    i32imm, i32imm, i32imm, KCACHE, KCACHE, i32imm, i32imm, i32imm, i32imm, 
    /* CF_ALU_POP_AFTER */
    i32imm, i32imm, i32imm, KCACHE, KCACHE, i32imm, i32imm, i32imm, i32imm, 
    /* CF_ALU_PUSH_BEFORE */
    i32imm, i32imm, i32imm, KCACHE, KCACHE, i32imm, i32imm, i32imm, i32imm, 
    /* CF_CALL_FS_EG */
    /* CF_CALL_FS_R600 */
    /* CF_CONTINUE_EG */
    i32imm, 
    /* CF_CONTINUE_R600 */
    i32imm, 
    /* CF_ELSE_EG */
    i32imm, i32imm, 
    /* CF_ELSE_R600 */
    i32imm, i32imm, 
    /* CF_END_CM */
    /* CF_END_EG */
    /* CF_END_R600 */
    /* CF_JUMP_EG */
    i32imm, i32imm, 
    /* CF_JUMP_R600 */
    i32imm, i32imm, 
    /* CF_PUSH_EG */
    i32imm, i32imm, 
    /* CF_PUSH_ELSE_R600 */
    i32imm, 
    /* CF_TC_EG */
    i32imm, i32imm, 
    /* CF_TC_R600 */
    i32imm, i32imm, 
    /* CF_VC_EG */
    i32imm, i32imm, 
    /* CF_VC_R600 */
    i32imm, i32imm, 
    /* CNDE_INT */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* CNDE_eg */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* CNDE_r600 */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* CNDGE_INT */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* CNDGE_eg */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* CNDGE_r600 */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* CNDGT_INT */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* CNDGT_eg */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* CNDGT_r600 */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* COS_cm */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* COS_eg */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* COS_r600 */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* COS_r700 */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* CUBE_eg_real */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* CUBE_r600_real */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* DOT4_eg */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* DOT4_r600 */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* EG_ExportBuf */
    R600_Reg128, i32imm, i32imm, i32imm, i32imm, i32imm, i32imm, 
    /* EG_ExportSwz */
    R600_Reg128, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, 
    /* END_LOOP_EG */
    i32imm, 
    /* END_LOOP_R600 */
    i32imm, 
    /* EXP_IEEE_cm */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* EXP_IEEE_eg */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* EXP_IEEE_r600 */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* FETCH_CLAUSE */
    i32imm, 
    /* FFBH_UINT */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* FFBL_INT */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* FLOOR */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* FLT16_TO_FLT32 */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* FLT32_TO_FLT16 */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* FLT_TO_INT_eg */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* FLT_TO_INT_r600 */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* FLT_TO_UINT_eg */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* FLT_TO_UINT_r600 */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* FMA_eg */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* FRACT */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* GROUP_BARRIER */
    /* INTERP_LOAD_P0 */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* INTERP_PAIR_XY */
    R600_TReg32_X, R600_TReg32_Y, i32imm, R600_TReg32_Y, R600_TReg32_X, 
    /* INTERP_PAIR_ZW */
    R600_TReg32_Z, R600_TReg32_W, i32imm, R600_TReg32_Y, R600_TReg32_X, 
    /* INTERP_VEC_LOAD */
    R600_Reg128, i32imm, 
    /* INTERP_XY */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* INTERP_ZW */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* INT_TO_FLT_eg */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* INT_TO_FLT_r600 */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* KILLGT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* LDS_ADD */
    R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_ADD_RET */
    R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_AND */
    R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_AND_RET */
    R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_BYTE_READ_RET */
    R600_Reg32, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_BYTE_WRITE */
    R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_CMPST */
    R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_CMPST_RET */
    R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_MAX_INT */
    R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_MAX_INT_RET */
    R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_MAX_UINT */
    R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_MAX_UINT_RET */
    R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_MIN_INT */
    R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_MIN_INT_RET */
    R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_MIN_UINT */
    R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_MIN_UINT_RET */
    R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_OR */
    R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_OR_RET */
    R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_READ_RET */
    R600_Reg32, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_SHORT_READ_RET */
    R600_Reg32, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_SHORT_WRITE */
    R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_SUB */
    R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_SUB_RET */
    R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_UBYTE_READ_RET */
    R600_Reg32, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_USHORT_READ_RET */
    R600_Reg32, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_WRITE */
    R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_WRXCHG */
    R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_WRXCHG_RET */
    R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_XOR */
    R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LDS_XOR_RET */
    R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, 
    /* LITERALS */
    LITERAL, LITERAL, 
    /* LOG_CLAMPED_eg */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* LOG_CLAMPED_r600 */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* LOG_IEEE_cm */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* LOG_IEEE_eg */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* LOG_IEEE_r600 */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* LOOP_BREAK_EG */
    i32imm, 
    /* LOOP_BREAK_R600 */
    i32imm, 
    /* LSHL_eg */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* LSHL_r600 */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* LSHR_eg */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* LSHR_r600 */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MAX */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MAX_DX10 */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MAX_INT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MAX_UINT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MIN */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MIN_DX10 */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MIN_INT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MIN_UINT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MOV */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MOVA_INT_eg */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MUL */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MULADD_IEEE_eg */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MULADD_IEEE_r600 */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MULADD_INT24_cm */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MULADD_UINT24_eg */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MULADD_eg */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MULADD_r600 */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MULHI_INT_cm */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MULHI_INT_cm24 */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MULHI_INT_eg */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MULHI_INT_r600 */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MULHI_UINT24_eg */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MULHI_UINT_cm */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MULHI_UINT_cm24 */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MULHI_UINT_eg */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MULHI_UINT_r600 */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MULLO_INT_cm */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MULLO_INT_eg */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MULLO_INT_r600 */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MULLO_UINT_cm */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MULLO_UINT_eg */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MULLO_UINT_r600 */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MUL_IEEE */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MUL_INT24_cm */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MUL_LIT_eg */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MUL_LIT_r600 */
    R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* MUL_UINT24_eg */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* NOT_INT */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* OR_INT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* PAD */
    /* POP_EG */
    i32imm, i32imm, 
    /* POP_R600 */
    i32imm, i32imm, 
    /* PRED_SETE */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* PRED_SETE_INT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* PRED_SETGE */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* PRED_SETGE_INT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* PRED_SETGT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* PRED_SETGT_INT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* PRED_SETNE */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* PRED_SETNE_INT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* R600_ExportBuf */
    R600_Reg128, i32imm, i32imm, i32imm, i32imm, i32imm, i32imm, 
    /* R600_ExportSwz */
    R600_Reg128, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, 
    /* RAT_ATOMIC_ADD_NORET */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_ADD_RTN */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_AND_NORET */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_AND_RTN */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_CMPXCHG_INT_NORET */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_CMPXCHG_INT_RTN */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_DEC_UINT_NORET */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_DEC_UINT_RTN */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_INC_UINT_NORET */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_INC_UINT_RTN */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_MAX_INT_NORET */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_MAX_INT_RTN */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_MAX_UINT_NORET */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_MAX_UINT_RTN */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_MIN_INT_NORET */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_MIN_INT_RTN */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_MIN_UINT_NORET */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_MIN_UINT_RTN */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_OR_NORET */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_OR_RTN */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_RSUB_NORET */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_RSUB_RTN */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_SUB_NORET */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_SUB_RTN */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_XCHG_INT_NORET */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_XCHG_INT_RTN */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_XOR_NORET */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_ATOMIC_XOR_RTN */
    R600_Reg128, R600_Reg128, R600_TReg32_X, 
    /* RAT_MSKOR */
    R600_Reg128, R600_TReg32_X, 
    /* RAT_STORE_DWORD128 */
    R600_Reg128, R600_TReg32_X, 
    /* RAT_STORE_DWORD32 */
    R600_TReg32_X, R600_TReg32_X, 
    /* RAT_STORE_DWORD64 */
    R600_Reg64, R600_TReg32_X, 
    /* RAT_STORE_TYPED_cm */
    R600_Reg128, R600_Reg128, i32imm, InstFlag, 
    /* RAT_STORE_TYPED_eg */
    R600_Reg128, R600_Reg128, i32imm, InstFlag, 
    /* RAT_WRITE_CACHELESS_128_eg */
    R600_Reg128, R600_TReg32_X, InstFlag, 
    /* RAT_WRITE_CACHELESS_32_eg */
    R600_TReg32_X, R600_TReg32_X, InstFlag, 
    /* RAT_WRITE_CACHELESS_64_eg */
    R600_Reg64, R600_TReg32_X, InstFlag, 
    /* RECIPSQRT_CLAMPED_cm */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* RECIPSQRT_CLAMPED_eg */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* RECIPSQRT_CLAMPED_r600 */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* RECIPSQRT_IEEE_cm */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* RECIPSQRT_IEEE_eg */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* RECIPSQRT_IEEE_r600 */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* RECIP_CLAMPED_cm */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* RECIP_CLAMPED_eg */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* RECIP_CLAMPED_r600 */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* RECIP_IEEE_cm */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* RECIP_IEEE_eg */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* RECIP_IEEE_r600 */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* RECIP_UINT_eg */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* RECIP_UINT_r600 */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* RNDNE */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* SETE */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* SETE_DX10 */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* SETE_INT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* SETGE_DX10 */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* SETGE_INT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* SETGE_UINT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* SETGT_DX10 */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* SETGT_INT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* SETGT_UINT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* SETNE_DX10 */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* SETNE_INT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* SGE */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* SGT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* SIN_cm */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* SIN_eg */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* SIN_r600 */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* SIN_r700 */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* SNE */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* SUBB_UINT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* SUB_INT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* TEX_GET_GRADIENTS_H */
    R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, 
    /* TEX_GET_GRADIENTS_V */
    R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, 
    /* TEX_GET_TEXTURE_RESINFO */
    R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, 
    /* TEX_LD */
    R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, 
    /* TEX_LDPTR */
    R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, 
    /* TEX_SAMPLE */
    R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, 
    /* TEX_SAMPLE_C */
    R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, 
    /* TEX_SAMPLE_C_G */
    R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, 
    /* TEX_SAMPLE_C_L */
    R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, 
    /* TEX_SAMPLE_C_LB */
    R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, 
    /* TEX_SAMPLE_G */
    R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, 
    /* TEX_SAMPLE_L */
    R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, 
    /* TEX_SAMPLE_LB */
    R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, 
    /* TEX_SET_GRADIENTS_H */
    R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, 
    /* TEX_SET_GRADIENTS_V */
    R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, 
    /* TEX_VTX_CONSTBUF */
    R600_Reg128, R600_TReg32_X, i32imm, i32imm, 
    /* TEX_VTX_TEXBUF */
    R600_Reg128, R600_TReg32_X, i32imm, i32imm, 
    /* TRUNC */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* UINT_TO_FLT_eg */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* UINT_TO_FLT_r600 */
    R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
    /* VTX_READ_128_cm */
    R600_Reg128, R600_TReg32_X, i32imm, i8imm, 
    /* VTX_READ_128_eg */
    R600_Reg128, R600_TReg32_X, i32imm, i8imm, 
    /* VTX_READ_16_cm */
    R600_TReg32_X, R600_TReg32_X, i32imm, i8imm, 
    /* VTX_READ_16_eg */
    R600_TReg32_X, R600_TReg32_X, i32imm, i8imm, 
    /* VTX_READ_32_cm */
    R600_TReg32_X, R600_TReg32_X, i32imm, i8imm, 
    /* VTX_READ_32_eg */
    R600_TReg32_X, R600_TReg32_X, i32imm, i8imm, 
    /* VTX_READ_64_cm */
    R600_Reg64, R600_TReg32_X, i32imm, i8imm, 
    /* VTX_READ_64_eg */
    R600_Reg64, R600_TReg32_X, i32imm, i8imm, 
    /* VTX_READ_8_cm */
    R600_TReg32_X, R600_TReg32_X, i32imm, i8imm, 
    /* VTX_READ_8_eg */
    R600_TReg32_X, R600_TReg32_X, i32imm, i8imm, 
    /* WHILE_LOOP_EG */
    i32imm, 
    /* WHILE_LOOP_R600 */
    i32imm, 
    /* XOR_INT */
    R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, 
  };
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
}
} // end namespace R600
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPE

#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
namespace llvm {
namespace R600 {
LLVM_READONLY
static int getMemOperandSize(int OpType) {
  switch (OpType) {
  default: return 0;
  }
}
} // end namespace R600
} // end namespace llvm
#endif // GET_INSTRINFO_MEM_OPERAND_SIZE

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
namespace llvm {
namespace R600 {
LLVM_READONLY static unsigned
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return LogicalOpIdx;
}
LLVM_READONLY static inline unsigned
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
  auto S = 0U;
  for (auto i = 0U; i < LogicalOpIdx; ++i)
    S += getLogicalOperandSize(Opcode, i);
  return S;
}
} // end namespace R600
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
namespace llvm {
namespace R600 {
LLVM_READONLY static int
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return -1;
}
} // end namespace R600
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP

#ifdef GET_INSTRINFO_MC_HELPER_DECLS
#undef GET_INSTRINFO_MC_HELPER_DECLS

namespace llvm {
class MCInst;
class FeatureBitset;

namespace R600_MC {

void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);

} // end namespace R600_MC
} // end namespace llvm

#endif // GET_INSTRINFO_MC_HELPER_DECLS

#ifdef GET_INSTRINFO_MC_HELPERS
#undef GET_INSTRINFO_MC_HELPERS

namespace llvm {
namespace R600_MC {

} // end namespace R600_MC
} // end namespace llvm

#endif // GET_GENISTRINFO_MC_HELPERS

#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
    defined(GET_AVAILABLE_OPCODE_CHECKER)
#define GET_COMPUTE_FEATURES
#endif
#ifdef GET_COMPUTE_FEATURES
#undef GET_COMPUTE_FEATURES
namespace llvm {
namespace R600_MC {

// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
};

inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
  FeatureBitset Features;
  return Features;
}

inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
  enum : uint8_t {
    CEFBS_None,
  };

  static constexpr FeatureBitset FeatureBitsets[] = {
    {}, // CEFBS_None
  };
  static constexpr uint8_t RequiredFeaturesRefs[] = {
    CEFBS_None, // PHI = 0
    CEFBS_None, // INLINEASM = 1
    CEFBS_None, // INLINEASM_BR = 2
    CEFBS_None, // CFI_INSTRUCTION = 3
    CEFBS_None, // EH_LABEL = 4
    CEFBS_None, // GC_LABEL = 5
    CEFBS_None, // ANNOTATION_LABEL = 6
    CEFBS_None, // KILL = 7
    CEFBS_None, // EXTRACT_SUBREG = 8
    CEFBS_None, // INSERT_SUBREG = 9
    CEFBS_None, // IMPLICIT_DEF = 10
    CEFBS_None, // INIT_UNDEF = 11
    CEFBS_None, // SUBREG_TO_REG = 12
    CEFBS_None, // COPY_TO_REGCLASS = 13
    CEFBS_None, // DBG_VALUE = 14
    CEFBS_None, // DBG_VALUE_LIST = 15
    CEFBS_None, // DBG_INSTR_REF = 16
    CEFBS_None, // DBG_PHI = 17
    CEFBS_None, // DBG_LABEL = 18
    CEFBS_None, // REG_SEQUENCE = 19
    CEFBS_None, // COPY = 20
    CEFBS_None, // BUNDLE = 21
    CEFBS_None, // LIFETIME_START = 22
    CEFBS_None, // LIFETIME_END = 23
    CEFBS_None, // PSEUDO_PROBE = 24
    CEFBS_None, // ARITH_FENCE = 25
    CEFBS_None, // STACKMAP = 26
    CEFBS_None, // FENTRY_CALL = 27
    CEFBS_None, // PATCHPOINT = 28
    CEFBS_None, // LOAD_STACK_GUARD = 29
    CEFBS_None, // PREALLOCATED_SETUP = 30
    CEFBS_None, // PREALLOCATED_ARG = 31
    CEFBS_None, // STATEPOINT = 32
    CEFBS_None, // LOCAL_ESCAPE = 33
    CEFBS_None, // FAULTING_OP = 34
    CEFBS_None, // PATCHABLE_OP = 35
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 36
    CEFBS_None, // PATCHABLE_RET = 37
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 38
    CEFBS_None, // PATCHABLE_TAIL_CALL = 39
    CEFBS_None, // PATCHABLE_EVENT_CALL = 40
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 41
    CEFBS_None, // ICALL_BRANCH_FUNNEL = 42
    CEFBS_None, // FAKE_USE = 43
    CEFBS_None, // MEMBARRIER = 44
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 45
    CEFBS_None, // CONVERGENCECTRL_ENTRY = 46
    CEFBS_None, // CONVERGENCECTRL_ANCHOR = 47
    CEFBS_None, // CONVERGENCECTRL_LOOP = 48
    CEFBS_None, // CONVERGENCECTRL_GLUE = 49
    CEFBS_None, // G_ASSERT_SEXT = 50
    CEFBS_None, // G_ASSERT_ZEXT = 51
    CEFBS_None, // G_ASSERT_ALIGN = 52
    CEFBS_None, // G_ADD = 53
    CEFBS_None, // G_SUB = 54
    CEFBS_None, // G_MUL = 55
    CEFBS_None, // G_SDIV = 56
    CEFBS_None, // G_UDIV = 57
    CEFBS_None, // G_SREM = 58
    CEFBS_None, // G_UREM = 59
    CEFBS_None, // G_SDIVREM = 60
    CEFBS_None, // G_UDIVREM = 61
    CEFBS_None, // G_AND = 62
    CEFBS_None, // G_OR = 63
    CEFBS_None, // G_XOR = 64
    CEFBS_None, // G_IMPLICIT_DEF = 65
    CEFBS_None, // G_PHI = 66
    CEFBS_None, // G_FRAME_INDEX = 67
    CEFBS_None, // G_GLOBAL_VALUE = 68
    CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 69
    CEFBS_None, // G_CONSTANT_POOL = 70
    CEFBS_None, // G_EXTRACT = 71
    CEFBS_None, // G_UNMERGE_VALUES = 72
    CEFBS_None, // G_INSERT = 73
    CEFBS_None, // G_MERGE_VALUES = 74
    CEFBS_None, // G_BUILD_VECTOR = 75
    CEFBS_None, // G_BUILD_VECTOR_TRUNC = 76
    CEFBS_None, // G_CONCAT_VECTORS = 77
    CEFBS_None, // G_PTRTOINT = 78
    CEFBS_None, // G_INTTOPTR = 79
    CEFBS_None, // G_BITCAST = 80
    CEFBS_None, // G_FREEZE = 81
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 82
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 83
    CEFBS_None, // G_INTRINSIC_TRUNC = 84
    CEFBS_None, // G_INTRINSIC_ROUND = 85
    CEFBS_None, // G_INTRINSIC_LRINT = 86
    CEFBS_None, // G_INTRINSIC_LLRINT = 87
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 88
    CEFBS_None, // G_READCYCLECOUNTER = 89
    CEFBS_None, // G_READSTEADYCOUNTER = 90
    CEFBS_None, // G_LOAD = 91
    CEFBS_None, // G_SEXTLOAD = 92
    CEFBS_None, // G_ZEXTLOAD = 93
    CEFBS_None, // G_INDEXED_LOAD = 94
    CEFBS_None, // G_INDEXED_SEXTLOAD = 95
    CEFBS_None, // G_INDEXED_ZEXTLOAD = 96
    CEFBS_None, // G_STORE = 97
    CEFBS_None, // G_INDEXED_STORE = 98
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 99
    CEFBS_None, // G_ATOMIC_CMPXCHG = 100
    CEFBS_None, // G_ATOMICRMW_XCHG = 101
    CEFBS_None, // G_ATOMICRMW_ADD = 102
    CEFBS_None, // G_ATOMICRMW_SUB = 103
    CEFBS_None, // G_ATOMICRMW_AND = 104
    CEFBS_None, // G_ATOMICRMW_NAND = 105
    CEFBS_None, // G_ATOMICRMW_OR = 106
    CEFBS_None, // G_ATOMICRMW_XOR = 107
    CEFBS_None, // G_ATOMICRMW_MAX = 108
    CEFBS_None, // G_ATOMICRMW_MIN = 109
    CEFBS_None, // G_ATOMICRMW_UMAX = 110
    CEFBS_None, // G_ATOMICRMW_UMIN = 111
    CEFBS_None, // G_ATOMICRMW_FADD = 112
    CEFBS_None, // G_ATOMICRMW_FSUB = 113
    CEFBS_None, // G_ATOMICRMW_FMAX = 114
    CEFBS_None, // G_ATOMICRMW_FMIN = 115
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 116
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 117
    CEFBS_None, // G_ATOMICRMW_USUB_COND = 118
    CEFBS_None, // G_ATOMICRMW_USUB_SAT = 119
    CEFBS_None, // G_FENCE = 120
    CEFBS_None, // G_PREFETCH = 121
    CEFBS_None, // G_BRCOND = 122
    CEFBS_None, // G_BRINDIRECT = 123
    CEFBS_None, // G_INVOKE_REGION_START = 124
    CEFBS_None, // G_INTRINSIC = 125
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 126
    CEFBS_None, // G_INTRINSIC_CONVERGENT = 127
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 128
    CEFBS_None, // G_ANYEXT = 129
    CEFBS_None, // G_TRUNC = 130
    CEFBS_None, // G_CONSTANT = 131
    CEFBS_None, // G_FCONSTANT = 132
    CEFBS_None, // G_VASTART = 133
    CEFBS_None, // G_VAARG = 134
    CEFBS_None, // G_SEXT = 135
    CEFBS_None, // G_SEXT_INREG = 136
    CEFBS_None, // G_ZEXT = 137
    CEFBS_None, // G_SHL = 138
    CEFBS_None, // G_LSHR = 139
    CEFBS_None, // G_ASHR = 140
    CEFBS_None, // G_FSHL = 141
    CEFBS_None, // G_FSHR = 142
    CEFBS_None, // G_ROTR = 143
    CEFBS_None, // G_ROTL = 144
    CEFBS_None, // G_ICMP = 145
    CEFBS_None, // G_FCMP = 146
    CEFBS_None, // G_SCMP = 147
    CEFBS_None, // G_UCMP = 148
    CEFBS_None, // G_SELECT = 149
    CEFBS_None, // G_UADDO = 150
    CEFBS_None, // G_UADDE = 151
    CEFBS_None, // G_USUBO = 152
    CEFBS_None, // G_USUBE = 153
    CEFBS_None, // G_SADDO = 154
    CEFBS_None, // G_SADDE = 155
    CEFBS_None, // G_SSUBO = 156
    CEFBS_None, // G_SSUBE = 157
    CEFBS_None, // G_UMULO = 158
    CEFBS_None, // G_SMULO = 159
    CEFBS_None, // G_UMULH = 160
    CEFBS_None, // G_SMULH = 161
    CEFBS_None, // G_UADDSAT = 162
    CEFBS_None, // G_SADDSAT = 163
    CEFBS_None, // G_USUBSAT = 164
    CEFBS_None, // G_SSUBSAT = 165
    CEFBS_None, // G_USHLSAT = 166
    CEFBS_None, // G_SSHLSAT = 167
    CEFBS_None, // G_SMULFIX = 168
    CEFBS_None, // G_UMULFIX = 169
    CEFBS_None, // G_SMULFIXSAT = 170
    CEFBS_None, // G_UMULFIXSAT = 171
    CEFBS_None, // G_SDIVFIX = 172
    CEFBS_None, // G_UDIVFIX = 173
    CEFBS_None, // G_SDIVFIXSAT = 174
    CEFBS_None, // G_UDIVFIXSAT = 175
    CEFBS_None, // G_FADD = 176
    CEFBS_None, // G_FSUB = 177
    CEFBS_None, // G_FMUL = 178
    CEFBS_None, // G_FMA = 179
    CEFBS_None, // G_FMAD = 180
    CEFBS_None, // G_FDIV = 181
    CEFBS_None, // G_FREM = 182
    CEFBS_None, // G_FPOW = 183
    CEFBS_None, // G_FPOWI = 184
    CEFBS_None, // G_FEXP = 185
    CEFBS_None, // G_FEXP2 = 186
    CEFBS_None, // G_FEXP10 = 187
    CEFBS_None, // G_FLOG = 188
    CEFBS_None, // G_FLOG2 = 189
    CEFBS_None, // G_FLOG10 = 190
    CEFBS_None, // G_FLDEXP = 191
    CEFBS_None, // G_FFREXP = 192
    CEFBS_None, // G_FNEG = 193
    CEFBS_None, // G_FPEXT = 194
    CEFBS_None, // G_FPTRUNC = 195
    CEFBS_None, // G_FPTOSI = 196
    CEFBS_None, // G_FPTOUI = 197
    CEFBS_None, // G_SITOFP = 198
    CEFBS_None, // G_UITOFP = 199
    CEFBS_None, // G_FPTOSI_SAT = 200
    CEFBS_None, // G_FPTOUI_SAT = 201
    CEFBS_None, // G_FABS = 202
    CEFBS_None, // G_FCOPYSIGN = 203
    CEFBS_None, // G_IS_FPCLASS = 204
    CEFBS_None, // G_FCANONICALIZE = 205
    CEFBS_None, // G_FMINNUM = 206
    CEFBS_None, // G_FMAXNUM = 207
    CEFBS_None, // G_FMINNUM_IEEE = 208
    CEFBS_None, // G_FMAXNUM_IEEE = 209
    CEFBS_None, // G_FMINIMUM = 210
    CEFBS_None, // G_FMAXIMUM = 211
    CEFBS_None, // G_GET_FPENV = 212
    CEFBS_None, // G_SET_FPENV = 213
    CEFBS_None, // G_RESET_FPENV = 214
    CEFBS_None, // G_GET_FPMODE = 215
    CEFBS_None, // G_SET_FPMODE = 216
    CEFBS_None, // G_RESET_FPMODE = 217
    CEFBS_None, // G_PTR_ADD = 218
    CEFBS_None, // G_PTRMASK = 219
    CEFBS_None, // G_SMIN = 220
    CEFBS_None, // G_SMAX = 221
    CEFBS_None, // G_UMIN = 222
    CEFBS_None, // G_UMAX = 223
    CEFBS_None, // G_ABS = 224
    CEFBS_None, // G_LROUND = 225
    CEFBS_None, // G_LLROUND = 226
    CEFBS_None, // G_BR = 227
    CEFBS_None, // G_BRJT = 228
    CEFBS_None, // G_VSCALE = 229
    CEFBS_None, // G_INSERT_SUBVECTOR = 230
    CEFBS_None, // G_EXTRACT_SUBVECTOR = 231
    CEFBS_None, // G_INSERT_VECTOR_ELT = 232
    CEFBS_None, // G_EXTRACT_VECTOR_ELT = 233
    CEFBS_None, // G_SHUFFLE_VECTOR = 234
    CEFBS_None, // G_SPLAT_VECTOR = 235
    CEFBS_None, // G_VECTOR_COMPRESS = 236
    CEFBS_None, // G_CTTZ = 237
    CEFBS_None, // G_CTTZ_ZERO_UNDEF = 238
    CEFBS_None, // G_CTLZ = 239
    CEFBS_None, // G_CTLZ_ZERO_UNDEF = 240
    CEFBS_None, // G_CTPOP = 241
    CEFBS_None, // G_BSWAP = 242
    CEFBS_None, // G_BITREVERSE = 243
    CEFBS_None, // G_FCEIL = 244
    CEFBS_None, // G_FCOS = 245
    CEFBS_None, // G_FSIN = 246
    CEFBS_None, // G_FTAN = 247
    CEFBS_None, // G_FACOS = 248
    CEFBS_None, // G_FASIN = 249
    CEFBS_None, // G_FATAN = 250
    CEFBS_None, // G_FATAN2 = 251
    CEFBS_None, // G_FCOSH = 252
    CEFBS_None, // G_FSINH = 253
    CEFBS_None, // G_FTANH = 254
    CEFBS_None, // G_FSQRT = 255
    CEFBS_None, // G_FFLOOR = 256
    CEFBS_None, // G_FRINT = 257
    CEFBS_None, // G_FNEARBYINT = 258
    CEFBS_None, // G_ADDRSPACE_CAST = 259
    CEFBS_None, // G_BLOCK_ADDR = 260
    CEFBS_None, // G_JUMP_TABLE = 261
    CEFBS_None, // G_DYN_STACKALLOC = 262
    CEFBS_None, // G_STACKSAVE = 263
    CEFBS_None, // G_STACKRESTORE = 264
    CEFBS_None, // G_STRICT_FADD = 265
    CEFBS_None, // G_STRICT_FSUB = 266
    CEFBS_None, // G_STRICT_FMUL = 267
    CEFBS_None, // G_STRICT_FDIV = 268
    CEFBS_None, // G_STRICT_FREM = 269
    CEFBS_None, // G_STRICT_FMA = 270
    CEFBS_None, // G_STRICT_FSQRT = 271
    CEFBS_None, // G_STRICT_FLDEXP = 272
    CEFBS_None, // G_READ_REGISTER = 273
    CEFBS_None, // G_WRITE_REGISTER = 274
    CEFBS_None, // G_MEMCPY = 275
    CEFBS_None, // G_MEMCPY_INLINE = 276
    CEFBS_None, // G_MEMMOVE = 277
    CEFBS_None, // G_MEMSET = 278
    CEFBS_None, // G_BZERO = 279
    CEFBS_None, // G_TRAP = 280
    CEFBS_None, // G_DEBUGTRAP = 281
    CEFBS_None, // G_UBSANTRAP = 282
    CEFBS_None, // G_VECREDUCE_SEQ_FADD = 283
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 284
    CEFBS_None, // G_VECREDUCE_FADD = 285
    CEFBS_None, // G_VECREDUCE_FMUL = 286
    CEFBS_None, // G_VECREDUCE_FMAX = 287
    CEFBS_None, // G_VECREDUCE_FMIN = 288
    CEFBS_None, // G_VECREDUCE_FMAXIMUM = 289
    CEFBS_None, // G_VECREDUCE_FMINIMUM = 290
    CEFBS_None, // G_VECREDUCE_ADD = 291
    CEFBS_None, // G_VECREDUCE_MUL = 292
    CEFBS_None, // G_VECREDUCE_AND = 293
    CEFBS_None, // G_VECREDUCE_OR = 294
    CEFBS_None, // G_VECREDUCE_XOR = 295
    CEFBS_None, // G_VECREDUCE_SMAX = 296
    CEFBS_None, // G_VECREDUCE_SMIN = 297
    CEFBS_None, // G_VECREDUCE_UMAX = 298
    CEFBS_None, // G_VECREDUCE_UMIN = 299
    CEFBS_None, // G_SBFX = 300
    CEFBS_None, // G_UBFX = 301
    CEFBS_None, // BRANCH = 302
    CEFBS_None, // BRANCH_COND_f32 = 303
    CEFBS_None, // BRANCH_COND_i32 = 304
    CEFBS_None, // BREAK = 305
    CEFBS_None, // BREAKC_f32 = 306
    CEFBS_None, // BREAKC_i32 = 307
    CEFBS_None, // BREAK_LOGICALNZ_f32 = 308
    CEFBS_None, // BREAK_LOGICALNZ_i32 = 309
    CEFBS_None, // BREAK_LOGICALZ_f32 = 310
    CEFBS_None, // BREAK_LOGICALZ_i32 = 311
    CEFBS_None, // CONST_COPY = 312
    CEFBS_None, // CONTINUE = 313
    CEFBS_None, // CONTINUEC_f32 = 314
    CEFBS_None, // CONTINUEC_i32 = 315
    CEFBS_None, // CONTINUE_LOGICALNZ_f32 = 316
    CEFBS_None, // CONTINUE_LOGICALNZ_i32 = 317
    CEFBS_None, // CONTINUE_LOGICALZ_f32 = 318
    CEFBS_None, // CONTINUE_LOGICALZ_i32 = 319
    CEFBS_None, // CUBE_eg_pseudo = 320
    CEFBS_None, // CUBE_r600_pseudo = 321
    CEFBS_None, // DEFAULT = 322
    CEFBS_None, // DOT_4 = 323
    CEFBS_None, // DUMMY_CHAIN = 324
    CEFBS_None, // ELSE = 325
    CEFBS_None, // END = 326
    CEFBS_None, // ENDFUNC = 327
    CEFBS_None, // ENDIF = 328
    CEFBS_None, // ENDLOOP = 329
    CEFBS_None, // ENDMAIN = 330
    CEFBS_None, // ENDSWITCH = 331
    CEFBS_None, // FABS_R600 = 332
    CEFBS_None, // FNEG_R600 = 333
    CEFBS_None, // FUNC = 334
    CEFBS_None, // IFC_f32 = 335
    CEFBS_None, // IFC_i32 = 336
    CEFBS_None, // IF_LOGICALNZ_f32 = 337
    CEFBS_None, // IF_LOGICALNZ_i32 = 338
    CEFBS_None, // IF_LOGICALZ_f32 = 339
    CEFBS_None, // IF_LOGICALZ_i32 = 340
    CEFBS_None, // IF_PREDICATE_SET = 341
    CEFBS_None, // JUMP = 342
    CEFBS_None, // JUMP_COND = 343
    CEFBS_None, // MASK_WRITE = 344
    CEFBS_None, // MOV_IMM_F32 = 345
    CEFBS_None, // MOV_IMM_GLOBAL_ADDR = 346
    CEFBS_None, // MOV_IMM_I32 = 347
    CEFBS_None, // PRED_X = 348
    CEFBS_None, // R600_EXTRACT_ELT_V2 = 349
    CEFBS_None, // R600_EXTRACT_ELT_V4 = 350
    CEFBS_None, // R600_INSERT_ELT_V2 = 351
    CEFBS_None, // R600_INSERT_ELT_V4 = 352
    CEFBS_None, // R600_RegisterLoad = 353
    CEFBS_None, // R600_RegisterStore = 354
    CEFBS_None, // RETDYN = 355
    CEFBS_None, // RETURN = 356
    CEFBS_None, // TXD = 357
    CEFBS_None, // TXD_SHADOW = 358
    CEFBS_None, // WHILELOOP = 359
    CEFBS_None, // ADD = 360
    CEFBS_None, // ADDC_UINT = 361
    CEFBS_None, // ADD_INT = 362
    CEFBS_None, // ALU_CLAUSE = 363
    CEFBS_None, // AND_INT = 364
    CEFBS_None, // ASHR_eg = 365
    CEFBS_None, // ASHR_r600 = 366
    CEFBS_None, // BCNT_INT = 367
    CEFBS_None, // BFE_INT_eg = 368
    CEFBS_None, // BFE_UINT_eg = 369
    CEFBS_None, // BFI_INT_eg = 370
    CEFBS_None, // BFM_INT_eg = 371
    CEFBS_None, // BIT_ALIGN_INT_eg = 372
    CEFBS_None, // CEIL = 373
    CEFBS_None, // CF_ALU = 374
    CEFBS_None, // CF_ALU_BREAK = 375
    CEFBS_None, // CF_ALU_CONTINUE = 376
    CEFBS_None, // CF_ALU_ELSE_AFTER = 377
    CEFBS_None, // CF_ALU_POP_AFTER = 378
    CEFBS_None, // CF_ALU_PUSH_BEFORE = 379
    CEFBS_None, // CF_CALL_FS_EG = 380
    CEFBS_None, // CF_CALL_FS_R600 = 381
    CEFBS_None, // CF_CONTINUE_EG = 382
    CEFBS_None, // CF_CONTINUE_R600 = 383
    CEFBS_None, // CF_ELSE_EG = 384
    CEFBS_None, // CF_ELSE_R600 = 385
    CEFBS_None, // CF_END_CM = 386
    CEFBS_None, // CF_END_EG = 387
    CEFBS_None, // CF_END_R600 = 388
    CEFBS_None, // CF_JUMP_EG = 389
    CEFBS_None, // CF_JUMP_R600 = 390
    CEFBS_None, // CF_PUSH_EG = 391
    CEFBS_None, // CF_PUSH_ELSE_R600 = 392
    CEFBS_None, // CF_TC_EG = 393
    CEFBS_None, // CF_TC_R600 = 394
    CEFBS_None, // CF_VC_EG = 395
    CEFBS_None, // CF_VC_R600 = 396
    CEFBS_None, // CNDE_INT = 397
    CEFBS_None, // CNDE_eg = 398
    CEFBS_None, // CNDE_r600 = 399
    CEFBS_None, // CNDGE_INT = 400
    CEFBS_None, // CNDGE_eg = 401
    CEFBS_None, // CNDGE_r600 = 402
    CEFBS_None, // CNDGT_INT = 403
    CEFBS_None, // CNDGT_eg = 404
    CEFBS_None, // CNDGT_r600 = 405
    CEFBS_None, // COS_cm = 406
    CEFBS_None, // COS_eg = 407
    CEFBS_None, // COS_r600 = 408
    CEFBS_None, // COS_r700 = 409
    CEFBS_None, // CUBE_eg_real = 410
    CEFBS_None, // CUBE_r600_real = 411
    CEFBS_None, // DOT4_eg = 412
    CEFBS_None, // DOT4_r600 = 413
    CEFBS_None, // EG_ExportBuf = 414
    CEFBS_None, // EG_ExportSwz = 415
    CEFBS_None, // END_LOOP_EG = 416
    CEFBS_None, // END_LOOP_R600 = 417
    CEFBS_None, // EXP_IEEE_cm = 418
    CEFBS_None, // EXP_IEEE_eg = 419
    CEFBS_None, // EXP_IEEE_r600 = 420
    CEFBS_None, // FETCH_CLAUSE = 421
    CEFBS_None, // FFBH_UINT = 422
    CEFBS_None, // FFBL_INT = 423
    CEFBS_None, // FLOOR = 424
    CEFBS_None, // FLT16_TO_FLT32 = 425
    CEFBS_None, // FLT32_TO_FLT16 = 426
    CEFBS_None, // FLT_TO_INT_eg = 427
    CEFBS_None, // FLT_TO_INT_r600 = 428
    CEFBS_None, // FLT_TO_UINT_eg = 429
    CEFBS_None, // FLT_TO_UINT_r600 = 430
    CEFBS_None, // FMA_eg = 431
    CEFBS_None, // FRACT = 432
    CEFBS_None, // GROUP_BARRIER = 433
    CEFBS_None, // INTERP_LOAD_P0 = 434
    CEFBS_None, // INTERP_PAIR_XY = 435
    CEFBS_None, // INTERP_PAIR_ZW = 436
    CEFBS_None, // INTERP_VEC_LOAD = 437
    CEFBS_None, // INTERP_XY = 438
    CEFBS_None, // INTERP_ZW = 439
    CEFBS_None, // INT_TO_FLT_eg = 440
    CEFBS_None, // INT_TO_FLT_r600 = 441
    CEFBS_None, // KILLGT = 442
    CEFBS_None, // LDS_ADD = 443
    CEFBS_None, // LDS_ADD_RET = 444
    CEFBS_None, // LDS_AND = 445
    CEFBS_None, // LDS_AND_RET = 446
    CEFBS_None, // LDS_BYTE_READ_RET = 447
    CEFBS_None, // LDS_BYTE_WRITE = 448
    CEFBS_None, // LDS_CMPST = 449
    CEFBS_None, // LDS_CMPST_RET = 450
    CEFBS_None, // LDS_MAX_INT = 451
    CEFBS_None, // LDS_MAX_INT_RET = 452
    CEFBS_None, // LDS_MAX_UINT = 453
    CEFBS_None, // LDS_MAX_UINT_RET = 454
    CEFBS_None, // LDS_MIN_INT = 455
    CEFBS_None, // LDS_MIN_INT_RET = 456
    CEFBS_None, // LDS_MIN_UINT = 457
    CEFBS_None, // LDS_MIN_UINT_RET = 458
    CEFBS_None, // LDS_OR = 459
    CEFBS_None, // LDS_OR_RET = 460
    CEFBS_None, // LDS_READ_RET = 461
    CEFBS_None, // LDS_SHORT_READ_RET = 462
    CEFBS_None, // LDS_SHORT_WRITE = 463
    CEFBS_None, // LDS_SUB = 464
    CEFBS_None, // LDS_SUB_RET = 465
    CEFBS_None, // LDS_UBYTE_READ_RET = 466
    CEFBS_None, // LDS_USHORT_READ_RET = 467
    CEFBS_None, // LDS_WRITE = 468
    CEFBS_None, // LDS_WRXCHG = 469
    CEFBS_None, // LDS_WRXCHG_RET = 470
    CEFBS_None, // LDS_XOR = 471
    CEFBS_None, // LDS_XOR_RET = 472
    CEFBS_None, // LITERALS = 473
    CEFBS_None, // LOG_CLAMPED_eg = 474
    CEFBS_None, // LOG_CLAMPED_r600 = 475
    CEFBS_None, // LOG_IEEE_cm = 476
    CEFBS_None, // LOG_IEEE_eg = 477
    CEFBS_None, // LOG_IEEE_r600 = 478
    CEFBS_None, // LOOP_BREAK_EG = 479
    CEFBS_None, // LOOP_BREAK_R600 = 480
    CEFBS_None, // LSHL_eg = 481
    CEFBS_None, // LSHL_r600 = 482
    CEFBS_None, // LSHR_eg = 483
    CEFBS_None, // LSHR_r600 = 484
    CEFBS_None, // MAX = 485
    CEFBS_None, // MAX_DX10 = 486
    CEFBS_None, // MAX_INT = 487
    CEFBS_None, // MAX_UINT = 488
    CEFBS_None, // MIN = 489
    CEFBS_None, // MIN_DX10 = 490
    CEFBS_None, // MIN_INT = 491
    CEFBS_None, // MIN_UINT = 492
    CEFBS_None, // MOV = 493
    CEFBS_None, // MOVA_INT_eg = 494
    CEFBS_None, // MUL = 495
    CEFBS_None, // MULADD_IEEE_eg = 496
    CEFBS_None, // MULADD_IEEE_r600 = 497
    CEFBS_None, // MULADD_INT24_cm = 498
    CEFBS_None, // MULADD_UINT24_eg = 499
    CEFBS_None, // MULADD_eg = 500
    CEFBS_None, // MULADD_r600 = 501
    CEFBS_None, // MULHI_INT_cm = 502
    CEFBS_None, // MULHI_INT_cm24 = 503
    CEFBS_None, // MULHI_INT_eg = 504
    CEFBS_None, // MULHI_INT_r600 = 505
    CEFBS_None, // MULHI_UINT24_eg = 506
    CEFBS_None, // MULHI_UINT_cm = 507
    CEFBS_None, // MULHI_UINT_cm24 = 508
    CEFBS_None, // MULHI_UINT_eg = 509
    CEFBS_None, // MULHI_UINT_r600 = 510
    CEFBS_None, // MULLO_INT_cm = 511
    CEFBS_None, // MULLO_INT_eg = 512
    CEFBS_None, // MULLO_INT_r600 = 513
    CEFBS_None, // MULLO_UINT_cm = 514
    CEFBS_None, // MULLO_UINT_eg = 515
    CEFBS_None, // MULLO_UINT_r600 = 516
    CEFBS_None, // MUL_IEEE = 517
    CEFBS_None, // MUL_INT24_cm = 518
    CEFBS_None, // MUL_LIT_eg = 519
    CEFBS_None, // MUL_LIT_r600 = 520
    CEFBS_None, // MUL_UINT24_eg = 521
    CEFBS_None, // NOT_INT = 522
    CEFBS_None, // OR_INT = 523
    CEFBS_None, // PAD = 524
    CEFBS_None, // POP_EG = 525
    CEFBS_None, // POP_R600 = 526
    CEFBS_None, // PRED_SETE = 527
    CEFBS_None, // PRED_SETE_INT = 528
    CEFBS_None, // PRED_SETGE = 529
    CEFBS_None, // PRED_SETGE_INT = 530
    CEFBS_None, // PRED_SETGT = 531
    CEFBS_None, // PRED_SETGT_INT = 532
    CEFBS_None, // PRED_SETNE = 533
    CEFBS_None, // PRED_SETNE_INT = 534
    CEFBS_None, // R600_ExportBuf = 535
    CEFBS_None, // R600_ExportSwz = 536
    CEFBS_None, // RAT_ATOMIC_ADD_NORET = 537
    CEFBS_None, // RAT_ATOMIC_ADD_RTN = 538
    CEFBS_None, // RAT_ATOMIC_AND_NORET = 539
    CEFBS_None, // RAT_ATOMIC_AND_RTN = 540
    CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_NORET = 541
    CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_RTN = 542
    CEFBS_None, // RAT_ATOMIC_DEC_UINT_NORET = 543
    CEFBS_None, // RAT_ATOMIC_DEC_UINT_RTN = 544
    CEFBS_None, // RAT_ATOMIC_INC_UINT_NORET = 545
    CEFBS_None, // RAT_ATOMIC_INC_UINT_RTN = 546
    CEFBS_None, // RAT_ATOMIC_MAX_INT_NORET = 547
    CEFBS_None, // RAT_ATOMIC_MAX_INT_RTN = 548
    CEFBS_None, // RAT_ATOMIC_MAX_UINT_NORET = 549
    CEFBS_None, // RAT_ATOMIC_MAX_UINT_RTN = 550
    CEFBS_None, // RAT_ATOMIC_MIN_INT_NORET = 551
    CEFBS_None, // RAT_ATOMIC_MIN_INT_RTN = 552
    CEFBS_None, // RAT_ATOMIC_MIN_UINT_NORET = 553
    CEFBS_None, // RAT_ATOMIC_MIN_UINT_RTN = 554
    CEFBS_None, // RAT_ATOMIC_OR_NORET = 555
    CEFBS_None, // RAT_ATOMIC_OR_RTN = 556
    CEFBS_None, // RAT_ATOMIC_RSUB_NORET = 557
    CEFBS_None, // RAT_ATOMIC_RSUB_RTN = 558
    CEFBS_None, // RAT_ATOMIC_SUB_NORET = 559
    CEFBS_None, // RAT_ATOMIC_SUB_RTN = 560
    CEFBS_None, // RAT_ATOMIC_XCHG_INT_NORET = 561
    CEFBS_None, // RAT_ATOMIC_XCHG_INT_RTN = 562
    CEFBS_None, // RAT_ATOMIC_XOR_NORET = 563
    CEFBS_None, // RAT_ATOMIC_XOR_RTN = 564
    CEFBS_None, // RAT_MSKOR = 565
    CEFBS_None, // RAT_STORE_DWORD128 = 566
    CEFBS_None, // RAT_STORE_DWORD32 = 567
    CEFBS_None, // RAT_STORE_DWORD64 = 568
    CEFBS_None, // RAT_STORE_TYPED_cm = 569
    CEFBS_None, // RAT_STORE_TYPED_eg = 570
    CEFBS_None, // RAT_WRITE_CACHELESS_128_eg = 571
    CEFBS_None, // RAT_WRITE_CACHELESS_32_eg = 572
    CEFBS_None, // RAT_WRITE_CACHELESS_64_eg = 573
    CEFBS_None, // RECIPSQRT_CLAMPED_cm = 574
    CEFBS_None, // RECIPSQRT_CLAMPED_eg = 575
    CEFBS_None, // RECIPSQRT_CLAMPED_r600 = 576
    CEFBS_None, // RECIPSQRT_IEEE_cm = 577
    CEFBS_None, // RECIPSQRT_IEEE_eg = 578
    CEFBS_None, // RECIPSQRT_IEEE_r600 = 579
    CEFBS_None, // RECIP_CLAMPED_cm = 580
    CEFBS_None, // RECIP_CLAMPED_eg = 581
    CEFBS_None, // RECIP_CLAMPED_r600 = 582
    CEFBS_None, // RECIP_IEEE_cm = 583
    CEFBS_None, // RECIP_IEEE_eg = 584
    CEFBS_None, // RECIP_IEEE_r600 = 585
    CEFBS_None, // RECIP_UINT_eg = 586
    CEFBS_None, // RECIP_UINT_r600 = 587
    CEFBS_None, // RNDNE = 588
    CEFBS_None, // SETE = 589
    CEFBS_None, // SETE_DX10 = 590
    CEFBS_None, // SETE_INT = 591
    CEFBS_None, // SETGE_DX10 = 592
    CEFBS_None, // SETGE_INT = 593
    CEFBS_None, // SETGE_UINT = 594
    CEFBS_None, // SETGT_DX10 = 595
    CEFBS_None, // SETGT_INT = 596
    CEFBS_None, // SETGT_UINT = 597
    CEFBS_None, // SETNE_DX10 = 598
    CEFBS_None, // SETNE_INT = 599
    CEFBS_None, // SGE = 600
    CEFBS_None, // SGT = 601
    CEFBS_None, // SIN_cm = 602
    CEFBS_None, // SIN_eg = 603
    CEFBS_None, // SIN_r600 = 604
    CEFBS_None, // SIN_r700 = 605
    CEFBS_None, // SNE = 606
    CEFBS_None, // SUBB_UINT = 607
    CEFBS_None, // SUB_INT = 608
    CEFBS_None, // TEX_GET_GRADIENTS_H = 609
    CEFBS_None, // TEX_GET_GRADIENTS_V = 610
    CEFBS_None, // TEX_GET_TEXTURE_RESINFO = 611
    CEFBS_None, // TEX_LD = 612
    CEFBS_None, // TEX_LDPTR = 613
    CEFBS_None, // TEX_SAMPLE = 614
    CEFBS_None, // TEX_SAMPLE_C = 615
    CEFBS_None, // TEX_SAMPLE_C_G = 616
    CEFBS_None, // TEX_SAMPLE_C_L = 617
    CEFBS_None, // TEX_SAMPLE_C_LB = 618
    CEFBS_None, // TEX_SAMPLE_G = 619
    CEFBS_None, // TEX_SAMPLE_L = 620
    CEFBS_None, // TEX_SAMPLE_LB = 621
    CEFBS_None, // TEX_SET_GRADIENTS_H = 622
    CEFBS_None, // TEX_SET_GRADIENTS_V = 623
    CEFBS_None, // TEX_VTX_CONSTBUF = 624
    CEFBS_None, // TEX_VTX_TEXBUF = 625
    CEFBS_None, // TRUNC = 626
    CEFBS_None, // UINT_TO_FLT_eg = 627
    CEFBS_None, // UINT_TO_FLT_r600 = 628
    CEFBS_None, // VTX_READ_128_cm = 629
    CEFBS_None, // VTX_READ_128_eg = 630
    CEFBS_None, // VTX_READ_16_cm = 631
    CEFBS_None, // VTX_READ_16_eg = 632
    CEFBS_None, // VTX_READ_32_cm = 633
    CEFBS_None, // VTX_READ_32_eg = 634
    CEFBS_None, // VTX_READ_64_cm = 635
    CEFBS_None, // VTX_READ_64_eg = 636
    CEFBS_None, // VTX_READ_8_cm = 637
    CEFBS_None, // VTX_READ_8_eg = 638
    CEFBS_None, // WHILE_LOOP_EG = 639
    CEFBS_None, // WHILE_LOOP_R600 = 640
    CEFBS_None, // XOR_INT = 641
  };

  assert(Opcode < 642);
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
}

} // end namespace R600_MC
} // end namespace llvm
#endif // GET_COMPUTE_FEATURES

#ifdef GET_AVAILABLE_OPCODE_CHECKER
#undef GET_AVAILABLE_OPCODE_CHECKER
namespace llvm {
namespace R600_MC {
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  return !MissingFeatures.any();
}
} // end namespace R600_MC
} // end namespace llvm
#endif // GET_AVAILABLE_OPCODE_CHECKER

#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
#undef ENABLE_INSTR_PREDICATE_VERIFIER
#include <sstream>

namespace llvm {
namespace R600_MC {

#ifndef NDEBUG
static const char *SubtargetFeatureNames[] = {
  nullptr
};

#endif // NDEBUG

void verifyInstructionPredicates(
    unsigned Opcode, const FeatureBitset &Features) {
#ifndef NDEBUG
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  if (MissingFeatures.any()) {
    std::ostringstream Msg;
    Msg << "Attempting to emit " << &R600InstrNameData[R600InstrNameIndices[Opcode]]
        << " instruction but the ";
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
      if (MissingFeatures.test(i))
        Msg << SubtargetFeatureNames[i] << " ";
    Msg << "predicate(s) are not met";
    report_fatal_error(Msg.str().c_str());
  }
#endif // NDEBUG
}
} // end namespace R600_MC
} // end namespace llvm
#endif // ENABLE_INSTR_PREDICATE_VERIFIER

#ifdef GET_INSTRMAP_INFO
#undef GET_INSTRMAP_INFO
namespace llvm {

namespace R600 {

enum DisableEncoding {
	DisableEncoding_
};

// getLDSNoRetOp
LLVM_READONLY
int getLDSNoRetOp(uint16_t Opcode) {
static const uint16_t getLDSNoRetOpTable[][2] = {
  { R600::LDS_ADD_RET, R600::LDS_ADD },
  { R600::LDS_AND_RET, R600::LDS_AND },
  { R600::LDS_MAX_INT_RET, R600::LDS_MAX_INT },
  { R600::LDS_MAX_UINT_RET, R600::LDS_MAX_UINT },
  { R600::LDS_MIN_INT_RET, R600::LDS_MIN_INT },
  { R600::LDS_MIN_UINT_RET, R600::LDS_MIN_UINT },
  { R600::LDS_OR_RET, R600::LDS_OR },
  { R600::LDS_SUB_RET, R600::LDS_SUB },
  { R600::LDS_WRXCHG_RET, R600::LDS_WRXCHG },
  { R600::LDS_XOR_RET, R600::LDS_XOR },
}; // End of getLDSNoRetOpTable

  unsigned mid;
  unsigned start = 0;
  unsigned end = 10;
  while (start < end) {
    mid = start + (end - start) / 2;
    if (Opcode == getLDSNoRetOpTable[mid][0]) {
      break;
    }
    if (Opcode < getLDSNoRetOpTable[mid][0])
      end = mid;
    else
      start = mid + 1;
  }
  if (start == end)
    return -1; // Instruction doesn't exist in this table.

  return getLDSNoRetOpTable[mid][1];
}

} // end namespace R600
} // end namespace llvm
#endif // GET_INSTRMAP_INFO