llvm/llvm/lib/Target/AMDGPU/R600ClauseMergePass.cpp

//===-- R600ClauseMergePass - Merge consecutive CF_ALU -------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
/// \file
/// R600EmitClauseMarker pass emits CFAlu instruction in a conservative manner.
/// This pass is merging consecutive CFAlus where applicable.
/// It needs to be called after IfCvt for best results.
//===----------------------------------------------------------------------===//

#include "MCTargetDesc/R600MCTargetDesc.h"
#include "R600.h"
#include "R600Subtarget.h"
#include "llvm/CodeGen/MachineFunctionPass.h"

usingnamespacellvm;

#define DEBUG_TYPE …

namespace {

static bool isCFAlu(const MachineInstr &MI) { … }

class R600ClauseMergePass : public MachineFunctionPass { … };

} // end anonymous namespace

INITIALIZE_PASS_BEGIN(R600ClauseMergePass, DEBUG_TYPE,
                      "R600 Clause Merge", false, false)
INITIALIZE_PASS_END(R600ClauseMergePass, DEBUG_TYPE,
                    "R600 Clause Merge", false, false)

char R600ClauseMergePass::ID = …;

char &llvm::R600ClauseMergePassID = …;

unsigned R600ClauseMergePass::getCFAluSize(const MachineInstr &MI) const { … }

bool R600ClauseMergePass::isCFAluEnabled(const MachineInstr &MI) const { … }

void R600ClauseMergePass::cleanPotentialDisabledCFAlu(
    MachineInstr &CFAlu) const { … }

bool R600ClauseMergePass::mergeIfPossible(MachineInstr &RootCFAlu,
                                          const MachineInstr &LatrCFAlu) const { … }

bool R600ClauseMergePass::runOnMachineFunction(MachineFunction &MF) { … }

StringRef R600ClauseMergePass::getPassName() const { … }

llvm::FunctionPass *llvm::createR600ClauseMergePass() { … }