llvm/llvm/lib/Target/ARM/ARMISelLowering.h

//===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file defines the interfaces that ARM uses to lower LLVM code into a
// selection DAG.
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
#define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H

#include "MCTargetDesc/ARMBaseInfo.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/Support/CodeGen.h"
#include <optional>
#include <utility>

namespace llvm {

class ARMSubtarget;
class DataLayout;
class FastISel;
class FunctionLoweringInfo;
class GlobalValue;
class InstrItineraryData;
class Instruction;
class IRBuilderBase;
class MachineBasicBlock;
class MachineInstr;
class SelectionDAG;
class TargetLibraryInfo;
class TargetMachine;
class TargetRegisterInfo;
class VectorType;

  namespace ARMISD {

  // ARM Specific DAG Nodes
  enum NodeType : unsigned { … };

  } // end namespace ARMISD

  namespace ARM {
  /// Possible values of current rounding mode, which is specified in bits
  /// 23:22 of FPSCR.
  enum Rounding { … };

  // Bit position of rounding mode bits in FPSCR.
  const unsigned RoundingBitsPos = …;

  // Bits of floating-point status. These are NZCV flags, QC bit and cumulative
  // FP exception bits.
  const unsigned FPStatusBits = …;

  // Some bits in the FPSCR are not yet defined.  They must be preserved when
  // modifying the contents.
  const unsigned FPReservedBits = …;
  } // namespace ARM

  /// Define some predicates that are used for node matching.
  namespace ARM {

    bool isBitFieldInvertedMask(unsigned v);

  } // end namespace ARM

  //===--------------------------------------------------------------------===//
  //  ARMTargetLowering - ARM Implementation of the TargetLowering interface

  class ARMTargetLowering : public TargetLowering { … };

  enum VMOVModImmType { … };

  namespace ARM {

    FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
                             const TargetLibraryInfo *libInfo);

  } // end namespace ARM

} // end namespace llvm

#endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H