//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file defines an instruction selector for the ARM target. // //===----------------------------------------------------------------------===// #include "ARM.h" #include "ARMBaseInstrInfo.h" #include "ARMTargetMachine.h" #include "MCTargetDesc/ARMAddressingModes.h" #include "Utils/ARMBaseInfo.h" #include "llvm/ADT/APSInt.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/CodeGen/TargetLowering.h" #include "llvm/IR/CallingConv.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/Function.h" #include "llvm/IR/Intrinsics.h" #include "llvm/IR/IntrinsicsARM.h" #include "llvm/IR/LLVMContext.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetOptions.h" #include <optional> usingnamespacellvm; #define DEBUG_TYPE … #define PASS_NAME … static cl::opt<bool> DisableShifterOp("disable-shifter-op", cl::Hidden, cl::desc("Disable isel of shifter-op"), cl::init(false)); //===--------------------------------------------------------------------===// /// ARMDAGToDAGISel - ARM specific code to select ARM machine /// instructions for SelectionDAG operations. /// namespace { class ARMDAGToDAGISel : public SelectionDAGISel { … }; class ARMDAGToDAGISelLegacy : public SelectionDAGISelLegacy { … }; } char ARMDAGToDAGISelLegacy::ID = …; INITIALIZE_PASS(…) /// isInt32Immediate - This method tests to see if the node is a 32-bit constant /// operand. If so Imm will receive the 32-bit value. static bool isInt32Immediate(SDNode *N, unsigned &Imm) { … } // isInt32Immediate - This method tests to see if a constant operand. // If so Imm will receive the 32 bit value. static bool isInt32Immediate(SDValue N, unsigned &Imm) { … } // isOpcWithIntImmediate - This method tests to see if the node is a specific // opcode and that it has a immediate integer right operand. // If so Imm will receive the 32 bit value. static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { … } /// Check whether a particular node is a constant value representable as /// (N * Scale) where (N in [\p RangeMin, \p RangeMax). /// /// \param ScaledConstant [out] - On success, the pre-scaled constant value. static bool isScaledConstantInRange(SDValue Node, int Scale, int RangeMin, int RangeMax, int &ScaledConstant) { … } void ARMDAGToDAGISel::PreprocessISelDAG() { … } /// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS /// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at /// least on current ARM implementations) which should be avoidded. bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const { … } bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift, ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt) { … } bool ARMDAGToDAGISel::canExtractShiftFromMul(const SDValue &N, unsigned MaxShift, unsigned &PowerOfTwo, SDValue &NewMulConst) const { … } void ARMDAGToDAGISel::replaceDAGValue(const SDValue &N, SDValue M) { … } bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N, SDValue &BaseReg, SDValue &Opc, bool CheckProfitability) { … } bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N, SDValue &BaseReg, SDValue &ShReg, SDValue &Opc, bool CheckProfitability) { … } // Determine whether an ISD::OR's operands are suitable to turn the operation // into an addition, which often has more compact encodings. bool ARMDAGToDAGISel::SelectAddLikeOr(SDNode *Parent, SDValue N, SDValue &Out) { … } bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm) { … } bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) { … } bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) { … } bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) { … } bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) { … } bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) { … } bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) { … } bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) { … } bool ARMDAGToDAGISel::IsAddressingMode5(SDValue N, SDValue &Base, SDValue &Offset, bool FP16) { … } bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N, SDValue &Base, SDValue &Offset) { … } bool ARMDAGToDAGISel::SelectAddrMode5FP16(SDValue N, SDValue &Base, SDValue &Offset) { … } bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr, SDValue &Align) { … } bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset) { … } bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label) { … } //===----------------------------------------------------------------------===// // Thumb Addressing Modes //===----------------------------------------------------------------------===// static bool shouldUseZeroOffsetLdSt(SDValue N) { … } bool ARMDAGToDAGISel::SelectThumbAddrModeRRSext(SDValue N, SDValue &Base, SDValue &Offset) { … } bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset) { … } bool ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base, SDValue &OffImm) { … } bool ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base, SDValue &OffImm) { … } bool ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base, SDValue &OffImm) { … } bool ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base, SDValue &OffImm) { … } bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm) { … } template <unsigned Shift> bool ARMDAGToDAGISel::SelectTAddrModeImm7(SDValue N, SDValue &Base, SDValue &OffImm) { … } //===----------------------------------------------------------------------===// // Thumb 2 Addressing Modes //===----------------------------------------------------------------------===// bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm) { … } template <unsigned Shift> bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N, SDValue &Base, SDValue &OffImm) { … } bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N, SDValue &Base, SDValue &OffImm) { … } bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N, SDValue &OffImm){ … } template <unsigned Shift> bool ARMDAGToDAGISel::SelectT2AddrModeImm7(SDValue N, SDValue &Base, SDValue &OffImm) { … } template <unsigned Shift> bool ARMDAGToDAGISel::SelectT2AddrModeImm7Offset(SDNode *Op, SDValue N, SDValue &OffImm) { … } bool ARMDAGToDAGISel::SelectT2AddrModeImm7Offset(SDNode *Op, SDValue N, SDValue &OffImm, unsigned Shift) { … } template <int Min, int Max> bool ARMDAGToDAGISel::SelectImmediateInRange(SDValue N, SDValue &OffImm) { … } bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N, SDValue &Base, SDValue &OffReg, SDValue &ShImm) { … } bool ARMDAGToDAGISel::SelectT2AddrModeExclusive(SDValue N, SDValue &Base, SDValue &OffImm) { … } //===--------------------------------------------------------------------===// /// getAL - Returns a ARMCC::AL immediate node. static inline SDValue getAL(SelectionDAG *CurDAG, const SDLoc &dl) { … } void ARMDAGToDAGISel::transferMemOperands(SDNode *N, SDNode *Result) { … } bool ARMDAGToDAGISel::tryARMIndexedLoad(SDNode *N) { … } bool ARMDAGToDAGISel::tryT1IndexedLoad(SDNode *N) { … } bool ARMDAGToDAGISel::tryT2IndexedLoad(SDNode *N) { … } bool ARMDAGToDAGISel::tryMVEIndexedLoad(SDNode *N) { … } /// Form a GPRPair pseudo register from a pair of GPR regs. SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { … } /// Form a D register from a pair of S registers. SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) { … } /// Form a quad register from a pair of D registers. SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { … } /// Form 4 consecutive D registers from a pair of Q registers. SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) { … } /// Form 4 consecutive S registers. SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) { … } /// Form 4 consecutive D registers. SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) { … } /// Form 4 consecutive Q registers. SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) { … } /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand /// of a NEON VLD or VST instruction. The supported values depend on the /// number of registers being loaded. SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs, bool is64BitVector) { … } static bool isVLDfixed(unsigned Opc) { … } static bool isVSTfixed(unsigned Opc) { … } // Get the register stride update opcode of a VLD/VST instruction that // is otherwise equivalent to the given fixed stride updating instruction. static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) { … } /// Returns true if the given increment is a Constant known to be equal to the /// access size performed by a NEON load/store. This means the "[rN]!" form can /// be used. static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) { … } void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, const uint16_t *DOpcodes, const uint16_t *QOpcodes0, const uint16_t *QOpcodes1) { … } void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, const uint16_t *DOpcodes, const uint16_t *QOpcodes0, const uint16_t *QOpcodes1) { … } void ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating, unsigned NumVecs, const uint16_t *DOpcodes, const uint16_t *QOpcodes) { … } template <typename SDValueVector> void ARMDAGToDAGISel::AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc, SDValue PredicateMask) { … } template <typename SDValueVector> void ARMDAGToDAGISel::AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc, SDValue PredicateMask, SDValue Inactive) { … } template <typename SDValueVector> void ARMDAGToDAGISel::AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc) { … } template <typename SDValueVector> void ARMDAGToDAGISel::AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc, EVT InactiveTy) { … } void ARMDAGToDAGISel::SelectMVE_WB(SDNode *N, const uint16_t *Opcodes, bool Predicated) { … } void ARMDAGToDAGISel::SelectMVE_LongShift(SDNode *N, uint16_t Opcode, bool Immediate, bool HasSaturationOperand) { … } void ARMDAGToDAGISel::SelectMVE_VADCSBC(SDNode *N, uint16_t OpcodeWithCarry, uint16_t OpcodeWithNoCarry, bool Add, bool Predicated) { … } void ARMDAGToDAGISel::SelectMVE_VSHLC(SDNode *N, bool Predicated) { … } static bool SDValueToConstBool(SDValue SDVal) { … } void ARMDAGToDAGISel::SelectBaseMVE_VMLLDAV(SDNode *N, bool Predicated, const uint16_t *OpcodesS, const uint16_t *OpcodesU, size_t Stride, size_t TySize) { … } void ARMDAGToDAGISel::SelectMVE_VMLLDAV(SDNode *N, bool Predicated, const uint16_t *OpcodesS, const uint16_t *OpcodesU) { … } void ARMDAGToDAGISel::SelectMVE_VRMLLDAVH(SDNode *N, bool Predicated, const uint16_t *OpcodesS, const uint16_t *OpcodesU) { … } void ARMDAGToDAGISel::SelectMVE_VLD(SDNode *N, unsigned NumVecs, const uint16_t *const *Opcodes, bool HasWriteback) { … } void ARMDAGToDAGISel::SelectMVE_VxDUP(SDNode *N, const uint16_t *Opcodes, bool Wrapping, bool Predicated) { … } void ARMDAGToDAGISel::SelectCDE_CXxD(SDNode *N, uint16_t Opcode, size_t NumExtraOps, bool HasAccum) { … } void ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool IsIntrinsic, bool isUpdating, unsigned NumVecs, const uint16_t *DOpcodes, const uint16_t *QOpcodes0, const uint16_t *QOpcodes1) { … } bool ARMDAGToDAGISel::tryInsertVectorElt(SDNode *N) { … } bool ARMDAGToDAGISel::transformFixedFloatingPointConversion(SDNode *N, SDNode *FMul, bool IsUnsigned, bool FixedToFloat) { … } bool ARMDAGToDAGISel::tryFP_TO_INT(SDNode *N, SDLoc dl) { … } bool ARMDAGToDAGISel::tryFMULFixed(SDNode *N, SDLoc dl) { … } bool ARMDAGToDAGISel::tryV6T2BitfieldExtractOp(SDNode *N, bool isSigned) { … } /// Target-specific DAG combining for ISD::SUB. /// Target-independent combining lowers SELECT_CC nodes of the form /// select_cc setg[ge] X, 0, X, -X /// select_cc setgt X, -1, X, -X /// select_cc setl[te] X, 0, -X, X /// select_cc setlt X, 1, -X, X /// which represent Integer ABS into: /// Y = sra (X, size(X)-1); sub (xor (X, Y), Y) /// ARM instruction selection detects the latter and matches it to /// ARM::ABS or ARM::t2ABS machine node. bool ARMDAGToDAGISel::tryABSOp(SDNode *N){ … } /// We've got special pseudo-instructions for these void ARMDAGToDAGISel::SelectCMP_SWAP(SDNode *N) { … } static std::optional<std::pair<unsigned, unsigned>> getContiguousRangeOfSetBits(const APInt &A) { … } void ARMDAGToDAGISel::SelectCMPZ(SDNode *N, bool &SwitchEQNEToPLMI) { … } static unsigned getVectorShuffleOpcode(EVT VT, unsigned Opc64[3], unsigned Opc128[3]) { … } void ARMDAGToDAGISel::Select(SDNode *N) { … } // Inspect a register string of the form // cp<coprocessor>:<opc1>:c<CRn>:c<CRm>:<opc2> (32bit) or // cp<coprocessor>:<opc1>:c<CRm> (64bit) inspect the fields of the string // and obtain the integer operands from them, adding these operands to the // provided vector. static void getIntOperandsFromRegisterString(StringRef RegString, SelectionDAG *CurDAG, const SDLoc &DL, std::vector<SDValue> &Ops) { … } // Maps a Banked Register string to its mask value. The mask value returned is // for use in the MRSbanked / MSRbanked instruction nodes as the Banked Register // mask operand, which expresses which register is to be used, e.g. r8, and in // which mode it is to be used, e.g. usr. Returns -1 to signify that the string // was invalid. static inline int getBankedRegisterMask(StringRef RegString) { … } // The flags here are common to those allowed for apsr in the A class cores and // those allowed for the special registers in the M class cores. Returns a // value representing which flags were present, -1 if invalid. static inline int getMClassFlagsMask(StringRef Flags) { … } // Maps MClass special registers string to its value for use in the // t2MRS_M/t2MSR_M instruction nodes as the SYSm value operand. // Returns -1 to signify that the string was invalid. static int getMClassRegisterMask(StringRef Reg, const ARMSubtarget *Subtarget) { … } static int getARClassRegisterMask(StringRef Reg, StringRef Flags) { … } // Lower the read_register intrinsic to ARM specific DAG nodes // using the supplied metadata string to select the instruction node to use // and the registers/masks to construct as operands for the node. bool ARMDAGToDAGISel::tryReadRegister(SDNode *N){ … } // Lower the write_register intrinsic to ARM specific DAG nodes // using the supplied metadata string to select the instruction node to use // and the registers/masks to use in the nodes bool ARMDAGToDAGISel::tryWriteRegister(SDNode *N){ … } bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){ … } bool ARMDAGToDAGISel::SelectInlineAsmMemoryOperand( const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector<SDValue> &OutOps) { … } /// createARMISelDag - This pass converts a legalized DAG into a /// ARM-specific DAG, ready for instruction scheduling. /// FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM, CodeGenOptLevel OptLevel) { … }
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