llvm/llvm/lib/Target/ARM/ARMSubtarget.cpp

//===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file implements the ARM specific subclass of TargetSubtargetInfo.
//
//===----------------------------------------------------------------------===//

#include "ARM.h"

#include "ARMCallLowering.h"
#include "ARMFrameLowering.h"
#include "ARMInstrInfo.h"
#include "ARMLegalizerInfo.h"
#include "ARMRegisterBankInfo.h"
#include "ARMSubtarget.h"
#include "ARMTargetMachine.h"
#include "MCTargetDesc/ARMMCTargetDesc.h"
#include "Thumb1FrameLowering.h"
#include "Thumb1InstrInfo.h"
#include "Thumb2InstrInfo.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/Twine.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCTargetOptions.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/TargetParser/ARMTargetParser.h"
#include "llvm/TargetParser/Triple.h"

usingnamespacellvm;

#define DEBUG_TYPE …

#define GET_SUBTARGETINFO_TARGET_DESC
#define GET_SUBTARGETINFO_CTOR
#include "ARMGenSubtargetInfo.inc"

static cl::opt<bool>
UseFusedMulOps("arm-use-mulops",
               cl::init(true), cl::Hidden);

enum ITMode { … };

static cl::opt<ITMode>
    IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
       cl::values(clEnumValN(DefaultIT, "arm-default-it",
                             "Generate any type of IT block"),
                  clEnumValN(RestrictedIT, "arm-restrict-it",
                             "Disallow complex IT blocks")));

/// ForceFastISel - Use the fast-isel, even for subtargets where it is not
/// currently supported (for testing only).
static cl::opt<bool>
ForceFastISel("arm-force-fast-isel",
               cl::init(false), cl::Hidden);

/// initializeSubtargetDependencies - Initializes using a CPU and feature string
/// so that we can use initializer lists for subtarget initialization.
ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
                                                            StringRef FS) { … }

ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
                                                        StringRef FS) { … }

ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
                           const std::string &FS,
                           const ARMBaseTargetMachine &TM, bool IsLittle,
                           bool MinSize)
    : … { … }

const CallLowering *ARMSubtarget::getCallLowering() const { … }

InstructionSelector *ARMSubtarget::getInstructionSelector() const { … }

const LegalizerInfo *ARMSubtarget::getLegalizerInfo() const { … }

const RegisterBankInfo *ARMSubtarget::getRegBankInfo() const { … }

bool ARMSubtarget::isXRaySupported() const { … }

void ARMSubtarget::initializeEnvironment() { … }

void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { … }

bool ARMSubtarget::isTargetHardFloat() const { … }

bool ARMSubtarget::isAPCS_ABI() const { … }
bool ARMSubtarget::isAAPCS_ABI() const { … }
bool ARMSubtarget::isAAPCS16_ABI() const { … }

bool ARMSubtarget::isROPI() const { … }
bool ARMSubtarget::isRWPI() const { … }

bool ARMSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const { … }

bool ARMSubtarget::isGVInGOT(const GlobalValue *GV) const { … }

unsigned ARMSubtarget::getMispredictionPenalty() const { … }

bool ARMSubtarget::enableMachineScheduler() const { … }

bool ARMSubtarget::enableSubRegLiveness() const { … }

bool ARMSubtarget::enableMachinePipeliner() const { … }

bool ARMSubtarget::useDFAforSMS() const { … }

// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
bool ARMSubtarget::enablePostRAScheduler() const { … }

bool ARMSubtarget::enablePostRAMachineScheduler() const { … }

bool ARMSubtarget::useStride4VFPs() const { … }

bool ARMSubtarget::useMovt() const { … }

bool ARMSubtarget::useFastISel() const { … }

unsigned ARMSubtarget::getGPRAllocationOrder(const MachineFunction &MF) const { … }

bool ARMSubtarget::ignoreCSRForAllocationOrder(const MachineFunction &MF,
                                               unsigned PhysReg) const { … }

bool ARMSubtarget::splitFramePointerPush(const MachineFunction &MF) const { … }