//===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// #include "ARMBaseInstrInfo.h" #include "ARMFeatures.h" #include "MCTargetDesc/ARMAddressingModes.h" #include "MCTargetDesc/ARMBaseInfo.h" #include "MCTargetDesc/ARMInstPrinter.h" #include "MCTargetDesc/ARMMCExpr.h" #include "MCTargetDesc/ARMMCTargetDesc.h" #include "TargetInfo/ARMTargetInfo.h" #include "Utils/ARMBaseInfo.h" #include "llvm/ADT/APFloat.h" #include "llvm/ADT/APInt.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallBitVector.h" #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringMap.h" #include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringSet.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/ADT/Twine.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCParser/MCAsmParserExtension.h" #include "llvm/MC/MCParser/MCAsmParserUtils.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/MC/MCParser/MCTargetAsmParser.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSection.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/ARMBuildAttributes.h" #include "llvm/Support/ARMEHABI.h" #include "llvm/Support/Casting.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/SMLoc.h" #include "llvm/Support/raw_ostream.h" #include "llvm/TargetParser/SubtargetFeature.h" #include "llvm/TargetParser/TargetParser.h" #include "llvm/TargetParser/Triple.h" #include <algorithm> #include <cassert> #include <cstddef> #include <cstdint> #include <iterator> #include <limits> #include <memory> #include <optional> #include <string> #include <utility> #include <vector> #define DEBUG_TYPE … usingnamespacellvm; namespace { class ARMOperand; enum class ImplicitItModeTy { … }; static cl::opt<ImplicitItModeTy> ImplicitItMode( "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly), cl::desc("Allow conditional instructions outside of an IT block"), cl::values(clEnumValN(ImplicitItModeTy::Always, "always", "Accept in both ISAs, emit implicit ITs in Thumb"), clEnumValN(ImplicitItModeTy::Never, "never", "Warn in ARM, reject in Thumb"), clEnumValN(ImplicitItModeTy::ARMOnly, "arm", "Accept in ARM, reject in Thumb"), clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb", "Warn in ARM, emit implicit ITs in Thumb"))); static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes", cl::init(false)); enum VectorLaneTy { … }; static inline unsigned extractITMaskBit(unsigned Mask, unsigned Position) { … } class UnwindContext { … }; // Various sets of ARM instruction mnemonics which are used by the asm parser class ARMMnemonicSets { … }; ARMMnemonicSets::ARMMnemonicSets(const MCSubtargetInfo &STI) { … } class ARMAsmParser : public MCTargetAsmParser { … }; /// ARMOperand - Instances of this class represent a parsed ARM machine /// operand. class ARMOperand : public MCParsedAsmOperand { … }; } // end anonymous namespace. void ARMOperand::print(raw_ostream &OS) const { … } /// @name Auto-generated Match Functions /// { static MCRegister MatchRegisterName(StringRef Name); /// } static bool isDataTypeToken(StringRef Tok) { … } static unsigned getMnemonicOpsEndInd(const OperandVector &Operands) { … } bool ARMAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) { … } ParseStatus ARMAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) { … } /// Try to parse a register name. The token must be an Identifier when called, /// and if it is a register name the token is eaten and the register is /// returned. Otherwise return an invalid MCRegister. MCRegister ARMAsmParser::tryParseRegister(bool AllowOutOfBoundReg) { … } std::optional<ARM_AM::ShiftOpc> ARMAsmParser::tryParseShiftToken() { … } // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. // If a recoverable error occurs, return 1. If an irrecoverable error // occurs, return -1. An irrecoverable error is one where tokens have been // consumed in the process of trying to parse the shifter (i.e., when it is // indeed a shifter operand, but malformed). int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) { … } /// Try to parse a register name. The token must be an Identifier when called. /// If it's a register, an AsmOperand is created. Another AsmOperand is created /// if there is a "writeback". 'true' if it's not a register. /// /// TODO this is likely to change to allow different register types and or to /// parse for a specific register type. bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) { … } /// MatchCoprocessorOperandName - Try to parse an coprocessor related /// instruction with a symbolic operand name. /// We accept "crN" syntax for GAS compatibility. /// <operand-name> ::= <prefix><number> /// If CoprocOp is 'c', then: /// <prefix> ::= c | cr /// If CoprocOp is 'p', then : /// <prefix> ::= p /// <number> ::= integer in range [0, 15] static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { … } /// parseITCondCode - Try to parse a condition code for an IT instruction. ParseStatus ARMAsmParser::parseITCondCode(OperandVector &Operands) { … } /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The /// token must be an Identifier when called, and if it is a coprocessor /// number, the token is eaten and the operand is added to the operand list. ParseStatus ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) { … } /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The /// token must be an Identifier when called, and if it is a coprocessor /// number, the token is eaten and the operand is added to the operand list. ParseStatus ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) { … } /// parseCoprocOptionOperand - Try to parse an coprocessor option operand. /// coproc_option : '{' imm0_255 '}' ParseStatus ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) { … } // For register list parsing, we need to map from raw GPR register numbering // to the enumeration values. The enumeration values aren't sorted by // register number due to our using "sp", "lr" and "pc" as canonical names. static MCRegister getNextRegister(MCRegister Reg) { … } // Insert an <Encoding, Register> pair in an ordered vector. Return true on // success, or false, if duplicate encoding found. static bool insertNoDuplicates(SmallVectorImpl<std::pair<unsigned, MCRegister>> &Regs, unsigned Enc, MCRegister Reg) { … } /// Parse a register list. bool ARMAsmParser::parseRegisterList(OperandVector &Operands, bool EnforceOrder, bool AllowRAAC, bool AllowOutOfBoundReg) { … } // Helper function to parse the lane index for vector lists. ParseStatus ARMAsmParser::parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) { … } // parse a vector register list ParseStatus ARMAsmParser::parseVectorList(OperandVector &Operands) { … } /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. ParseStatus ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) { … } ParseStatus ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) { … } /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options. ParseStatus ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) { … } /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. ParseStatus ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) { … } /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. ParseStatus ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) { … } /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for /// use in the MRS/MSR instructions added to support virtualization. ParseStatus ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) { … } // FIXME: Unify the different methods for handling shift operators // and use TableGen matching mechanisms to do the validation rather than // separate parsing paths. ParseStatus ARMAsmParser::parsePKHImm(OperandVector &Operands, ARM_AM::ShiftOpc Op, int Low, int High) { … } ParseStatus ARMAsmParser::parseSetEndImm(OperandVector &Operands) { … } /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT /// instructions. Legal values are: /// lsl #n 'n' in [0,31] /// asr #n 'n' in [1,32] /// n == 32 encoded as n == 0. ParseStatus ARMAsmParser::parseShifterImm(OperandVector &Operands) { … } /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family /// of instructions. Legal values are: /// ror #n 'n' in {0, 8, 16, 24} ParseStatus ARMAsmParser::parseRotImm(OperandVector &Operands) { … } ParseStatus ARMAsmParser::parseModImm(OperandVector &Operands) { … } ParseStatus ARMAsmParser::parseBitfield(OperandVector &Operands) { … } ParseStatus ARMAsmParser::parsePostIdxReg(OperandVector &Operands) { … } ParseStatus ARMAsmParser::parseAM3Offset(OperandVector &Operands) { … } // Finds the index of the first CondCode operator, if there is none returns 0 unsigned findCondCodeInd(const OperandVector &Operands, unsigned MnemonicOpsEndInd) { … } unsigned findCCOutInd(const OperandVector &Operands, unsigned MnemonicOpsEndInd) { … } /// Convert parsed operands to MCInst. Needed here because this instruction /// only has two register operands, but multiplication is commutative so /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN". void ARMAsmParser::cvtThumbMultiply(MCInst &Inst, const OperandVector &Operands) { … } void ARMAsmParser::cvtThumbBranches(MCInst &Inst, const OperandVector &Operands) { … } void ARMAsmParser::cvtMVEVMOVQtoDReg( MCInst &Inst, const OperandVector &Operands) { … } /// Parse an ARM memory expression, return false if successful else return true /// or an error. The first token must be a '[' when called. bool ARMAsmParser::parseMemory(OperandVector &Operands) { … } /// parseMemRegOffsetShift - one of these two: /// ( lsl | lsr | asr | ror ) , # shift_amount /// rrx /// return true if it parses a shift otherwise it returns false. bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, unsigned &Amount) { … } /// parseFPImm - A floating point immediate expression operand. ParseStatus ARMAsmParser::parseFPImm(OperandVector &Operands) { … } /// Parse a arm instruction operand. For now this parses the operand regardless /// of the mnemonic. bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { … } bool ARMAsmParser::parseImmExpr(int64_t &Out) { … } // parsePrefix - Parse ARM 16-bit relocations expression prefixes, i.e. // :lower16: and :upper16: and Thumb 8-bit relocation expression prefixes, i.e. // :upper8_15:, :upper0_7:, :lower8_15: and :lower0_7: bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { … } /// Given a mnemonic, split out possible predication code and carry /// setting letters to form a canonical mnemonic and flags. // // FIXME: Would be nice to autogen this. // FIXME: This is a bit of a maze of special cases. StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, StringRef ExtraToken, ARMCC::CondCodes &PredicationCode, ARMVCC::VPTCodes &VPTPredicationCode, bool &CarrySetting, unsigned &ProcessorIMod, StringRef &ITMask) { … } /// Given a canonical mnemonic, determine if the instruction ever allows /// inclusion of carry set or predication code operands. // // FIXME: It would be nice to autogen this. void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic, StringRef ExtraToken, StringRef FullInst, bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode, bool &CanAcceptVPTPredicationCode) { … } bool operandsContainWide(OperandVector &Operands, unsigned MnemonicOpsEndInd) { … } // Some Thumb instructions have two operand forms that are not // available as three operand, convert to two operand form if possible. // // FIXME: We would really like to be able to tablegen'erate this. void ARMAsmParser::tryConvertingToTwoOperandForm( StringRef Mnemonic, ARMCC::CondCodes PredicationCode, bool CarrySetting, OperandVector &Operands, unsigned MnemonicOpsEndInd) { … } // this function returns true if the operand is one of the following // relocations: :upper8_15:, :upper0_7:, :lower8_15: or :lower0_7: static bool isThumbI8Relocation(MCParsedAsmOperand &MCOp) { … } bool ARMAsmParser::shouldOmitVectorPredicateOperand( StringRef Mnemonic, OperandVector &Operands, unsigned MnemonicOpsEndInd) { … } // FIXME: This bit should probably be handled via an explicit match class // in the .td files that matches the suffix instead of having it be // a literal string token the way it is now. static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { … } static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID); // The GNU assembler has aliases of ldrd, strd, ldrexd, strexd, ldaexd, and // stlexd with the second register omitted. We don't have a way to do that in // tablegen, so fix it up here. // // We have to be careful to not emit an invalid Rt2 here, because the rest of // the assembly parser could then generate confusing diagnostics refering to // it. If we do find anything that prevents us from doing the transformation we // bail out, and let the assembly parser report an error on the instruction as // it is written. void ARMAsmParser::fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands, unsigned MnemonicOpsEndInd) { … } // Dual-register instruction have the following syntax: // <mnemonic> <predicate>? <coproc>, <Rdest>, <Rdest+1>, <Rsrc>, ..., #imm // This function tries to remove <Rdest+1> and replace <Rdest> with a pair // operand. If the conversion fails an error is diagnosed, and the function // returns true. bool ARMAsmParser::CDEConvertDualRegOperand(StringRef Mnemonic, OperandVector &Operands, unsigned MnemonicOpsEndInd) { … } void removeCondCode(OperandVector &Operands, unsigned &MnemonicOpsEndInd) { … } void removeCCOut(OperandVector &Operands, unsigned &MnemonicOpsEndInd) { … } void removeVPTCondCode(OperandVector &Operands, unsigned &MnemonicOpsEndInd) { … } /// Parse an arm instruction mnemonic followed by its operands. bool ARMAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) { … } // Validate context-sensitive operand constraints. // return 'true' if register list contains non-low GPR registers, // 'false' otherwise. If Reg is in the register list or is HiReg, set // 'containsReg' to true. static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo, MCRegister Reg, MCRegister HiReg, bool &containsReg) { … } // Check if the specified regisgter is in the register list of the inst, // starting at the indicated operand number. static bool listContainsReg(const MCInst &Inst, unsigned OpNo, MCRegister Reg) { … } // Return true if instruction has the interesting property of being // allowed in IT blocks, but not being predicable. static bool instIsBreakpoint(const MCInst &Inst) { … } unsigned getRegListInd(const OperandVector &Operands, unsigned MnemonicOpsEndInd) { … } bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands, unsigned MnemonicOpsEndInd, unsigned ListIndex, bool IsARPop) { … } bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands, unsigned MnemonicOpsEndInd, unsigned ListIndex) { … } bool ARMAsmParser::validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands, bool Load, bool ARMMode, bool Writeback, unsigned MnemonicOpsEndInd) { … } static int findFirstVectorPredOperandIdx(const MCInstrDesc &MCID) { … } static bool isVectorPredicable(const MCInstrDesc &MCID) { … } static bool isARMMCExpr(MCParsedAsmOperand &MCOp) { … } // FIXME: We would really like to be able to tablegen'erate this. bool ARMAsmParser::validateInstruction(MCInst &Inst, const OperandVector &Operands, unsigned MnemonicOpsEndInd) { … } static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) { … } static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) { … } bool ARMAsmParser::processInstruction(MCInst &Inst, const OperandVector &Operands, unsigned MnemonicOpsEndInd, MCStreamer &Out) { … } unsigned ARMAsmParser::checkEarlyTargetMatchPredicate(MCInst &Inst, const OperandVector &Operands) { … } unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { … } namespace llvm { template <> inline bool IsCPSRDead<MCInst>(const MCInst *Instr) { … } } // end namespace llvm // Returns true if Inst is unpredictable if it is in and IT block, but is not // the last instruction in the block. bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const { … } unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst, SmallVectorImpl<NearMissInfo> &NearMisses, bool MatchingInlineAsm, bool &EmitInITBlock, MCStreamer &Out) { … } static std::string ARMMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID = 0); static const char *getSubtargetFeatureName(uint64_t Val); bool ARMAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) { … } /// ParseDirective parses the arm specific directives bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { … } /// parseLiteralValues /// ::= .hword expression [, expression]* /// ::= .short expression [, expression]* /// ::= .word expression [, expression]* bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) { … } /// parseDirectiveThumb /// ::= .thumb bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { … } /// parseDirectiveARM /// ::= .arm bool ARMAsmParser::parseDirectiveARM(SMLoc L) { … } MCSymbolRefExpr::VariantKind ARMAsmParser::getVariantKindForName(StringRef Name) const { … } void ARMAsmParser::doBeforeLabelEmit(MCSymbol *Symbol, SMLoc IDLoc) { … } void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) { … } /// parseDirectiveThumbFunc /// ::= .thumbfunc symbol_name bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { … } /// parseDirectiveSyntax /// ::= .syntax unified | divided bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { … } /// parseDirectiveCode /// ::= .code 16 | 32 bool ARMAsmParser::parseDirectiveCode(SMLoc L) { … } /// parseDirectiveReq /// ::= name .req registername bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { … } /// parseDirectiveUneq /// ::= .unreq registername bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) { … } // After changing arch/CPU, try to put the ARM/Thumb mode back to what it was // before, if supported by the new target, or emit mapping symbols for the mode // switch. void ARMAsmParser::FixModeAfterArchChange(bool WasThumb, SMLoc Loc) { … } /// parseDirectiveArch /// ::= .arch token bool ARMAsmParser::parseDirectiveArch(SMLoc L) { … } /// parseDirectiveEabiAttr /// ::= .eabi_attribute int, int [, "str"] /// ::= .eabi_attribute Tag_name, int [, "str"] bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { … } /// parseDirectiveCPU /// ::= .cpu str bool ARMAsmParser::parseDirectiveCPU(SMLoc L) { … } /// parseDirectiveFPU /// ::= .fpu str bool ARMAsmParser::parseDirectiveFPU(SMLoc L) { … } /// parseDirectiveFnStart /// ::= .fnstart bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) { … } /// parseDirectiveFnEnd /// ::= .fnend bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) { … } /// parseDirectiveCantUnwind /// ::= .cantunwind bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) { … } /// parseDirectivePersonality /// ::= .personality name bool ARMAsmParser::parseDirectivePersonality(SMLoc L) { … } /// parseDirectiveHandlerData /// ::= .handlerdata bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) { … } /// parseDirectiveSetFP /// ::= .setfp fpreg, spreg [, offset] bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) { … } /// parseDirectivePad /// ::= .pad offset bool ARMAsmParser::parseDirectivePad(SMLoc L) { … } /// parseDirectiveRegSave /// ::= .save { registers } /// ::= .vsave { registers } bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) { … } /// parseDirectiveInst /// ::= .inst opcode [, ...] /// ::= .inst.n opcode [, ...] /// ::= .inst.w opcode [, ...] bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) { … } /// parseDirectiveLtorg /// ::= .ltorg | .pool bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) { … } bool ARMAsmParser::parseDirectiveEven(SMLoc L) { … } /// parseDirectivePersonalityIndex /// ::= .personalityindex index bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) { … } /// parseDirectiveUnwindRaw /// ::= .unwind_raw offset, opcode [, opcode...] bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) { … } /// parseDirectiveTLSDescSeq /// ::= .tlsdescseq tls-variable bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) { … } /// parseDirectiveMovSP /// ::= .movsp reg [, #offset] bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) { … } /// parseDirectiveObjectArch /// ::= .object_arch name bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) { … } /// parseDirectiveAlign /// ::= .align bool ARMAsmParser::parseDirectiveAlign(SMLoc L) { … } /// parseDirectiveThumbSet /// ::= .thumb_set name, value bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) { … } /// parseDirectiveSEHAllocStack /// ::= .seh_stackalloc /// ::= .seh_stackalloc_w bool ARMAsmParser::parseDirectiveSEHAllocStack(SMLoc L, bool Wide) { … } /// parseDirectiveSEHSaveRegs /// ::= .seh_save_regs /// ::= .seh_save_regs_w bool ARMAsmParser::parseDirectiveSEHSaveRegs(SMLoc L, bool Wide) { … } /// parseDirectiveSEHSaveSP /// ::= .seh_save_sp bool ARMAsmParser::parseDirectiveSEHSaveSP(SMLoc L) { … } /// parseDirectiveSEHSaveFRegs /// ::= .seh_save_fregs bool ARMAsmParser::parseDirectiveSEHSaveFRegs(SMLoc L) { … } /// parseDirectiveSEHSaveLR /// ::= .seh_save_lr bool ARMAsmParser::parseDirectiveSEHSaveLR(SMLoc L) { … } /// parseDirectiveSEHPrologEnd /// ::= .seh_endprologue /// ::= .seh_endprologue_fragment bool ARMAsmParser::parseDirectiveSEHPrologEnd(SMLoc L, bool Fragment) { … } /// parseDirectiveSEHNop /// ::= .seh_nop /// ::= .seh_nop_w bool ARMAsmParser::parseDirectiveSEHNop(SMLoc L, bool Wide) { … } /// parseDirectiveSEHEpilogStart /// ::= .seh_startepilogue /// ::= .seh_startepilogue_cond bool ARMAsmParser::parseDirectiveSEHEpilogStart(SMLoc L, bool Condition) { … } /// parseDirectiveSEHEpilogEnd /// ::= .seh_endepilogue bool ARMAsmParser::parseDirectiveSEHEpilogEnd(SMLoc L) { … } /// parseDirectiveSEHCustom /// ::= .seh_custom bool ARMAsmParser::parseDirectiveSEHCustom(SMLoc L) { … } /// Force static initialization. extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMAsmParser() { … } #define GET_REGISTER_MATCHER #define GET_SUBTARGET_FEATURE_NAME #define GET_MATCHER_IMPLEMENTATION #define GET_MNEMONIC_SPELL_CHECKER #include "ARMGenAsmMatcher.inc" // Some diagnostics need to vary with subtarget features, so they are handled // here. For example, the DPR class has either 16 or 32 registers, depending // on the FPU available. const char * ARMAsmParser::getCustomOperandDiag(ARMMatchResultTy MatchError) { … } // Process the list of near-misses, throwing away ones we don't want to report // to the user, and converting the rest to a source location and string that // should be reported. void ARMAsmParser::FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn, SmallVectorImpl<NearMissMessage> &NearMissesOut, SMLoc IDLoc, OperandVector &Operands) { … } void ARMAsmParser::ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses, SMLoc IDLoc, OperandVector &Operands) { … } bool ARMAsmParser::enableArchExtFeature(StringRef Name, SMLoc &ExtLoc) { … } /// parseDirectiveArchExtension /// ::= .arch_extension [no]feature bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) { … } // Define this matcher function after the auto-generated include so we // have the match class enum definitions. unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, unsigned Kind) { … } bool ARMAsmParser::isMnemonicVPTPredicable(StringRef Mnemonic, StringRef ExtraToken) { … } std::unique_ptr<ARMOperand> ARMAsmParser::defaultCondCodeOp() { … } std::unique_ptr<ARMOperand> ARMAsmParser::defaultCCOutOp() { … } std::unique_ptr<ARMOperand> ARMAsmParser::defaultVPTPredOp() { … }
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