llvm/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp

//===- HexagonGenPredicate.cpp --------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#include "HexagonInstrInfo.h"
#include "HexagonSubtarget.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/InitializePasses.h"
#include "llvm/Pass.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include <cassert>
#include <iterator>
#include <map>
#include <queue>
#include <set>
#include <utility>

#define DEBUG_TYPE …

usingnamespacellvm;

namespace llvm {

  void initializeHexagonGenPredicatePass(PassRegistry& Registry);
  FunctionPass *createHexagonGenPredicate();

} // end namespace llvm

namespace {

  // FIXME: Use TargetInstrInfo::RegSubRegPair
  struct RegisterSubReg { … };

  struct PrintRegister { … };

  raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR)
    LLVM_ATTRIBUTE_UNUSED;
  raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) { … }

  class HexagonGenPredicate : public MachineFunctionPass { … };

} // end anonymous namespace

char HexagonGenPredicate::ID = …;

INITIALIZE_PASS_BEGIN(HexagonGenPredicate, "hexagon-gen-pred",
  "Hexagon generate predicate operations", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_END(HexagonGenPredicate, "hexagon-gen-pred",
  "Hexagon generate predicate operations", false, false)

bool HexagonGenPredicate::isPredReg(Register R) { … }

unsigned HexagonGenPredicate::getPredForm(unsigned Opc) { … }

bool HexagonGenPredicate::isConvertibleToPredForm(const MachineInstr *MI) { … }

void HexagonGenPredicate::collectPredicateGPR(MachineFunction &MF) { … }

void HexagonGenPredicate::processPredicateGPR(const RegisterSubReg &Reg) { … }

RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) { … }

bool HexagonGenPredicate::isScalarCmp(unsigned Opc) { … }

bool HexagonGenPredicate::isScalarPred(RegisterSubReg PredReg) { … }

bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) { … }

bool HexagonGenPredicate::eliminatePredCopies(MachineFunction &MF) { … }

bool HexagonGenPredicate::runOnMachineFunction(MachineFunction &MF) { … }

FunctionPass *llvm::createHexagonGenPredicate() { … }