llvm/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp

//===- HexagonShuffler.cpp - Instruction bundle shuffling -----------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This implements the shuffling of insns inside a bundle according to the
// packet formation rules of the Hexagon ISA.
//
//===----------------------------------------------------------------------===//

#include "MCTargetDesc/HexagonShuffler.h"
#include "MCTargetDesc/HexagonBaseInfo.h"
#include "MCTargetDesc/HexagonMCInstrInfo.h"
#include "MCTargetDesc/HexagonMCTargetDesc.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/Twine.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/SourceMgr.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <optional>
#include <utility>

#define DEBUG_TYPE

usingnamespacellvm;

namespace {

// Insn shuffling priority.
class HexagonBid {};

// Slot shuffling allocation.
class HexagonUnitAuction {};

} // end anonymous namespace

unsigned HexagonResource::setWeight(unsigned s) {}

HexagonCVIResource::HexagonCVIResource(MCInstrInfo const &MCII,
                                       MCSubtargetInfo const &STI,
                                       unsigned s,
                                       MCInst const *id)
    :{}

struct CVIUnits {};
HVXInstsT;

static unsigned makeAllBits(unsigned startBit, unsigned Lanes)
{}

static bool checkHVXPipes(const HVXInstsT &hvxInsts, unsigned startIdx,
                          unsigned usedUnits) {}

HexagonShuffler::HexagonShuffler(MCContext &Context, bool ReportErrors,
                                 MCInstrInfo const &MCII,
                                 MCSubtargetInfo const &STI)
    :{}

void HexagonShuffler::reset() {}

void HexagonShuffler::append(MCInst const &ID, MCInst const *Extender,
                             unsigned S) {}


static const unsigned Slot0Mask =;
static const unsigned Slot1Mask =;
static const unsigned Slot3Mask =;
static const unsigned slotSingleLoad =;
static const unsigned slotSingleStore =;

void HexagonShuffler::restrictSlot1AOK(HexagonPacketSummary const &Summary) {}

void HexagonShuffler::restrictNoSlot1Store(
    HexagonPacketSummary const &Summary) {}

bool HexagonShuffler::applySlotRestrictions(HexagonPacketSummary const &Summary,
                                            const bool DoShuffle) {}

void HexagonShuffler::restrictBranchOrder(HexagonPacketSummary const &Summary) {}

void HexagonShuffler::permitNonSlot() {}

bool HexagonShuffler::ValidResourceUsage(HexagonPacketSummary const &Summary) {}

bool HexagonShuffler::restrictStoreLoadOrder(
    HexagonPacketSummary const &Summary) {}

static std::string SlotMaskToText(unsigned SlotMask) {}

HexagonShuffler::HexagonPacketSummary HexagonShuffler::GetPacketSummary() {}

bool HexagonShuffler::ValidPacketMemoryOps(
    HexagonPacketSummary const &Summary) const {}

void HexagonShuffler::restrictPreferSlot3(HexagonPacketSummary const &Summary,
                                          const bool DoShuffle) {}

/// Check that the packet is legal and enforce relative insn order.
bool HexagonShuffler::check(const bool RequireShuffle) {}

std::optional<HexagonShuffler::HexagonPacket>
HexagonShuffler::tryAuction(HexagonPacketSummary const &Summary) {}

bool HexagonShuffler::shuffle() {}

void HexagonShuffler::reportResourceError(HexagonPacketSummary const &Summary, StringRef Err) {}


void HexagonShuffler::reportResourceUsage(HexagonPacketSummary const &Summary) {}

void HexagonShuffler::reportError(Twine const &Msg) {}