#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM
namespace llvm {
}
#endif
#ifdef GET_SUBTARGETINFO_MACRO
#undef GET_SUBTARGETINFO_MACRO
#endif
#ifdef GET_SUBTARGETINFO_MC_DESC
#undef GET_SUBTARGETINFO_MC_DESC
namespace llvm {
#ifdef DBGFIELD
#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
#endif
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
#define DBGFIELD …
#else
#define DBGFIELD …
#endif
namespace LanaiItineraryFU {
const InstrStage::FuncUnits ALU_FU = 1ULL << 0;
const InstrStage::FuncUnits LDST_FU = 1ULL << 1;
}
extern const llvm::InstrStage LanaiStages[] = {
{ 0, 0, 0, llvm::InstrStage::Required },
{ 1, LanaiItineraryFU::ALU_FU, -1, (llvm::InstrStage::ReservationKinds)0 },
{ 1, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 },
{ 2, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 },
{ 0, 0, 0, llvm::InstrStage::Required }
};
extern const unsigned LanaiOperandCycles[] = {
0,
0
};
extern const unsigned LanaiForwardingPaths[] = {
0,
0
};
static const llvm::InstrItinerary LanaiItinerary[] = {
{ 0, 0, 0, 0, 0 },
{ 1, 1, 2, 0, 0 },
{ 1, 1, 2, 0, 0 },
{ 1, 2, 3, 0, 0 },
{ 1, 3, 4, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 1, 2, 3, 0, 0 },
{ 1, 3, 4, 0, 0 },
{ 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }
};
extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[] = {
{ 0, 0, 0 },
{ 1, 1, 0},
{ 2, 1, 0}
};
extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[] = {
{ 0, 0},
{ 1, 0},
{ 2, 0},
{ 4, 0}
};
extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[] = {
{0, 0, 0},
};
static const llvm::MCSchedClassDesc LanaiSchedModelSchedClasses[] = {
{DBGFIELD("InvalidSchedClass") 8191, false, false, false, 0, 0, 0, 0, 0, 0},
{DBGFIELD("IIC_ALU_WriteALU") 1, false, false, false, 1, 1, 1, 1, 0, 0},
{DBGFIELD("IIC_ALU") 8191, false, false, false, 0, 0, 0, 0, 0, 0},
{DBGFIELD("IIC_LD_WriteLD") 1, false, false, false, 2, 1, 2, 1, 0, 0},
{DBGFIELD("IIC_LDSW_WriteLDSW") 1, false, false, false, 2, 1, 2, 1, 0, 0},
{DBGFIELD("WriteLD") 1, false, false, false, 2, 1, 2, 1, 0, 0},
{DBGFIELD("IIC_ST_WriteST") 1, false, false, false, 2, 1, 2, 1, 0, 0},
{DBGFIELD("IIC_STSW_WriteSTSW") 1, false, false, false, 2, 1, 3, 1, 0, 0},
};
#undef DBGFIELD
static const llvm::MCSchedModel NoSchedModel = {
MCSchedModel::DefaultIssueWidth,
MCSchedModel::DefaultMicroOpBufferSize,
MCSchedModel::DefaultLoopMicroOpBufferSize,
MCSchedModel::DefaultLoadLatency,
MCSchedModel::DefaultHighLatency,
MCSchedModel::DefaultMispredictPenalty,
false,
false,
false,
0,
nullptr, nullptr, 0, 0,
nullptr,
nullptr
};
static const unsigned LanaiSchedModelProcResourceSubUnits[] = {
0,
};
static const llvm::MCProcResourceDesc LanaiSchedModelProcResources[] = {
{"InvalidUnit", 0, 0, 0, 0},
{"ALU", 1, 0, 0, nullptr},
{"LdSt", 1, 0, 0, nullptr},
};
static const llvm::MCSchedModel LanaiSchedModel = {
1,
0,
0,
2,
MCSchedModel::DefaultHighLatency,
10,
false,
false,
false,
1,
LanaiSchedModelProcResources,
LanaiSchedModelSchedClasses,
3,
8,
LanaiItinerary,
nullptr
};
extern const llvm::SubtargetSubTypeKV LanaiSubTypeKV[] = {
{ "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LanaiSchedModel },
{ "v11", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LanaiSchedModel },
};
namespace Lanai_MC {
unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
return 0;
}
}
struct LanaiGenMCSubtargetInfo : public MCSubtargetInfo {
LanaiGenMCSubtargetInfo(const Triple &TT,
StringRef CPU, StringRef TuneCPU, StringRef FS,
ArrayRef<SubtargetFeatureKV> PF,
ArrayRef<SubtargetSubTypeKV> PD,
const MCWriteProcResEntry *WPR,
const MCWriteLatencyEntry *WL,
const MCReadAdvanceEntry *RA, const InstrStage *IS,
const unsigned *OC, const unsigned *FP) :
MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD,
WPR, WL, RA, IS, OC, FP) { }
unsigned resolveVariantSchedClass(unsigned SchedClass,
const MCInst *MI, const MCInstrInfo *MCII,
unsigned CPUID) const override {
return Lanai_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
}
};
static inline MCSubtargetInfo *createLanaiMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
return new LanaiGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, {}, LanaiSubTypeKV,
LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable,
LanaiStages, LanaiOperandCycles, LanaiForwardingPaths);
}
}
#endif
#ifdef GET_SUBTARGETINFO_TARGET_DESC
#undef GET_SUBTARGETINFO_TARGET_DESC
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
void llvm::LanaiSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
}
#endif
#ifdef GET_SUBTARGETINFO_HEADER
#undef GET_SUBTARGETINFO_HEADER
namespace llvm {
class DFAPacketizer;
namespace Lanai_MC {
unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
}
struct LanaiGenSubtargetInfo : public TargetSubtargetInfo {
explicit LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
public:
unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
};
}
#endif
#ifdef GET_SUBTARGETINFO_CTOR
#undef GET_SUBTARGETINFO_CTOR
#include "llvm/CodeGen/TargetSchedule.h"
namespace llvm {
extern const llvm::SubtargetFeatureKV LanaiFeatureKV[];
extern const llvm::SubtargetSubTypeKV LanaiSubTypeKV[];
extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[];
extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[];
extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[];
extern const llvm::InstrStage LanaiStages[];
extern const unsigned LanaiOperandCycles[];
extern const unsigned LanaiForwardingPaths[];
LanaiGenSubtargetInfo::LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
: TargetSubtargetInfo(TT, CPU, TuneCPU, FS, {}, ArrayRef(LanaiSubTypeKV, 2),
LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable,
LanaiStages, LanaiOperandCycles, LanaiForwardingPaths) {}
unsigned LanaiGenSubtargetInfo
::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
report_fatal_error("Expected a variant SchedClass");
}
unsigned LanaiGenSubtargetInfo
::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
return Lanai_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
}
}
#endif
#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
#endif
#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
#endif