/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM namespace llvm { namespace Mips { enum { … }; } // end namespace Mips } // end namespace llvm #endif // GET_INSTRINFO_ENUM #ifdef GET_INSTRINFO_SCHED_ENUM #undef GET_INSTRINFO_SCHED_ENUM namespace llvm { namespace Mips { namespace Sched { enum { NoInstrModel = 0, IIPseudo = 1, II_B = 2, II_BCCZAL = 3, II_MTC1 = 4, II_MFC1 = 5, II_JALR = 6, II_JAL = 7, II_CVT = 8, II_DMULT = 9, II_DMULTU = 10, II_DDIV = 11, II_DDIVU = 12, II_IndirectBranchPseudo = 13, II_MADD = 14, II_MADDU = 15, II_MFHI_MFLO = 16, II_MSUB = 17, II_MSUBU = 18, II_MTHI_MTLO = 19, II_MULT = 20, II_MULTU = 21, II_ReturnPseudo = 22, II_DIV = 23, II_DIVU = 24, II_J = 25, II_JR = 26, II_TRAP = 27, II_ADD = 28, II_ADDIUPC = 29, II_ADDIU = 30, II_ADDR_PS = 31, II_ADDU = 32, II_ADDI = 33, II_ALIGN = 34, II_ALUIPC = 35, II_AND = 36, II_ANDI = 37, II_AUI = 38, II_AUIPC = 39, IIM16Alu = 40, II_BADDU = 41, II_BC = 42, II_BALC = 43, II_BBIT = 44, II_BC1CCZ = 45, II_BC1F = 46, II_BC1FL = 47, II_BC1T = 48, II_BC1TL = 49, II_BC2CCZ = 50, II_BCC = 51, II_BCCC = 52, II_BCCZ = 53, II_BCCZC = 54, II_BCCZALS = 55, II_BITSWAP = 56, II_BREAK = 57, II_CACHE = 58, II_CACHEE = 59, II_CEIL = 60, II_CFC1 = 61, II_CFC2 = 62, II_INS = 63, II_CLASS_D = 64, II_CLASS_S = 65, II_CLO = 66, II_CLZ = 67, II_CMP_CC_D = 68, II_CMP_CC_S = 69, II_CRC32B = 70, II_CRC32CB = 71, II_CRC32CD = 72, II_CRC32CH = 73, II_CRC32CW = 74, II_CRC32D = 75, II_CRC32H = 76, II_CRC32W = 77, II_CTC1 = 78, II_CTC2 = 79, II_C_CC_D = 80, II_C_CC_S = 81, II_DADD = 82, II_DADDI = 83, II_DADDIU = 84, II_DADDU = 85, II_DAHI = 86, II_DALIGN = 87, II_DATI = 88, II_DAUI = 89, II_DBITSWAP = 90, II_DCLO = 91, II_DCLZ = 92, II_DERET = 93, II_EXT = 94, II_DI = 95, II_DLSA = 96, II_DMFC0 = 97, II_DMFC1 = 98, II_DMFC2 = 99, II_DMFGC0 = 100, II_DMOD = 101, II_DMODU = 102, II_DMT = 103, II_DMTC0 = 104, II_DMTC1 = 105, II_DMTC2 = 106, II_DMTGC0 = 107, II_DMUH = 108, II_DMUHU = 109, II_DMUL = 110, II_POP = 111, II_DROTR = 112, II_DROTR32 = 113, II_DROTRV = 114, II_DSBH = 115, II_DSHD = 116, II_DSLL = 117, II_DSLL32 = 118, II_DSLLV = 119, II_DSRA = 120, II_DSRA32 = 121, II_DSRAV = 122, II_DSRL = 123, II_DSRL32 = 124, II_DSRLV = 125, II_DSUB = 126, II_DSUBU = 127, II_DVP = 128, II_DVPE = 129, II_EHB = 130, II_EI = 131, II_EMT = 132, II_ERET = 133, II_ERETNC = 134, II_EVP = 135, II_EVPE = 136, II_ABS = 137, II_SQRT_D = 138, II_ADD_D = 139, II_ADD_PS = 140, II_ADD_S = 141, II_DIV_D = 142, II_DIV_S = 143, II_FLOOR = 144, II_MOV_D = 145, II_MOV_S = 146, II_MUL_D = 147, II_MUL_PS = 148, II_MUL_S = 149, II_NEG = 150, II_FORK = 151, II_SQRT_S = 152, II_SUB_D = 153, II_SUB_PS = 154, II_SUB_S = 155, II_GINVI = 156, II_GINVT = 157, II_HYPCALL = 158, II_JALR_HB = 159, II_JALRC = 160, II_JALRS = 161, II_JALS = 162, II_JIALC = 163, II_JIC = 164, II_JRADDIUSP = 165, II_JRC = 166, II_JR_HB = 167, II_LB = 168, II_LBE = 169, II_LBU = 170, II_LBUE = 171, II_LD = 172, II_LDC1 = 173, II_LDC2 = 174, II_LDC3 = 175, II_LDL = 176, II_LDPC = 177, II_LDR = 178, II_LDXC1 = 179, II_LH = 180, II_LHE = 181, II_LHU = 182, II_LHUE = 183, II_LI = 184, II_LL = 185, II_LLD = 186, II_LLE = 187, II_LSA = 188, II_LUI = 189, II_LUXC1 = 190, II_LW = 191, II_LWC1 = 192, II_LWC2 = 193, II_LWC3 = 194, II_LWE = 195, II_LWL = 196, II_LWLE = 197, II_LWM = 198, II_LWPC = 199, II_LWP = 200, II_LWR = 201, II_LWRE = 202, II_LWUPC = 203, II_LWU = 204, II_LWXC1 = 205, II_LWXS = 206, II_MADDF_D = 207, II_MADDF_S = 208, II_MADD_D = 209, II_MADD_S = 210, II_MAX_D = 211, II_MAXA_D = 212, II_MAX_S = 213, II_MAXA_S = 214, II_MFC0 = 215, II_MFC2 = 216, II_MFGC0 = 217, II_MFHC0 = 218, II_MFHC1 = 219, II_MFHGC0 = 220, II_MFTR = 221, II_MIN_S = 222, II_MINA_D = 223, II_MIN_D = 224, II_MINA_S = 225, II_MOD = 226, II_MODU = 227, II_MOVE = 228, II_MOVF_D = 229, II_MOVF = 230, II_MOVF_S = 231, II_MOVN_D = 232, II_MOVN = 233, II_MOVN_S = 234, II_MOVT_D = 235, II_MOVT = 236, II_MOVT_S = 237, II_MOVZ_D = 238, II_MOVZ = 239, II_MOVZ_S = 240, II_MSUBF_D = 241, II_MSUBF_S = 242, II_MSUB_D = 243, II_MSUB_S = 244, II_MTC0 = 245, II_MTC2 = 246, II_MTGC0 = 247, II_MTHC0 = 248, II_MTHC1 = 249, II_MTHGC0 = 250, II_MTTR = 251, II_MUH = 252, II_MUHU = 253, II_MUL = 254, II_MULR_PS = 255, II_MULU = 256, II_NMADD_D = 257, II_NMADD_S = 258, II_NMSUB_D = 259, II_NMSUB_S = 260, II_NOR = 261, II_NOT = 262, II_OR = 263, II_ORI = 264, II_PAUSE = 265, II_PREF = 266, II_PREFE = 267, II_RDHWR = 268, II_RDPGPR = 269, II_RECIP_D = 270, II_RECIP_S = 271, II_RINT_D = 272, II_RINT_S = 273, II_ROTR = 274, II_ROTRV = 275, II_ROUND = 276, II_RSQRT_D = 277, II_RSQRT_S = 278, II_RESTORE = 279, II_SB = 280, II_SBE = 281, II_SC = 282, II_SCD = 283, II_SCE = 284, II_SD = 285, II_SDBBP = 286, II_SDC1 = 287, II_SDC2 = 288, II_SDC3 = 289, II_SDL = 290, II_SDR = 291, II_SDXC1 = 292, II_SEB = 293, II_SEH = 294, II_SELCCZ = 295, II_SELCCZ_D = 296, II_SELCCZ_S = 297, II_SEL_D = 298, II_SEL_S = 299, II_SEQ_SNE = 300, II_SEQI_SNEI = 301, II_SH = 302, II_SHE = 303, II_SIGRIE = 304, II_SLL = 305, II_SLLV = 306, II_SLT_SLTU = 307, II_SLTI_SLTIU = 308, II_SRA = 309, II_SRAV = 310, II_SRL = 311, II_SRLV = 312, II_SSNOP = 313, II_SUB = 314, II_SUBU = 315, II_SUXC1 = 316, II_SW = 317, II_SWC1 = 318, II_SWC2 = 319, II_SWC3 = 320, II_SWE = 321, II_SWL = 322, II_SWLE = 323, II_SWM = 324, II_SWP = 325, II_SWR = 326, II_SWRE = 327, II_SWXC1 = 328, II_SYNC = 329, II_SYNCI = 330, II_SYSCALL = 331, II_SAVE = 332, II_TEQ = 333, II_TEQI = 334, II_TGE = 335, II_TGEI = 336, II_TGEIU = 337, II_TGEU = 338, II_TLBGINV = 339, II_TLBGINVF = 340, II_TLBGP = 341, II_TLBGR = 342, II_TLBGWI = 343, II_TLBGWR = 344, II_TLBINV = 345, II_TLBINVF = 346, II_TLBP = 347, II_TLBR = 348, II_TLBWI = 349, II_TLBWR = 350, II_TLT = 351, II_TLTI = 352, II_TTLTIU = 353, II_TLTU = 354, II_TNE = 355, II_TNEI = 356, II_TRUNC = 357, II_WAIT = 358, II_WRPGPR = 359, II_WSBH = 360, II_XOR = 361, II_XORI = 362, II_YIELD = 363, AND = 364, LUi = 365, NOR = 366, OR = 367, SLTi_SLTiu = 368, SUB = 369, SUBu = 370, XOR = 371, SSNOP = 372, NOP = 373, B = 374, BAL = 375, BAL_BR_BGEZAL_BGEZALL_BLTZAL_BLTZALL = 376, BEQ_BEQL_BNE_BNEL = 377, BGEZ_BGEZL_BGTZ_BGTZL_BLEZ_BLEZL_BLTZ_BLTZL = 378, BREAK = 379, DERET = 380, ERET = 381, ERet_RetRA = 382, ERETNC = 383, J_TAILCALL = 384, JR_TAILCALLREG_TAILCALLREGHB = 385, JR_HB = 386, PseudoIndirectBranch_PseudoIndirectHazardBranch = 387, PseudoReturn = 388, SDBBP = 389, SYSCALL = 390, TEQ = 391, TEQI = 392, TGE = 393, TGEI = 394, TGEIU = 395, TGEU = 396, TLT = 397, TLTI = 398, TLTU = 399, TNE = 400, TNEI = 401, TRAP = 402, TTLTIU = 403, WAIT = 404, PAUSE = 405, JAL = 406, JALR_JALRHBPseudo_JALRPseudo = 407, JALR_HB = 408, JALX = 409, TLBINV = 410, TLBINVF = 411, TLBP = 412, TLBR = 413, TLBWI = 414, TLBWR = 415, MFC0 = 416, MTC0 = 417, MFC2 = 418, MTC2 = 419, HYPCALL = 420, MFGC0 = 421, MFHGC0 = 422, MTGC0 = 423, MTHGC0 = 424, TLBGINV = 425, TLBGINVF = 426, TLBGP = 427, TLBGR = 428, TLBGWI = 429, TLBGWR = 430, LB = 431, LBu = 432, LH = 433, LHu = 434, LW = 435, LL = 436, LWC2 = 437, LWC3 = 438, LDC2 = 439, LDC3 = 440, LBE = 441, LBuE = 442, LHE = 443, LHuE = 444, LWE = 445, LLE = 446, LWPC = 447, LWL = 448, LWR = 449, LWLE = 450, LWRE = 451, SB = 452, SH = 453, SW = 454, SWC2 = 455, SWC3 = 456, SDC2 = 457, SDC3 = 458, SC = 459, SBE = 460, SHE = 461, SWE = 462, SCE = 463, SWL = 464, SWR = 465, SWLE = 466, SWRE = 467, PREF = 468, PREFE = 469, CACHE = 470, CACHEE = 471, SYNC = 472, SYNCI = 473, CLO = 474, CLZ = 475, DI = 476, EI = 477, MFHI_MFLO_PseudoMFHI_PseudoMFLO = 478, EHB = 479, RDHWR = 480, WSBH = 481, MOVN_I_I = 482, MOVZ_I_I = 483, DIV_PseudoSDIV_SDIV = 484, DIVU_PseudoUDIV_UDIV = 485, MUL = 486, MULT_PseudoMULT = 487, MULTu_PseudoMULTu = 488, MADD_PseudoMADD = 489, MADDU_PseudoMADDU = 490, MSUB_PseudoMSUB = 491, MSUBU_PseudoMSUBU = 492, MTHI_MTLO_PseudoMTLOHI = 493, EXT = 494, INS = 495, ADD = 496, ADDi = 497, ADDiu = 498, ANDi = 499, ORi = 500, ROTR = 501, SEB = 502, SEH = 503, SLT_SLTu = 504, SLL = 505, SRA = 506, SRL = 507, XORi = 508, ADDu = 509, SLLV = 510, SRAV = 511, SRLV = 512, LSA = 513, COPY = 514, VSHF_B_VSHF_D_VSHF_H_VSHF_W = 515, BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 516, BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 517, INSERT_B_INSERT_D_INSERT_H_INSERT_W = 518, SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 519, BSETI_B_BSETI_D_BSETI_H_BSETI_W_BSET_B_BSET_D_BSET_H_BSET_W = 520, BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 521, BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 522, BSELI_B_BSEL_V = 523, BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 524, BSEL_D_PSEUDO_BSEL_FD_PSEUDO_BSEL_FW_PSEUDO_BSEL_H_PSEUDO_BSEL_W_PSEUDO = 525, PCNT_B_PCNT_D_PCNT_H_PCNT_W = 526, SAT_S_B_SAT_S_D_SAT_S_H_SAT_S_W_SAT_U_B_SAT_U_D_SAT_U_H_SAT_U_W = 527, BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W = 528, CFCMSA_CTCMSA = 529, FABS_S_FABS_D32_FABS_D64 = 530, MOVF_D32_MOVF_D64 = 531, MOVF_S = 532, MOVT_D32_MOVT_D64 = 533, MOVT_S = 534, FMOV_D32_FMOV_D64 = 535, FMOV_S = 536, FNEG_S_FNEG_D32_FNEG_D64 = 537, ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W = 538, ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 539, ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 540, ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W_ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W = 541, AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W = 542, SHF_B_SHF_H_SHF_W = 543, FILL_B_FILL_D_FILL_H_FILL_W = 544, SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W_SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 545, MOVE_V = 546, LDI_B_LDI_D_LDI_H_LDI_W = 547, AND_V_NOR_V_OR_V_XOR_V = 548, ANDI_B_NORI_B_ORI_B_XORI_B = 549, AND_V_D_PSEUDO_AND_V_H_PSEUDO_AND_V_W_PSEUDO_NOR_V_D_PSEUDO_NOR_V_H_PSEUDO_NOR_V_W_PSEUDO_OR_V_D_PSEUDO_OR_V_H_PSEUDO_OR_V_W_PSEUDO_XOR_V_D_PSEUDO_XOR_V_H_PSEUDO_XOR_V_W_PSEUDO = 550, FILL_FD_PSEUDO_FILL_FW_PSEUDO = 551, INSERT_FD_PSEUDO_INSERT_FW_PSEUDO = 552, FEXP2_D_FEXP2_W = 553, CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W = 554, CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W = 555, CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 556, CMP_UN_D = 557, CMP_UN_S = 558, CMP_UEQ_D = 559, CMP_UEQ_S = 560, CMP_EQ_D = 561, CMP_EQ_S = 562, CMP_LT_D = 563, CMP_LT_S = 564, CMP_ULT_D = 565, CMP_ULT_S = 566, CMP_LE_D = 567, CMP_LE_S = 568, CMP_ULE_D = 569, CMP_ULE_S = 570, FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 571, FSUEQ_D_FSUEQ_W = 572, FSULE_D_FSULE_W = 573, FSULT_D_FSULT_W = 574, FSUNE_D_FSUNE_W = 575, FSUN_D_FSUN_W = 576, FCAF_D_FCAF_W = 577, FCEQ_D_FCEQ_W = 578, FCLE_D_FCLE_W = 579, FCLT_D_FCLT_W = 580, FCNE_D_FCNE_W = 581, FCOR_D_FCOR_W = 582, FCUEQ_D_FCUEQ_W = 583, FCULE_D_FCULE_W = 584, FCULT_D_FCULT_W = 585, FCUNE_D_FCUNE_W = 586, FCUN_D_FCUN_W = 587, FABS_D_FABS_W = 588, FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W = 589, FFQL_D_FFQL_W = 590, FFQR_D_FFQR_W = 591, FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W = 592, FRINT_D_FRINT_W = 593, FTQ_H_FTQ_W = 594, FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 595, FEXDO_H_FEXDO_W = 596, FEXUPL_D_FEXUPL_W = 597, FEXUPR_D_FEXUPR_W = 598, FCLASS_D_FCLASS_W = 599, FMAX_A_D_FMAX_A_W = 600, FMAX_D_FMAX_W = 601, FMIN_A_D_FMIN_A_W = 602, FMIN_D_FMIN_W = 603, FLOG2_D_FLOG2_W = 604, ILVL_B_ILVL_D_ILVL_H_ILVL_W_ILVR_B_ILVR_D_ILVR_H_ILVR_W = 605, ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W_ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W = 606, INSVE_B_INSVE_D_INSVE_H_INSVE_W = 607, SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W = 608, SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 609, SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 610, SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W = 611, SUBV_B_SUBV_D_SUBV_H_SUBV_W = 612, MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W = 613, DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W_DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W = 614, HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W = 615, HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W = 616, MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W = 617, MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W = 618, MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W = 619, MAXI_S_B_MAXI_S_D_MAXI_S_H_MAXI_S_W_MAXI_U_B_MAXI_U_D_MAXI_U_H_MAXI_U_W_MINI_S_B_MINI_S_D_MINI_S_H_MINI_S_W_MINI_U_B_MINI_U_D_MINI_U_H_MINI_U_W = 620, SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 621, SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 622, SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 623, SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 624, SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 625, PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W_PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W = 626, NLOC_B_NLOC_D_NLOC_H_NLOC_W_NLZC_B_NLZC_D_NLZC_H_NLZC_W = 627, FADD_D32_FADD_D64 = 628, FADD_PS64 = 629, FADD_S = 630, FMUL_D32_FMUL_D64 = 631, FMUL_PS64 = 632, FMUL_S = 633, FSUB_D32_FSUB_D64 = 634, FSUB_PS64 = 635, FSUB_S = 636, TRUNC_L_D64_TRUNC_L_S_TRUNC_W_D32_TRUNC_W_D64_TRUNC_W_S = 637, CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S = 638, CVT_PS_S64_CVT_S_PL64_CVT_S_PU64 = 639, C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64 = 640, C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S = 641, FCMP_D32_FCMP_D64 = 642, FCMP_S32 = 643, PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W = 644, PLL_PS64_PLU_PS64_PUL_PS64_PUU_PS64 = 645, FDIV_S = 646, FDIV_D32_FDIV_D64 = 647, FSQRT_S = 648, FSQRT_D32_FSQRT_D64 = 649, FRCP_D_FRCP_W = 650, FRSQRT_D_FRSQRT_W = 651, RECIP_D32_RECIP_D64 = 652, RSQRT_D32_RSQRT_D64 = 653, RECIP_S = 654, RSQRT_S = 655, FMADD_D_FMADD_W = 656, FMSUB_D_FMSUB_W = 657, FDIV_W = 658, FDIV_D = 659, FSQRT_W = 660, FSQRT_D = 661, FMUL_D_FMUL_W = 662, FADD_D_FADD_W = 663, FSUB_D_FSUB_W = 664, DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 665, DPSUB_S_D_DPSUB_S_H_DPSUB_S_W_DPSUB_U_D_DPSUB_U_H_DPSUB_U_W = 666, DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W = 667, MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W = 668, MADDV_B_MADDV_D_MADDV_H_MADDV_W = 669, MULV_B_MULV_D_MULV_H_MULV_W = 670, MADDR_Q_H_MADDR_Q_W = 671, MADD_Q_H_MADD_Q_W = 672, MSUBR_Q_H_MSUBR_Q_W = 673, MSUB_Q_H_MSUB_Q_W = 674, MULR_Q_H_MULR_Q_W = 675, MUL_Q_H_MUL_Q_W = 676, MADD_D32_MADD_D64 = 677, MADD_S = 678, MSUB_D32_MSUB_D64 = 679, MSUB_S = 680, NMADD_D32_NMADD_D64 = 681, NMADD_S = 682, NMSUB_D32_NMSUB_D64 = 683, NMSUB_S = 684, CTC1 = 685, MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64 = 686, MTHC1_D32_MTHC1_D64 = 687, COPY_U_B_COPY_U_H_COPY_U_W = 688, COPY_S_B_COPY_S_D_COPY_S_H_COPY_S_W = 689, BC1F = 690, BC1FL = 691, BC1T = 692, BC1TL = 693, CFC1 = 694, MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64 = 695, MFHC1_D32_MFHC1_D64 = 696, MOVF_I = 697, MOVT_I = 698, SDC1_SDC164 = 699, SDXC1_SDXC164 = 700, SWC1 = 701, SWXC1 = 702, SUXC1_SUXC164 = 703, ST_B_ST_D_ST_H_ST_W = 704, ST_F16 = 705, MOVN_I_D32_MOVN_I_D64 = 706, MOVN_I_S = 707, MOVZ_I_D32_MOVZ_I_D64 = 708, MOVZ_I_S = 709, LDC1_LDC164 = 710, LDXC1_LDXC164 = 711, LWC1 = 712, LWXC1 = 713, LUXC1_LUXC164 = 714, LD_B_LD_D_LD_H_LD_W = 715, LD_F16 = 716, CEIL_L_D64_CEIL_L_S_CEIL_W_D32_CEIL_W_D64_CEIL_W_S = 717, FLOOR_L_D64_FLOOR_L_S_FLOOR_W_D32_FLOOR_W_D64_FLOOR_W_S = 718, ROUND_L_D64_ROUND_L_S_ROUND_W_D32_ROUND_W_D64_ROUND_W_S = 719, ROTRV = 720, ATOMIC_SWAP_I16_POSTRA_ATOMIC_SWAP_I32_POSTRA_ATOMIC_SWAP_I64_POSTRA_ATOMIC_SWAP_I8_POSTRA = 721, ATOMIC_CMP_SWAP_I16_POSTRA_ATOMIC_CMP_SWAP_I32_POSTRA_ATOMIC_CMP_SWAP_I64_POSTRA_ATOMIC_CMP_SWAP_I8_POSTRA = 722, ATOMIC_LOAD_ADD_I16_POSTRA_ATOMIC_LOAD_ADD_I32_POSTRA_ATOMIC_LOAD_ADD_I64_POSTRA_ATOMIC_LOAD_ADD_I8_POSTRA_ATOMIC_LOAD_AND_I16_POSTRA_ATOMIC_LOAD_AND_I32_POSTRA_ATOMIC_LOAD_AND_I64_POSTRA_ATOMIC_LOAD_AND_I8_POSTRA_ATOMIC_LOAD_MAX_I16_POSTRA_ATOMIC_LOAD_MAX_I32_POSTRA_ATOMIC_LOAD_MAX_I64_POSTRA_ATOMIC_LOAD_MAX_I8_POSTRA_ATOMIC_LOAD_MIN_I16_POSTRA_ATOMIC_LOAD_MIN_I32_POSTRA_ATOMIC_LOAD_MIN_I64_POSTRA_ATOMIC_LOAD_MIN_I8_POSTRA_ATOMIC_LOAD_NAND_I16_POSTRA_ATOMIC_LOAD_NAND_I32_POSTRA_ATOMIC_LOAD_NAND_I64_POSTRA_ATOMIC_LOAD_NAND_I8_POSTRA_ATOMIC_LOAD_OR_I16_POSTRA_ATOMIC_LOAD_OR_I32_POSTRA_ATOMIC_LOAD_OR_I64_POSTRA_ATOMIC_LOAD_OR_I8_POSTRA_ATOMIC_LOAD_SUB_I16_POSTRA_ATOMIC_LOAD_SUB_I32_POSTRA_ATOMIC_LOAD_SUB_I64_POSTRA_ATOMIC_LOAD_SUB_I8_POSTRA_ATOMIC_LOAD_UMAX_I16_POSTRA_ATOMIC_LOAD_UMAX_I32_POSTRA_ATOMIC_LOAD_UMAX_I64_POSTRA_ATOMIC_LOAD_UMAX_I8_POSTRA_ATOMIC_LOAD_UMIN_I16_POSTRA_ATOMIC_LOAD_UMIN_I32_POSTRA_ATOMIC_LOAD_UMIN_I64_POSTRA_ATOMIC_LOAD_UMIN_I8_POSTRA_ATOMIC_LOAD_XOR_I16_POSTRA_ATOMIC_LOAD_XOR_I32_POSTRA_ATOMIC_LOAD_XOR_I64_POSTRA_ATOMIC_LOAD_XOR_I8_POSTRA = 723, LEA_ADDiu = 724, ADDIUPC = 725, ALIGN = 726, ALUIPC = 727, AUI = 728, AUIPC = 729, BITSWAP = 730, CLO_R6 = 731, CLZ_R6 = 732, LSA_R6 = 733, SELEQZ_SELNEZ = 734, AddiuRxImmX16_AddiuRxRxImm16_AddiuRxRxImmX16_AddiuRxRyOffMemX16_AddiuRxPcImmX16_AddiuSpImm16_AddiuSpImmX16_AdduRxRyRz16_AndRxRxRy16_CmpRxRy16_CmpiRxImm16_CmpiRxImmX16_LiRxImm16_LiRxImmX16_LiRxImmAlignX16_Move32R16_MoveR3216_Mfhi16_Mflo16_NegRxRy16_NotRxRy16_OrRxRxRy16_SebRx16_SehRx16_SllX16_SllvRxRy16_SltiRxImm16_SltiRxImmX16_SltiuRxImm16_SltiuRxImmX16_SltRxRy16_SltuRxRy16_SravRxRy16_SraX16_SrlvRxRy16_SrlX16_SubuRxRyRz16_XorRxRxRy16 = 735, SltiCCRxImmX16_SltiuCCRxImmX16_SltCCRxRy16_SltuRxRyRz16_SltuCCRxRy16 = 736, Constant32_LwConstant32_GotPrologue16_CONSTPOOL_ENTRY = 737, ADDIUPC_MM_ADDIUR1SP_MM_ADDIUR2_MM_ADDIUS5_MM_ADDIUSP_MM_ADDiu_MM_LEA_ADDiu_MM = 738, ADDU16_MM_ADDu_MM = 739, ADD_MM = 740, ADDi_MM = 741, AND16_MM_ANDI16_MM_AND_MM = 742, ANDi_MM = 743, CLO_MM = 744, CLZ_MM = 745, EXT_MM = 746, INS_MM = 747, LI16_MM = 748, LUi_MM = 749, MOVE16_MM = 750, MOVEP_MM = 751, NOR_MM = 752, NOT16_MM = 753, OR16_MM_OR_MM = 754, ORi_MM = 755, ROTRV_MM = 756, ROTR_MM = 757, SEB_MM = 758, SEH_MM = 759, SLL16_MM_SLL_MM = 760, SLLV_MM = 761, SLT_MM_SLTu_MM = 762, SLTi_MM_SLTiu_MM = 763, SRAV_MM = 764, SRA_MM = 765, SRL16_MM_SRL_MM = 766, SRLV_MM = 767, SSNOP_MM = 768, SUBU16_MM_SUBu_MM = 769, SUB_MM = 770, WSBH_MM = 771, XOR16_MM_XOR_MM = 772, XORi_MM = 773, ADDIUPC_MMR6 = 774, ADDIU_MMR6 = 775, ADDU16_MMR6_ADDU_MMR6 = 776, ADD_MMR6 = 777, ALIGN_MMR6 = 778, ALUIPC_MMR6 = 779, AND16_MMR6_ANDI16_MMR6_AND_MMR6 = 780, ANDI_MMR6 = 781, AUIPC_MMR6 = 782, AUI_MMR6 = 783, BITSWAP_MMR6 = 784, CLO_MMR6 = 785, CLZ_MMR6 = 786, EXT_MMR6 = 787, INS_MMR6 = 788, LI16_MMR6 = 789, LSA_MMR6 = 790, LUI_MMR6 = 791, MOVE16_MMR6 = 792, NOR_MMR6 = 793, NOT16_MMR6 = 794, OR16_MMR6_OR_MMR6 = 795, ORI_MMR6 = 796, SELEQZ_MMR6_SELNEZ_MMR6 = 797, SLL16_MMR6_SLL_MMR6 = 798, SRL16_MMR6 = 799, SSNOP_MMR6 = 800, SUBU16_MMR6_SUBU_MMR6 = 801, SUB_MMR6 = 802, WSBH_MMR6 = 803, XOR16_MMR6_XOR_MMR6 = 804, XORI_MMR6 = 805, AND64_ANDi64 = 806, DEXT64_32 = 807, DSLL64_32 = 808, ORi64 = 809, SEB64 = 810, SEH64 = 811, SLL64_32_SLL64_64 = 812, SLT64_SLTu64 = 813, SLTi64_SLTiu64 = 814, XOR64_XORi64 = 815, DADD = 816, DADDi = 817, DADDiu = 818, DADDu = 819, DCLO = 820, DCLZ = 821, DEXT_DEXTM_DEXTU = 822, DINS_DINSM_DINSU = 823, DROTR = 824, DROTR32 = 825, DROTRV = 826, DSBH = 827, DSHD = 828, DSLL = 829, DSLL32 = 830, DSLLV = 831, DSRA = 832, DSRA32 = 833, DSRAV = 834, DSRL = 835, DSRL32 = 836, DSRLV = 837, DSUB = 838, DSUBu = 839, LEA_ADDiu64 = 840, LUi64 = 841, NOR64 = 842, OR64 = 843, DALIGN = 844, DAHI = 845, DATI = 846, DAUI = 847, DCLO_R6 = 848, DCLZ_R6 = 849, DBITSWAP = 850, DLSA_DLSA_R6 = 851, SELEQZ64_SELNEZ64 = 852, MADD = 853, MADDU = 854, MSUB = 855, MSUBU = 856, PseudoMADD_MM = 857, PseudoMADDU_MM = 858, PseudoMSUB_MM = 859, PseudoMSUBU_MM = 860, PseudoMULT_MM = 861, PseudoMULTu_MM = 862, PseudoMULT = 863, PseudoMULTu = 864, PseudoSDIV_SDIV = 865, PseudoUDIV_UDIV = 866, PseudoMFHI_MM_PseudoMFLO_MM = 867, PseudoMTLOHI_MM = 868, MUH = 869, MUHU = 870, MULU = 871, MUL_R6 = 872, MOD = 873, MODU = 874, MultRxRy16_MultuRxRy16_MultRxRyRz16_MultuRxRyRz16 = 875, DivRxRy16 = 876, DivuRxRy16 = 877, MULT_MM = 878, MULTu_MM = 879, MADD_MM = 880, MADDU_MM = 881, MSUB_MM = 882, MSUBU_MM = 883, MUL_MM = 884, SDIV_MM_SDIV_MM_Pseudo = 885, UDIV_MM_UDIV_MM_Pseudo = 886, MFHI16_MM_MFLO16_MM_MFHI_MM_MFLO_MM = 887, MOVF_I_MM = 888, MOVT_I_MM = 889, MTHI_MM_MTLO_MM = 890, RDHWR_MM = 891, MUHU_MMR6 = 892, MUH_MMR6 = 893, MULU_MMR6 = 894, MUL_MMR6 = 895, MODU_MMR6 = 896, MOD_MMR6 = 897, DIVU_MMR6 = 898, DIV_MMR6 = 899, RDHWR_MMR6 = 900, DMULU = 901, DMULT_PseudoDMULT = 902, DMULTu_PseudoDMULTu = 903, DSDIV_PseudoDSDIV = 904, DUDIV_PseudoDUDIV = 905, MFHI64_MFLO64_PseudoMFHI64_PseudoMFLO64 = 906, PseudoMTLOHI64 = 907, MTHI64_MTLO64 = 908, RDHWR64 = 909, MOVN_I_I64_MOVN_I64_I_MOVN_I64_I64 = 910, MOVZ_I_I64_MOVZ_I64_I_MOVZ_I64_I64 = 911, DMUH = 912, DMUHU = 913, DMUL_R6 = 914, DDIV = 915, DMOD = 916, DDIVU = 917, DMODU = 918, BAL_BR_BLTZAL = 919, BEQ_BNE = 920, BGTZ_BGEZ_BLEZ_BLTZ = 921, J = 922, JR = 923, ERet = 924, NAL = 925, BGEZAL = 926, BALC = 927, BEQZALC_BGEZALC_BGTZALC_BLEZALC_BLTZALC_BNEZALC = 928, JIALC = 929, BC = 930, BC2EQZ_BC2NEZ = 931, BEQC_BGEC_BGEUC_BLTC_BLTUC_BNEC_BNVC_BOVC = 932, BEQZC_BGEZC_BGTZC_BLEZC_BLTZC_BNEZC = 933, JIC = 934, JR_HB_R6 = 935, SIGRIE = 936, PseudoIndirectBranchR6_PseudoIndrectHazardBranchR6 = 937, TAILCALLR6REG_TAILCALLHBR6REG = 938, SDBBP_R6 = 939, Bimm16_BimmX16_BeqzRxImm16_BeqzRxImmX16_BnezRxImm16_BnezRxImmX16_Bteqz16_BteqzX16_Btnez16_BtnezX16_JrRa16_JrcRa16_JrcRx16 = 940, BteqzT8CmpX16_BteqzT8CmpiX16_BteqzT8SltX16_BteqzT8SltuX16_BteqzT8SltiX16_BteqzT8SltiuX16_BtnezT8CmpX16_BtnezT8CmpiX16_BtnezT8SltX16_BtnezT8SltuX16_BtnezT8SltiX16_BtnezT8SltiuX16_RetRA16 = 941, Jal16_JalB16 = 942, JumpLinkReg16 = 943, Break16 = 944, SelBeqZ_SelTBteqZCmp_SelTBteqZCmpi_SelTBteqZSlt_SelTBteqZSlti_SelTBteqZSltu_SelTBteqZSltiu_SelBneZ_SelTBtneZCmp_SelTBtneZCmpi_SelTBtneZSlt_SelTBtneZSlti_SelTBtneZSltu_SelTBtneZSltiu = 945, B16_MM_B_MM = 946, BAL_BR_MM = 947, BC1F_MM = 948, BC1T_MM = 949, BEQZ16_MM_BGEZ_MM_BGTZ_MM_BLEZ_MM_BLTZ_MM_BNEZ16_MM = 950, BEQZC_MM_BNEZC_MM = 951, BEQ_MM_BNE_MM = 952, DERET_MM = 953, ERET_MM = 954, JR16_MM_JR_MM = 955, J_MM = 956, B_MM_Pseudo = 957, BGEZALS_MM_BLTZALS_MM = 958, BGEZAL_MM_BLTZAL_MM = 959, JALR16_MM_JALR_MM = 960, JALRS16_MM_JALRS_MM = 961, JALS_MM = 962, JALX_MM_JAL_MM = 963, TAILCALLREG_MM = 964, TAILCALL_MM = 965, PseudoIndirectBranch_MM = 966, BREAK16_MM_BREAK_MM = 967, SDBBP16_MM_SDBBP_MM = 968, SYSCALL_MM = 969, TEQI_MM = 970, TEQ_MM = 971, TGEIU_MM = 972, TGEI_MM = 973, TGEU_MM = 974, TGE_MM = 975, TLTIU_MM = 976, TLTI_MM = 977, TLTU_MM = 978, TLT_MM = 979, TNEI_MM = 980, TNE_MM = 981, TRAP_MM = 982, BC16_MMR6_BC_MMR6 = 983, BC1EQZC_MMR6_BC1NEZC_MMR6 = 984, BC2EQZC_MMR6_BC2NEZC_MMR6 = 985, BEQC_MMR6_BGEC_MMR6_BGEUC_MMR6_BLTC_MMR6_BLTUC_MMR6_BNEC_MMR6_BNVC_MMR6_BOVC_MMR6 = 986, BEQZC16_MMR6_BNEZC16_MMR6 = 987, BEQZC_MMR6_BGEZC_MMR6_BGTZC_MMR6_BLEZC_MMR6_BLTZC_MMR6_BNEZC_MMR6 = 988, DERET_MMR6 = 989, ERETNC_MMR6 = 990, JAL_MMR6 = 991, ERET_MMR6 = 992, JIC_MMR6 = 993, JRADDIUSP_JRCADDIUSP_MMR6 = 994, JRC16_MM = 995, JRC16_MMR6 = 996, SIGRIE_MMR6 = 997, B_MMR6_Pseudo = 998, PseudoIndirectBranch_MMR6 = 999, BALC_MMR6 = 1000, BEQZALC_MMR6_BGEZALC_MMR6_BGTZALC_MMR6_BLEZALC_MMR6_BLTZALC_MMR6_BNEZALC_MMR6 = 1001, JALRC16_MMR6 = 1002, JALRC_HB_MMR6 = 1003, JALRC_MMR6 = 1004, JIALC_MMR6 = 1005, TAILCALLREG_MMR6 = 1006, TAILCALL_MMR6 = 1007, BREAK16_MMR6_BREAK_MMR6 = 1008, SDBBP_MMR6_SDBBP16_MMR6 = 1009, BEQ64_BNE64 = 1010, BGEZ64_BGTZ64_BLEZ64_BLTZ64 = 1011, JR64 = 1012, JALR64_JALR64Pseudo_JALRHB64Pseudo = 1013, JALR_HB64 = 1014, JR_HB64 = 1015, TAILCALLREG64_TAILCALLREGHB64 = 1016, PseudoReturn64 = 1017, BEQC64_BGEC64_BGEUC64_BLTC64_BLTUC64_BNEC64 = 1018, BEQZC64_BGEZC64_BGTZC64_BLEZC64_BLTZC64_BNEZC64 = 1019, JIC64 = 1020, PseudoIndirectBranch64_PseudoIndirectHazardBranch64 = 1021, JIALC64 = 1022, JR_HB64_R6 = 1023, TAILCALL64R6REG_TAILCALLHB64R6REG = 1024, PseudoIndirectBranch64R6_PseudoIndrectHazardBranch64R6 = 1025, EVP = 1026, DVP = 1027, TLBP_MM = 1028, TLBR_MM = 1029, TLBWI_MM = 1030, TLBWR_MM = 1031, DI_MM = 1032, EI_MM = 1033, EHB_MM = 1034, PAUSE_MM = 1035, WAIT_MM = 1036, RDPGPR_MMR6 = 1037, WRPGPR_MMR6 = 1038, TLBINV_MMR6 = 1039, TLBINVF_MMR6 = 1040, MFHC0_MMR6 = 1041, MFC0_MMR6 = 1042, MFHC2_MMR6_MFC2_MMR6 = 1043, MTHC0_MMR6 = 1044, MTC0_MMR6 = 1045, MTHC2_MMR6_MTC2_MMR6 = 1046, EVP_MMR6 = 1047, DVP_MMR6 = 1048, DI_MMR6 = 1049, EI_MMR6 = 1050, EHB_MMR6 = 1051, PAUSE_MMR6 = 1052, WAIT_MMR6 = 1053, DMFC0 = 1054, DMTC0 = 1055, DMFC2 = 1056, DMTC2 = 1057, CFC2_MM = 1058, CTC2_MM = 1059, DMT = 1060, DVPE = 1061, EMT = 1062, EVPE = 1063, MFTR = 1064, MTTR = 1065, YIELD = 1066, FORK = 1067, DMFGC0 = 1068, DMTGC0 = 1069, HYPCALL_MM = 1070, TLBGINVF_MM = 1071, TLBGINV_MM = 1072, TLBGP_MM = 1073, TLBGR_MM = 1074, TLBGWI_MM = 1075, TLBGWR_MM = 1076, MFGC0_MM = 1077, MFHGC0_MM = 1078, MTGC0_MM = 1079, MTHGC0_MM = 1080, SC_MMR6 = 1081, LDC2_R6 = 1082, LL_R6 = 1083, LWC2_R6 = 1084, SWC2_R6 = 1085, SDC2_R6 = 1086, SC_R6 = 1087, PREF_R6 = 1088, CACHE_R6 = 1089, GINVI = 1090, GINVT = 1091, LBE_MM = 1092, LBuE_MM = 1093, LHE_MM = 1094, LHuE_MM = 1095, LWE_MM = 1096, LWLE_MM = 1097, LWRE_MM = 1098, LLE_MM = 1099, SBE_MM = 1100, SB_MM = 1101, SHE_MM = 1102, SWE_MM = 1103, SWLE_MM = 1104, SWRE_MM = 1105, SCE_MM = 1106, PREFE_MM = 1107, CACHEE_MM = 1108, Restore16_RestoreX16 = 1109, LbRxRyOffMemX16 = 1110, LbuRxRyOffMemX16 = 1111, LhRxRyOffMemX16 = 1112, LhuRxRyOffMemX16 = 1113, LwRxRyOffMemX16_LwRxSpImmX16_LwRxPcTcp16_LwRxPcTcpX16 = 1114, Save16_SaveX16 = 1115, SbRxRyOffMemX16 = 1116, ShRxRyOffMemX16 = 1117, SwRxRyOffMemX16_SwRxSpImmX16 = 1118, LBU16_MM_LBu_MM = 1119, LB_MM = 1120, LHU16_MM_LHu_MM = 1121, LH_MM = 1122, LL_MM = 1123, LW16_MM_LWGP_MM_LWSP_MM_LW_MM = 1124, LWL_MM = 1125, LWM16_MM_LWM32_MM = 1126, LWP_MM = 1127, LWR_MM = 1128, LWU_MM = 1129, LWXS_MM = 1130, SB16_MM = 1131, SC_MM = 1132, SH16_MM_SH_MM = 1133, SW16_MM_SWSP_MM_SW_MM = 1134, SWL_MM = 1135, SWM16_MM_SWM32_MM = 1136, SWM_MM = 1137, SWP_MM = 1138, SWR_MM = 1139, PREF_MM_PREFX_MM = 1140, CACHE_MM = 1141, SYNC_MM = 1142, SYNCI_MM = 1143, GINVI_MMR6 = 1144, GINVT_MMR6 = 1145, LBU_MMR6 = 1146, LB_MMR6 = 1147, LDC2_MMR6 = 1148, LL_MMR6 = 1149, LWM16_MMR6 = 1150, LWC2_MMR6 = 1151, LWPC_MMR6 = 1152, LW_MMR6 = 1153, SB16_MMR6_SB_MMR6 = 1154, SDC2_MMR6 = 1155, SH16_MMR6_SH_MMR6 = 1156, SW16_MMR6_SWSP_MMR6_SW_MMR6 = 1157, SWC2_MMR6 = 1158, SWM16_MMR6 = 1159, SYNC_MMR6 = 1160, SYNCI_MMR6 = 1161, PREF_MMR6 = 1162, CACHE_MMR6 = 1163, LD = 1164, LL64_LLD = 1165, LWu = 1166, LB64 = 1167, LBu64 = 1168, LH64 = 1169, LHu64 = 1170, LW64 = 1171, LWL64 = 1172, LWR64 = 1173, LDL = 1174, LDR = 1175, SD = 1176, SC64_SCD = 1177, SB64 = 1178, SH64 = 1179, SW64 = 1180, SWL64 = 1181, SWR64 = 1182, SDL = 1183, SDR = 1184, LWUPC = 1185, LDPC = 1186, LLD_R6 = 1187, LL64_R6 = 1188, SC64_R6 = 1189, SCD_R6 = 1190, CRC32B = 1191, CRC32H = 1192, CRC32W = 1193, CRC32CB = 1194, CRC32CH = 1195, CRC32CW = 1196, CRC32D = 1197, CRC32CD = 1198, BADDu = 1199, BBIT0_BBIT032_BBIT1_BBIT132 = 1200, CINS_CINS32_CINS64_32_CINS_i32 = 1201, DMFC2_OCTEON = 1202, DMTC2_OCTEON = 1203, DPOP_POP = 1204, EXTS_EXTS32 = 1205, MTM0_MTM1_MTM2_MTP0_MTP1_MTP2 = 1206, SEQ_SNE = 1207, SEQi_SNEi = 1208, V3MULU_VMM0_VMULU = 1209, DMUL = 1210, SAA_SAAD = 1211, ADDR_PS64 = 1212, CVT_PS_PW64_CVT_PW_PS64 = 1213, MULR_PS64 = 1214, PseudoTRUNC_W_D_PseudoTRUNC_W_D32_PseudoTRUNC_W_S = 1215, MOVT_I64 = 1216, MOVF_I64 = 1217, MOVZ_I64_S = 1218, MOVN_I64_D64 = 1219, MOVN_I64_S = 1220, MOVZ_I64_D64 = 1221, SELEQZ_S_SELNEZ_S = 1222, SELEQZ_D_SELNEZ_D = 1223, MAX_S_MAXA_S = 1224, MAX_D_MAXA_D = 1225, MIN_S_MINA_D = 1226, MIN_D_MINA_S = 1227, CLASS_S = 1228, CLASS_D = 1229, RINT_S = 1230, RINT_D = 1231, BC1EQZ_BC1NEZ = 1232, SEL_D = 1233, SEL_S = 1234, MADDF_S = 1235, MSUBF_S = 1236, MADDF_D = 1237, MSUBF_D = 1238, MOVF_D32_MM = 1239, MOVF_S_MM = 1240, MOVN_I_D32_MM = 1241, MOVN_I_S_MM = 1242, MOVT_D32_MM = 1243, MOVT_S_MM = 1244, MOVZ_I_D32_MM = 1245, MOVZ_I_S_MM = 1246, CVT_D32_S_MM_CVT_D32_W_MM_CVT_D64_S_MM_CVT_D64_W_MM_CVT_L_D64_MM_CVT_L_S_MM_CVT_S_D32_MM_CVT_S_D64_MM_CVT_S_W_MM_CVT_W_D32_MM_CVT_W_D64_MM_CVT_W_S_MM = 1247, CEIL_W_MM_CEIL_W_S_MM = 1248, FLOOR_W_MM_FLOOR_W_S_MM = 1249, NMADD_S_MM = 1250, NMADD_D32_MM = 1251, NMSUB_S_MM = 1252, NMSUB_D32_MM = 1253, MADD_S_MM = 1254, MADD_D32_MM = 1255, ROUND_W_MM_ROUND_W_S_MM = 1256, TRUNC_W_MM_TRUNC_W_S_MM = 1257, C_F_D32_MM_C_F_D64_MM = 1258, C_F_S_MM = 1259, C_EQ_D32_MM_C_EQ_D64_MM_C_LE_D32_MM_C_LE_D64_MM_C_LT_D32_MM_C_LT_D64_MM_C_SF_D32_MM_C_SF_D64_MM_C_UN_D32_MM_C_UN_D64_MM = 1260, C_EQ_S_MM_C_LE_S_MM_C_LT_S_MM_C_SF_S_MM_C_UN_S_MM = 1261, C_NGE_D32_MM_C_NGE_D64_MM_C_NGL_D32_MM_C_NGL_D64_MM_C_NGT_D32_MM_C_NGT_D64_MM_C_OLE_D32_MM_C_OLE_D64_MM_C_OLT_D32_MM_C_OLT_D64_MM_C_SEQ_D32_MM_C_SEQ_D64_MM_C_UEQ_D32_MM_C_UEQ_D64_MM_C_ULE_D32_MM_C_ULE_D64_MM_C_ULT_D32_MM_C_ULT_D64_MM = 1262, C_NGE_S_MM_C_NGL_S_MM_C_NGT_S_MM_C_OLE_S_MM_C_OLT_S_MM_C_SEQ_S_MM_C_UEQ_S_MM_C_ULE_S_MM_C_ULT_S_MM = 1263, C_NGLE_D32_MM_C_NGLE_D64_MM = 1264, C_NGLE_S_MM = 1265, FCMP_S32_MM = 1266, FCMP_D32_MM = 1267, MFC1_MM = 1268, MFHC1_D32_MM_MFHC1_D64_MM = 1269, MTC1_MM_MTC1_D64_MM = 1270, MTHC1_D32_MM_MTHC1_D64_MM = 1271, FABS_D32_MM_FABS_D64_MM = 1272, FABS_S_MM = 1273, FNEG_D32_MM_FNEG_D64_MM_FNEG_S_MM = 1274, FADD_D32_MM_FADD_D64_MM = 1275, FADD_S_MM = 1276, FMOV_D32_MM_FMOV_D64_MM = 1277, FMOV_S_MM = 1278, FMUL_D32_MM_FMUL_D64_MM = 1279, FMUL_S_MM = 1280, FSUB_D32_MM_FSUB_D64_MM = 1281, FSUB_S_MM = 1282, MSUB_S_MM = 1283, MSUB_D32_MM = 1284, FDIV_S_MM = 1285, FDIV_D32_MM_FDIV_D64_MM = 1286, FSQRT_S_MM = 1287, FSQRT_D32_MM_FSQRT_D64_MM = 1288, RECIP_S_MM_RSQRT_S_MM = 1289, RECIP_D32_MM_RECIP_D64_MM_RSQRT_D32_MM_RSQRT_D64_MM = 1290, SDC1_MM_D32_SDC1_MM_D64 = 1291, SWC1_MM = 1292, SUXC1_MM = 1293, SWXC1_MM = 1294, CFC1_MM = 1295, CTC1_MM = 1296, LDC1_MM_D32_LDC1_MM_D64 = 1297, LUXC1_MM = 1298, LWC1_MM = 1299, LWXC1_MM = 1300, FNEG_S_MMR6 = 1301, CMP_AF_D_MMR6_CMP_EQ_D_MMR6_CMP_LE_D_MMR6_CMP_LT_D_MMR6_CMP_UN_D_MMR6 = 1302, CMP_AF_S_MMR6_CMP_EQ_S_MMR6_CMP_LE_S_MMR6_CMP_LT_S_MMR6_CMP_UN_S_MMR6 = 1303, CMP_SAF_D_MMR6_CMP_SEQ_D_MMR6_CMP_SLE_D_MMR6_CMP_SLT_D_MMR6_CMP_SUN_D_MMR6_CMP_UEQ_D_MMR6_CMP_ULE_D_MMR6_CMP_ULT_D_MMR6 = 1304, CMP_SAF_S_MMR6_CMP_SEQ_S_MMR6_CMP_SLE_S_MMR6_CMP_SLT_S_MMR6_CMP_SUN_S_MMR6_CMP_UEQ_S_MMR6_CMP_ULE_S_MMR6_CMP_ULT_S_MMR6 = 1305, CMP_SUEQ_D_MMR6_CMP_SULE_D_MMR6_CMP_SULT_D_MMR6 = 1306, CMP_SUEQ_S_MMR6_CMP_SULE_S_MMR6_CMP_SULT_S_MMR6 = 1307, CVT_D_L_MMR6_CVT_L_D_MMR6_CVT_L_S_MMR6_CVT_S_L_MMR6_CVT_S_W_MMR6_CVT_W_S_MMR6 = 1308, TRUNC_L_D_MMR6_TRUNC_L_S_MMR6_TRUNC_W_D_MMR6_TRUNC_W_S_MMR6 = 1309, ROUND_L_D_MMR6_ROUND_L_S_MMR6_ROUND_W_D_MMR6_ROUND_W_S_MMR6 = 1310, FLOOR_L_D_MMR6_FLOOR_L_S_MMR6_FLOOR_W_D_MMR6_FLOOR_W_S_MMR6 = 1311, CEIL_L_D_MMR6_CEIL_L_S_MMR6_CEIL_W_D_MMR6_CEIL_W_S_MMR6 = 1312, MFC1_MMR6 = 1313, MTC1_MMR6 = 1314, CLASS_S_MMR6_CLASS_D_MMR6 = 1315, FADD_S_MMR6 = 1316, MAX_D_MMR6 = 1317, MAX_S_MMR6 = 1318, MIN_D_MMR6 = 1319, MIN_S_MMR6 = 1320, MAXA_D_MMR6 = 1321, MAXA_S_MMR6 = 1322, MINA_D_MMR6 = 1323, MINA_S_MMR6 = 1324, SELEQZ_D_MMR6_SELNEZ_D_MMR6 = 1325, SELEQZ_S_MMR6_SELNEZ_S_MMR6 = 1326, SEL_D_MMR6 = 1327, SEL_S_MMR6 = 1328, RINT_S_MMR6_RINT_D_MMR6 = 1329, MADDF_D_MMR6 = 1330, MADDF_S_MMR6 = 1331, MSUBF_D_MMR6 = 1332, MSUBF_S_MMR6 = 1333, FMOV_S_MMR6 = 1334, FMUL_S_MMR6 = 1335, FSUB_S_MMR6 = 1336, FMOV_D_MMR6 = 1337, FDIV_S_MMR6 = 1338, SDC1_D64_MMR6 = 1339, LDC1_D64_MMR6 = 1340, DMFC1 = 1341, DMTC1 = 1342, SWDSP = 1343, LWDSP = 1344, PseudoMTLOHI_DSP = 1345, EXTRV_RS_W = 1346, EXTRV_R_W = 1347, EXTRV_S_H = 1348, EXTRV_W = 1349, EXTR_RS_W = 1350, EXTR_R_W = 1351, EXTR_S_H = 1352, EXTR_W = 1353, INSV = 1354, MTHLIP = 1355, MTHI_DSP = 1356, MTLO_DSP = 1357, ABSQ_S_PH = 1358, ABSQ_S_W = 1359, ADDQ_PH = 1360, ADDQ_S_PH = 1361, ADDQ_S_W = 1362, ADDSC = 1363, ADDU_QB = 1364, ADDU_S_QB = 1365, ADDWC = 1366, BITREV = 1367, BPOSGE32 = 1368, CMPGU_EQ_QB = 1369, CMPGU_LE_QB = 1370, CMPGU_LT_QB = 1371, CMPU_EQ_QB = 1372, CMPU_LE_QB = 1373, CMPU_LT_QB = 1374, CMP_EQ_PH = 1375, CMP_LE_PH = 1376, CMP_LT_PH = 1377, DPAQ_SA_L_W = 1378, DPAQ_S_W_PH = 1379, DPAU_H_QBL = 1380, DPAU_H_QBR = 1381, DPSQ_SA_L_W = 1382, DPSQ_S_W_PH = 1383, DPSU_H_QBL = 1384, DPSU_H_QBR = 1385, EXTPDPV = 1386, EXTPDP = 1387, EXTPV = 1388, EXTP = 1389, LBUX = 1390, LHX = 1391, LWX = 1392, MADDU_DSP = 1393, MADD_DSP = 1394, MAQ_SA_W_PHL = 1395, MAQ_SA_W_PHR = 1396, MAQ_S_W_PHL = 1397, MAQ_S_W_PHR = 1398, MFHI_DSP = 1399, MFLO_DSP = 1400, MODSUB = 1401, MSUBU_DSP = 1402, MSUB_DSP = 1403, MULEQ_S_W_PHL = 1404, MULEQ_S_W_PHR = 1405, MULEU_S_PH_QBL = 1406, MULEU_S_PH_QBR = 1407, MULQ_RS_PH = 1408, MULSAQ_S_W_PH = 1409, MULTU_DSP = 1410, MULT_DSP = 1411, PACKRL_PH = 1412, PICK_PH = 1413, PICK_QB = 1414, PRECEQU_PH_QBLA = 1415, PRECEQU_PH_QBL = 1416, PRECEQU_PH_QBRA = 1417, PRECEQU_PH_QBR = 1418, PRECEQ_W_PHL = 1419, PRECEQ_W_PHR = 1420, PRECEU_PH_QBLA = 1421, PRECEU_PH_QBL = 1422, PRECEU_PH_QBRA = 1423, PRECEU_PH_QBR = 1424, PRECRQU_S_QB_PH = 1425, PRECRQ_PH_W = 1426, PRECRQ_QB_PH = 1427, PRECRQ_RS_PH_W = 1428, RADDU_W_QB = 1429, RDDSP = 1430, REPLV_PH = 1431, REPLV_QB = 1432, REPL_PH = 1433, REPL_QB = 1434, SHILOV = 1435, SHILO = 1436, SHLLV_PH = 1437, SHLLV_QB = 1438, SHLLV_S_PH = 1439, SHLLV_S_W = 1440, SHLL_PH = 1441, SHLL_QB = 1442, SHLL_S_PH = 1443, SHLL_S_W = 1444, SHRAV_PH = 1445, SHRAV_R_PH = 1446, SHRAV_R_W = 1447, SHRA_PH = 1448, SHRA_R_PH = 1449, SHRA_R_W = 1450, SHRLV_QB = 1451, SHRL_QB = 1452, SUBQ_PH = 1453, SUBQ_S_PH = 1454, SUBQ_S_W = 1455, SUBU_QB = 1456, SUBU_S_QB = 1457, WRDSP = 1458, PseudoCMPU_EQ_QB_PseudoCMPU_LE_QB_PseudoCMPU_LT_QB_PseudoCMP_EQ_PH_PseudoCMP_LE_PH_PseudoCMP_LT_PH = 1459, PseudoPICK_PH_PseudoPICK_QB = 1460, ABSQ_S_QB = 1461, ADDQH_PH = 1462, ADDQH_R_PH = 1463, ADDQH_R_W = 1464, ADDQH_W = 1465, ADDUH_QB = 1466, ADDUH_R_QB = 1467, ADDU_PH = 1468, ADDU_S_PH = 1469, APPEND = 1470, BALIGN = 1471, CMPGDU_EQ_QB = 1472, CMPGDU_LE_QB = 1473, CMPGDU_LT_QB = 1474, DPA_W_PH = 1475, DPAQX_SA_W_PH = 1476, DPAQX_S_W_PH = 1477, DPAX_W_PH = 1478, DPS_W_PH = 1479, DPSQX_S_W_PH = 1480, DPSQX_SA_W_PH = 1481, DPSX_W_PH = 1482, MUL_PH = 1483, MUL_S_PH = 1484, MULQ_RS_W = 1485, MULQ_S_PH = 1486, MULQ_S_W = 1487, MULSA_W_PH = 1488, PRECR_QB_PH = 1489, PRECR_SRA_PH_W = 1490, PRECR_SRA_R_PH_W = 1491, PREPEND = 1492, SHRA_QB = 1493, SHRA_R_QB = 1494, SHRAV_QB = 1495, SHRAV_R_QB = 1496, SHRL_PH = 1497, SHRLV_PH = 1498, SUBQH_PH = 1499, SUBQH_R_PH = 1500, SUBQH_W = 1501, SUBQH_R_W = 1502, SUBU_PH = 1503, SUBU_S_PH = 1504, SUBUH_QB = 1505, SUBUH_R_QB = 1506, LWDSP_MM = 1507, SWDSP_MM = 1508, ABSQ_S_PH_MM = 1509, ABSQ_S_W_MM = 1510, ADDQ_PH_MM = 1511, ADDQ_S_PH_MM = 1512, ADDQ_S_W_MM = 1513, ADDSC_MM = 1514, ADDU_QB_MM = 1515, ADDU_S_QB_MM = 1516, ADDWC_MM = 1517, BITREV_MM = 1518, BPOSGE32_MM = 1519, CMPGU_EQ_QB_MM = 1520, CMPGU_LE_QB_MM = 1521, CMPGU_LT_QB_MM = 1522, CMPU_EQ_QB_MM = 1523, CMPU_LE_QB_MM = 1524, CMPU_LT_QB_MM = 1525, CMP_EQ_PH_MM = 1526, CMP_LE_PH_MM = 1527, CMP_LT_PH_MM = 1528, DPAQ_SA_L_W_MM = 1529, DPAQ_S_W_PH_MM = 1530, DPAU_H_QBL_MM = 1531, DPAU_H_QBR_MM = 1532, DPSQ_SA_L_W_MM = 1533, DPSQ_S_W_PH_MM = 1534, DPSU_H_QBL_MM = 1535, DPSU_H_QBR_MM = 1536, EXTPDPV_MM = 1537, EXTPDP_MM = 1538, EXTPV_MM = 1539, EXTP_MM = 1540, EXTRV_RS_W_MM = 1541, EXTRV_R_W_MM = 1542, EXTRV_S_H_MM = 1543, EXTRV_W_MM = 1544, EXTR_RS_W_MM = 1545, EXTR_R_W_MM = 1546, EXTR_S_H_MM = 1547, EXTR_W_MM = 1548, INSV_MM = 1549, LBUX_MM = 1550, LHX_MM = 1551, LWX_MM = 1552, MADDU_DSP_MM = 1553, MADD_DSP_MM = 1554, MAQ_SA_W_PHL_MM = 1555, MAQ_SA_W_PHR_MM = 1556, MAQ_S_W_PHL_MM = 1557, MAQ_S_W_PHR_MM = 1558, MFHI_DSP_MM = 1559, MFLO_DSP_MM = 1560, MODSUB_MM = 1561, MOVEP_MMR6 = 1562, MOVN_I_MM = 1563, MOVZ_I_MM = 1564, MSUBU_DSP_MM = 1565, MSUB_DSP_MM = 1566, MTHI_DSP_MM = 1567, MTHLIP_MM = 1568, MTLO_DSP_MM = 1569, MULEQ_S_W_PHL_MM = 1570, MULEQ_S_W_PHR_MM = 1571, MULEU_S_PH_QBL_MM = 1572, MULEU_S_PH_QBR_MM = 1573, MULQ_RS_PH_MM = 1574, MULSAQ_S_W_PH_MM = 1575, MULTU_DSP_MM = 1576, MULT_DSP_MM = 1577, PACKRL_PH_MM = 1578, PICK_PH_MM = 1579, PICK_QB_MM = 1580, PRECEQU_PH_QBLA_MM = 1581, PRECEQU_PH_QBL_MM = 1582, PRECEQU_PH_QBRA_MM = 1583, PRECEQU_PH_QBR_MM = 1584, PRECEQ_W_PHL_MM = 1585, PRECEQ_W_PHR_MM = 1586, PRECEU_PH_QBLA_MM = 1587, PRECEU_PH_QBL_MM = 1588, PRECEU_PH_QBRA_MM = 1589, PRECEU_PH_QBR_MM = 1590, PRECRQU_S_QB_PH_MM = 1591, PRECRQ_PH_W_MM = 1592, PRECRQ_QB_PH_MM = 1593, PRECRQ_RS_PH_W_MM = 1594, RADDU_W_QB_MM = 1595, RDDSP_MM = 1596, REPLV_PH_MM = 1597, REPLV_QB_MM = 1598, REPL_PH_MM = 1599, REPL_QB_MM = 1600, SHILOV_MM = 1601, SHILO_MM = 1602, SHLLV_PH_MM = 1603, SHLLV_QB_MM = 1604, SHLLV_S_PH_MM = 1605, SHLLV_S_W_MM = 1606, SHLL_PH_MM = 1607, SHLL_QB_MM = 1608, SHLL_S_PH_MM = 1609, SHLL_S_W_MM = 1610, SHRAV_PH_MM = 1611, SHRAV_R_PH_MM = 1612, SHRAV_R_W_MM = 1613, SHRA_PH_MM = 1614, SHRA_R_PH_MM = 1615, SHRA_R_W_MM = 1616, SHRLV_QB_MM = 1617, SHRL_QB_MM = 1618, SUBQ_PH_MM = 1619, SUBQ_S_PH_MM = 1620, SUBQ_S_W_MM = 1621, SUBU_QB_MM = 1622, SUBU_S_QB_MM = 1623, WRDSP_MM = 1624, ABSQ_S_QB_MMR2 = 1625, ADDQH_PH_MMR2 = 1626, ADDQH_R_PH_MMR2 = 1627, ADDQH_R_W_MMR2 = 1628, ADDQH_W_MMR2 = 1629, ADDUH_QB_MMR2 = 1630, ADDUH_R_QB_MMR2 = 1631, ADDU_PH_MMR2 = 1632, ADDU_S_PH_MMR2 = 1633, APPEND_MMR2 = 1634, BALIGN_MMR2 = 1635, CMPGDU_EQ_QB_MMR2 = 1636, CMPGDU_LE_QB_MMR2 = 1637, CMPGDU_LT_QB_MMR2 = 1638, DPA_W_PH_MMR2 = 1639, DPAQX_SA_W_PH_MMR2 = 1640, DPAQX_S_W_PH_MMR2 = 1641, DPAX_W_PH_MMR2 = 1642, DPS_W_PH_MMR2 = 1643, DPSQX_S_W_PH_MMR2 = 1644, DPSQX_SA_W_PH_MMR2 = 1645, DPSX_W_PH_MMR2 = 1646, MUL_PH_MMR2 = 1647, MUL_S_PH_MMR2 = 1648, MULQ_RS_W_MMR2 = 1649, MULQ_S_PH_MMR2 = 1650, MULQ_S_W_MMR2 = 1651, MULSA_W_PH_MMR2 = 1652, PRECR_QB_PH_MMR2 = 1653, PRECR_SRA_PH_W_MMR2 = 1654, PRECR_SRA_R_PH_W_MMR2 = 1655, PREPEND_MMR2 = 1656, SHRA_QB_MMR2 = 1657, SHRA_R_QB_MMR2 = 1658, SHRAV_QB_MMR2 = 1659, SHRAV_R_QB_MMR2 = 1660, SHRL_PH_MMR2 = 1661, SHRLV_PH_MMR2 = 1662, SUBQH_PH_MMR2 = 1663, SUBQH_R_PH_MMR2 = 1664, SUBQH_W_MMR2 = 1665, SUBQH_R_W_MMR2 = 1666, SUBU_PH_MMR2 = 1667, SUBU_S_PH_MMR2 = 1668, SUBUH_QB_MMR2 = 1669, SUBUH_R_QB_MMR2 = 1670, BPOSGE32C_MMR3 = 1671, CMP_F_D = 1672, CMP_F_S = 1673, CMP_SAF_D = 1674, CMP_SAF_S = 1675, CMP_SEQ_D = 1676, CMP_SEQ_S = 1677, CMP_SLE_D = 1678, CMP_SLE_S = 1679, CMP_SLT_D = 1680, CMP_SLT_S = 1681, CMP_SUEQ_D = 1682, CMP_SUEQ_S = 1683, CMP_SULE_D = 1684, CMP_SULE_S = 1685, CMP_SULT_D = 1686, CMP_SULT_S = 1687, CMP_SUN_D = 1688, CMP_SUN_S = 1689, SCHED_LIST_END = 1690 }; } // end namespace Sched } // end namespace Mips } // end namespace llvm #endif // GET_INSTRINFO_SCHED_ENUM #if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) namespace llvm { struct MipsInstrTable { MCInstrDesc Insts[2900]; static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo"); MCOperandInfo OperandInfo[1142]; static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps"); MCPhysReg ImplicitOps[67]; }; } // end namespace llvm #endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) #ifdef GET_INSTRINFO_MC_DESC #undef GET_INSTRINFO_MC_DESC namespace llvm { static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0); static constexpr unsigned MipsImpOpBase = sizeof MipsInstrTable::OperandInfo / (sizeof(MCPhysReg)); extern const MipsInstrTable MipsDescs = { { { 2899, 2, 1, 4, 1066, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2899 = YIELD { 2898, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 588, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #2898 = XorRxRxRy16 { 2897, 3, 1, 4, 773, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2897 = XORi_MM { 2896, 3, 1, 4, 815, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2896 = XORi64 { 2895, 3, 1, 4, 508, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2895 = XORi { 2894, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2894 = XOR_V { 2893, 3, 1, 4, 804, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2893 = XOR_MMR6 { 2892, 3, 1, 4, 772, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2892 = XOR_MM { 2891, 3, 1, 4, 805, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2891 = XORI_MMR6 { 2890, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2890 = XORI_B { 2889, 3, 1, 4, 815, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2889 = XOR64 { 2888, 3, 1, 2, 804, 0, 0, MipsImpOpBase + 0, 573, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2888 = XOR16_MMR6 { 2887, 3, 1, 2, 772, 0, 0, MipsImpOpBase + 0, 573, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2887 = XOR16_MM { 2886, 3, 1, 4, 371, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2886 = XOR { 2885, 2, 1, 4, 803, 0, 0, MipsImpOpBase + 0, 152, 0, 0x6ULL }, // Inst #2885 = WSBH_MMR6 { 2884, 2, 1, 4, 771, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #2884 = WSBH_MM { 2883, 2, 1, 4, 481, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #2883 = WSBH { 2882, 2, 1, 4, 1038, 0, 0, MipsImpOpBase + 0, 152, 0, 0x6ULL }, // Inst #2882 = WRPGPR_MMR6 { 2881, 2, 0, 4, 1624, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2881 = WRDSP_MM { 2880, 2, 0, 4, 1458, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2880 = WRDSP { 2879, 1, 0, 4, 1053, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2879 = WAIT_MMR6 { 2878, 1, 0, 4, 1036, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2878 = WAIT_MM { 2877, 0, 0, 4, 404, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2877 = WAIT { 2876, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #2876 = VSHF_W { 2875, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 206, 0, 0x6ULL }, // Inst #2875 = VSHF_H { 2874, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 198, 0, 0x6ULL }, // Inst #2874 = VSHF_D { 2873, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 618, 0, 0x6ULL }, // Inst #2873 = VSHF_B { 2872, 3, 1, 4, 1209, 0, 5, MipsImpOpBase + 62, 235, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2872 = VMULU { 2871, 3, 1, 4, 1209, 0, 4, MipsImpOpBase + 42, 235, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2871 = VMM0 { 2870, 3, 1, 4, 1209, 0, 3, MipsImpOpBase + 59, 235, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2870 = V3MULU { 2869, 2, 0, 4, 886, 0, 2, MipsImpOpBase + 7, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2869 = UDIV_MM { 2868, 2, 0, 4, 866, 0, 2, MipsImpOpBase + 7, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2868 = UDIV { 2867, 2, 0, 4, 403, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2867 = TTLTIU { 2866, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #2866 = TRUNC_W_S_MMR6 { 2865, 2, 1, 4, 1257, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #2865 = TRUNC_W_S_MM { 2864, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #2864 = TRUNC_W_S { 2863, 2, 1, 4, 1257, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #2863 = TRUNC_W_MM { 2862, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #2862 = TRUNC_W_D_MMR6 { 2861, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #2861 = TRUNC_W_D64 { 2860, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #2860 = TRUNC_W_D32 { 2859, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #2859 = TRUNC_L_S_MMR6 { 2858, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #2858 = TRUNC_L_S { 2857, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #2857 = TRUNC_L_D_MMR6 { 2856, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #2856 = TRUNC_L_D64 { 2855, 3, 0, 4, 981, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2855 = TNE_MM { 2854, 2, 0, 4, 980, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2854 = TNEI_MM { 2853, 2, 0, 4, 401, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2853 = TNEI { 2852, 3, 0, 4, 400, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2852 = TNE { 2851, 3, 0, 4, 979, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2851 = TLT_MM { 2850, 3, 0, 4, 978, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2850 = TLTU_MM { 2849, 3, 0, 4, 399, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2849 = TLTU { 2848, 2, 0, 4, 977, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2848 = TLTI_MM { 2847, 2, 0, 4, 976, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2847 = TLTIU_MM { 2846, 2, 0, 4, 398, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2846 = TLTI { 2845, 3, 0, 4, 397, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2845 = TLT { 2844, 0, 0, 4, 1031, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2844 = TLBWR_MM { 2843, 0, 0, 4, 415, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2843 = TLBWR { 2842, 0, 0, 4, 1030, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2842 = TLBWI_MM { 2841, 0, 0, 4, 414, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2841 = TLBWI { 2840, 0, 0, 4, 1029, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2840 = TLBR_MM { 2839, 0, 0, 4, 413, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2839 = TLBR { 2838, 0, 0, 4, 1028, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2838 = TLBP_MM { 2837, 0, 0, 4, 412, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2837 = TLBP { 2836, 0, 0, 4, 1039, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2836 = TLBINV_MMR6 { 2835, 0, 0, 4, 1040, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2835 = TLBINVF_MMR6 { 2834, 0, 0, 4, 411, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2834 = TLBINVF { 2833, 0, 0, 4, 410, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2833 = TLBINV { 2832, 0, 0, 4, 1076, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2832 = TLBGWR_MM { 2831, 0, 0, 4, 430, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2831 = TLBGWR { 2830, 0, 0, 4, 1075, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2830 = TLBGWI_MM { 2829, 0, 0, 4, 429, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2829 = TLBGWI { 2828, 0, 0, 4, 1074, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2828 = TLBGR_MM { 2827, 0, 0, 4, 428, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2827 = TLBGR { 2826, 0, 0, 4, 1073, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2826 = TLBGP_MM { 2825, 0, 0, 4, 427, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2825 = TLBGP { 2824, 0, 0, 4, 1072, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2824 = TLBGINV_MM { 2823, 0, 0, 4, 1071, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2823 = TLBGINVF_MM { 2822, 0, 0, 4, 426, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2822 = TLBGINVF { 2821, 0, 0, 4, 425, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2821 = TLBGINV { 2820, 3, 0, 4, 975, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2820 = TGE_MM { 2819, 3, 0, 4, 974, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2819 = TGEU_MM { 2818, 3, 0, 4, 396, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2818 = TGEU { 2817, 2, 0, 4, 973, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2817 = TGEI_MM { 2816, 2, 0, 4, 972, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2816 = TGEIU_MM { 2815, 2, 0, 4, 395, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2815 = TGEIU { 2814, 2, 0, 4, 394, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2814 = TGEI { 2813, 3, 0, 4, 393, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2813 = TGE { 2812, 3, 0, 4, 971, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2812 = TEQ_MM { 2811, 2, 0, 4, 970, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2811 = TEQI_MM { 2810, 2, 0, 4, 392, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2810 = TEQI { 2809, 3, 0, 4, 391, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2809 = TEQ { 2808, 3, 0, 4, 1118, 0, 0, MipsImpOpBase + 0, 585, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2808 = SwRxSpImmX16 { 2807, 3, 0, 4, 1118, 0, 0, MipsImpOpBase + 0, 926, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2807 = SwRxRyOffMemX16 { 2806, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 408, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #2806 = SubuRxRyRz16 { 2805, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 588, 0, 0x0ULL }, // Inst #2805 = SrlvRxRy16 { 2804, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 532, 0, 0x0ULL }, // Inst #2804 = SrlX16 { 2803, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 588, 0, 0x0ULL }, // Inst #2803 = SravRxRy16 { 2802, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 532, 0, 0x0ULL }, // Inst #2802 = SraX16 { 2801, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 406, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2801 = SltuRxRy16 { 2800, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 580, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2800 = SltiuRxImmX16 { 2799, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 580, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2799 = SltiuRxImm16 { 2798, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 580, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2798 = SltiRxImmX16 { 2797, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 580, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2797 = SltiRxImm16 { 2796, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 406, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2796 = SltRxRy16 { 2795, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 588, 0, 0x0ULL }, // Inst #2795 = SllvRxRy16 { 2794, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 532, 0, 0x0ULL }, // Inst #2794 = SllX16 { 2793, 3, 0, 4, 1117, 0, 0, MipsImpOpBase + 0, 926, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2793 = ShRxRyOffMemX16 { 2792, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1140, 0, 0x0ULL }, // Inst #2792 = SehRx16 { 2791, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1140, 0, 0x0ULL }, // Inst #2791 = SebRx16 { 2790, 3, 0, 4, 1116, 0, 0, MipsImpOpBase + 0, 926, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2790 = SbRxRyOffMemX16 { 2789, 0, 0, 2, 1115, 1, 1, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2789 = SaveX16 { 2788, 0, 0, 2, 1115, 1, 1, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2788 = Save16 { 2787, 1, 0, 4, 969, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2787 = SYSCALL_MM { 2786, 1, 0, 4, 390, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2786 = SYSCALL { 2785, 1, 0, 4, 1160, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2785 = SYNC_MMR6 { 2784, 1, 0, 4, 1142, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2784 = SYNC_MM { 2783, 2, 0, 4, 1161, 0, 0, MipsImpOpBase + 0, 1138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2783 = SYNCI_MMR6 { 2782, 2, 0, 4, 1143, 0, 0, MipsImpOpBase + 0, 1138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2782 = SYNCI_MM { 2781, 2, 0, 4, 473, 0, 0, MipsImpOpBase + 0, 1138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2781 = SYNCI { 2780, 1, 0, 4, 472, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2780 = SYNC { 2779, 3, 0, 4, 1157, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2779 = SW_MMR6 { 2778, 3, 0, 4, 1134, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2778 = SW_MM { 2777, 3, 0, 4, 1294, 0, 0, MipsImpOpBase + 0, 923, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2777 = SWXC1_MM { 2776, 3, 0, 4, 702, 0, 0, MipsImpOpBase + 0, 923, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2776 = SWXC1 { 2775, 3, 0, 2, 1157, 0, 0, MipsImpOpBase + 0, 920, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2775 = SWSP_MMR6 { 2774, 3, 0, 2, 1134, 0, 0, MipsImpOpBase + 0, 920, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2774 = SWSP_MM { 2773, 3, 0, 4, 1139, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2773 = SWR_MM { 2772, 3, 0, 4, 1105, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2772 = SWRE_MM { 2771, 3, 0, 4, 467, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2771 = SWRE { 2770, 3, 0, 4, 1182, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2770 = SWR64 { 2769, 3, 0, 4, 465, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2769 = SWR { 2768, 4, 0, 4, 1138, 0, 0, MipsImpOpBase + 0, 916, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2768 = SWP_MM { 2767, 3, 0, 4, 1136, 0, 0, MipsImpOpBase + 0, 361, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2767 = SWM32_MM { 2766, 3, 0, 2, 1159, 0, 0, MipsImpOpBase + 0, 913, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2766 = SWM16_MMR6 { 2765, 3, 0, 2, 1136, 0, 0, MipsImpOpBase + 0, 913, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2765 = SWM16_MM { 2764, 3, 0, 4, 1135, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2764 = SWL_MM { 2763, 3, 0, 4, 1104, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2763 = SWLE_MM { 2762, 3, 0, 4, 466, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2762 = SWLE { 2761, 3, 0, 4, 1181, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2761 = SWL64 { 2760, 3, 0, 4, 464, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2760 = SWL { 2759, 3, 0, 4, 1103, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2759 = SWE_MM { 2758, 3, 0, 4, 462, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2758 = SWE { 2757, 3, 0, 4, 1508, 0, 0, MipsImpOpBase + 0, 903, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2757 = SWDSP_MM { 2756, 3, 0, 4, 1343, 0, 0, MipsImpOpBase + 0, 903, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2756 = SWDSP { 2755, 3, 0, 4, 456, 0, 0, MipsImpOpBase + 0, 861, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2755 = SWC3 { 2754, 3, 0, 4, 1085, 0, 0, MipsImpOpBase + 0, 855, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2754 = SWC2_R6 { 2753, 3, 0, 4, 1158, 0, 0, MipsImpOpBase + 0, 858, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2753 = SWC2_MMR6 { 2752, 3, 0, 4, 455, 0, 0, MipsImpOpBase + 0, 855, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2752 = SWC2 { 2751, 3, 0, 4, 1292, 0, 0, MipsImpOpBase + 0, 900, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2751 = SWC1_MM { 2750, 3, 0, 4, 701, 0, 0, MipsImpOpBase + 0, 900, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2750 = SWC1 { 2749, 3, 0, 4, 1180, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2749 = SW64 { 2748, 3, 0, 2, 1157, 0, 0, MipsImpOpBase + 0, 1072, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2748 = SW16_MMR6 { 2747, 3, 0, 2, 1134, 0, 0, MipsImpOpBase + 0, 1072, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2747 = SW16_MM { 2746, 3, 0, 4, 454, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2746 = SW { 2745, 3, 0, 4, 1293, 0, 0, MipsImpOpBase + 0, 879, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #2745 = SUXC1_MM { 2744, 3, 0, 4, 703, 0, 0, MipsImpOpBase + 0, 879, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #2744 = SUXC164 { 2743, 3, 0, 4, 703, 0, 0, MipsImpOpBase + 0, 876, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #2743 = SUXC1 { 2742, 3, 1, 4, 769, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2742 = SUBu_MM { 2741, 3, 1, 4, 370, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2741 = SUBu { 2740, 3, 1, 4, 802, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2740 = SUB_MMR6 { 2739, 3, 1, 4, 770, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2739 = SUB_MM { 2738, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2738 = SUBV_W { 2737, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2737 = SUBV_H { 2736, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2736 = SUBV_D { 2735, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2735 = SUBV_B { 2734, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2734 = SUBVI_W { 2733, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2733 = SUBVI_H { 2732, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2732 = SUBVI_D { 2731, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2731 = SUBVI_B { 2730, 3, 1, 4, 1623, 0, 1, MipsImpOpBase + 10, 545, 0, 0x6ULL }, // Inst #2730 = SUBU_S_QB_MM { 2729, 3, 1, 4, 1457, 0, 1, MipsImpOpBase + 10, 545, 0, 0x6ULL }, // Inst #2729 = SUBU_S_QB { 2728, 3, 1, 4, 1668, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2728 = SUBU_S_PH_MMR2 { 2727, 3, 1, 4, 1504, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2727 = SUBU_S_PH { 2726, 3, 1, 4, 1622, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2726 = SUBU_QB_MM { 2725, 3, 1, 4, 1456, 0, 1, MipsImpOpBase + 10, 545, 0, 0x6ULL }, // Inst #2725 = SUBU_QB { 2724, 3, 1, 4, 1667, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2724 = SUBU_PH_MMR2 { 2723, 3, 1, 4, 1503, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2723 = SUBU_PH { 2722, 3, 1, 4, 801, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2722 = SUBU_MMR6 { 2721, 3, 1, 4, 1670, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2721 = SUBUH_R_QB_MMR2 { 2720, 3, 1, 4, 1506, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2720 = SUBUH_R_QB { 2719, 3, 1, 4, 1669, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2719 = SUBUH_QB_MMR2 { 2718, 3, 1, 4, 1505, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2718 = SUBUH_QB { 2717, 3, 1, 2, 801, 0, 0, MipsImpOpBase + 0, 554, 0, 0x0ULL }, // Inst #2717 = SUBU16_MMR6 { 2716, 3, 1, 2, 769, 0, 0, MipsImpOpBase + 0, 554, 0, 0x0ULL }, // Inst #2716 = SUBU16_MM { 2715, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2715 = SUBS_U_W { 2714, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2714 = SUBS_U_H { 2713, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2713 = SUBS_U_D { 2712, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2712 = SUBS_U_B { 2711, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2711 = SUBS_S_W { 2710, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2710 = SUBS_S_H { 2709, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2709 = SUBS_S_D { 2708, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2708 = SUBS_S_B { 2707, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2707 = SUBSUU_S_W { 2706, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2706 = SUBSUU_S_H { 2705, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2705 = SUBSUU_S_D { 2704, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2704 = SUBSUU_S_B { 2703, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2703 = SUBSUS_U_W { 2702, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2702 = SUBSUS_U_H { 2701, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2701 = SUBSUS_U_D { 2700, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2700 = SUBSUS_U_B { 2699, 3, 1, 4, 1621, 0, 1, MipsImpOpBase + 10, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2699 = SUBQ_S_W_MM { 2698, 3, 1, 4, 1455, 0, 1, MipsImpOpBase + 10, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2698 = SUBQ_S_W { 2697, 3, 1, 4, 1620, 0, 1, MipsImpOpBase + 10, 545, 0, 0x6ULL }, // Inst #2697 = SUBQ_S_PH_MM { 2696, 3, 1, 4, 1454, 0, 1, MipsImpOpBase + 10, 545, 0, 0x6ULL }, // Inst #2696 = SUBQ_S_PH { 2695, 3, 1, 4, 1619, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2695 = SUBQ_PH_MM { 2694, 3, 1, 4, 1453, 0, 1, MipsImpOpBase + 10, 545, 0, 0x6ULL }, // Inst #2694 = SUBQ_PH { 2693, 3, 1, 4, 1665, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2693 = SUBQH_W_MMR2 { 2692, 3, 1, 4, 1501, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2692 = SUBQH_W { 2691, 3, 1, 4, 1666, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2691 = SUBQH_R_W_MMR2 { 2690, 3, 1, 4, 1502, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2690 = SUBQH_R_W { 2689, 3, 1, 4, 1664, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2689 = SUBQH_R_PH_MMR2 { 2688, 3, 1, 4, 1500, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2688 = SUBQH_R_PH { 2687, 3, 1, 4, 1663, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2687 = SUBQH_PH_MMR2 { 2686, 3, 1, 4, 1499, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2686 = SUBQH_PH { 2685, 3, 1, 4, 369, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2685 = SUB { 2684, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 891, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2684 = ST_W { 2683, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 888, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2683 = ST_H { 2682, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 885, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2682 = ST_D { 2681, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 882, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2681 = ST_B { 2680, 0, 0, 4, 800, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2680 = SSNOP_MMR6 { 2679, 0, 0, 4, 768, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2679 = SSNOP_MM { 2678, 0, 0, 4, 372, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2678 = SSNOP { 2677, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2677 = SRL_W { 2676, 3, 1, 4, 766, 0, 0, MipsImpOpBase + 0, 241, 0, 0x1ULL }, // Inst #2676 = SRL_MM { 2675, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2675 = SRL_H { 2674, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2674 = SRL_D { 2673, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2673 = SRL_B { 2672, 3, 1, 4, 767, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2672 = SRLV_MM { 2671, 3, 1, 4, 512, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2671 = SRLV { 2670, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2670 = SRLR_W { 2669, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2669 = SRLR_H { 2668, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2668 = SRLR_D { 2667, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2667 = SRLR_B { 2666, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2666 = SRLRI_W { 2665, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2665 = SRLRI_H { 2664, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2664 = SRLRI_D { 2663, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2663 = SRLRI_B { 2662, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2662 = SRLI_W { 2661, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2661 = SRLI_H { 2660, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2660 = SRLI_D { 2659, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2659 = SRLI_B { 2658, 3, 1, 2, 799, 0, 0, MipsImpOpBase + 0, 539, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2658 = SRL16_MMR6 { 2657, 3, 1, 2, 766, 0, 0, MipsImpOpBase + 0, 539, 0, 0x0ULL }, // Inst #2657 = SRL16_MM { 2656, 3, 1, 4, 507, 0, 0, MipsImpOpBase + 0, 241, 0, 0x1ULL }, // Inst #2656 = SRL { 2655, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2655 = SRA_W { 2654, 3, 1, 4, 765, 0, 0, MipsImpOpBase + 0, 241, 0, 0x1ULL }, // Inst #2654 = SRA_MM { 2653, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2653 = SRA_H { 2652, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2652 = SRA_D { 2651, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2651 = SRA_B { 2650, 3, 1, 4, 764, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2650 = SRAV_MM { 2649, 3, 1, 4, 511, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2649 = SRAV { 2648, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2648 = SRAR_W { 2647, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2647 = SRAR_H { 2646, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2646 = SRAR_D { 2645, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2645 = SRAR_B { 2644, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2644 = SRARI_W { 2643, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2643 = SRARI_H { 2642, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2642 = SRARI_D { 2641, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2641 = SRARI_B { 2640, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2640 = SRAI_W { 2639, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2639 = SRAI_H { 2638, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2638 = SRAI_D { 2637, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2637 = SRAI_B { 2636, 3, 1, 4, 506, 0, 0, MipsImpOpBase + 0, 241, 0, 0x1ULL }, // Inst #2636 = SRA { 2635, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1135, 0, 0x6ULL }, // Inst #2635 = SPLAT_W { 2634, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1132, 0, 0x6ULL }, // Inst #2634 = SPLAT_H { 2633, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1129, 0, 0x6ULL }, // Inst #2633 = SPLAT_D { 2632, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1126, 0, 0x6ULL }, // Inst #2632 = SPLAT_B { 2631, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2631 = SPLATI_W { 2630, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2630 = SPLATI_H { 2629, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2629 = SPLATI_D { 2628, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2628 = SPLATI_B { 2627, 3, 1, 4, 1208, 0, 0, MipsImpOpBase + 0, 232, 0, 0x2ULL }, // Inst #2627 = SNEi { 2626, 3, 1, 4, 1207, 0, 0, MipsImpOpBase + 0, 235, 0, 0x1ULL }, // Inst #2626 = SNE { 2625, 3, 1, 4, 762, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2625 = SLTu_MM { 2624, 3, 1, 4, 813, 0, 0, MipsImpOpBase + 0, 1120, 0, 0x1ULL }, // Inst #2624 = SLTu64 { 2623, 3, 1, 4, 504, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2623 = SLTu { 2622, 3, 1, 4, 763, 0, 0, MipsImpOpBase + 0, 241, 0, 0x2ULL }, // Inst #2622 = SLTiu_MM { 2621, 3, 1, 4, 814, 0, 0, MipsImpOpBase + 0, 1123, 0, 0x2ULL }, // Inst #2621 = SLTiu64 { 2620, 3, 1, 4, 368, 0, 0, MipsImpOpBase + 0, 241, 0, 0x2ULL }, // Inst #2620 = SLTiu { 2619, 3, 1, 4, 763, 0, 0, MipsImpOpBase + 0, 241, 0, 0x2ULL }, // Inst #2619 = SLTi_MM { 2618, 3, 1, 4, 814, 0, 0, MipsImpOpBase + 0, 1123, 0, 0x2ULL }, // Inst #2618 = SLTi64 { 2617, 3, 1, 4, 368, 0, 0, MipsImpOpBase + 0, 241, 0, 0x2ULL }, // Inst #2617 = SLTi { 2616, 3, 1, 4, 762, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2616 = SLT_MM { 2615, 3, 1, 4, 813, 0, 0, MipsImpOpBase + 0, 1120, 0, 0x1ULL }, // Inst #2615 = SLT64 { 2614, 3, 1, 4, 504, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2614 = SLT { 2613, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2613 = SLL_W { 2612, 3, 1, 4, 798, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2612 = SLL_MMR6 { 2611, 3, 1, 4, 760, 0, 0, MipsImpOpBase + 0, 241, 0, 0x1ULL }, // Inst #2611 = SLL_MM { 2610, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2610 = SLL_H { 2609, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2609 = SLL_D { 2608, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2608 = SLL_B { 2607, 3, 1, 4, 761, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2607 = SLLV_MM { 2606, 3, 1, 4, 510, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2606 = SLLV { 2605, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2605 = SLLI_W { 2604, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2604 = SLLI_H { 2603, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2603 = SLLI_D { 2602, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2602 = SLLI_B { 2601, 2, 1, 4, 812, 0, 0, MipsImpOpBase + 0, 389, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2601 = SLL64_64 { 2600, 2, 1, 4, 812, 0, 0, MipsImpOpBase + 0, 758, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2600 = SLL64_32 { 2599, 3, 1, 2, 798, 0, 0, MipsImpOpBase + 0, 539, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2599 = SLL16_MMR6 { 2598, 3, 1, 2, 760, 0, 0, MipsImpOpBase + 0, 539, 0, 0x0ULL }, // Inst #2598 = SLL16_MM { 2597, 3, 1, 4, 505, 0, 0, MipsImpOpBase + 0, 241, 0, 0x1ULL }, // Inst #2597 = SLL { 2596, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1116, 0, 0x6ULL }, // Inst #2596 = SLD_W { 2595, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1112, 0, 0x6ULL }, // Inst #2595 = SLD_H { 2594, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1108, 0, 0x6ULL }, // Inst #2594 = SLD_D { 2593, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1104, 0, 0x6ULL }, // Inst #2593 = SLD_B { 2592, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 614, 0, 0x6ULL }, // Inst #2592 = SLDI_W { 2591, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 610, 0, 0x6ULL }, // Inst #2591 = SLDI_H { 2590, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 606, 0, 0x6ULL }, // Inst #2590 = SLDI_D { 2589, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #2589 = SLDI_B { 2588, 1, 0, 4, 997, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2588 = SIGRIE_MMR6 { 2587, 1, 0, 4, 936, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2587 = SIGRIE { 2586, 3, 0, 4, 1156, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2586 = SH_MMR6 { 2585, 3, 0, 4, 1133, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2585 = SH_MM { 2584, 3, 1, 4, 1618, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2584 = SHRL_QB_MM { 2583, 3, 1, 4, 1452, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2583 = SHRL_QB { 2582, 3, 1, 4, 1661, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2582 = SHRL_PH_MMR2 { 2581, 3, 1, 4, 1497, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2581 = SHRL_PH { 2580, 3, 1, 4, 1617, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2580 = SHRLV_QB_MM { 2579, 3, 1, 4, 1451, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2579 = SHRLV_QB { 2578, 3, 1, 4, 1662, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2578 = SHRLV_PH_MMR2 { 2577, 3, 1, 4, 1498, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2577 = SHRLV_PH { 2576, 3, 1, 4, 1616, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2576 = SHRA_R_W_MM { 2575, 3, 1, 4, 1450, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2575 = SHRA_R_W { 2574, 3, 1, 4, 1658, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2574 = SHRA_R_QB_MMR2 { 2573, 3, 1, 4, 1494, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2573 = SHRA_R_QB { 2572, 3, 1, 4, 1615, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2572 = SHRA_R_PH_MM { 2571, 3, 1, 4, 1449, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2571 = SHRA_R_PH { 2570, 3, 1, 4, 1657, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2570 = SHRA_QB_MMR2 { 2569, 3, 1, 4, 1493, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2569 = SHRA_QB { 2568, 3, 1, 4, 1614, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2568 = SHRA_PH_MM { 2567, 3, 1, 4, 1448, 0, 0, MipsImpOpBase + 0, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2567 = SHRA_PH { 2566, 3, 1, 4, 1613, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2566 = SHRAV_R_W_MM { 2565, 3, 1, 4, 1447, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2565 = SHRAV_R_W { 2564, 3, 1, 4, 1660, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2564 = SHRAV_R_QB_MMR2 { 2563, 3, 1, 4, 1496, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2563 = SHRAV_R_QB { 2562, 3, 1, 4, 1612, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2562 = SHRAV_R_PH_MM { 2561, 3, 1, 4, 1446, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2561 = SHRAV_R_PH { 2560, 3, 1, 4, 1659, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2560 = SHRAV_QB_MMR2 { 2559, 3, 1, 4, 1495, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2559 = SHRAV_QB { 2558, 3, 1, 4, 1611, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2558 = SHRAV_PH_MM { 2557, 3, 1, 4, 1445, 0, 0, MipsImpOpBase + 0, 1098, 0, 0x6ULL }, // Inst #2557 = SHRAV_PH { 2556, 3, 1, 4, 1610, 0, 1, MipsImpOpBase + 58, 241, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2556 = SHLL_S_W_MM { 2555, 3, 1, 4, 1444, 0, 1, MipsImpOpBase + 58, 241, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2555 = SHLL_S_W { 2554, 3, 1, 4, 1609, 0, 1, MipsImpOpBase + 58, 1101, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2554 = SHLL_S_PH_MM { 2553, 3, 1, 4, 1443, 0, 1, MipsImpOpBase + 58, 1101, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2553 = SHLL_S_PH { 2552, 3, 1, 4, 1608, 0, 1, MipsImpOpBase + 58, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2552 = SHLL_QB_MM { 2551, 3, 1, 4, 1442, 0, 1, MipsImpOpBase + 58, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2551 = SHLL_QB { 2550, 3, 1, 4, 1607, 0, 1, MipsImpOpBase + 58, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2550 = SHLL_PH_MM { 2549, 3, 1, 4, 1441, 0, 1, MipsImpOpBase + 58, 1101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2549 = SHLL_PH { 2548, 3, 1, 4, 1606, 0, 1, MipsImpOpBase + 58, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2548 = SHLLV_S_W_MM { 2547, 3, 1, 4, 1440, 0, 1, MipsImpOpBase + 58, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2547 = SHLLV_S_W { 2546, 3, 1, 4, 1605, 0, 1, MipsImpOpBase + 58, 1098, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2546 = SHLLV_S_PH_MM { 2545, 3, 1, 4, 1439, 0, 1, MipsImpOpBase + 58, 1098, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2545 = SHLLV_S_PH { 2544, 3, 1, 4, 1604, 0, 1, MipsImpOpBase + 58, 1098, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2544 = SHLLV_QB_MM { 2543, 3, 1, 4, 1438, 0, 1, MipsImpOpBase + 58, 1098, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2543 = SHLLV_QB { 2542, 3, 1, 4, 1603, 0, 1, MipsImpOpBase + 58, 1098, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2542 = SHLLV_PH_MM { 2541, 3, 1, 4, 1437, 0, 1, MipsImpOpBase + 58, 1098, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2541 = SHLLV_PH { 2540, 3, 1, 4, 1602, 0, 0, MipsImpOpBase + 0, 1095, 0, 0x6ULL }, // Inst #2540 = SHILO_MM { 2539, 3, 1, 4, 1601, 0, 0, MipsImpOpBase + 0, 1037, 0, 0x6ULL }, // Inst #2539 = SHILOV_MM { 2538, 3, 1, 4, 1435, 0, 0, MipsImpOpBase + 0, 1037, 0, 0x6ULL }, // Inst #2538 = SHILOV { 2537, 3, 1, 4, 1436, 0, 0, MipsImpOpBase + 0, 1095, 0, 0x6ULL }, // Inst #2537 = SHILO { 2536, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2536 = SHF_W { 2535, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2535 = SHF_H { 2534, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2534 = SHF_B { 2533, 3, 0, 4, 1102, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2533 = SHE_MM { 2532, 3, 0, 4, 461, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2532 = SHE { 2531, 3, 0, 4, 1179, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2531 = SH64 { 2530, 3, 0, 2, 1156, 0, 0, MipsImpOpBase + 0, 1072, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2530 = SH16_MMR6 { 2529, 3, 0, 2, 1133, 0, 0, MipsImpOpBase + 0, 1072, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2529 = SH16_MM { 2528, 3, 0, 4, 453, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2528 = SH { 2527, 3, 1, 4, 1208, 0, 0, MipsImpOpBase + 0, 232, 0, 0x2ULL }, // Inst #2527 = SEQi { 2526, 3, 1, 4, 1207, 0, 0, MipsImpOpBase + 0, 235, 0, 0x1ULL }, // Inst #2526 = SEQ { 2525, 4, 1, 4, 1328, 0, 0, MipsImpOpBase + 0, 1091, 0, 0x6ULL }, // Inst #2525 = SEL_S_MMR6 { 2524, 4, 1, 4, 1234, 0, 0, MipsImpOpBase + 0, 1091, 0, 0x6ULL }, // Inst #2524 = SEL_S { 2523, 4, 1, 4, 1327, 0, 0, MipsImpOpBase + 0, 932, 0, 0x6ULL }, // Inst #2523 = SEL_D_MMR6 { 2522, 4, 1, 4, 1233, 0, 0, MipsImpOpBase + 0, 932, 0, 0x6ULL }, // Inst #2522 = SEL_D { 2521, 3, 1, 4, 1326, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2521 = SELNEZ_S_MMR6 { 2520, 3, 1, 4, 1222, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2520 = SELNEZ_S { 2519, 3, 1, 4, 797, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2519 = SELNEZ_MMR6 { 2518, 3, 1, 4, 1325, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2518 = SELNEZ_D_MMR6 { 2517, 3, 1, 4, 1223, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2517 = SELNEZ_D { 2516, 3, 1, 4, 852, 0, 0, MipsImpOpBase + 0, 235, 0, 0x6ULL }, // Inst #2516 = SELNEZ64 { 2515, 3, 1, 4, 734, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2515 = SELNEZ { 2514, 3, 1, 4, 1326, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2514 = SELEQZ_S_MMR6 { 2513, 3, 1, 4, 1222, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2513 = SELEQZ_S { 2512, 3, 1, 4, 797, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2512 = SELEQZ_MMR6 { 2511, 3, 1, 4, 1325, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2511 = SELEQZ_D_MMR6 { 2510, 3, 1, 4, 1223, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2510 = SELEQZ_D { 2509, 3, 1, 4, 852, 0, 0, MipsImpOpBase + 0, 235, 0, 0x6ULL }, // Inst #2509 = SELEQZ64 { 2508, 3, 1, 4, 734, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2508 = SELEQZ { 2507, 2, 1, 4, 759, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #2507 = SEH_MM { 2506, 2, 1, 4, 811, 0, 0, MipsImpOpBase + 0, 389, 0, 0x1ULL }, // Inst #2506 = SEH64 { 2505, 2, 1, 4, 503, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #2505 = SEH { 2504, 2, 1, 4, 758, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #2504 = SEB_MM { 2503, 2, 1, 4, 810, 0, 0, MipsImpOpBase + 0, 389, 0, 0x1ULL }, // Inst #2503 = SEB64 { 2502, 2, 1, 4, 502, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #2502 = SEB { 2501, 3, 0, 4, 700, 0, 0, MipsImpOpBase + 0, 879, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2501 = SDXC164 { 2500, 3, 0, 4, 700, 0, 0, MipsImpOpBase + 0, 876, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2500 = SDXC1 { 2499, 3, 0, 4, 1184, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2499 = SDR { 2498, 3, 0, 4, 1183, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2498 = SDL { 2497, 2, 0, 4, 885, 0, 2, MipsImpOpBase + 7, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2497 = SDIV_MM { 2496, 2, 0, 4, 865, 0, 2, MipsImpOpBase + 7, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2496 = SDIV { 2495, 3, 0, 4, 458, 0, 0, MipsImpOpBase + 0, 861, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2495 = SDC3 { 2494, 3, 0, 4, 1086, 0, 0, MipsImpOpBase + 0, 855, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2494 = SDC2_R6 { 2493, 3, 0, 4, 1155, 0, 0, MipsImpOpBase + 0, 858, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2493 = SDC2_MMR6 { 2492, 3, 0, 4, 457, 0, 0, MipsImpOpBase + 0, 855, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2492 = SDC2 { 2491, 3, 0, 4, 1291, 0, 0, MipsImpOpBase + 0, 852, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2491 = SDC1_MM_D64 { 2490, 3, 0, 4, 1291, 0, 0, MipsImpOpBase + 0, 504, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2490 = SDC1_MM_D32 { 2489, 3, 0, 4, 1339, 0, 0, MipsImpOpBase + 0, 852, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2489 = SDC1_D64_MMR6 { 2488, 3, 0, 4, 699, 0, 0, MipsImpOpBase + 0, 852, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2488 = SDC164 { 2487, 3, 0, 4, 699, 0, 0, MipsImpOpBase + 0, 504, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2487 = SDC1 { 2486, 1, 0, 4, 939, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2486 = SDBBP_R6 { 2485, 1, 0, 4, 1009, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2485 = SDBBP_MMR6 { 2484, 1, 0, 4, 968, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2484 = SDBBP_MM { 2483, 1, 0, 2, 1009, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2483 = SDBBP16_MMR6 { 2482, 1, 0, 2, 968, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2482 = SDBBP16_MM { 2481, 1, 0, 4, 389, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2481 = SDBBP { 2480, 3, 0, 4, 1176, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2480 = SD { 2479, 4, 1, 4, 1087, 0, 0, MipsImpOpBase + 0, 1079, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2479 = SC_R6 { 2478, 4, 1, 4, 1081, 0, 0, MipsImpOpBase + 0, 1075, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2478 = SC_MMR6 { 2477, 4, 1, 4, 1132, 0, 0, MipsImpOpBase + 0, 1075, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2477 = SC_MM { 2476, 4, 1, 4, 1106, 0, 0, MipsImpOpBase + 0, 1075, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2476 = SCE_MM { 2475, 4, 1, 4, 463, 0, 0, MipsImpOpBase + 0, 1075, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2475 = SCE { 2474, 4, 1, 4, 1190, 0, 0, MipsImpOpBase + 0, 1087, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2474 = SCD_R6 { 2473, 4, 1, 4, 1177, 0, 0, MipsImpOpBase + 0, 1083, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2473 = SCD { 2472, 4, 1, 4, 1189, 0, 0, MipsImpOpBase + 0, 1079, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2472 = SC64_R6 { 2471, 4, 1, 4, 1177, 0, 0, MipsImpOpBase + 0, 1075, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2471 = SC64 { 2470, 4, 1, 4, 459, 0, 0, MipsImpOpBase + 0, 1075, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2470 = SC { 2469, 3, 0, 4, 1154, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2469 = SB_MMR6 { 2468, 3, 0, 4, 1101, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2468 = SB_MM { 2467, 3, 0, 4, 1100, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2467 = SBE_MM { 2466, 3, 0, 4, 460, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2466 = SBE { 2465, 3, 0, 4, 1178, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2465 = SB64 { 2464, 3, 0, 2, 1154, 0, 0, MipsImpOpBase + 0, 1072, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2464 = SB16_MMR6 { 2463, 3, 0, 2, 1131, 0, 0, MipsImpOpBase + 0, 1072, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2463 = SB16_MM { 2462, 3, 0, 4, 452, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2462 = SB { 2461, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2461 = SAT_U_W { 2460, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2460 = SAT_U_H { 2459, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2459 = SAT_U_D { 2458, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2458 = SAT_U_B { 2457, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2457 = SAT_S_W { 2456, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2456 = SAT_S_H { 2455, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2455 = SAT_S_D { 2454, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2454 = SAT_S_B { 2453, 2, 0, 4, 1211, 0, 0, MipsImpOpBase + 0, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2453 = SAAD { 2452, 2, 0, 4, 1211, 0, 0, MipsImpOpBase + 0, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2452 = SAA { 2451, 0, 0, 2, 1109, 1, 1, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2451 = RestoreX16 { 2450, 0, 0, 2, 1109, 1, 1, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2450 = Restore16 { 2449, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #2449 = RSQRT_S_MM { 2448, 2, 1, 4, 655, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #2448 = RSQRT_S { 2447, 2, 1, 4, 1290, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #2447 = RSQRT_D64_MM { 2446, 2, 1, 4, 653, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #2446 = RSQRT_D64 { 2445, 2, 1, 4, 1290, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #2445 = RSQRT_D32_MM { 2444, 2, 1, 4, 653, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #2444 = RSQRT_D32 { 2443, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #2443 = ROUND_W_S_MMR6 { 2442, 2, 1, 4, 1256, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #2442 = ROUND_W_S_MM { 2441, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #2441 = ROUND_W_S { 2440, 2, 1, 4, 1256, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #2440 = ROUND_W_MM { 2439, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #2439 = ROUND_W_D_MMR6 { 2438, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #2438 = ROUND_W_D64 { 2437, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #2437 = ROUND_W_D32 { 2436, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #2436 = ROUND_L_S_MMR6 { 2435, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #2435 = ROUND_L_S { 2434, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #2434 = ROUND_L_D_MMR6 { 2433, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #2433 = ROUND_L_D64 { 2432, 3, 1, 4, 757, 0, 0, MipsImpOpBase + 0, 241, 0, 0x1ULL }, // Inst #2432 = ROTR_MM { 2431, 3, 1, 4, 756, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2431 = ROTRV_MM { 2430, 3, 1, 4, 720, 0, 0, MipsImpOpBase + 0, 238, 0, 0x1ULL }, // Inst #2430 = ROTRV { 2429, 3, 1, 4, 501, 0, 0, MipsImpOpBase + 0, 241, 0, 0x1ULL }, // Inst #2429 = ROTR { 2428, 2, 1, 4, 1329, 0, 0, MipsImpOpBase + 0, 643, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2428 = RINT_S_MMR6 { 2427, 2, 1, 4, 1230, 0, 0, MipsImpOpBase + 0, 643, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2427 = RINT_S { 2426, 2, 1, 4, 1329, 0, 0, MipsImpOpBase + 0, 635, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2426 = RINT_D_MMR6 { 2425, 2, 1, 4, 1231, 0, 0, MipsImpOpBase + 0, 635, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2425 = RINT_D { 2424, 2, 1, 4, 1600, 0, 0, MipsImpOpBase + 0, 1070, 0, 0x6ULL }, // Inst #2424 = REPL_QB_MM { 2423, 2, 1, 4, 1434, 0, 0, MipsImpOpBase + 0, 1070, 0, 0x6ULL }, // Inst #2423 = REPL_QB { 2422, 2, 1, 4, 1599, 0, 0, MipsImpOpBase + 0, 1070, 0, 0x6ULL }, // Inst #2422 = REPL_PH_MM { 2421, 2, 1, 4, 1433, 0, 0, MipsImpOpBase + 0, 1070, 0, 0x6ULL }, // Inst #2421 = REPL_PH { 2420, 2, 1, 4, 1598, 0, 0, MipsImpOpBase + 0, 1068, 0, 0x6ULL }, // Inst #2420 = REPLV_QB_MM { 2419, 2, 1, 4, 1432, 0, 0, MipsImpOpBase + 0, 1068, 0, 0x6ULL }, // Inst #2419 = REPLV_QB { 2418, 2, 1, 4, 1597, 0, 0, MipsImpOpBase + 0, 1068, 0, 0x6ULL }, // Inst #2418 = REPLV_PH_MM { 2417, 2, 1, 4, 1431, 0, 0, MipsImpOpBase + 0, 1068, 0, 0x6ULL }, // Inst #2417 = REPLV_PH { 2416, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #2416 = RECIP_S_MM { 2415, 2, 1, 4, 654, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #2415 = RECIP_S { 2414, 2, 1, 4, 1290, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #2414 = RECIP_D64_MM { 2413, 2, 1, 4, 652, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #2413 = RECIP_D64 { 2412, 2, 1, 4, 1290, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #2412 = RECIP_D32_MM { 2411, 2, 1, 4, 652, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #2411 = RECIP_D32 { 2410, 2, 1, 4, 1037, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2410 = RDPGPR_MMR6 { 2409, 3, 1, 4, 900, 0, 0, MipsImpOpBase + 0, 1062, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2409 = RDHWR_MMR6 { 2408, 3, 1, 4, 891, 0, 0, MipsImpOpBase + 0, 1062, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2408 = RDHWR_MM { 2407, 3, 1, 4, 909, 0, 0, MipsImpOpBase + 0, 1065, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2407 = RDHWR64 { 2406, 3, 1, 4, 480, 0, 0, MipsImpOpBase + 0, 1062, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2406 = RDHWR { 2405, 2, 1, 4, 1596, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2405 = RDDSP_MM { 2404, 2, 1, 4, 1430, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2404 = RDDSP { 2403, 2, 1, 4, 1595, 0, 0, MipsImpOpBase + 0, 1050, 0, 0x6ULL }, // Inst #2403 = RADDU_W_QB_MM { 2402, 2, 1, 4, 1429, 0, 0, MipsImpOpBase + 0, 1050, 0, 0x6ULL }, // Inst #2402 = RADDU_W_QB { 2401, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2401 = PUU_PS64 { 2400, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2400 = PUL_PS64 { 2399, 4, 1, 4, 1656, 0, 0, MipsImpOpBase + 0, 576, 0, 0x6ULL }, // Inst #2399 = PREPEND_MMR2 { 2398, 4, 1, 4, 1492, 0, 0, MipsImpOpBase + 0, 576, 0, 0x6ULL }, // Inst #2398 = PREPEND { 2397, 3, 0, 4, 1088, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2397 = PREF_R6 { 2396, 3, 0, 4, 1162, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2396 = PREF_MMR6 { 2395, 3, 0, 4, 1140, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2395 = PREF_MM { 2394, 3, 0, 4, 1140, 0, 0, MipsImpOpBase + 0, 1059, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2394 = PREFX_MM { 2393, 3, 0, 4, 1107, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2393 = PREFE_MM { 2392, 3, 0, 4, 469, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2392 = PREFE { 2391, 3, 0, 4, 468, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2391 = PREF { 2390, 4, 1, 4, 1655, 0, 0, MipsImpOpBase + 0, 1055, 0, 0x6ULL }, // Inst #2390 = PRECR_SRA_R_PH_W_MMR2 { 2389, 4, 1, 4, 1491, 0, 0, MipsImpOpBase + 0, 1055, 0, 0x6ULL }, // Inst #2389 = PRECR_SRA_R_PH_W { 2388, 4, 1, 4, 1654, 0, 0, MipsImpOpBase + 0, 1055, 0, 0x6ULL }, // Inst #2388 = PRECR_SRA_PH_W_MMR2 { 2387, 4, 1, 4, 1490, 0, 0, MipsImpOpBase + 0, 1055, 0, 0x6ULL }, // Inst #2387 = PRECR_SRA_PH_W { 2386, 3, 1, 4, 1653, 0, 0, MipsImpOpBase + 0, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2386 = PRECR_QB_PH_MMR2 { 2385, 3, 1, 4, 1489, 0, 0, MipsImpOpBase + 0, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2385 = PRECR_QB_PH { 2384, 3, 1, 4, 1594, 0, 1, MipsImpOpBase + 58, 1052, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2384 = PRECRQ_RS_PH_W_MM { 2383, 3, 1, 4, 1428, 0, 1, MipsImpOpBase + 58, 1052, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2383 = PRECRQ_RS_PH_W { 2382, 3, 1, 4, 1593, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2382 = PRECRQ_QB_PH_MM { 2381, 3, 1, 4, 1427, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2381 = PRECRQ_QB_PH { 2380, 3, 1, 4, 1592, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2380 = PRECRQ_PH_W_MM { 2379, 3, 1, 4, 1426, 0, 0, MipsImpOpBase + 0, 1052, 0, 0x6ULL }, // Inst #2379 = PRECRQ_PH_W { 2378, 3, 1, 4, 1591, 0, 1, MipsImpOpBase + 58, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2378 = PRECRQU_S_QB_PH_MM { 2377, 3, 1, 4, 1425, 0, 1, MipsImpOpBase + 58, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2377 = PRECRQU_S_QB_PH { 2376, 2, 1, 4, 1590, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2376 = PRECEU_PH_QBR_MM { 2375, 2, 1, 4, 1589, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2375 = PRECEU_PH_QBRA_MM { 2374, 2, 1, 4, 1423, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2374 = PRECEU_PH_QBRA { 2373, 2, 1, 4, 1424, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2373 = PRECEU_PH_QBR { 2372, 2, 1, 4, 1588, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2372 = PRECEU_PH_QBL_MM { 2371, 2, 1, 4, 1587, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2371 = PRECEU_PH_QBLA_MM { 2370, 2, 1, 4, 1421, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2370 = PRECEU_PH_QBLA { 2369, 2, 1, 4, 1422, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2369 = PRECEU_PH_QBL { 2368, 2, 1, 4, 1586, 0, 0, MipsImpOpBase + 0, 1050, 0, 0x6ULL }, // Inst #2368 = PRECEQ_W_PHR_MM { 2367, 2, 1, 4, 1420, 0, 0, MipsImpOpBase + 0, 1050, 0, 0x6ULL }, // Inst #2367 = PRECEQ_W_PHR { 2366, 2, 1, 4, 1585, 0, 0, MipsImpOpBase + 0, 1050, 0, 0x6ULL }, // Inst #2366 = PRECEQ_W_PHL_MM { 2365, 2, 1, 4, 1419, 0, 0, MipsImpOpBase + 0, 1050, 0, 0x6ULL }, // Inst #2365 = PRECEQ_W_PHL { 2364, 2, 1, 4, 1584, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2364 = PRECEQU_PH_QBR_MM { 2363, 2, 1, 4, 1583, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2363 = PRECEQU_PH_QBRA_MM { 2362, 2, 1, 4, 1417, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2362 = PRECEQU_PH_QBRA { 2361, 2, 1, 4, 1418, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2361 = PRECEQU_PH_QBR { 2360, 2, 1, 4, 1582, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2360 = PRECEQU_PH_QBL_MM { 2359, 2, 1, 4, 1581, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2359 = PRECEQU_PH_QBLA_MM { 2358, 2, 1, 4, 1415, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2358 = PRECEQU_PH_QBLA { 2357, 2, 1, 4, 1416, 0, 0, MipsImpOpBase + 0, 535, 0, 0x6ULL }, // Inst #2357 = PRECEQU_PH_QBL { 2356, 2, 1, 4, 1204, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #2356 = POP { 2355, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2355 = PLU_PS64 { 2354, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2354 = PLL_PS64 { 2353, 3, 1, 4, 1580, 1, 0, MipsImpOpBase + 14, 545, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2353 = PICK_QB_MM { 2352, 3, 1, 4, 1414, 1, 0, MipsImpOpBase + 14, 545, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2352 = PICK_QB { 2351, 3, 1, 4, 1579, 1, 0, MipsImpOpBase + 14, 545, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2351 = PICK_PH_MM { 2350, 3, 1, 4, 1413, 1, 0, MipsImpOpBase + 14, 545, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2350 = PICK_PH { 2349, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #2349 = PCNT_W { 2348, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 1046, 0, 0x6ULL }, // Inst #2348 = PCNT_H { 2347, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #2347 = PCNT_D { 2346, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 968, 0, 0x6ULL }, // Inst #2346 = PCNT_B { 2345, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2345 = PCKOD_W { 2344, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2344 = PCKOD_H { 2343, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2343 = PCKOD_D { 2342, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2342 = PCKOD_B { 2341, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2341 = PCKEV_W { 2340, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2340 = PCKEV_H { 2339, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2339 = PCKEV_D { 2338, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2338 = PCKEV_B { 2337, 0, 0, 4, 1052, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2337 = PAUSE_MMR6 { 2336, 0, 0, 4, 1035, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2336 = PAUSE_MM { 2335, 0, 0, 4, 405, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2335 = PAUSE { 2334, 3, 1, 4, 1578, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2334 = PACKRL_PH_MM { 2333, 3, 1, 4, 1412, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2333 = PACKRL_PH { 2332, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 588, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #2332 = OrRxRxRy16 { 2331, 3, 1, 4, 755, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2331 = ORi_MM { 2330, 3, 1, 4, 809, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2330 = ORi64 { 2329, 3, 1, 4, 500, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2329 = ORi { 2328, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2328 = OR_V { 2327, 3, 1, 4, 795, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2327 = OR_MMR6 { 2326, 3, 1, 4, 754, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2326 = OR_MM { 2325, 3, 1, 4, 796, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2325 = ORI_MMR6 { 2324, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2324 = ORI_B { 2323, 3, 1, 4, 843, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2323 = OR64 { 2322, 3, 1, 2, 795, 0, 0, MipsImpOpBase + 0, 573, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2322 = OR16_MMR6 { 2321, 3, 1, 2, 754, 0, 0, MipsImpOpBase + 0, 573, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2321 = OR16_MM { 2320, 3, 1, 4, 367, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2320 = OR { 2319, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 406, 0, 0x0ULL }, // Inst #2319 = NotRxRy16 { 2318, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 406, 0, 0x0ULL }, // Inst #2318 = NegRxRy16 { 2317, 2, 1, 2, 794, 0, 0, MipsImpOpBase + 0, 1048, 0, 0x0ULL }, // Inst #2317 = NOT16_MMR6 { 2316, 2, 1, 2, 753, 0, 0, MipsImpOpBase + 0, 1048, 0, 0x0ULL }, // Inst #2316 = NOT16_MM { 2315, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2315 = NOR_V { 2314, 3, 1, 4, 793, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2314 = NOR_MMR6 { 2313, 3, 1, 4, 752, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2313 = NOR_MM { 2312, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2312 = NORI_B { 2311, 3, 1, 4, 842, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2311 = NOR64 { 2310, 3, 1, 4, 366, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2310 = NOR { 2309, 4, 1, 4, 1252, 0, 0, MipsImpOpBase + 0, 948, 0, 0x4ULL }, // Inst #2309 = NMSUB_S_MM { 2308, 4, 1, 4, 684, 0, 0, MipsImpOpBase + 0, 948, 0, 0x4ULL }, // Inst #2308 = NMSUB_S { 2307, 4, 1, 4, 683, 0, 0, MipsImpOpBase + 0, 944, 0, 0x4ULL }, // Inst #2307 = NMSUB_D64 { 2306, 4, 1, 4, 1253, 0, 0, MipsImpOpBase + 0, 940, 0, 0x4ULL }, // Inst #2306 = NMSUB_D32_MM { 2305, 4, 1, 4, 683, 0, 0, MipsImpOpBase + 0, 940, 0, 0x4ULL }, // Inst #2305 = NMSUB_D32 { 2304, 4, 1, 4, 1250, 0, 0, MipsImpOpBase + 0, 948, 0, 0x4ULL }, // Inst #2304 = NMADD_S_MM { 2303, 4, 1, 4, 682, 0, 0, MipsImpOpBase + 0, 948, 0, 0x4ULL }, // Inst #2303 = NMADD_S { 2302, 4, 1, 4, 681, 0, 0, MipsImpOpBase + 0, 944, 0, 0x4ULL }, // Inst #2302 = NMADD_D64 { 2301, 4, 1, 4, 1251, 0, 0, MipsImpOpBase + 0, 940, 0, 0x4ULL }, // Inst #2301 = NMADD_D32_MM { 2300, 4, 1, 4, 681, 0, 0, MipsImpOpBase + 0, 940, 0, 0x4ULL }, // Inst #2300 = NMADD_D32 { 2299, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #2299 = NLZC_W { 2298, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 1046, 0, 0x6ULL }, // Inst #2298 = NLZC_H { 2297, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #2297 = NLZC_D { 2296, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 968, 0, 0x6ULL }, // Inst #2296 = NLZC_B { 2295, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #2295 = NLOC_W { 2294, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 1046, 0, 0x6ULL }, // Inst #2294 = NLOC_H { 2293, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #2293 = NLOC_D { 2292, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 968, 0, 0x6ULL }, // Inst #2292 = NLOC_B { 2291, 0, 0, 4, 925, 0, 1, MipsImpOpBase + 3, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2291 = NAL { 2290, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1044, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2290 = MoveR3216 { 2289, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1042, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2289 = Move32R16 { 2288, 1, 1, 2, 735, 1, 0, MipsImpOpBase + 40, 845, 0, 0x0ULL }, // Inst #2288 = Mflo16 { 2287, 1, 1, 2, 735, 1, 0, MipsImpOpBase + 38, 845, 0|(1ULL<<MCID::MoveReg), 0x0ULL }, // Inst #2287 = Mfhi16 { 2286, 3, 1, 4, 1648, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2286 = MUL_S_PH_MMR2 { 2285, 3, 1, 4, 1484, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2285 = MUL_S_PH { 2284, 3, 1, 4, 872, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2284 = MUL_R6 { 2283, 3, 1, 4, 676, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2283 = MUL_Q_W { 2282, 3, 1, 4, 676, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2282 = MUL_Q_H { 2281, 3, 1, 4, 1647, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2281 = MUL_PH_MMR2 { 2280, 3, 1, 4, 1483, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2280 = MUL_PH { 2279, 3, 1, 4, 895, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2279 = MUL_MMR6 { 2278, 3, 1, 4, 884, 0, 2, MipsImpOpBase + 7, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2278 = MUL_MM { 2277, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2277 = MULV_W { 2276, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2276 = MULV_H { 2275, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2275 = MULV_D { 2274, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2274 = MULV_B { 2273, 3, 1, 4, 894, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2273 = MULU_MMR6 { 2272, 3, 1, 4, 871, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2272 = MULU { 2271, 2, 0, 4, 879, 0, 2, MipsImpOpBase + 7, 152, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2271 = MULTu_MM { 2270, 2, 0, 4, 488, 0, 2, MipsImpOpBase + 7, 152, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2270 = MULTu { 2269, 2, 0, 4, 878, 0, 2, MipsImpOpBase + 7, 152, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2269 = MULT_MM { 2268, 3, 1, 4, 1577, 0, 0, MipsImpOpBase + 0, 448, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #2268 = MULT_DSP_MM { 2267, 3, 1, 4, 1411, 0, 0, MipsImpOpBase + 0, 448, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #2267 = MULT_DSP { 2266, 3, 1, 4, 1576, 0, 0, MipsImpOpBase + 0, 448, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #2266 = MULTU_DSP_MM { 2265, 3, 1, 4, 1410, 0, 0, MipsImpOpBase + 0, 448, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #2265 = MULTU_DSP { 2264, 2, 0, 4, 487, 0, 2, MipsImpOpBase + 7, 152, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2264 = MULT { 2263, 4, 1, 4, 1652, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #2263 = MULSA_W_PH_MMR2 { 2262, 4, 1, 4, 1488, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #2262 = MULSA_W_PH { 2261, 4, 1, 4, 1575, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2261 = MULSAQ_S_W_PH_MM { 2260, 4, 1, 4, 1409, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2260 = MULSAQ_S_W_PH { 2259, 3, 1, 4, 675, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2259 = MULR_Q_W { 2258, 3, 1, 4, 675, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2258 = MULR_Q_H { 2257, 3, 1, 4, 1214, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2257 = MULR_PS64 { 2256, 3, 1, 4, 1651, 0, 1, MipsImpOpBase + 57, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2256 = MULQ_S_W_MMR2 { 2255, 3, 1, 4, 1487, 0, 1, MipsImpOpBase + 57, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2255 = MULQ_S_W { 2254, 3, 1, 4, 1650, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2254 = MULQ_S_PH_MMR2 { 2253, 3, 1, 4, 1486, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2253 = MULQ_S_PH { 2252, 3, 1, 4, 1649, 0, 1, MipsImpOpBase + 57, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2252 = MULQ_RS_W_MMR2 { 2251, 3, 1, 4, 1485, 0, 1, MipsImpOpBase + 57, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2251 = MULQ_RS_W { 2250, 3, 1, 4, 1574, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2250 = MULQ_RS_PH_MM { 2249, 3, 1, 4, 1408, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2249 = MULQ_RS_PH { 2248, 3, 1, 4, 1573, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2248 = MULEU_S_PH_QBR_MM { 2247, 3, 1, 4, 1407, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2247 = MULEU_S_PH_QBR { 2246, 3, 1, 4, 1572, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2246 = MULEU_S_PH_QBL_MM { 2245, 3, 1, 4, 1406, 0, 1, MipsImpOpBase + 57, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2245 = MULEU_S_PH_QBL { 2244, 3, 1, 4, 1571, 0, 1, MipsImpOpBase + 57, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2244 = MULEQ_S_W_PHR_MM { 2243, 3, 1, 4, 1405, 0, 1, MipsImpOpBase + 57, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2243 = MULEQ_S_W_PHR { 2242, 3, 1, 4, 1570, 0, 1, MipsImpOpBase + 57, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2242 = MULEQ_S_W_PHL_MM { 2241, 3, 1, 4, 1404, 0, 1, MipsImpOpBase + 57, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2241 = MULEQ_S_W_PHL { 2240, 3, 1, 4, 486, 0, 2, MipsImpOpBase + 7, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2240 = MUL { 2239, 3, 1, 4, 893, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2239 = MUH_MMR6 { 2238, 3, 1, 4, 892, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2238 = MUHU_MMR6 { 2237, 3, 1, 4, 870, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2237 = MUHU { 2236, 3, 1, 4, 869, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2236 = MUH { 2235, 5, 1, 4, 1065, 0, 0, MipsImpOpBase + 0, 959, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2235 = MTTR { 2234, 1, 0, 4, 1206, 0, 1, MipsImpOpBase + 56, 318, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2234 = MTP2 { 2233, 1, 0, 4, 1206, 0, 1, MipsImpOpBase + 55, 318, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2233 = MTP1 { 2232, 1, 0, 4, 1206, 0, 1, MipsImpOpBase + 54, 318, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2232 = MTP0 { 2231, 1, 0, 4, 1206, 0, 4, MipsImpOpBase + 50, 318, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2231 = MTM2 { 2230, 1, 0, 4, 1206, 0, 4, MipsImpOpBase + 46, 318, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2230 = MTM1 { 2229, 1, 0, 4, 1206, 0, 4, MipsImpOpBase + 42, 318, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2229 = MTM0 { 2228, 1, 0, 4, 890, 0, 1, MipsImpOpBase + 40, 197, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2228 = MTLO_MM { 2227, 2, 1, 4, 1569, 0, 0, MipsImpOpBase + 0, 1040, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2227 = MTLO_DSP_MM { 2226, 2, 1, 4, 1357, 0, 0, MipsImpOpBase + 0, 1040, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2226 = MTLO_DSP { 2225, 1, 0, 4, 908, 0, 1, MipsImpOpBase + 41, 318, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2225 = MTLO64 { 2224, 1, 0, 4, 493, 0, 1, MipsImpOpBase + 40, 197, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2224 = MTLO { 2223, 3, 1, 4, 1568, 0, 1, MipsImpOpBase + 4, 1037, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2223 = MTHLIP_MM { 2222, 3, 1, 4, 1355, 0, 1, MipsImpOpBase + 4, 1037, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2222 = MTHLIP { 2221, 1, 0, 4, 890, 0, 1, MipsImpOpBase + 38, 197, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2221 = MTHI_MM { 2220, 2, 1, 4, 1567, 0, 0, MipsImpOpBase + 0, 1035, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2220 = MTHI_DSP_MM { 2219, 2, 1, 4, 1356, 0, 0, MipsImpOpBase + 0, 1035, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2219 = MTHI_DSP { 2218, 1, 0, 4, 908, 0, 1, MipsImpOpBase + 39, 318, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2218 = MTHI64 { 2217, 1, 0, 4, 493, 0, 1, MipsImpOpBase + 38, 197, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2217 = MTHI { 2216, 3, 1, 4, 1080, 0, 0, MipsImpOpBase + 0, 401, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2216 = MTHGC0_MM { 2215, 3, 1, 4, 424, 0, 0, MipsImpOpBase + 0, 401, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2215 = MTHGC0 { 2214, 2, 1, 4, 1046, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2214 = MTHC2_MMR6 { 2213, 3, 1, 4, 1271, 0, 0, MipsImpOpBase + 0, 1032, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2213 = MTHC1_D64_MM { 2212, 3, 1, 4, 687, 0, 0, MipsImpOpBase + 0, 1032, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2212 = MTHC1_D64 { 2211, 3, 1, 4, 1271, 0, 0, MipsImpOpBase + 0, 1029, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2211 = MTHC1_D32_MM { 2210, 3, 1, 4, 687, 0, 0, MipsImpOpBase + 0, 1029, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2210 = MTHC1_D32 { 2209, 3, 1, 4, 1044, 0, 0, MipsImpOpBase + 0, 401, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2209 = MTHC0_MMR6 { 2208, 3, 1, 4, 1079, 0, 0, MipsImpOpBase + 0, 401, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2208 = MTGC0_MM { 2207, 3, 1, 4, 423, 0, 0, MipsImpOpBase + 0, 401, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2207 = MTGC0 { 2206, 2, 1, 4, 1046, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2206 = MTC2_MMR6 { 2205, 3, 1, 4, 419, 0, 0, MipsImpOpBase + 0, 1026, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2205 = MTC2 { 2204, 2, 1, 4, 1314, 0, 0, MipsImpOpBase + 0, 404, 0|(1ULL<<MCID::Bitcast), 0x6ULL }, // Inst #2204 = MTC1_MMR6 { 2203, 2, 1, 4, 1270, 0, 0, MipsImpOpBase + 0, 404, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #2203 = MTC1_MM { 2202, 2, 1, 4, 1270, 0, 0, MipsImpOpBase + 0, 418, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #2202 = MTC1_D64_MM { 2201, 2, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 418, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #2201 = MTC1_D64 { 2200, 2, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 404, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #2200 = MTC1 { 2199, 3, 1, 4, 1045, 0, 0, MipsImpOpBase + 0, 401, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2199 = MTC0_MMR6 { 2198, 3, 1, 4, 417, 0, 0, MipsImpOpBase + 0, 401, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2198 = MTC0 { 2197, 4, 1, 4, 1283, 0, 0, MipsImpOpBase + 0, 948, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2197 = MSUB_S_MM { 2196, 4, 1, 4, 680, 0, 0, MipsImpOpBase + 0, 948, 0, 0x4ULL }, // Inst #2196 = MSUB_S { 2195, 4, 1, 4, 674, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #2195 = MSUB_Q_W { 2194, 4, 1, 4, 674, 0, 0, MipsImpOpBase + 0, 206, 0, 0x6ULL }, // Inst #2194 = MSUB_Q_H { 2193, 2, 0, 4, 882, 2, 2, MipsImpOpBase + 32, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2193 = MSUB_MM { 2192, 4, 1, 4, 1566, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #2192 = MSUB_DSP_MM { 2191, 4, 1, 4, 1403, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #2191 = MSUB_DSP { 2190, 4, 1, 4, 679, 0, 0, MipsImpOpBase + 0, 944, 0, 0x4ULL }, // Inst #2190 = MSUB_D64 { 2189, 4, 1, 4, 1284, 0, 0, MipsImpOpBase + 0, 940, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2189 = MSUB_D32_MM { 2188, 4, 1, 4, 679, 0, 0, MipsImpOpBase + 0, 940, 0, 0x4ULL }, // Inst #2188 = MSUB_D32 { 2187, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #2187 = MSUBV_W { 2186, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 206, 0, 0x6ULL }, // Inst #2186 = MSUBV_H { 2185, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 198, 0, 0x6ULL }, // Inst #2185 = MSUBV_D { 2184, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 618, 0, 0x6ULL }, // Inst #2184 = MSUBV_B { 2183, 2, 0, 4, 883, 2, 2, MipsImpOpBase + 32, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2183 = MSUBU_MM { 2182, 4, 1, 4, 1565, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #2182 = MSUBU_DSP_MM { 2181, 4, 1, 4, 1402, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #2181 = MSUBU_DSP { 2180, 2, 0, 4, 856, 2, 2, MipsImpOpBase + 32, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2180 = MSUBU { 2179, 4, 1, 4, 673, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #2179 = MSUBR_Q_W { 2178, 4, 1, 4, 673, 0, 0, MipsImpOpBase + 0, 206, 0, 0x6ULL }, // Inst #2178 = MSUBR_Q_H { 2177, 4, 1, 4, 1333, 0, 0, MipsImpOpBase + 0, 936, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2177 = MSUBF_S_MMR6 { 2176, 4, 1, 4, 1236, 0, 0, MipsImpOpBase + 0, 936, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2176 = MSUBF_S { 2175, 4, 1, 4, 1332, 0, 0, MipsImpOpBase + 0, 932, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2175 = MSUBF_D_MMR6 { 2174, 4, 1, 4, 1238, 0, 0, MipsImpOpBase + 0, 932, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2174 = MSUBF_D { 2173, 2, 0, 4, 855, 2, 2, MipsImpOpBase + 32, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2173 = MSUB { 2172, 4, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 1022, 0, 0x4ULL }, // Inst #2172 = MOVZ_I_S_MM { 2171, 4, 1, 4, 709, 0, 0, MipsImpOpBase + 0, 1022, 0, 0x4ULL }, // Inst #2171 = MOVZ_I_S { 2170, 4, 1, 4, 1564, 0, 0, MipsImpOpBase + 0, 1014, 0, 0x4ULL }, // Inst #2170 = MOVZ_I_MM { 2169, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 1018, 0, 0x4ULL }, // Inst #2169 = MOVZ_I_I64 { 2168, 4, 1, 4, 483, 0, 0, MipsImpOpBase + 0, 1014, 0, 0x4ULL }, // Inst #2168 = MOVZ_I_I { 2167, 4, 1, 4, 708, 0, 0, MipsImpOpBase + 0, 1010, 0, 0x4ULL }, // Inst #2167 = MOVZ_I_D64 { 2166, 4, 1, 4, 1245, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2166 = MOVZ_I_D32_MM { 2165, 4, 1, 4, 708, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2165 = MOVZ_I_D32 { 2164, 4, 1, 4, 1218, 0, 0, MipsImpOpBase + 0, 1002, 0, 0x4ULL }, // Inst #2164 = MOVZ_I64_S { 2163, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2163 = MOVZ_I64_I64 { 2162, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 994, 0, 0x4ULL }, // Inst #2162 = MOVZ_I64_I { 2161, 4, 1, 4, 1221, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2161 = MOVZ_I64_D64 { 2160, 4, 1, 4, 1244, 0, 0, MipsImpOpBase + 0, 986, 0, 0x4ULL }, // Inst #2160 = MOVT_S_MM { 2159, 4, 1, 4, 534, 0, 0, MipsImpOpBase + 0, 986, 0, 0x4ULL }, // Inst #2159 = MOVT_S { 2158, 4, 1, 4, 889, 0, 0, MipsImpOpBase + 0, 978, 0, 0x4ULL }, // Inst #2158 = MOVT_I_MM { 2157, 4, 1, 4, 1216, 0, 0, MipsImpOpBase + 0, 982, 0, 0x4ULL }, // Inst #2157 = MOVT_I64 { 2156, 4, 1, 4, 698, 0, 0, MipsImpOpBase + 0, 978, 0, 0x4ULL }, // Inst #2156 = MOVT_I { 2155, 4, 1, 4, 533, 0, 0, MipsImpOpBase + 0, 974, 0, 0x4ULL }, // Inst #2155 = MOVT_D64 { 2154, 4, 1, 4, 1243, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2154 = MOVT_D32_MM { 2153, 4, 1, 4, 533, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2153 = MOVT_D32 { 2152, 4, 1, 4, 1242, 0, 0, MipsImpOpBase + 0, 1022, 0, 0x4ULL }, // Inst #2152 = MOVN_I_S_MM { 2151, 4, 1, 4, 707, 0, 0, MipsImpOpBase + 0, 1022, 0, 0x4ULL }, // Inst #2151 = MOVN_I_S { 2150, 4, 1, 4, 1563, 0, 0, MipsImpOpBase + 0, 1014, 0, 0x4ULL }, // Inst #2150 = MOVN_I_MM { 2149, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 1018, 0, 0x4ULL }, // Inst #2149 = MOVN_I_I64 { 2148, 4, 1, 4, 482, 0, 0, MipsImpOpBase + 0, 1014, 0, 0x4ULL }, // Inst #2148 = MOVN_I_I { 2147, 4, 1, 4, 706, 0, 0, MipsImpOpBase + 0, 1010, 0, 0x4ULL }, // Inst #2147 = MOVN_I_D64 { 2146, 4, 1, 4, 1241, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2146 = MOVN_I_D32_MM { 2145, 4, 1, 4, 706, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2145 = MOVN_I_D32 { 2144, 4, 1, 4, 1220, 0, 0, MipsImpOpBase + 0, 1002, 0, 0x4ULL }, // Inst #2144 = MOVN_I64_S { 2143, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2143 = MOVN_I64_I64 { 2142, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 994, 0, 0x4ULL }, // Inst #2142 = MOVN_I64_I { 2141, 4, 1, 4, 1219, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2141 = MOVN_I64_D64 { 2140, 4, 1, 4, 1240, 0, 0, MipsImpOpBase + 0, 986, 0, 0x4ULL }, // Inst #2140 = MOVF_S_MM { 2139, 4, 1, 4, 532, 0, 0, MipsImpOpBase + 0, 986, 0, 0x4ULL }, // Inst #2139 = MOVF_S { 2138, 4, 1, 4, 888, 0, 0, MipsImpOpBase + 0, 978, 0, 0x4ULL }, // Inst #2138 = MOVF_I_MM { 2137, 4, 1, 4, 1217, 0, 0, MipsImpOpBase + 0, 982, 0, 0x4ULL }, // Inst #2137 = MOVF_I64 { 2136, 4, 1, 4, 697, 0, 0, MipsImpOpBase + 0, 978, 0, 0x4ULL }, // Inst #2136 = MOVF_I { 2135, 4, 1, 4, 531, 0, 0, MipsImpOpBase + 0, 974, 0, 0x4ULL }, // Inst #2135 = MOVF_D64 { 2134, 4, 1, 4, 1239, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2134 = MOVF_D32_MM { 2133, 4, 1, 4, 531, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2133 = MOVF_D32 { 2132, 2, 1, 4, 546, 0, 0, MipsImpOpBase + 0, 968, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2132 = MOVE_V { 2131, 4, 2, 2, 1562, 0, 0, MipsImpOpBase + 0, 964, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2131 = MOVEP_MMR6 { 2130, 4, 2, 2, 751, 0, 0, MipsImpOpBase + 0, 964, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2130 = MOVEP_MM { 2129, 2, 1, 2, 792, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2129 = MOVE16_MMR6 { 2128, 2, 1, 2, 750, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2128 = MOVE16_MM { 2127, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2127 = MOD_U_W { 2126, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2126 = MOD_U_H { 2125, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2125 = MOD_U_D { 2124, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2124 = MOD_U_B { 2123, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2123 = MOD_S_W { 2122, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2122 = MOD_S_H { 2121, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2121 = MOD_S_D { 2120, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2120 = MOD_S_B { 2119, 3, 1, 4, 897, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #2119 = MOD_MMR6 { 2118, 3, 1, 4, 896, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #2118 = MODU_MMR6 { 2117, 3, 1, 4, 874, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #2117 = MODU { 2116, 3, 1, 4, 1561, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2116 = MODSUB_MM { 2115, 3, 1, 4, 1401, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2115 = MODSUB { 2114, 3, 1, 4, 873, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #2114 = MOD { 2113, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2113 = MIN_U_W { 2112, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2112 = MIN_U_H { 2111, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2111 = MIN_U_D { 2110, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2110 = MIN_U_B { 2109, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2109 = MIN_S_W { 2108, 3, 1, 4, 1320, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2108 = MIN_S_MMR6 { 2107, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2107 = MIN_S_H { 2106, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2106 = MIN_S_D { 2105, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2105 = MIN_S_B { 2104, 3, 1, 4, 1226, 0, 0, MipsImpOpBase + 0, 771, 0, 0x6ULL }, // Inst #2104 = MIN_S { 2103, 3, 1, 4, 1319, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2103 = MIN_D_MMR6 { 2102, 3, 1, 4, 1227, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #2102 = MIN_D { 2101, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2101 = MIN_A_W { 2100, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2100 = MIN_A_H { 2099, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2099 = MIN_A_D { 2098, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2098 = MIN_A_B { 2097, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2097 = MINI_U_W { 2096, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2096 = MINI_U_H { 2095, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2095 = MINI_U_D { 2094, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2094 = MINI_U_B { 2093, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2093 = MINI_S_W { 2092, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2092 = MINI_S_H { 2091, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2091 = MINI_S_D { 2090, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2090 = MINI_S_B { 2089, 3, 1, 4, 1324, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2089 = MINA_S_MMR6 { 2088, 3, 1, 4, 1227, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2088 = MINA_S { 2087, 3, 1, 4, 1323, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2087 = MINA_D_MMR6 { 2086, 3, 1, 4, 1226, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2086 = MINA_D { 2085, 5, 1, 4, 1064, 0, 0, MipsImpOpBase + 0, 959, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2085 = MFTR { 2084, 1, 1, 4, 887, 1, 0, MipsImpOpBase + 36, 197, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2084 = MFLO_MM { 2083, 2, 1, 4, 1560, 0, 0, MipsImpOpBase + 0, 382, 0, 0x6ULL }, // Inst #2083 = MFLO_DSP_MM { 2082, 2, 1, 4, 1400, 0, 0, MipsImpOpBase + 0, 382, 0|(1ULL<<MCID::MoveReg), 0x6ULL }, // Inst #2082 = MFLO_DSP { 2081, 1, 1, 4, 906, 1, 0, MipsImpOpBase + 37, 318, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2081 = MFLO64 { 2080, 1, 1, 2, 887, 1, 0, MipsImpOpBase + 36, 197, 0|(1ULL<<MCID::MoveReg), 0x0ULL }, // Inst #2080 = MFLO16_MM { 2079, 1, 1, 4, 478, 1, 0, MipsImpOpBase + 36, 197, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2079 = MFLO { 2078, 1, 1, 4, 887, 1, 0, MipsImpOpBase + 36, 197, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2078 = MFHI_MM { 2077, 2, 1, 4, 1559, 0, 0, MipsImpOpBase + 0, 382, 0, 0x6ULL }, // Inst #2077 = MFHI_DSP_MM { 2076, 2, 1, 4, 1399, 0, 0, MipsImpOpBase + 0, 382, 0|(1ULL<<MCID::MoveReg), 0x6ULL }, // Inst #2076 = MFHI_DSP { 2075, 1, 1, 4, 906, 1, 0, MipsImpOpBase + 37, 318, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2075 = MFHI64 { 2074, 1, 1, 2, 887, 1, 0, MipsImpOpBase + 36, 197, 0|(1ULL<<MCID::MoveReg), 0x0ULL }, // Inst #2074 = MFHI16_MM { 2073, 1, 1, 4, 478, 1, 0, MipsImpOpBase + 36, 197, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2073 = MFHI { 2072, 3, 1, 4, 1078, 0, 0, MipsImpOpBase + 0, 384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2072 = MFHGC0_MM { 2071, 3, 1, 4, 422, 0, 0, MipsImpOpBase + 0, 384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2071 = MFHGC0 { 2070, 2, 1, 4, 1043, 0, 0, MipsImpOpBase + 0, 647, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2070 = MFHC2_MMR6 { 2069, 2, 1, 4, 1269, 0, 0, MipsImpOpBase + 0, 952, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2069 = MFHC1_D64_MM { 2068, 2, 1, 4, 696, 0, 0, MipsImpOpBase + 0, 952, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2068 = MFHC1_D64 { 2067, 2, 1, 4, 1269, 0, 0, MipsImpOpBase + 0, 957, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2067 = MFHC1_D32_MM { 2066, 2, 1, 4, 696, 0, 0, MipsImpOpBase + 0, 957, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2066 = MFHC1_D32 { 2065, 3, 1, 4, 1041, 0, 0, MipsImpOpBase + 0, 384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2065 = MFHC0_MMR6 { 2064, 3, 1, 4, 1077, 0, 0, MipsImpOpBase + 0, 384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2064 = MFGC0_MM { 2063, 3, 1, 4, 421, 0, 0, MipsImpOpBase + 0, 384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2063 = MFGC0 { 2062, 2, 1, 4, 1043, 0, 0, MipsImpOpBase + 0, 647, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2062 = MFC2_MMR6 { 2061, 3, 1, 4, 418, 0, 0, MipsImpOpBase + 0, 954, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2061 = MFC2 { 2060, 2, 1, 4, 1313, 0, 0, MipsImpOpBase + 0, 387, 0|(1ULL<<MCID::Bitcast), 0x6ULL }, // Inst #2060 = MFC1_MMR6 { 2059, 2, 1, 4, 1268, 0, 0, MipsImpOpBase + 0, 387, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #2059 = MFC1_MM { 2058, 2, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 952, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2058 = MFC1_D64 { 2057, 2, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 387, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #2057 = MFC1 { 2056, 3, 1, 4, 1042, 0, 0, MipsImpOpBase + 0, 384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2056 = MFC0_MMR6 { 2055, 3, 1, 4, 416, 0, 0, MipsImpOpBase + 0, 384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2055 = MFC0 { 2054, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2054 = MAX_U_W { 2053, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2053 = MAX_U_H { 2052, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2052 = MAX_U_D { 2051, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2051 = MAX_U_B { 2050, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2050 = MAX_S_W { 2049, 3, 1, 4, 1318, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2049 = MAX_S_MMR6 { 2048, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2048 = MAX_S_H { 2047, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2047 = MAX_S_D { 2046, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2046 = MAX_S_B { 2045, 3, 1, 4, 1224, 0, 0, MipsImpOpBase + 0, 771, 0, 0x6ULL }, // Inst #2045 = MAX_S { 2044, 3, 1, 4, 1317, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2044 = MAX_D_MMR6 { 2043, 3, 1, 4, 1225, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #2043 = MAX_D { 2042, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #2042 = MAX_A_W { 2041, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #2041 = MAX_A_H { 2040, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #2040 = MAX_A_D { 2039, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2039 = MAX_A_B { 2038, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2038 = MAXI_U_W { 2037, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2037 = MAXI_U_H { 2036, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2036 = MAXI_U_D { 2035, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2035 = MAXI_U_B { 2034, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #2034 = MAXI_S_W { 2033, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #2033 = MAXI_S_H { 2032, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #2032 = MAXI_S_D { 2031, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #2031 = MAXI_S_B { 2030, 3, 1, 4, 1322, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2030 = MAXA_S_MMR6 { 2029, 3, 1, 4, 1224, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2029 = MAXA_S { 2028, 3, 1, 4, 1321, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2028 = MAXA_D_MMR6 { 2027, 3, 1, 4, 1225, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2027 = MAXA_D { 2026, 4, 1, 4, 1558, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2026 = MAQ_S_W_PHR_MM { 2025, 4, 1, 4, 1398, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2025 = MAQ_S_W_PHR { 2024, 4, 1, 4, 1557, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2024 = MAQ_S_W_PHL_MM { 2023, 4, 1, 4, 1397, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2023 = MAQ_S_W_PHL { 2022, 4, 1, 4, 1556, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2022 = MAQ_SA_W_PHR_MM { 2021, 4, 1, 4, 1396, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2021 = MAQ_SA_W_PHR { 2020, 4, 1, 4, 1555, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2020 = MAQ_SA_W_PHL_MM { 2019, 4, 1, 4, 1395, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2019 = MAQ_SA_W_PHL { 2018, 4, 1, 4, 1254, 0, 0, MipsImpOpBase + 0, 948, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2018 = MADD_S_MM { 2017, 4, 1, 4, 678, 0, 0, MipsImpOpBase + 0, 948, 0, 0x4ULL }, // Inst #2017 = MADD_S { 2016, 4, 1, 4, 672, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #2016 = MADD_Q_W { 2015, 4, 1, 4, 672, 0, 0, MipsImpOpBase + 0, 206, 0, 0x6ULL }, // Inst #2015 = MADD_Q_H { 2014, 2, 0, 4, 880, 2, 2, MipsImpOpBase + 32, 152, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2014 = MADD_MM { 2013, 4, 1, 4, 1554, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #2013 = MADD_DSP_MM { 2012, 4, 1, 4, 1394, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #2012 = MADD_DSP { 2011, 4, 1, 4, 677, 0, 0, MipsImpOpBase + 0, 944, 0, 0x4ULL }, // Inst #2011 = MADD_D64 { 2010, 4, 1, 4, 1255, 0, 0, MipsImpOpBase + 0, 940, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2010 = MADD_D32_MM { 2009, 4, 1, 4, 677, 0, 0, MipsImpOpBase + 0, 940, 0, 0x4ULL }, // Inst #2009 = MADD_D32 { 2008, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #2008 = MADDV_W { 2007, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 206, 0, 0x6ULL }, // Inst #2007 = MADDV_H { 2006, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 198, 0, 0x6ULL }, // Inst #2006 = MADDV_D { 2005, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 618, 0, 0x6ULL }, // Inst #2005 = MADDV_B { 2004, 2, 0, 4, 881, 2, 2, MipsImpOpBase + 32, 152, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2004 = MADDU_MM { 2003, 4, 1, 4, 1553, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #2003 = MADDU_DSP_MM { 2002, 4, 1, 4, 1393, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #2002 = MADDU_DSP { 2001, 2, 0, 4, 854, 2, 2, MipsImpOpBase + 32, 152, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2001 = MADDU { 2000, 4, 1, 4, 671, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #2000 = MADDR_Q_W { 1999, 4, 1, 4, 671, 0, 0, MipsImpOpBase + 0, 206, 0, 0x6ULL }, // Inst #1999 = MADDR_Q_H { 1998, 4, 1, 4, 1331, 0, 0, MipsImpOpBase + 0, 936, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1998 = MADDF_S_MMR6 { 1997, 4, 1, 4, 1235, 0, 0, MipsImpOpBase + 0, 936, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1997 = MADDF_S { 1996, 4, 1, 4, 1330, 0, 0, MipsImpOpBase + 0, 932, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1996 = MADDF_D_MMR6 { 1995, 4, 1, 4, 1237, 0, 0, MipsImpOpBase + 0, 932, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1995 = MADDF_D { 1994, 2, 0, 4, 853, 2, 2, MipsImpOpBase + 32, 152, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1994 = MADD { 1993, 3, 1, 4, 1114, 0, 0, MipsImpOpBase + 0, 585, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1993 = LwRxSpImmX16 { 1992, 3, 1, 4, 1114, 0, 0, MipsImpOpBase + 0, 926, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1992 = LwRxRyOffMemX16 { 1991, 3, 1, 4, 1114, 0, 0, MipsImpOpBase + 0, 929, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1991 = LwRxPcTcpX16 { 1990, 3, 1, 2, 1114, 0, 0, MipsImpOpBase + 0, 929, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1990 = LwRxPcTcp16 { 1989, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 580, 0, 0x0ULL }, // Inst #1989 = LiRxImmX16 { 1988, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 580, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1988 = LiRxImmAlignX16 { 1987, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 580, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1987 = LiRxImm16 { 1986, 3, 1, 4, 1113, 0, 0, MipsImpOpBase + 0, 926, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1986 = LhuRxRyOffMemX16 { 1985, 3, 1, 4, 1112, 0, 0, MipsImpOpBase + 0, 926, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1985 = LhRxRyOffMemX16 { 1984, 3, 1, 4, 1111, 0, 0, MipsImpOpBase + 0, 926, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1984 = LbuRxRyOffMemX16 { 1983, 3, 1, 4, 1110, 0, 0, MipsImpOpBase + 0, 926, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1983 = LbRxRyOffMemX16 { 1982, 3, 1, 4, 1166, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1982 = LWu { 1981, 3, 1, 4, 1153, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1981 = LW_MMR6 { 1980, 3, 1, 4, 1124, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1980 = LW_MM { 1979, 3, 1, 4, 1552, 0, 0, MipsImpOpBase + 0, 849, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1979 = LWX_MM { 1978, 3, 1, 4, 1130, 0, 0, MipsImpOpBase + 0, 849, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #1978 = LWXS_MM { 1977, 3, 1, 4, 1300, 0, 0, MipsImpOpBase + 0, 923, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1977 = LWXC1_MM { 1976, 3, 1, 4, 713, 0, 0, MipsImpOpBase + 0, 923, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1976 = LWXC1 { 1975, 3, 1, 4, 1392, 0, 0, MipsImpOpBase + 0, 849, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1975 = LWX { 1974, 3, 1, 4, 1129, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1974 = LWU_MM { 1973, 2, 1, 4, 1185, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1973 = LWUPC { 1972, 3, 1, 2, 1124, 0, 0, MipsImpOpBase + 0, 920, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1972 = LWSP_MM { 1971, 4, 1, 4, 1128, 0, 0, MipsImpOpBase + 0, 909, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1971 = LWR_MM { 1970, 4, 1, 4, 1098, 0, 0, MipsImpOpBase + 0, 909, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1970 = LWRE_MM { 1969, 4, 1, 4, 451, 0, 0, MipsImpOpBase + 0, 909, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1969 = LWRE { 1968, 4, 1, 4, 1173, 0, 0, MipsImpOpBase + 0, 872, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1968 = LWR64 { 1967, 4, 1, 4, 449, 0, 0, MipsImpOpBase + 0, 909, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1967 = LWR { 1966, 4, 2, 4, 1127, 0, 0, MipsImpOpBase + 0, 916, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1966 = LWP_MM { 1965, 2, 1, 4, 1152, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1965 = LWPC_MMR6 { 1964, 2, 1, 4, 447, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1964 = LWPC { 1963, 3, 1, 4, 1126, 0, 0, MipsImpOpBase + 0, 361, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1963 = LWM32_MM { 1962, 3, 1, 2, 1150, 0, 0, MipsImpOpBase + 0, 913, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1962 = LWM16_MMR6 { 1961, 3, 1, 2, 1126, 0, 0, MipsImpOpBase + 0, 913, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1961 = LWM16_MM { 1960, 4, 1, 4, 1125, 0, 0, MipsImpOpBase + 0, 909, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1960 = LWL_MM { 1959, 4, 1, 4, 1097, 0, 0, MipsImpOpBase + 0, 909, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1959 = LWLE_MM { 1958, 4, 1, 4, 450, 0, 0, MipsImpOpBase + 0, 909, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1958 = LWLE { 1957, 4, 1, 4, 1172, 0, 0, MipsImpOpBase + 0, 872, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1957 = LWL64 { 1956, 4, 1, 4, 448, 0, 0, MipsImpOpBase + 0, 909, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1956 = LWL { 1955, 3, 1, 2, 1124, 0, 0, MipsImpOpBase + 0, 906, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1955 = LWGP_MM { 1954, 3, 1, 4, 1096, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1954 = LWE_MM { 1953, 3, 1, 4, 445, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1953 = LWE { 1952, 3, 1, 4, 1507, 0, 0, MipsImpOpBase + 0, 903, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1952 = LWDSP_MM { 1951, 3, 1, 4, 1344, 0, 0, MipsImpOpBase + 0, 903, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1951 = LWDSP { 1950, 3, 1, 4, 438, 0, 0, MipsImpOpBase + 0, 861, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1950 = LWC3 { 1949, 3, 1, 4, 1084, 0, 0, MipsImpOpBase + 0, 855, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1949 = LWC2_R6 { 1948, 3, 1, 4, 1151, 0, 0, MipsImpOpBase + 0, 858, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1948 = LWC2_MMR6 { 1947, 3, 1, 4, 437, 0, 0, MipsImpOpBase + 0, 855, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1947 = LWC2 { 1946, 3, 1, 4, 1299, 0, 0, MipsImpOpBase + 0, 900, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1946 = LWC1_MM { 1945, 3, 1, 4, 712, 0, 0, MipsImpOpBase + 0, 900, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1945 = LWC1 { 1944, 3, 1, 4, 1171, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1944 = LW64 { 1943, 3, 1, 2, 1124, 0, 0, MipsImpOpBase + 0, 846, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1943 = LW16_MM { 1942, 3, 1, 4, 435, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1942 = LW { 1941, 2, 1, 4, 749, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // Inst #1941 = LUi_MM { 1940, 2, 1, 4, 841, 0, 0, MipsImpOpBase + 0, 366, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // Inst #1940 = LUi64 { 1939, 2, 1, 4, 365, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // Inst #1939 = LUi { 1938, 3, 1, 4, 1298, 0, 0, MipsImpOpBase + 0, 879, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #1938 = LUXC1_MM { 1937, 3, 1, 4, 714, 0, 0, MipsImpOpBase + 0, 879, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #1937 = LUXC164 { 1936, 3, 1, 4, 714, 0, 0, MipsImpOpBase + 0, 876, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #1936 = LUXC1 { 1935, 2, 1, 4, 791, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #1935 = LUI_MMR6 { 1934, 4, 1, 4, 733, 0, 0, MipsImpOpBase + 0, 569, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1934 = LSA_R6 { 1933, 4, 1, 4, 790, 0, 0, MipsImpOpBase + 0, 569, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1933 = LSA_MMR6 { 1932, 4, 1, 4, 513, 0, 0, MipsImpOpBase + 0, 569, 0, 0x6ULL }, // Inst #1932 = LSA { 1931, 3, 1, 4, 1083, 0, 0, MipsImpOpBase + 0, 894, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1931 = LL_R6 { 1930, 3, 1, 4, 1149, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1930 = LL_MMR6 { 1929, 3, 1, 4, 1123, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1929 = LL_MM { 1928, 3, 1, 4, 1099, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1928 = LLE_MM { 1927, 3, 1, 4, 446, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1927 = LLE { 1926, 3, 1, 4, 1187, 0, 0, MipsImpOpBase + 0, 897, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1926 = LLD_R6 { 1925, 3, 1, 4, 1165, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1925 = LLD { 1924, 3, 1, 4, 1188, 0, 0, MipsImpOpBase + 0, 894, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1924 = LL64_R6 { 1923, 3, 1, 4, 1165, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1923 = LL64 { 1922, 3, 1, 4, 436, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1922 = LL { 1921, 2, 1, 2, 789, 0, 0, MipsImpOpBase + 0, 537, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1921 = LI16_MMR6 { 1920, 2, 1, 2, 748, 0, 0, MipsImpOpBase + 0, 537, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1920 = LI16_MM { 1919, 3, 1, 4, 1121, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1919 = LHu_MM { 1918, 3, 1, 4, 1095, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1918 = LHuE_MM { 1917, 3, 1, 4, 444, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1917 = LHuE { 1916, 3, 1, 4, 1170, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1916 = LHu64 { 1915, 3, 1, 4, 434, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1915 = LHu { 1914, 3, 1, 4, 1122, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1914 = LH_MM { 1913, 3, 1, 4, 1551, 0, 0, MipsImpOpBase + 0, 849, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1913 = LHX_MM { 1912, 3, 1, 4, 1391, 0, 0, MipsImpOpBase + 0, 849, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1912 = LHX { 1911, 3, 1, 2, 1121, 0, 0, MipsImpOpBase + 0, 846, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1911 = LHU16_MM { 1910, 3, 1, 4, 1094, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1910 = LHE_MM { 1909, 3, 1, 4, 443, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1909 = LHE { 1908, 3, 1, 4, 1169, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1908 = LH64 { 1907, 3, 1, 4, 433, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1907 = LH { 1906, 3, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 319, 0, 0x2ULL }, // Inst #1906 = LEA_ADDiu_MM { 1905, 3, 1, 4, 840, 0, 0, MipsImpOpBase + 0, 368, 0, 0x2ULL }, // Inst #1905 = LEA_ADDiu64 { 1904, 3, 1, 4, 724, 0, 0, MipsImpOpBase + 0, 319, 0, 0x2ULL }, // Inst #1904 = LEA_ADDiu { 1903, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 891, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1903 = LD_W { 1902, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 888, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1902 = LD_H { 1901, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 885, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1901 = LD_D { 1900, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 882, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1900 = LD_B { 1899, 3, 1, 4, 711, 0, 0, MipsImpOpBase + 0, 879, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1899 = LDXC164 { 1898, 3, 1, 4, 711, 0, 0, MipsImpOpBase + 0, 876, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1898 = LDXC1 { 1897, 4, 1, 4, 1175, 0, 0, MipsImpOpBase + 0, 872, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1897 = LDR { 1896, 2, 1, 4, 1186, 0, 0, MipsImpOpBase + 0, 366, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1896 = LDPC { 1895, 4, 1, 4, 1174, 0, 0, MipsImpOpBase + 0, 872, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1895 = LDL { 1894, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 870, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // Inst #1894 = LDI_W { 1893, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 868, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // Inst #1893 = LDI_H { 1892, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 866, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // Inst #1892 = LDI_D { 1891, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 864, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // Inst #1891 = LDI_B { 1890, 3, 1, 4, 440, 0, 0, MipsImpOpBase + 0, 861, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1890 = LDC3 { 1889, 3, 1, 4, 1082, 0, 0, MipsImpOpBase + 0, 855, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1889 = LDC2_R6 { 1888, 3, 1, 4, 1148, 0, 0, MipsImpOpBase + 0, 858, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1888 = LDC2_MMR6 { 1887, 3, 1, 4, 439, 0, 0, MipsImpOpBase + 0, 855, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1887 = LDC2 { 1886, 3, 1, 4, 1297, 0, 0, MipsImpOpBase + 0, 852, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1886 = LDC1_MM_D64 { 1885, 3, 1, 4, 1297, 0, 0, MipsImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1885 = LDC1_MM_D32 { 1884, 3, 1, 4, 1340, 0, 0, MipsImpOpBase + 0, 852, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1884 = LDC1_D64_MMR6 { 1883, 3, 1, 4, 710, 0, 0, MipsImpOpBase + 0, 852, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1883 = LDC164 { 1882, 3, 1, 4, 710, 0, 0, MipsImpOpBase + 0, 504, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1882 = LDC1 { 1881, 3, 1, 4, 1164, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1881 = LD { 1880, 3, 1, 4, 1119, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1880 = LBu_MM { 1879, 3, 1, 4, 1093, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1879 = LBuE_MM { 1878, 3, 1, 4, 442, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1878 = LBuE { 1877, 3, 1, 4, 1168, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1877 = LBu64 { 1876, 3, 1, 4, 432, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1876 = LBu { 1875, 3, 1, 4, 1147, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1875 = LB_MMR6 { 1874, 3, 1, 4, 1120, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1874 = LB_MM { 1873, 3, 1, 4, 1146, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1873 = LBU_MMR6 { 1872, 3, 1, 4, 1550, 0, 0, MipsImpOpBase + 0, 849, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1872 = LBUX_MM { 1871, 3, 1, 4, 1390, 0, 0, MipsImpOpBase + 0, 849, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1871 = LBUX { 1870, 3, 1, 2, 1119, 0, 0, MipsImpOpBase + 0, 846, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1870 = LBU16_MM { 1869, 3, 1, 4, 1092, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1869 = LBE_MM { 1868, 3, 1, 4, 441, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1868 = LBE { 1867, 3, 1, 4, 1167, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1867 = LB64 { 1866, 3, 1, 4, 431, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1866 = LB { 1865, 1, 0, 2, 943, 0, 1, MipsImpOpBase + 3, 845, 0|(1ULL<<MCID::Call), 0x0ULL }, // Inst #1865 = JumpLinkReg16 { 1864, 1, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 845, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1864 = JrcRx16 { 1863, 0, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1863 = JrcRa16 { 1862, 0, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1862 = JrRa16 { 1861, 1, 0, 6, 942, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1861 = JalB16 { 1860, 1, 0, 6, 942, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::Call), 0x0ULL }, // Inst #1860 = Jal16 { 1859, 1, 0, 4, 956, 0, 1, MipsImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL }, // Inst #1859 = J_MM { 1858, 1, 0, 4, 955, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1858 = JR_MM { 1857, 1, 0, 4, 935, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1857 = JR_HB_R6 { 1856, 1, 0, 4, 1023, 0, 0, MipsImpOpBase + 0, 318, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1856 = JR_HB64_R6 { 1855, 1, 0, 4, 1015, 0, 0, MipsImpOpBase + 0, 318, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // Inst #1855 = JR_HB64 { 1854, 1, 0, 4, 386, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // Inst #1854 = JR_HB { 1853, 1, 0, 2, 994, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1853 = JRCADDIUSP_MMR6 { 1852, 1, 0, 2, 996, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1852 = JRC16_MMR6 { 1851, 1, 0, 2, 995, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1851 = JRC16_MM { 1850, 1, 0, 2, 994, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1850 = JRADDIUSP { 1849, 1, 0, 4, 1012, 0, 0, MipsImpOpBase + 0, 318, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1849 = JR64 { 1848, 1, 0, 2, 955, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1848 = JR16_MM { 1847, 1, 0, 4, 923, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1847 = JR { 1846, 2, 0, 4, 993, 0, 1, MipsImpOpBase + 2, 371, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1846 = JIC_MMR6 { 1845, 2, 0, 4, 1020, 0, 1, MipsImpOpBase + 2, 366, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1845 = JIC64 { 1844, 2, 0, 4, 934, 0, 1, MipsImpOpBase + 2, 371, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1844 = JIC { 1843, 2, 0, 4, 1005, 0, 1, MipsImpOpBase + 3, 371, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1843 = JIALC_MMR6 { 1842, 2, 0, 4, 1022, 0, 1, MipsImpOpBase + 3, 366, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1842 = JIALC64 { 1841, 2, 0, 4, 929, 0, 1, MipsImpOpBase + 3, 371, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1841 = JIALC { 1840, 1, 0, 4, 963, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // Inst #1840 = JAL_MM { 1839, 1, 0, 4, 963, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // Inst #1839 = JALX_MM { 1838, 1, 0, 4, 409, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // Inst #1838 = JALX { 1837, 1, 0, 4, 962, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL }, // Inst #1837 = JALS_MM { 1836, 2, 1, 4, 960, 0, 1, MipsImpOpBase + 3, 152, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1836 = JALR_MM { 1835, 2, 1, 4, 1014, 0, 0, MipsImpOpBase + 0, 389, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // Inst #1835 = JALR_HB64 { 1834, 2, 1, 4, 408, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // Inst #1834 = JALR_HB { 1833, 2, 1, 4, 961, 0, 1, MipsImpOpBase + 3, 152, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1833 = JALRS_MM { 1832, 1, 0, 2, 961, 0, 1, MipsImpOpBase + 3, 197, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1832 = JALRS16_MM { 1831, 2, 1, 4, 1004, 0, 1, MipsImpOpBase + 3, 152, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1831 = JALRC_MMR6 { 1830, 2, 1, 4, 1003, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL }, // Inst #1830 = JALRC_HB_MMR6 { 1829, 1, 0, 2, 1002, 0, 1, MipsImpOpBase + 3, 197, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #1829 = JALRC16_MMR6 { 1828, 2, 1, 4, 1013, 0, 1, MipsImpOpBase + 3, 389, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1828 = JALR64 { 1827, 1, 0, 2, 960, 0, 1, MipsImpOpBase + 3, 197, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #1827 = JALR16_MM { 1826, 2, 1, 4, 407, 0, 1, MipsImpOpBase + 3, 152, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1826 = JALR { 1825, 1, 0, 4, 406, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // Inst #1825 = JAL { 1824, 1, 0, 4, 922, 0, 1, MipsImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL }, // Inst #1824 = J { 1823, 5, 1, 4, 788, 0, 0, MipsImpOpBase + 0, 801, 0, 0x1ULL }, // Inst #1823 = INS_MMR6 { 1822, 5, 1, 4, 747, 0, 0, MipsImpOpBase + 0, 801, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1822 = INS_MM { 1821, 3, 1, 4, 1549, 2, 0, MipsImpOpBase + 30, 822, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1821 = INSV_MM { 1820, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 840, 0, 0x6ULL }, // Inst #1820 = INSVE_W { 1819, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 835, 0, 0x6ULL }, // Inst #1819 = INSVE_H { 1818, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 830, 0, 0x6ULL }, // Inst #1818 = INSVE_D { 1817, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 825, 0, 0x6ULL }, // Inst #1817 = INSVE_B { 1816, 3, 1, 4, 1354, 2, 0, MipsImpOpBase + 30, 822, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1816 = INSV { 1815, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 818, 0, 0x6ULL }, // Inst #1815 = INSERT_W { 1814, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 814, 0, 0x6ULL }, // Inst #1814 = INSERT_H { 1813, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 810, 0, 0x6ULL }, // Inst #1813 = INSERT_D { 1812, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 806, 0, 0x6ULL }, // Inst #1812 = INSERT_B { 1811, 5, 1, 4, 495, 0, 0, MipsImpOpBase + 0, 801, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1811 = INS { 1810, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1810 = ILVR_W { 1809, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1809 = ILVR_H { 1808, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1808 = ILVR_D { 1807, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1807 = ILVR_B { 1806, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1806 = ILVOD_W { 1805, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1805 = ILVOD_H { 1804, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1804 = ILVOD_D { 1803, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1803 = ILVOD_B { 1802, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1802 = ILVL_W { 1801, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1801 = ILVL_H { 1800, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1800 = ILVL_D { 1799, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1799 = ILVL_B { 1798, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1798 = ILVEV_W { 1797, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1797 = ILVEV_H { 1796, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1796 = ILVEV_D { 1795, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1795 = ILVEV_B { 1794, 1, 0, 4, 1070, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1794 = HYPCALL_MM { 1793, 1, 0, 4, 420, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1793 = HYPCALL { 1792, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 736, 0, 0x6ULL }, // Inst #1792 = HSUB_U_W { 1791, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 733, 0, 0x6ULL }, // Inst #1791 = HSUB_U_H { 1790, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 730, 0, 0x6ULL }, // Inst #1790 = HSUB_U_D { 1789, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 736, 0, 0x6ULL }, // Inst #1789 = HSUB_S_W { 1788, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 733, 0, 0x6ULL }, // Inst #1788 = HSUB_S_H { 1787, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 730, 0, 0x6ULL }, // Inst #1787 = HSUB_S_D { 1786, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 736, 0, 0x6ULL }, // Inst #1786 = HADD_U_W { 1785, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 733, 0, 0x6ULL }, // Inst #1785 = HADD_U_H { 1784, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 730, 0, 0x6ULL }, // Inst #1784 = HADD_U_D { 1783, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 736, 0, 0x6ULL }, // Inst #1783 = HADD_S_W { 1782, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 733, 0, 0x6ULL }, // Inst #1782 = HADD_S_H { 1781, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 730, 0, 0x6ULL }, // Inst #1781 = HADD_S_D { 1780, 2, 0, 4, 1145, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1780 = GINVT_MMR6 { 1779, 2, 0, 4, 1091, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1779 = GINVT { 1778, 1, 0, 4, 1144, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1778 = GINVI_MMR6 { 1777, 1, 0, 4, 1090, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1777 = GINVI { 1776, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1776 = FTRUNC_U_W { 1775, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1775 = FTRUNC_U_D { 1774, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1774 = FTRUNC_S_W { 1773, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1773 = FTRUNC_S_D { 1772, 3, 1, 4, 594, 0, 0, MipsImpOpBase + 0, 786, 0, 0x6ULL }, // Inst #1772 = FTQ_W { 1771, 3, 1, 4, 594, 0, 0, MipsImpOpBase + 0, 783, 0, 0x6ULL }, // Inst #1771 = FTQ_H { 1770, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1770 = FTINT_U_W { 1769, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1769 = FTINT_U_D { 1768, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1768 = FTINT_S_W { 1767, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1767 = FTINT_S_D { 1766, 3, 1, 4, 576, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1766 = FSUN_W { 1765, 3, 1, 4, 576, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1765 = FSUN_D { 1764, 3, 1, 4, 575, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1764 = FSUNE_W { 1763, 3, 1, 4, 575, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1763 = FSUNE_D { 1762, 3, 1, 4, 574, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1762 = FSULT_W { 1761, 3, 1, 4, 574, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1761 = FSULT_D { 1760, 3, 1, 4, 573, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1760 = FSULE_W { 1759, 3, 1, 4, 573, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1759 = FSULE_D { 1758, 3, 1, 4, 572, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1758 = FSUEQ_W { 1757, 3, 1, 4, 572, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1757 = FSUEQ_D { 1756, 3, 1, 4, 664, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1756 = FSUB_W { 1755, 3, 1, 4, 1336, 0, 0, MipsImpOpBase + 0, 771, 0, 0x6ULL }, // Inst #1755 = FSUB_S_MMR6 { 1754, 3, 1, 4, 1282, 0, 0, MipsImpOpBase + 0, 771, 0, 0x4ULL }, // Inst #1754 = FSUB_S_MM { 1753, 3, 1, 4, 636, 0, 0, MipsImpOpBase + 0, 771, 0, 0x4ULL }, // Inst #1753 = FSUB_S { 1752, 3, 1, 4, 635, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1752 = FSUB_PS64 { 1751, 3, 1, 4, 1281, 0, 0, MipsImpOpBase + 0, 548, 0, 0x4ULL }, // Inst #1751 = FSUB_D64_MM { 1750, 3, 1, 4, 634, 0, 0, MipsImpOpBase + 0, 548, 0, 0x4ULL }, // Inst #1750 = FSUB_D64 { 1749, 3, 1, 4, 1281, 0, 0, MipsImpOpBase + 0, 768, 0, 0x4ULL }, // Inst #1749 = FSUB_D32_MM { 1748, 3, 1, 4, 634, 0, 0, MipsImpOpBase + 0, 768, 0, 0x4ULL }, // Inst #1748 = FSUB_D32 { 1747, 3, 1, 4, 664, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1747 = FSUB_D { 1746, 2, 1, 4, 660, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1746 = FSQRT_W { 1745, 2, 1, 4, 1287, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1745 = FSQRT_S_MM { 1744, 2, 1, 4, 648, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1744 = FSQRT_S { 1743, 2, 1, 4, 1288, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1743 = FSQRT_D64_MM { 1742, 2, 1, 4, 649, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1742 = FSQRT_D64 { 1741, 2, 1, 4, 1288, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #1741 = FSQRT_D32_MM { 1740, 2, 1, 4, 649, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #1740 = FSQRT_D32 { 1739, 2, 1, 4, 661, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1739 = FSQRT_D { 1738, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1738 = FSOR_W { 1737, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1737 = FSOR_D { 1736, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1736 = FSNE_W { 1735, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1735 = FSNE_D { 1734, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1734 = FSLT_W { 1733, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1733 = FSLT_D { 1732, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1732 = FSLE_W { 1731, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1731 = FSLE_D { 1730, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1730 = FSEQ_W { 1729, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1729 = FSEQ_D { 1728, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1728 = FSAF_W { 1727, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1727 = FSAF_D { 1726, 2, 1, 4, 651, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1726 = FRSQRT_W { 1725, 2, 1, 4, 651, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1725 = FRSQRT_D { 1724, 2, 1, 4, 593, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1724 = FRINT_W { 1723, 2, 1, 4, 593, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1723 = FRINT_D { 1722, 2, 1, 4, 650, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1722 = FRCP_W { 1721, 2, 1, 4, 650, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1721 = FRCP_D { 1720, 3, 2, 4, 1067, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1720 = FORK { 1719, 2, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1719 = FNEG_S_MMR6 { 1718, 2, 1, 4, 1274, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1718 = FNEG_S_MM { 1717, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1717 = FNEG_S { 1716, 2, 1, 4, 1274, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1716 = FNEG_D64_MM { 1715, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1715 = FNEG_D64 { 1714, 2, 1, 4, 1274, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #1714 = FNEG_D32_MM { 1713, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #1713 = FNEG_D32 { 1712, 3, 1, 4, 662, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1712 = FMUL_W { 1711, 3, 1, 4, 1335, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1711 = FMUL_S_MMR6 { 1710, 3, 1, 4, 1280, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1710 = FMUL_S_MM { 1709, 3, 1, 4, 633, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1709 = FMUL_S { 1708, 3, 1, 4, 632, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1708 = FMUL_PS64 { 1707, 3, 1, 4, 1279, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1707 = FMUL_D64_MM { 1706, 3, 1, 4, 631, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1706 = FMUL_D64 { 1705, 3, 1, 4, 1279, 0, 0, MipsImpOpBase + 0, 768, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1705 = FMUL_D32_MM { 1704, 3, 1, 4, 631, 0, 0, MipsImpOpBase + 0, 768, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1704 = FMUL_D32 { 1703, 3, 1, 4, 662, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1703 = FMUL_D { 1702, 4, 1, 4, 657, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #1702 = FMSUB_W { 1701, 4, 1, 4, 657, 0, 0, MipsImpOpBase + 0, 198, 0, 0x6ULL }, // Inst #1701 = FMSUB_D { 1700, 2, 1, 4, 1334, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1700 = FMOV_S_MMR6 { 1699, 2, 1, 4, 1278, 0, 0, MipsImpOpBase + 0, 643, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #1699 = FMOV_S_MM { 1698, 2, 1, 4, 536, 0, 0, MipsImpOpBase + 0, 643, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #1698 = FMOV_S { 1697, 2, 1, 4, 1337, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1697 = FMOV_D_MMR6 { 1696, 2, 1, 4, 1277, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1696 = FMOV_D64_MM { 1695, 2, 1, 4, 535, 0, 0, MipsImpOpBase + 0, 635, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #1695 = FMOV_D64 { 1694, 2, 1, 4, 1277, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #1694 = FMOV_D32_MM { 1693, 2, 1, 4, 535, 0, 0, MipsImpOpBase + 0, 766, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #1693 = FMOV_D32 { 1692, 3, 1, 4, 603, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1692 = FMIN_W { 1691, 3, 1, 4, 603, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1691 = FMIN_D { 1690, 3, 1, 4, 602, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1690 = FMIN_A_W { 1689, 3, 1, 4, 602, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1689 = FMIN_A_D { 1688, 3, 1, 4, 601, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1688 = FMAX_W { 1687, 3, 1, 4, 601, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1687 = FMAX_D { 1686, 3, 1, 4, 600, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1686 = FMAX_A_W { 1685, 3, 1, 4, 600, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1685 = FMAX_A_D { 1684, 4, 1, 4, 656, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #1684 = FMADD_W { 1683, 4, 1, 4, 656, 0, 0, MipsImpOpBase + 0, 198, 0, 0x6ULL }, // Inst #1683 = FMADD_D { 1682, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1682 = FLOOR_W_S_MMR6 { 1681, 2, 1, 4, 1249, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1681 = FLOOR_W_S_MM { 1680, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1680 = FLOOR_W_S { 1679, 2, 1, 4, 1249, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #1679 = FLOOR_W_MM { 1678, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #1678 = FLOOR_W_D_MMR6 { 1677, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #1677 = FLOOR_W_D64 { 1676, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #1676 = FLOOR_W_D32 { 1675, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1675 = FLOOR_L_S_MMR6 { 1674, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1674 = FLOOR_L_S { 1673, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1673 = FLOOR_L_D_MMR6 { 1672, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1672 = FLOOR_L_D64 { 1671, 2, 1, 4, 604, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1671 = FLOG2_W { 1670, 2, 1, 4, 604, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1670 = FLOG2_D { 1669, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 799, 0, 0x6ULL }, // Inst #1669 = FILL_W { 1668, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 797, 0, 0x6ULL }, // Inst #1668 = FILL_H { 1667, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 795, 0, 0x6ULL }, // Inst #1667 = FILL_D { 1666, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 793, 0, 0x6ULL }, // Inst #1666 = FILL_B { 1665, 2, 1, 4, 591, 0, 0, MipsImpOpBase + 0, 791, 0, 0x6ULL }, // Inst #1665 = FFQR_W { 1664, 2, 1, 4, 591, 0, 0, MipsImpOpBase + 0, 789, 0, 0x6ULL }, // Inst #1664 = FFQR_D { 1663, 2, 1, 4, 590, 0, 0, MipsImpOpBase + 0, 791, 0, 0x6ULL }, // Inst #1663 = FFQL_W { 1662, 2, 1, 4, 590, 0, 0, MipsImpOpBase + 0, 789, 0, 0x6ULL }, // Inst #1662 = FFQL_D { 1661, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1661 = FFINT_U_W { 1660, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1660 = FFINT_U_D { 1659, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1659 = FFINT_S_W { 1658, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1658 = FFINT_S_D { 1657, 2, 1, 4, 598, 0, 0, MipsImpOpBase + 0, 791, 0, 0x6ULL }, // Inst #1657 = FEXUPR_W { 1656, 2, 1, 4, 598, 0, 0, MipsImpOpBase + 0, 789, 0, 0x6ULL }, // Inst #1656 = FEXUPR_D { 1655, 2, 1, 4, 597, 0, 0, MipsImpOpBase + 0, 791, 0, 0x6ULL }, // Inst #1655 = FEXUPL_W { 1654, 2, 1, 4, 597, 0, 0, MipsImpOpBase + 0, 789, 0, 0x6ULL }, // Inst #1654 = FEXUPL_D { 1653, 3, 1, 4, 553, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1653 = FEXP2_W { 1652, 3, 1, 4, 553, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1652 = FEXP2_D { 1651, 3, 1, 4, 596, 0, 0, MipsImpOpBase + 0, 786, 0, 0x6ULL }, // Inst #1651 = FEXDO_W { 1650, 3, 1, 4, 596, 0, 0, MipsImpOpBase + 0, 783, 0, 0x6ULL }, // Inst #1650 = FEXDO_H { 1649, 3, 1, 4, 658, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1649 = FDIV_W { 1648, 3, 1, 4, 1338, 0, 0, MipsImpOpBase + 0, 771, 0, 0x6ULL }, // Inst #1648 = FDIV_S_MMR6 { 1647, 3, 1, 4, 1285, 0, 0, MipsImpOpBase + 0, 771, 0, 0x4ULL }, // Inst #1647 = FDIV_S_MM { 1646, 3, 1, 4, 646, 0, 0, MipsImpOpBase + 0, 771, 0, 0x4ULL }, // Inst #1646 = FDIV_S { 1645, 3, 1, 4, 1286, 0, 0, MipsImpOpBase + 0, 548, 0, 0x4ULL }, // Inst #1645 = FDIV_D64_MM { 1644, 3, 1, 4, 647, 0, 0, MipsImpOpBase + 0, 548, 0, 0x4ULL }, // Inst #1644 = FDIV_D64 { 1643, 3, 1, 4, 1286, 0, 0, MipsImpOpBase + 0, 768, 0, 0x4ULL }, // Inst #1643 = FDIV_D32_MM { 1642, 3, 1, 4, 647, 0, 0, MipsImpOpBase + 0, 768, 0, 0x4ULL }, // Inst #1642 = FDIV_D32 { 1641, 3, 1, 4, 659, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1641 = FDIV_D { 1640, 3, 1, 4, 587, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1640 = FCUN_W { 1639, 3, 1, 4, 587, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1639 = FCUN_D { 1638, 3, 1, 4, 586, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1638 = FCUNE_W { 1637, 3, 1, 4, 586, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1637 = FCUNE_D { 1636, 3, 1, 4, 585, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1636 = FCULT_W { 1635, 3, 1, 4, 585, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1635 = FCULT_D { 1634, 3, 1, 4, 584, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1634 = FCULE_W { 1633, 3, 1, 4, 584, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1633 = FCULE_D { 1632, 3, 1, 4, 583, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1632 = FCUEQ_W { 1631, 3, 1, 4, 583, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1631 = FCUEQ_D { 1630, 3, 1, 4, 582, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1630 = FCOR_W { 1629, 3, 1, 4, 582, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1629 = FCOR_D { 1628, 3, 1, 4, 581, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1628 = FCNE_W { 1627, 3, 1, 4, 581, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1627 = FCNE_D { 1626, 3, 0, 4, 1266, 0, 1, MipsImpOpBase + 29, 780, 0, 0x44ULL }, // Inst #1626 = FCMP_S32_MM { 1625, 3, 0, 4, 643, 0, 1, MipsImpOpBase + 29, 780, 0, 0x44ULL }, // Inst #1625 = FCMP_S32 { 1624, 3, 0, 4, 642, 0, 1, MipsImpOpBase + 29, 777, 0, 0x44ULL }, // Inst #1624 = FCMP_D64 { 1623, 3, 0, 4, 1267, 0, 1, MipsImpOpBase + 29, 774, 0, 0x44ULL }, // Inst #1623 = FCMP_D32_MM { 1622, 3, 0, 4, 642, 0, 1, MipsImpOpBase + 29, 774, 0, 0x44ULL }, // Inst #1622 = FCMP_D32 { 1621, 3, 1, 4, 580, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1621 = FCLT_W { 1620, 3, 1, 4, 580, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1620 = FCLT_D { 1619, 3, 1, 4, 579, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1619 = FCLE_W { 1618, 3, 1, 4, 579, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1618 = FCLE_D { 1617, 2, 1, 4, 599, 0, 0, MipsImpOpBase + 0, 252, 0, 0x6ULL }, // Inst #1617 = FCLASS_W { 1616, 2, 1, 4, 599, 0, 0, MipsImpOpBase + 0, 250, 0, 0x6ULL }, // Inst #1616 = FCLASS_D { 1615, 3, 1, 4, 578, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1615 = FCEQ_W { 1614, 3, 1, 4, 578, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1614 = FCEQ_D { 1613, 3, 1, 4, 577, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1613 = FCAF_W { 1612, 3, 1, 4, 577, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1612 = FCAF_D { 1611, 3, 1, 4, 663, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1611 = FADD_W { 1610, 3, 1, 4, 1316, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1610 = FADD_S_MMR6 { 1609, 3, 1, 4, 1276, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1609 = FADD_S_MM { 1608, 3, 1, 4, 630, 0, 0, MipsImpOpBase + 0, 771, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1608 = FADD_S { 1607, 3, 1, 4, 629, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1607 = FADD_PS64 { 1606, 3, 1, 4, 1275, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1606 = FADD_D64_MM { 1605, 3, 1, 4, 628, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1605 = FADD_D64 { 1604, 3, 1, 4, 1275, 0, 0, MipsImpOpBase + 0, 768, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1604 = FADD_D32_MM { 1603, 3, 1, 4, 628, 0, 0, MipsImpOpBase + 0, 768, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1603 = FADD_D32 { 1602, 3, 1, 4, 663, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1602 = FADD_D { 1601, 2, 1, 4, 1273, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1601 = FABS_S_MM { 1600, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1600 = FABS_S { 1599, 2, 1, 4, 1272, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1599 = FABS_D64_MM { 1598, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1598 = FABS_D64 { 1597, 2, 1, 4, 1272, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #1597 = FABS_D32_MM { 1596, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 766, 0, 0x4ULL }, // Inst #1596 = FABS_D32 { 1595, 4, 1, 4, 787, 0, 0, MipsImpOpBase + 0, 659, 0, 0x1ULL }, // Inst #1595 = EXT_MMR6 { 1594, 4, 1, 4, 746, 0, 0, MipsImpOpBase + 0, 659, 0, 0x1ULL }, // Inst #1594 = EXT_MM { 1593, 4, 1, 4, 1205, 0, 0, MipsImpOpBase + 0, 651, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1593 = EXTS32 { 1592, 4, 1, 4, 1205, 0, 0, MipsImpOpBase + 0, 651, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1592 = EXTS { 1591, 3, 1, 4, 1548, 0, 1, MipsImpOpBase + 28, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1591 = EXTR_W_MM { 1590, 3, 1, 4, 1353, 0, 1, MipsImpOpBase + 28, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1590 = EXTR_W { 1589, 3, 1, 4, 1547, 0, 1, MipsImpOpBase + 28, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1589 = EXTR_S_H_MM { 1588, 3, 1, 4, 1352, 0, 1, MipsImpOpBase + 28, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1588 = EXTR_S_H { 1587, 3, 1, 4, 1546, 0, 1, MipsImpOpBase + 28, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1587 = EXTR_R_W_MM { 1586, 3, 1, 4, 1351, 0, 1, MipsImpOpBase + 28, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1586 = EXTR_R_W { 1585, 3, 1, 4, 1545, 0, 1, MipsImpOpBase + 28, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1585 = EXTR_RS_W_MM { 1584, 3, 1, 4, 1350, 0, 1, MipsImpOpBase + 28, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1584 = EXTR_RS_W { 1583, 3, 1, 4, 1544, 0, 1, MipsImpOpBase + 28, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1583 = EXTRV_W_MM { 1582, 3, 1, 4, 1349, 0, 1, MipsImpOpBase + 28, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1582 = EXTRV_W { 1581, 3, 1, 4, 1543, 0, 1, MipsImpOpBase + 28, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1581 = EXTRV_S_H_MM { 1580, 3, 1, 4, 1348, 0, 1, MipsImpOpBase + 28, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1580 = EXTRV_S_H { 1579, 3, 1, 4, 1542, 0, 1, MipsImpOpBase + 28, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1579 = EXTRV_R_W_MM { 1578, 3, 1, 4, 1347, 0, 1, MipsImpOpBase + 28, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1578 = EXTRV_R_W { 1577, 3, 1, 4, 1541, 0, 1, MipsImpOpBase + 28, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1577 = EXTRV_RS_W_MM { 1576, 3, 1, 4, 1346, 0, 1, MipsImpOpBase + 28, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1576 = EXTRV_RS_W { 1575, 3, 1, 4, 1540, 1, 1, MipsImpOpBase + 23, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1575 = EXTP_MM { 1574, 3, 1, 4, 1539, 1, 1, MipsImpOpBase + 23, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1574 = EXTPV_MM { 1573, 3, 1, 4, 1388, 1, 1, MipsImpOpBase + 23, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1573 = EXTPV { 1572, 3, 1, 4, 1538, 1, 2, MipsImpOpBase + 25, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1572 = EXTPDP_MM { 1571, 3, 1, 4, 1537, 1, 2, MipsImpOpBase + 25, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1571 = EXTPDPV_MM { 1570, 3, 1, 4, 1386, 1, 2, MipsImpOpBase + 25, 763, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1570 = EXTPDPV { 1569, 3, 1, 4, 1387, 1, 2, MipsImpOpBase + 25, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1569 = EXTPDP { 1568, 3, 1, 4, 1389, 1, 1, MipsImpOpBase + 23, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1568 = EXTP { 1567, 4, 1, 4, 494, 0, 0, MipsImpOpBase + 0, 659, 0, 0x1ULL }, // Inst #1567 = EXT { 1566, 1, 1, 4, 1047, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1566 = EVP_MMR6 { 1565, 1, 1, 4, 1063, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1565 = EVPE { 1564, 1, 1, 4, 1026, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1564 = EVP { 1563, 0, 0, 4, 992, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1563 = ERET_MMR6 { 1562, 0, 0, 4, 954, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1562 = ERET_MM { 1561, 0, 0, 4, 990, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1561 = ERETNC_MMR6 { 1560, 0, 0, 4, 383, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1560 = ERETNC { 1559, 0, 0, 4, 381, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1559 = ERET { 1558, 1, 1, 4, 1062, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1558 = EMT { 1557, 1, 1, 4, 1050, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1557 = EI_MMR6 { 1556, 1, 1, 4, 1033, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1556 = EI_MM { 1555, 1, 1, 4, 477, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1555 = EI { 1554, 0, 0, 4, 1051, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1554 = EHB_MMR6 { 1553, 0, 0, 4, 1034, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1553 = EHB_MM { 1552, 0, 0, 4, 479, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1552 = EHB { 1551, 2, 0, 2, 877, 0, 2, MipsImpOpBase + 7, 406, 0, 0x0ULL }, // Inst #1551 = DivuRxRy16 { 1550, 2, 0, 2, 876, 0, 2, MipsImpOpBase + 7, 406, 0, 0x0ULL }, // Inst #1550 = DivRxRy16 { 1549, 1, 1, 4, 1048, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1549 = DVP_MMR6 { 1548, 1, 1, 4, 1061, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1548 = DVPE { 1547, 1, 1, 4, 1027, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1547 = DVP { 1546, 2, 0, 4, 905, 0, 2, MipsImpOpBase + 20, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1546 = DUDIV { 1545, 3, 1, 4, 839, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #1545 = DSUBu { 1544, 3, 1, 4, 838, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1544 = DSUB { 1543, 3, 1, 4, 837, 0, 0, MipsImpOpBase + 0, 755, 0, 0x1ULL }, // Inst #1543 = DSRLV { 1542, 3, 1, 4, 836, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1542 = DSRL32 { 1541, 3, 1, 4, 835, 0, 0, MipsImpOpBase + 0, 232, 0, 0x1ULL }, // Inst #1541 = DSRL { 1540, 3, 1, 4, 834, 0, 0, MipsImpOpBase + 0, 755, 0, 0x1ULL }, // Inst #1540 = DSRAV { 1539, 3, 1, 4, 833, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1539 = DSRA32 { 1538, 3, 1, 4, 832, 0, 0, MipsImpOpBase + 0, 232, 0, 0x1ULL }, // Inst #1538 = DSRA { 1537, 3, 1, 4, 831, 0, 0, MipsImpOpBase + 0, 755, 0, 0x1ULL }, // Inst #1537 = DSLLV { 1536, 2, 1, 4, 808, 0, 0, MipsImpOpBase + 0, 758, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1536 = DSLL64_32 { 1535, 3, 1, 4, 830, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1535 = DSLL32 { 1534, 3, 1, 4, 829, 0, 0, MipsImpOpBase + 0, 232, 0, 0x1ULL }, // Inst #1534 = DSLL { 1533, 2, 1, 4, 828, 0, 0, MipsImpOpBase + 0, 389, 0, 0x1ULL }, // Inst #1533 = DSHD { 1532, 2, 0, 4, 904, 0, 2, MipsImpOpBase + 20, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1532 = DSDIV { 1531, 2, 1, 4, 827, 0, 0, MipsImpOpBase + 0, 389, 0, 0x1ULL }, // Inst #1531 = DSBH { 1530, 3, 1, 4, 826, 0, 0, MipsImpOpBase + 0, 755, 0, 0x1ULL }, // Inst #1530 = DROTRV { 1529, 3, 1, 4, 825, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1529 = DROTR32 { 1528, 3, 1, 4, 824, 0, 0, MipsImpOpBase + 0, 232, 0, 0x1ULL }, // Inst #1528 = DROTR { 1527, 4, 1, 4, 1643, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1527 = DPS_W_PH_MMR2 { 1526, 4, 1, 4, 1479, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1526 = DPS_W_PH { 1525, 4, 1, 4, 1646, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1525 = DPSX_W_PH_MMR2 { 1524, 4, 1, 4, 1482, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1524 = DPSX_W_PH { 1523, 4, 1, 4, 1536, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1523 = DPSU_H_QBR_MM { 1522, 4, 1, 4, 1385, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1522 = DPSU_H_QBR { 1521, 4, 1, 4, 1535, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1521 = DPSU_H_QBL_MM { 1520, 4, 1, 4, 1384, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1520 = DPSU_H_QBL { 1519, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 747, 0, 0x6ULL }, // Inst #1519 = DPSUB_U_W { 1518, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 743, 0, 0x6ULL }, // Inst #1518 = DPSUB_U_H { 1517, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1517 = DPSUB_U_D { 1516, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 747, 0, 0x6ULL }, // Inst #1516 = DPSUB_S_W { 1515, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 743, 0, 0x6ULL }, // Inst #1515 = DPSUB_S_H { 1514, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1514 = DPSUB_S_D { 1513, 4, 1, 4, 1534, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1513 = DPSQ_S_W_PH_MM { 1512, 4, 1, 4, 1383, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1512 = DPSQ_S_W_PH { 1511, 4, 1, 4, 1533, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1511 = DPSQ_SA_L_W_MM { 1510, 4, 1, 4, 1382, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1510 = DPSQ_SA_L_W { 1509, 4, 1, 4, 1644, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1509 = DPSQX_S_W_PH_MMR2 { 1508, 4, 1, 4, 1480, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1508 = DPSQX_S_W_PH { 1507, 4, 1, 4, 1645, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1507 = DPSQX_SA_W_PH_MMR2 { 1506, 4, 1, 4, 1481, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1506 = DPSQX_SA_W_PH { 1505, 2, 1, 4, 1204, 0, 0, MipsImpOpBase + 0, 389, 0, 0x1ULL }, // Inst #1505 = DPOP { 1504, 4, 1, 4, 1639, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1504 = DPA_W_PH_MMR2 { 1503, 4, 1, 4, 1475, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1503 = DPA_W_PH { 1502, 4, 1, 4, 1642, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1502 = DPAX_W_PH_MMR2 { 1501, 4, 1, 4, 1478, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1501 = DPAX_W_PH { 1500, 4, 1, 4, 1532, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1500 = DPAU_H_QBR_MM { 1499, 4, 1, 4, 1381, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1499 = DPAU_H_QBR { 1498, 4, 1, 4, 1531, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1498 = DPAU_H_QBL_MM { 1497, 4, 1, 4, 1380, 0, 0, MipsImpOpBase + 0, 751, 0, 0x6ULL }, // Inst #1497 = DPAU_H_QBL { 1496, 4, 1, 4, 1530, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1496 = DPAQ_S_W_PH_MM { 1495, 4, 1, 4, 1379, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1495 = DPAQ_S_W_PH { 1494, 4, 1, 4, 1529, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1494 = DPAQ_SA_L_W_MM { 1493, 4, 1, 4, 1378, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1493 = DPAQ_SA_L_W { 1492, 4, 1, 4, 1641, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1492 = DPAQX_S_W_PH_MMR2 { 1491, 4, 1, 4, 1477, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1491 = DPAQX_S_W_PH { 1490, 4, 1, 4, 1640, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1490 = DPAQX_SA_W_PH_MMR2 { 1489, 4, 1, 4, 1476, 0, 1, MipsImpOpBase + 22, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1489 = DPAQX_SA_W_PH { 1488, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 747, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1488 = DPADD_U_W { 1487, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 743, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1487 = DPADD_U_H { 1486, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 739, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1486 = DPADD_U_D { 1485, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 747, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1485 = DPADD_S_W { 1484, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 743, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1484 = DPADD_S_H { 1483, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 739, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1483 = DPADD_S_D { 1482, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 736, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1482 = DOTP_U_W { 1481, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 733, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1481 = DOTP_U_H { 1480, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 730, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1480 = DOTP_U_D { 1479, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 736, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1479 = DOTP_S_W { 1478, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 733, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1478 = DOTP_S_H { 1477, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 730, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1477 = DOTP_S_D { 1476, 3, 1, 4, 914, 0, 0, MipsImpOpBase + 0, 235, 0, 0x6ULL }, // Inst #1476 = DMUL_R6 { 1475, 3, 1, 4, 901, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1475 = DMULU { 1474, 2, 0, 4, 903, 0, 2, MipsImpOpBase + 20, 389, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #1474 = DMULTu { 1473, 2, 0, 4, 902, 0, 2, MipsImpOpBase + 20, 389, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #1473 = DMULT { 1472, 3, 1, 4, 1210, 0, 5, MipsImpOpBase + 15, 235, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #1472 = DMUL { 1471, 3, 1, 4, 913, 0, 0, MipsImpOpBase + 0, 235, 0, 0x6ULL }, // Inst #1471 = DMUHU { 1470, 3, 1, 4, 912, 0, 0, MipsImpOpBase + 0, 235, 0, 0x6ULL }, // Inst #1470 = DMUH { 1469, 3, 1, 4, 1069, 0, 0, MipsImpOpBase + 0, 724, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1469 = DMTGC0 { 1468, 2, 2, 4, 1203, 0, 0, MipsImpOpBase + 0, 366, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1468 = DMTC2_OCTEON { 1467, 3, 1, 4, 1057, 0, 0, MipsImpOpBase + 0, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1467 = DMTC2 { 1466, 2, 1, 4, 1342, 0, 0, MipsImpOpBase + 0, 416, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #1466 = DMTC1 { 1465, 3, 1, 4, 1055, 0, 0, MipsImpOpBase + 0, 724, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1465 = DMTC0 { 1464, 1, 1, 4, 1060, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1464 = DMT { 1463, 3, 1, 4, 918, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1463 = DMODU { 1462, 3, 1, 4, 916, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1462 = DMOD { 1461, 3, 1, 4, 1068, 0, 0, MipsImpOpBase + 0, 716, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1461 = DMFGC0 { 1460, 2, 2, 4, 1202, 0, 0, MipsImpOpBase + 0, 366, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1460 = DMFC2_OCTEON { 1459, 3, 1, 4, 1056, 0, 0, MipsImpOpBase + 0, 721, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1459 = DMFC2 { 1458, 2, 1, 4, 1341, 0, 0, MipsImpOpBase + 0, 719, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #1458 = DMFC1 { 1457, 3, 1, 4, 1054, 0, 0, MipsImpOpBase + 0, 716, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1457 = DMFC0 { 1456, 4, 1, 4, 851, 0, 0, MipsImpOpBase + 0, 707, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1456 = DLSA_R6 { 1455, 4, 1, 4, 851, 0, 0, MipsImpOpBase + 0, 707, 0, 0x6ULL }, // Inst #1455 = DLSA { 1454, 1, 1, 4, 1049, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1454 = DI_MMR6 { 1453, 1, 1, 4, 1032, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1453 = DI_MM { 1452, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1452 = DIV_U_W { 1451, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1451 = DIV_U_H { 1450, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1450 = DIV_U_D { 1449, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1449 = DIV_U_B { 1448, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1448 = DIV_S_W { 1447, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1447 = DIV_S_H { 1446, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1446 = DIV_S_D { 1445, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1445 = DIV_S_B { 1444, 3, 1, 4, 899, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1444 = DIV_MMR6 { 1443, 3, 1, 4, 898, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1443 = DIVU_MMR6 { 1442, 3, 1, 4, 485, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1442 = DIVU { 1441, 3, 1, 4, 484, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1441 = DIV { 1440, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 711, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1440 = DINSU { 1439, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 711, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1439 = DINSM { 1438, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 711, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1438 = DINS { 1437, 1, 1, 4, 476, 0, 0, MipsImpOpBase + 0, 197, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1437 = DI { 1436, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 651, 0, 0x1ULL }, // Inst #1436 = DEXTU { 1435, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 651, 0, 0x1ULL }, // Inst #1435 = DEXTM { 1434, 4, 1, 4, 807, 0, 0, MipsImpOpBase + 0, 655, 0, 0x1ULL }, // Inst #1434 = DEXT64_32 { 1433, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 651, 0, 0x1ULL }, // Inst #1433 = DEXT { 1432, 0, 0, 4, 989, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1432 = DERET_MMR6 { 1431, 0, 0, 4, 953, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1431 = DERET_MM { 1430, 0, 0, 4, 380, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1430 = DERET { 1429, 3, 1, 4, 917, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1429 = DDIVU { 1428, 3, 1, 4, 915, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1428 = DDIV { 1427, 2, 1, 4, 849, 0, 0, MipsImpOpBase + 0, 389, 0, 0x6ULL }, // Inst #1427 = DCLZ_R6 { 1426, 2, 1, 4, 821, 0, 0, MipsImpOpBase + 0, 389, 0, 0x1ULL }, // Inst #1426 = DCLZ { 1425, 2, 1, 4, 848, 0, 0, MipsImpOpBase + 0, 389, 0, 0x6ULL }, // Inst #1425 = DCLO_R6 { 1424, 2, 1, 4, 820, 0, 0, MipsImpOpBase + 0, 389, 0, 0x1ULL }, // Inst #1424 = DCLO { 1423, 2, 1, 4, 850, 0, 0, MipsImpOpBase + 0, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1423 = DBITSWAP { 1422, 3, 1, 4, 847, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1422 = DAUI { 1421, 3, 1, 4, 846, 0, 0, MipsImpOpBase + 0, 704, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1421 = DATI { 1420, 4, 1, 4, 844, 0, 0, MipsImpOpBase + 0, 707, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1420 = DALIGN { 1419, 3, 1, 4, 845, 0, 0, MipsImpOpBase + 0, 704, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1419 = DAHI { 1418, 3, 1, 4, 819, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #1418 = DADDu { 1417, 3, 1, 4, 818, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // Inst #1417 = DADDiu { 1416, 3, 1, 4, 817, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1416 = DADDi { 1415, 3, 1, 4, 816, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1415 = DADD { 1414, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 580, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1414 = CmpiRxImmX16 { 1413, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 580, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1413 = CmpiRxImm16 { 1412, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 406, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1412 = CmpRxRy16 { 1411, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1411 = C_UN_S_MM { 1410, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1410 = C_UN_S { 1409, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1409 = C_UN_D64_MM { 1408, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1408 = C_UN_D64 { 1407, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1407 = C_UN_D32_MM { 1406, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1406 = C_UN_D32 { 1405, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1405 = C_ULT_S_MM { 1404, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1404 = C_ULT_S { 1403, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1403 = C_ULT_D64_MM { 1402, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1402 = C_ULT_D64 { 1401, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1401 = C_ULT_D32_MM { 1400, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1400 = C_ULT_D32 { 1399, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1399 = C_ULE_S_MM { 1398, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1398 = C_ULE_S { 1397, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1397 = C_ULE_D64_MM { 1396, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1396 = C_ULE_D64 { 1395, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1395 = C_ULE_D32_MM { 1394, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1394 = C_ULE_D32 { 1393, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1393 = C_UEQ_S_MM { 1392, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1392 = C_UEQ_S { 1391, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1391 = C_UEQ_D64_MM { 1390, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1390 = C_UEQ_D64 { 1389, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1389 = C_UEQ_D32_MM { 1388, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1388 = C_UEQ_D32 { 1387, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1387 = C_SF_S_MM { 1386, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1386 = C_SF_S { 1385, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1385 = C_SF_D64_MM { 1384, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1384 = C_SF_D64 { 1383, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1383 = C_SF_D32_MM { 1382, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1382 = C_SF_D32 { 1381, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1381 = C_SEQ_S_MM { 1380, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1380 = C_SEQ_S { 1379, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1379 = C_SEQ_D64_MM { 1378, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1378 = C_SEQ_D64 { 1377, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1377 = C_SEQ_D32_MM { 1376, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1376 = C_SEQ_D32 { 1375, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1375 = C_OLT_S_MM { 1374, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1374 = C_OLT_S { 1373, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1373 = C_OLT_D64_MM { 1372, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1372 = C_OLT_D64 { 1371, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1371 = C_OLT_D32_MM { 1370, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1370 = C_OLT_D32 { 1369, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1369 = C_OLE_S_MM { 1368, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1368 = C_OLE_S { 1367, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1367 = C_OLE_D64_MM { 1366, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1366 = C_OLE_D64 { 1365, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1365 = C_OLE_D32_MM { 1364, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1364 = C_OLE_D32 { 1363, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1363 = C_NGT_S_MM { 1362, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1362 = C_NGT_S { 1361, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1361 = C_NGT_D64_MM { 1360, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1360 = C_NGT_D64 { 1359, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1359 = C_NGT_D32_MM { 1358, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1358 = C_NGT_D32 { 1357, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1357 = C_NGL_S_MM { 1356, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1356 = C_NGL_S { 1355, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1355 = C_NGL_D64_MM { 1354, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1354 = C_NGL_D64 { 1353, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1353 = C_NGL_D32_MM { 1352, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1352 = C_NGL_D32 { 1351, 3, 1, 4, 1265, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1351 = C_NGLE_S_MM { 1350, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1350 = C_NGLE_S { 1349, 3, 1, 4, 1264, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1349 = C_NGLE_D64_MM { 1348, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1348 = C_NGLE_D64 { 1347, 3, 1, 4, 1264, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1347 = C_NGLE_D32_MM { 1346, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1346 = C_NGLE_D32 { 1345, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1345 = C_NGE_S_MM { 1344, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1344 = C_NGE_S { 1343, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1343 = C_NGE_D64_MM { 1342, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1342 = C_NGE_D64 { 1341, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1341 = C_NGE_D32_MM { 1340, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1340 = C_NGE_D32 { 1339, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1339 = C_LT_S_MM { 1338, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1338 = C_LT_S { 1337, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1337 = C_LT_D64_MM { 1336, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1336 = C_LT_D64 { 1335, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1335 = C_LT_D32_MM { 1334, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1334 = C_LT_D32 { 1333, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1333 = C_LE_S_MM { 1332, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1332 = C_LE_S { 1331, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1331 = C_LE_D64_MM { 1330, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1330 = C_LE_D64 { 1329, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1329 = C_LE_D32_MM { 1328, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1328 = C_LE_D32 { 1327, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1327 = C_F_S_MM { 1326, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1326 = C_F_S { 1325, 3, 1, 4, 1258, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1325 = C_F_D64_MM { 1324, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1324 = C_F_D64 { 1323, 3, 1, 4, 1258, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1323 = C_F_D32_MM { 1322, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1322 = C_F_D32 { 1321, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1321 = C_EQ_S_MM { 1320, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 701, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1320 = C_EQ_S { 1319, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1319 = C_EQ_D64_MM { 1318, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 698, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1318 = C_EQ_D64 { 1317, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1317 = C_EQ_D32_MM { 1316, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1316 = C_EQ_D32 { 1315, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1315 = CVT_W_S_MMR6 { 1314, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1314 = CVT_W_S_MM { 1313, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1313 = CVT_W_S { 1312, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #1312 = CVT_W_D64_MM { 1311, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #1311 = CVT_W_D64 { 1310, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #1310 = CVT_W_D32_MM { 1309, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #1309 = CVT_W_D32 { 1308, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1308 = CVT_S_W_MMR6 { 1307, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1307 = CVT_S_W_MM { 1306, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1306 = CVT_S_W { 1305, 2, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #1305 = CVT_S_PU64 { 1304, 2, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #1304 = CVT_S_PL64 { 1303, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1303 = CVT_S_L_MMR6 { 1302, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #1302 = CVT_S_L { 1301, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #1301 = CVT_S_D64_MM { 1300, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #1300 = CVT_S_D64 { 1299, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #1299 = CVT_S_D32_MM { 1298, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #1298 = CVT_S_D32 { 1297, 2, 1, 4, 1213, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1297 = CVT_PW_PS64 { 1296, 3, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 692, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1296 = CVT_PS_S64 { 1295, 2, 1, 4, 1213, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1295 = CVT_PS_PW64 { 1294, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1294 = CVT_L_S_MMR6 { 1293, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1293 = CVT_L_S_MM { 1292, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1292 = CVT_L_S { 1291, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1291 = CVT_L_D_MMR6 { 1290, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1290 = CVT_L_D64_MM { 1289, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1289 = CVT_L_D64 { 1288, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1288 = CVT_D_L_MMR6 { 1287, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1287 = CVT_D64_W_MM { 1286, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1286 = CVT_D64_W { 1285, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1285 = CVT_D64_S_MM { 1284, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1284 = CVT_D64_S { 1283, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1283 = CVT_D64_L { 1282, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 690, 0, 0x4ULL }, // Inst #1282 = CVT_D32_W_MM { 1281, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 690, 0, 0x4ULL }, // Inst #1281 = CVT_D32_W { 1280, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 690, 0, 0x4ULL }, // Inst #1280 = CVT_D32_S_MM { 1279, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 690, 0, 0x4ULL }, // Inst #1279 = CVT_D32_S { 1278, 2, 0, 4, 529, 0, 0, MipsImpOpBase + 0, 688, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1278 = CTCMSA { 1277, 2, 1, 4, 1059, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1277 = CTC2_MM { 1276, 2, 1, 4, 1296, 0, 0, MipsImpOpBase + 0, 684, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1276 = CTC1_MM { 1275, 2, 1, 4, 685, 0, 0, MipsImpOpBase + 0, 684, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1275 = CTC1 { 1274, 3, 1, 4, 1193, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1274 = CRC32W { 1273, 3, 1, 4, 1192, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1273 = CRC32H { 1272, 3, 1, 4, 1197, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1272 = CRC32D { 1271, 3, 1, 4, 1196, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1271 = CRC32CW { 1270, 3, 1, 4, 1195, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1270 = CRC32CH { 1269, 3, 1, 4, 1198, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1269 = CRC32CD { 1268, 3, 1, 4, 1194, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1268 = CRC32CB { 1267, 3, 1, 4, 1191, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1267 = CRC32B { 1266, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 681, 0, 0x6ULL }, // Inst #1266 = COPY_U_W { 1265, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 678, 0, 0x6ULL }, // Inst #1265 = COPY_U_H { 1264, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 672, 0, 0x6ULL }, // Inst #1264 = COPY_U_B { 1263, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 681, 0, 0x6ULL }, // Inst #1263 = COPY_S_W { 1262, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 678, 0, 0x6ULL }, // Inst #1262 = COPY_S_H { 1261, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 675, 0, 0x6ULL }, // Inst #1261 = COPY_S_D { 1260, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 672, 0, 0x6ULL }, // Inst #1260 = COPY_S_B { 1259, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1259 = CMP_UN_S_MMR6 { 1258, 3, 1, 4, 558, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1258 = CMP_UN_S { 1257, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1257 = CMP_UN_D_MMR6 { 1256, 3, 1, 4, 557, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1256 = CMP_UN_D { 1255, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1255 = CMP_ULT_S_MMR6 { 1254, 3, 1, 4, 566, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1254 = CMP_ULT_S { 1253, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1253 = CMP_ULT_D_MMR6 { 1252, 3, 1, 4, 565, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1252 = CMP_ULT_D { 1251, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1251 = CMP_ULE_S_MMR6 { 1250, 3, 1, 4, 570, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1250 = CMP_ULE_S { 1249, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1249 = CMP_ULE_D_MMR6 { 1248, 3, 1, 4, 569, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1248 = CMP_ULE_D { 1247, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1247 = CMP_UEQ_S_MMR6 { 1246, 3, 1, 4, 560, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1246 = CMP_UEQ_S { 1245, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1245 = CMP_UEQ_D_MMR6 { 1244, 3, 1, 4, 559, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1244 = CMP_UEQ_D { 1243, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1243 = CMP_SUN_S_MMR6 { 1242, 3, 1, 4, 1689, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1242 = CMP_SUN_S { 1241, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1241 = CMP_SUN_D_MMR6 { 1240, 3, 1, 4, 1688, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1240 = CMP_SUN_D { 1239, 3, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1239 = CMP_SULT_S_MMR6 { 1238, 3, 1, 4, 1687, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1238 = CMP_SULT_S { 1237, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1237 = CMP_SULT_D_MMR6 { 1236, 3, 1, 4, 1686, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1236 = CMP_SULT_D { 1235, 3, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1235 = CMP_SULE_S_MMR6 { 1234, 3, 1, 4, 1685, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1234 = CMP_SULE_S { 1233, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1233 = CMP_SULE_D_MMR6 { 1232, 3, 1, 4, 1684, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1232 = CMP_SULE_D { 1231, 3, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1231 = CMP_SUEQ_S_MMR6 { 1230, 3, 1, 4, 1683, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1230 = CMP_SUEQ_S { 1229, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1229 = CMP_SUEQ_D_MMR6 { 1228, 3, 1, 4, 1682, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1228 = CMP_SUEQ_D { 1227, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1227 = CMP_SLT_S_MMR6 { 1226, 3, 1, 4, 1681, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1226 = CMP_SLT_S { 1225, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1225 = CMP_SLT_D_MMR6 { 1224, 3, 1, 4, 1680, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1224 = CMP_SLT_D { 1223, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1223 = CMP_SLE_S_MMR6 { 1222, 3, 1, 4, 1679, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1222 = CMP_SLE_S { 1221, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1221 = CMP_SLE_D_MMR6 { 1220, 3, 1, 4, 1678, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1220 = CMP_SLE_D { 1219, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1219 = CMP_SEQ_S_MMR6 { 1218, 3, 1, 4, 1677, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1218 = CMP_SEQ_S { 1217, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1217 = CMP_SEQ_D_MMR6 { 1216, 3, 1, 4, 1676, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1216 = CMP_SEQ_D { 1215, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1215 = CMP_SAF_S_MMR6 { 1214, 3, 1, 4, 1675, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1214 = CMP_SAF_S { 1213, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1213 = CMP_SAF_D_MMR6 { 1212, 3, 1, 4, 1674, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1212 = CMP_SAF_D { 1211, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1211 = CMP_LT_S_MMR6 { 1210, 3, 1, 4, 564, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1210 = CMP_LT_S { 1209, 2, 0, 4, 1528, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1209 = CMP_LT_PH_MM { 1208, 2, 0, 4, 1377, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1208 = CMP_LT_PH { 1207, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1207 = CMP_LT_D_MMR6 { 1206, 3, 1, 4, 563, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1206 = CMP_LT_D { 1205, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1205 = CMP_LE_S_MMR6 { 1204, 3, 1, 4, 568, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1204 = CMP_LE_S { 1203, 2, 0, 4, 1527, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1203 = CMP_LE_PH_MM { 1202, 2, 0, 4, 1376, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1202 = CMP_LE_PH { 1201, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1201 = CMP_LE_D_MMR6 { 1200, 3, 1, 4, 567, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1200 = CMP_LE_D { 1199, 3, 1, 4, 1673, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1199 = CMP_F_S { 1198, 3, 1, 4, 1672, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1198 = CMP_F_D { 1197, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1197 = CMP_EQ_S_MMR6 { 1196, 3, 1, 4, 562, 0, 0, MipsImpOpBase + 0, 669, 0, 0x16ULL }, // Inst #1196 = CMP_EQ_S { 1195, 2, 0, 4, 1526, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1195 = CMP_EQ_PH_MM { 1194, 2, 0, 4, 1375, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1194 = CMP_EQ_PH { 1193, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1193 = CMP_EQ_D_MMR6 { 1192, 3, 1, 4, 561, 0, 0, MipsImpOpBase + 0, 666, 0, 0x16ULL }, // Inst #1192 = CMP_EQ_D { 1191, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1191 = CMP_AF_S_MMR6 { 1190, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1190 = CMP_AF_D_MMR6 { 1189, 2, 0, 4, 1525, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1189 = CMPU_LT_QB_MM { 1188, 2, 0, 4, 1374, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1188 = CMPU_LT_QB { 1187, 2, 0, 4, 1524, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1187 = CMPU_LE_QB_MM { 1186, 2, 0, 4, 1373, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1186 = CMPU_LE_QB { 1185, 2, 0, 4, 1523, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1185 = CMPU_EQ_QB_MM { 1184, 2, 0, 4, 1372, 0, 1, MipsImpOpBase + 14, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1184 = CMPU_EQ_QB { 1183, 3, 1, 4, 1522, 0, 0, MipsImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1183 = CMPGU_LT_QB_MM { 1182, 3, 1, 4, 1371, 0, 0, MipsImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1182 = CMPGU_LT_QB { 1181, 3, 1, 4, 1521, 0, 0, MipsImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1181 = CMPGU_LE_QB_MM { 1180, 3, 1, 4, 1370, 0, 0, MipsImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1180 = CMPGU_LE_QB { 1179, 3, 1, 4, 1520, 0, 0, MipsImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1179 = CMPGU_EQ_QB_MM { 1178, 3, 1, 4, 1369, 0, 0, MipsImpOpBase + 0, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1178 = CMPGU_EQ_QB { 1177, 3, 1, 4, 1638, 0, 1, MipsImpOpBase + 14, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1177 = CMPGDU_LT_QB_MMR2 { 1176, 3, 1, 4, 1474, 0, 1, MipsImpOpBase + 14, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1176 = CMPGDU_LT_QB { 1175, 3, 1, 4, 1637, 0, 1, MipsImpOpBase + 14, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1175 = CMPGDU_LE_QB_MMR2 { 1174, 3, 1, 4, 1473, 0, 1, MipsImpOpBase + 14, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1174 = CMPGDU_LE_QB { 1173, 3, 1, 4, 1636, 0, 1, MipsImpOpBase + 14, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1173 = CMPGDU_EQ_QB_MMR2 { 1172, 3, 1, 4, 1472, 0, 1, MipsImpOpBase + 14, 663, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1172 = CMPGDU_EQ_QB { 1171, 2, 1, 4, 732, 0, 0, MipsImpOpBase + 0, 152, 0, 0x6ULL }, // Inst #1171 = CLZ_R6 { 1170, 2, 1, 4, 786, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1170 = CLZ_MMR6 { 1169, 2, 1, 4, 745, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #1169 = CLZ_MM { 1168, 2, 1, 4, 475, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #1168 = CLZ { 1167, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1167 = CLT_U_W { 1166, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1166 = CLT_U_H { 1165, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1165 = CLT_U_D { 1164, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1164 = CLT_U_B { 1163, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1163 = CLT_S_W { 1162, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1162 = CLT_S_H { 1161, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1161 = CLT_S_D { 1160, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1160 = CLT_S_B { 1159, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #1159 = CLTI_U_W { 1158, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #1158 = CLTI_U_H { 1157, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #1157 = CLTI_U_D { 1156, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #1156 = CLTI_U_B { 1155, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #1155 = CLTI_S_W { 1154, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #1154 = CLTI_S_H { 1153, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #1153 = CLTI_S_D { 1152, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #1152 = CLTI_S_B { 1151, 2, 1, 4, 731, 0, 0, MipsImpOpBase + 0, 152, 0, 0x6ULL }, // Inst #1151 = CLO_R6 { 1150, 2, 1, 4, 785, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1150 = CLO_MMR6 { 1149, 2, 1, 4, 744, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #1149 = CLO_MM { 1148, 2, 1, 4, 474, 0, 0, MipsImpOpBase + 0, 152, 0, 0x1ULL }, // Inst #1148 = CLO { 1147, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1147 = CLE_U_W { 1146, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1146 = CLE_U_H { 1145, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1145 = CLE_U_D { 1144, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1144 = CLE_U_B { 1143, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1143 = CLE_S_W { 1142, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1142 = CLE_S_H { 1141, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1141 = CLE_S_D { 1140, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1140 = CLE_S_B { 1139, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #1139 = CLEI_U_W { 1138, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #1138 = CLEI_U_H { 1137, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #1137 = CLEI_U_D { 1136, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #1136 = CLEI_U_B { 1135, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #1135 = CLEI_S_W { 1134, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #1134 = CLEI_S_H { 1133, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #1133 = CLEI_S_D { 1132, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #1132 = CLEI_S_B { 1131, 2, 1, 4, 1315, 0, 0, MipsImpOpBase + 0, 643, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1131 = CLASS_S_MMR6 { 1130, 2, 1, 4, 1228, 0, 0, MipsImpOpBase + 0, 643, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1130 = CLASS_S { 1129, 2, 1, 4, 1315, 0, 0, MipsImpOpBase + 0, 635, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1129 = CLASS_D_MMR6 { 1128, 2, 1, 4, 1229, 0, 0, MipsImpOpBase + 0, 635, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1128 = CLASS_D { 1127, 4, 1, 4, 1201, 0, 0, MipsImpOpBase + 0, 659, 0, 0x1ULL }, // Inst #1127 = CINS_i32 { 1126, 4, 1, 4, 1201, 0, 0, MipsImpOpBase + 0, 655, 0, 0x1ULL }, // Inst #1126 = CINS64_32 { 1125, 4, 1, 4, 1201, 0, 0, MipsImpOpBase + 0, 651, 0, 0x1ULL }, // Inst #1125 = CINS32 { 1124, 4, 1, 4, 1201, 0, 0, MipsImpOpBase + 0, 651, 0, 0x1ULL }, // Inst #1124 = CINS { 1123, 2, 1, 4, 529, 0, 0, MipsImpOpBase + 0, 649, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1123 = CFCMSA { 1122, 2, 1, 4, 1058, 0, 0, MipsImpOpBase + 0, 647, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1122 = CFC2_MM { 1121, 2, 1, 4, 1295, 0, 0, MipsImpOpBase + 0, 645, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1121 = CFC1_MM { 1120, 2, 1, 4, 694, 0, 0, MipsImpOpBase + 0, 645, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1120 = CFC1 { 1119, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1119 = CEQ_W { 1118, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1118 = CEQ_H { 1117, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1117 = CEQ_D { 1116, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1116 = CEQ_B { 1115, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #1115 = CEQI_W { 1114, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #1114 = CEQI_H { 1113, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #1113 = CEQI_D { 1112, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #1112 = CEQI_B { 1111, 2, 1, 4, 1312, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1111 = CEIL_W_S_MMR6 { 1110, 2, 1, 4, 1248, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1110 = CEIL_W_S_MM { 1109, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 643, 0, 0x4ULL }, // Inst #1109 = CEIL_W_S { 1108, 2, 1, 4, 1248, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #1108 = CEIL_W_MM { 1107, 2, 1, 4, 1312, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #1107 = CEIL_W_D_MMR6 { 1106, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 641, 0, 0x4ULL }, // Inst #1106 = CEIL_W_D64 { 1105, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 639, 0, 0x4ULL }, // Inst #1105 = CEIL_W_D32 { 1104, 2, 1, 4, 1312, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1104 = CEIL_L_S_MMR6 { 1103, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 637, 0, 0x4ULL }, // Inst #1103 = CEIL_L_S { 1102, 2, 1, 4, 1312, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1102 = CEIL_L_D_MMR6 { 1101, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 635, 0, 0x4ULL }, // Inst #1101 = CEIL_L_D64 { 1100, 3, 0, 4, 1089, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1100 = CACHE_R6 { 1099, 3, 0, 4, 1163, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1099 = CACHE_MMR6 { 1098, 3, 0, 4, 1141, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1098 = CACHE_MM { 1097, 3, 0, 4, 1108, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1097 = CACHEE_MM { 1096, 3, 0, 4, 471, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1096 = CACHEE { 1095, 3, 0, 4, 470, 0, 0, MipsImpOpBase + 0, 632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1095 = CACHE { 1094, 1, 0, 4, 940, 1, 0, MipsImpOpBase + 9, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1094 = BtnezX16 { 1093, 1, 0, 2, 940, 1, 0, MipsImpOpBase + 9, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1093 = Btnez16 { 1092, 1, 0, 4, 940, 1, 0, MipsImpOpBase + 9, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1092 = BteqzX16 { 1091, 1, 0, 2, 940, 1, 0, MipsImpOpBase + 9, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1091 = Bteqz16 { 1090, 0, 0, 2, 944, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1090 = Break16 { 1089, 2, 0, 4, 940, 0, 0, MipsImpOpBase + 0, 630, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1089 = BnezRxImmX16 { 1088, 2, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 630, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1088 = BnezRxImm16 { 1087, 1, 0, 4, 940, 0, 0, MipsImpOpBase + 0, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1087 = BimmX16 { 1086, 1, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1086 = Bimm16 { 1085, 2, 0, 4, 940, 0, 0, MipsImpOpBase + 0, 630, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1085 = BeqzRxImmX16 { 1084, 2, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 630, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1084 = BeqzRxImm16 { 1083, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 628, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1083 = BZ_W { 1082, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 622, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1082 = BZ_V { 1081, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 626, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1081 = BZ_H { 1080, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 624, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1080 = BZ_D { 1079, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 622, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1079 = BZ_B { 1078, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1078 = BSET_W { 1077, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1077 = BSET_H { 1076, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1076 = BSET_D { 1075, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1075 = BSET_B { 1074, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #1074 = BSETI_W { 1073, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #1073 = BSETI_H { 1072, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #1072 = BSETI_D { 1071, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #1071 = BSETI_B { 1070, 4, 1, 4, 523, 0, 0, MipsImpOpBase + 0, 618, 0, 0x6ULL }, // Inst #1070 = BSEL_V { 1069, 4, 1, 4, 523, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #1069 = BSELI_B { 1068, 2, 0, 4, 1008, 0, 0, MipsImpOpBase + 0, 13, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1068 = BREAK_MMR6 { 1067, 2, 0, 4, 967, 0, 0, MipsImpOpBase + 0, 13, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1067 = BREAK_MM { 1066, 1, 0, 2, 1008, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1066 = BREAK16_MMR6 { 1065, 1, 0, 2, 967, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1065 = BREAK16_MM { 1064, 2, 0, 4, 379, 0, 0, MipsImpOpBase + 0, 13, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1064 = BREAK { 1063, 1, 0, 4, 1519, 0, 0, MipsImpOpBase + 0, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1063 = BPOSGE32_MM { 1062, 1, 0, 4, 1671, 0, 0, MipsImpOpBase + 0, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1062 = BPOSGE32C_MMR3 { 1061, 1, 0, 4, 1368, 0, 0, MipsImpOpBase + 0, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1061 = BPOSGE32 { 1060, 3, 0, 4, 986, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1060 = BOVC_MMR6 { 1059, 3, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1059 = BOVC { 1058, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 628, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1058 = BNZ_W { 1057, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 622, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1057 = BNZ_V { 1056, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 626, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1056 = BNZ_H { 1055, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 624, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1055 = BNZ_D { 1054, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 622, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1054 = BNZ_B { 1053, 3, 0, 4, 986, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1053 = BNVC_MMR6 { 1052, 3, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1052 = BNVC { 1051, 3, 0, 4, 952, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1051 = BNE_MM { 1050, 2, 0, 4, 988, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // Inst #1050 = BNEZC_MMR6 { 1049, 2, 0, 4, 951, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1049 = BNEZC_MM { 1048, 2, 0, 4, 1019, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1048 = BNEZC64 { 1047, 2, 0, 2, 987, 0, 1, MipsImpOpBase + 2, 600, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1047 = BNEZC16_MMR6 { 1046, 2, 0, 4, 933, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1046 = BNEZC { 1045, 2, 0, 4, 1001, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1045 = BNEZALC_MMR6 { 1044, 2, 0, 4, 928, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1044 = BNEZALC { 1043, 2, 0, 2, 950, 0, 1, MipsImpOpBase + 2, 600, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1043 = BNEZ16_MM { 1042, 3, 0, 4, 377, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #1042 = BNEL { 1041, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #1041 = BNEG_W { 1040, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #1040 = BNEG_H { 1039, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #1039 = BNEG_D { 1038, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1038 = BNEG_B { 1037, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #1037 = BNEGI_W { 1036, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #1036 = BNEGI_H { 1035, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #1035 = BNEGI_D { 1034, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #1034 = BNEGI_B { 1033, 3, 0, 4, 986, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1033 = BNEC_MMR6 { 1032, 3, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 351, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1032 = BNEC64 { 1031, 3, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1031 = BNEC { 1030, 3, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 351, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1030 = BNE64 { 1029, 3, 0, 4, 920, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1029 = BNE { 1028, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 618, 0, 0x6ULL }, // Inst #1028 = BMZ_V { 1027, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #1027 = BMZI_B { 1026, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 618, 0, 0x6ULL }, // Inst #1026 = BMNZ_V { 1025, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #1025 = BMNZI_B { 1024, 2, 0, 4, 950, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1024 = BLTZ_MM { 1023, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #1023 = BLTZL { 1022, 2, 0, 4, 988, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1022 = BLTZC_MMR6 { 1021, 2, 0, 4, 1019, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1021 = BLTZC64 { 1020, 2, 0, 4, 933, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1020 = BLTZC { 1019, 2, 0, 4, 959, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #1019 = BLTZAL_MM { 1018, 2, 0, 4, 958, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1018 = BLTZALS_MM { 1017, 2, 0, 4, 376, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #1017 = BLTZALL { 1016, 2, 0, 4, 1001, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1016 = BLTZALC_MMR6 { 1015, 2, 0, 4, 928, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1015 = BLTZALC { 1014, 2, 0, 4, 919, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #1014 = BLTZAL { 1013, 2, 0, 4, 1011, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1013 = BLTZ64 { 1012, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1012 = BLTZ { 1011, 3, 0, 4, 986, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1011 = BLTUC_MMR6 { 1010, 3, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 351, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1010 = BLTUC64 { 1009, 3, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1009 = BLTUC { 1008, 3, 0, 4, 986, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1008 = BLTC_MMR6 { 1007, 3, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 351, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1007 = BLTC64 { 1006, 3, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1006 = BLTC { 1005, 2, 0, 4, 950, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1005 = BLEZ_MM { 1004, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #1004 = BLEZL { 1003, 2, 0, 4, 988, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1003 = BLEZC_MMR6 { 1002, 2, 0, 4, 1019, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1002 = BLEZC64 { 1001, 2, 0, 4, 933, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1001 = BLEZC { 1000, 2, 0, 4, 1001, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1000 = BLEZALC_MMR6 { 999, 2, 0, 4, 928, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #999 = BLEZALC { 998, 2, 0, 4, 1011, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #998 = BLEZ64 { 997, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #997 = BLEZ { 996, 2, 1, 4, 784, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #996 = BITSWAP_MMR6 { 995, 2, 1, 4, 730, 0, 0, MipsImpOpBase + 0, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #995 = BITSWAP { 994, 2, 1, 4, 1518, 0, 0, MipsImpOpBase + 0, 152, 0, 0x6ULL }, // Inst #994 = BITREV_MM { 993, 2, 1, 4, 1367, 0, 0, MipsImpOpBase + 0, 152, 0, 0x6ULL }, // Inst #993 = BITREV { 992, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #992 = BINSR_W { 991, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 206, 0, 0x6ULL }, // Inst #991 = BINSR_H { 990, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 198, 0, 0x6ULL }, // Inst #990 = BINSR_D { 989, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 618, 0, 0x6ULL }, // Inst #989 = BINSR_B { 988, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 614, 0, 0x6ULL }, // Inst #988 = BINSRI_W { 987, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 610, 0, 0x6ULL }, // Inst #987 = BINSRI_H { 986, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 606, 0, 0x6ULL }, // Inst #986 = BINSRI_D { 985, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #985 = BINSRI_B { 984, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 202, 0, 0x6ULL }, // Inst #984 = BINSL_W { 983, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 206, 0, 0x6ULL }, // Inst #983 = BINSL_H { 982, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 198, 0, 0x6ULL }, // Inst #982 = BINSL_D { 981, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 618, 0, 0x6ULL }, // Inst #981 = BINSL_B { 980, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 614, 0, 0x6ULL }, // Inst #980 = BINSLI_W { 979, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 610, 0, 0x6ULL }, // Inst #979 = BINSLI_H { 978, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 606, 0, 0x6ULL }, // Inst #978 = BINSLI_D { 977, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #977 = BINSLI_B { 976, 2, 0, 4, 950, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #976 = BGTZ_MM { 975, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #975 = BGTZL { 974, 2, 0, 4, 988, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #974 = BGTZC_MMR6 { 973, 2, 0, 4, 1019, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #973 = BGTZC64 { 972, 2, 0, 4, 933, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #972 = BGTZC { 971, 2, 0, 4, 1001, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #971 = BGTZALC_MMR6 { 970, 2, 0, 4, 928, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #970 = BGTZALC { 969, 2, 0, 4, 1011, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #969 = BGTZ64 { 968, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #968 = BGTZ { 967, 2, 0, 4, 950, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #967 = BGEZ_MM { 966, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #966 = BGEZL { 965, 2, 0, 4, 988, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #965 = BGEZC_MMR6 { 964, 2, 0, 4, 1019, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #964 = BGEZC64 { 963, 2, 0, 4, 933, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #963 = BGEZC { 962, 2, 0, 4, 959, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #962 = BGEZAL_MM { 961, 2, 0, 4, 958, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #961 = BGEZALS_MM { 960, 2, 0, 4, 376, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #960 = BGEZALL { 959, 2, 0, 4, 1001, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #959 = BGEZALC_MMR6 { 958, 2, 0, 4, 928, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #958 = BGEZALC { 957, 2, 0, 4, 926, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #957 = BGEZAL { 956, 2, 0, 4, 1011, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #956 = BGEZ64 { 955, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #955 = BGEZ { 954, 3, 0, 4, 986, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #954 = BGEUC_MMR6 { 953, 3, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 351, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #953 = BGEUC64 { 952, 3, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #952 = BGEUC { 951, 3, 0, 4, 986, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #951 = BGEC_MMR6 { 950, 3, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 351, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #950 = BGEC64 { 949, 3, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #949 = BGEC { 948, 3, 0, 4, 952, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #948 = BEQ_MM { 947, 2, 0, 4, 988, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // Inst #947 = BEQZC_MMR6 { 946, 2, 0, 4, 951, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #946 = BEQZC_MM { 945, 2, 0, 4, 1019, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #945 = BEQZC64 { 944, 2, 0, 2, 987, 0, 1, MipsImpOpBase + 2, 600, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #944 = BEQZC16_MMR6 { 943, 2, 0, 4, 933, 0, 1, MipsImpOpBase + 2, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #943 = BEQZC { 942, 2, 0, 4, 1001, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #942 = BEQZALC_MMR6 { 941, 2, 0, 4, 928, 0, 1, MipsImpOpBase + 3, 357, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #941 = BEQZALC { 940, 2, 0, 2, 950, 0, 1, MipsImpOpBase + 2, 600, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #940 = BEQZ16_MM { 939, 3, 0, 4, 377, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #939 = BEQL { 938, 3, 0, 4, 986, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #938 = BEQC_MMR6 { 937, 3, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 351, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #937 = BEQC64 { 936, 3, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #936 = BEQC { 935, 3, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 351, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #935 = BEQ64 { 934, 3, 0, 4, 920, 0, 1, MipsImpOpBase + 2, 194, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #934 = BEQ { 933, 1, 0, 4, 983, 0, 0, MipsImpOpBase + 0, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x16ULL }, // Inst #933 = BC_MMR6 { 932, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #932 = BCLR_W { 931, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #931 = BCLR_H { 930, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #930 = BCLR_D { 929, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #929 = BCLR_B { 928, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #928 = BCLRI_W { 927, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #927 = BCLRI_H { 926, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #926 = BCLRI_D { 925, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #925 = BCLRI_B { 924, 2, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 598, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #924 = BC2NEZC_MMR6 { 923, 2, 0, 4, 931, 0, 0, MipsImpOpBase + 0, 598, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #923 = BC2NEZ { 922, 2, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 598, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #922 = BC2EQZC_MMR6 { 921, 2, 0, 4, 931, 0, 0, MipsImpOpBase + 0, 598, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #921 = BC2EQZ { 920, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 596, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // Inst #920 = BC1T_MM { 919, 2, 0, 4, 693, 0, 1, MipsImpOpBase + 2, 596, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL }, // Inst #919 = BC1TL { 918, 2, 0, 4, 692, 0, 1, MipsImpOpBase + 2, 596, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // Inst #918 = BC1T { 917, 2, 0, 4, 984, 0, 1, MipsImpOpBase + 2, 594, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #917 = BC1NEZC_MMR6 { 916, 2, 0, 4, 1232, 0, 0, MipsImpOpBase + 0, 594, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #916 = BC1NEZ { 915, 2, 0, 4, 948, 0, 1, MipsImpOpBase + 2, 596, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // Inst #915 = BC1F_MM { 914, 2, 0, 4, 691, 0, 1, MipsImpOpBase + 2, 596, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL }, // Inst #914 = BC1FL { 913, 2, 0, 4, 690, 0, 1, MipsImpOpBase + 2, 596, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // Inst #913 = BC1F { 912, 2, 0, 4, 984, 0, 1, MipsImpOpBase + 2, 594, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #912 = BC1EQZC_MMR6 { 911, 2, 0, 4, 1232, 0, 0, MipsImpOpBase + 0, 594, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #911 = BC1EQZ { 910, 1, 0, 2, 983, 0, 1, MipsImpOpBase + 2, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #910 = BC16_MMR6 { 909, 1, 0, 4, 930, 0, 0, MipsImpOpBase + 0, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #909 = BC { 908, 3, 0, 4, 1200, 0, 1, MipsImpOpBase + 2, 591, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // Inst #908 = BBIT132 { 907, 3, 0, 4, 1200, 0, 1, MipsImpOpBase + 2, 591, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // Inst #907 = BBIT1 { 906, 3, 0, 4, 1200, 0, 1, MipsImpOpBase + 2, 591, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // Inst #906 = BBIT032 { 905, 3, 0, 4, 1200, 0, 1, MipsImpOpBase + 2, 591, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // Inst #905 = BBIT0 { 904, 4, 1, 4, 1635, 0, 0, MipsImpOpBase + 0, 576, 0, 0x6ULL }, // Inst #904 = BALIGN_MMR2 { 903, 4, 1, 4, 1471, 0, 0, MipsImpOpBase + 0, 576, 0, 0x6ULL }, // Inst #903 = BALIGN { 902, 1, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #902 = BALC_MMR6 { 901, 1, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #901 = BALC { 900, 1, 0, 4, 375, 0, 1, MipsImpOpBase + 3, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #900 = BAL { 899, 3, 1, 4, 1199, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #899 = BADDu { 898, 1, 0, 2, 946, 0, 1, MipsImpOpBase + 2, 190, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #898 = B16_MM { 897, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 588, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #897 = AndRxRxRy16 { 896, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 408, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #896 = AdduRxRyRz16 { 895, 1, 0, 4, 735, 1, 1, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #895 = AddiuSpImmX16 { 894, 1, 0, 2, 735, 1, 1, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #894 = AddiuSpImm16 { 893, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 585, 0, 0x0ULL }, // Inst #893 = AddiuRxRyOffMemX16 { 892, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 582, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #892 = AddiuRxRxImmX16 { 891, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 582, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #891 = AddiuRxRxImm16 { 890, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 580, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #890 = AddiuRxPcImmX16 { 889, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 580, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #889 = AddiuRxImmX16 { 888, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #888 = AVE_U_W { 887, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #887 = AVE_U_H { 886, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #886 = AVE_U_D { 885, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #885 = AVE_U_B { 884, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #884 = AVE_S_W { 883, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #883 = AVE_S_H { 882, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #882 = AVE_S_D { 881, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #881 = AVE_S_B { 880, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #880 = AVER_U_W { 879, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #879 = AVER_U_H { 878, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #878 = AVER_U_D { 877, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #877 = AVER_U_B { 876, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #876 = AVER_S_W { 875, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #875 = AVER_S_H { 874, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #874 = AVER_S_D { 873, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #873 = AVER_S_B { 872, 3, 1, 4, 783, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #872 = AUI_MMR6 { 871, 2, 1, 4, 782, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #871 = AUIPC_MMR6 { 870, 2, 1, 4, 729, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #870 = AUIPC { 869, 3, 1, 4, 728, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #869 = AUI { 868, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #868 = ASUB_U_W { 867, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #867 = ASUB_U_H { 866, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #866 = ASUB_U_D { 865, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #865 = ASUB_U_B { 864, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 160, 0, 0x6ULL }, // Inst #864 = ASUB_S_W { 863, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 157, 0, 0x6ULL }, // Inst #863 = ASUB_S_H { 862, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 154, 0, 0x6ULL }, // Inst #862 = ASUB_S_D { 861, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #861 = ASUB_S_B { 860, 4, 1, 4, 1634, 0, 0, MipsImpOpBase + 0, 576, 0, 0x6ULL }, // Inst #860 = APPEND_MMR2 { 859, 4, 1, 4, 1470, 0, 0, MipsImpOpBase + 0, 576, 0, 0x6ULL }, // Inst #859 = APPEND { 858, 3, 1, 4, 743, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #858 = ANDi_MM { 857, 3, 1, 4, 806, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #857 = ANDi64 { 856, 3, 1, 4, 499, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #856 = ANDi { 855, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #855 = AND_V { 854, 3, 1, 4, 780, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #854 = AND_MMR6 { 853, 3, 1, 4, 742, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #853 = AND_MM { 852, 3, 1, 4, 781, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #852 = ANDI_MMR6 { 851, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #851 = ANDI_B { 850, 3, 1, 2, 780, 0, 0, MipsImpOpBase + 0, 539, 0, 0x0ULL }, // Inst #850 = ANDI16_MMR6 { 849, 3, 1, 2, 742, 0, 0, MipsImpOpBase + 0, 539, 0, 0x0ULL }, // Inst #849 = ANDI16_MM { 848, 3, 1, 4, 806, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #848 = AND64 { 847, 3, 1, 2, 780, 0, 0, MipsImpOpBase + 0, 573, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #847 = AND16_MMR6 { 846, 3, 1, 2, 742, 0, 0, MipsImpOpBase + 0, 573, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #846 = AND16_MM { 845, 3, 1, 4, 364, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #845 = AND { 844, 2, 1, 4, 779, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #844 = ALUIPC_MMR6 { 843, 2, 1, 4, 727, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #843 = ALUIPC { 842, 4, 1, 4, 778, 0, 0, MipsImpOpBase + 0, 569, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #842 = ALIGN_MMR6 { 841, 4, 1, 4, 726, 0, 0, MipsImpOpBase + 0, 569, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #841 = ALIGN { 840, 3, 1, 4, 739, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #840 = ADDu_MM { 839, 3, 1, 4, 509, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #839 = ADDu { 838, 3, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #838 = ADDiu_MM { 837, 3, 1, 4, 498, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // Inst #837 = ADDiu { 836, 3, 1, 4, 741, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #836 = ADDi_MM { 835, 3, 1, 4, 497, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #835 = ADDi { 834, 3, 1, 4, 777, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #834 = ADD_MMR6 { 833, 3, 1, 4, 740, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #833 = ADD_MM { 832, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #832 = ADD_A_W { 831, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #831 = ADD_A_H { 830, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #830 = ADD_A_D { 829, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #829 = ADD_A_B { 828, 3, 1, 4, 1517, 1, 1, MipsImpOpBase + 12, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #828 = ADDWC_MM { 827, 3, 1, 4, 1366, 1, 1, MipsImpOpBase + 12, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #827 = ADDWC { 826, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #826 = ADDV_W { 825, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #825 = ADDV_H { 824, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #824 = ADDV_D { 823, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #823 = ADDV_B { 822, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 566, 0, 0x6ULL }, // Inst #822 = ADDVI_W { 821, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 563, 0, 0x6ULL }, // Inst #821 = ADDVI_H { 820, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 560, 0, 0x6ULL }, // Inst #820 = ADDVI_D { 819, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #819 = ADDVI_B { 818, 3, 1, 4, 1516, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #818 = ADDU_S_QB_MM { 817, 3, 1, 4, 1365, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #817 = ADDU_S_QB { 816, 3, 1, 4, 1633, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #816 = ADDU_S_PH_MMR2 { 815, 3, 1, 4, 1469, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #815 = ADDU_S_PH { 814, 3, 1, 4, 1515, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #814 = ADDU_QB_MM { 813, 3, 1, 4, 1364, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #813 = ADDU_QB { 812, 3, 1, 4, 1632, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #812 = ADDU_PH_MMR2 { 811, 3, 1, 4, 1468, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #811 = ADDU_PH { 810, 3, 1, 4, 776, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #810 = ADDU_MMR6 { 809, 3, 1, 4, 1631, 0, 0, MipsImpOpBase + 0, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #809 = ADDUH_R_QB_MMR2 { 808, 3, 1, 4, 1467, 0, 0, MipsImpOpBase + 0, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #808 = ADDUH_R_QB { 807, 3, 1, 4, 1630, 0, 0, MipsImpOpBase + 0, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #807 = ADDUH_QB_MMR2 { 806, 3, 1, 4, 1466, 0, 0, MipsImpOpBase + 0, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #806 = ADDUH_QB { 805, 3, 1, 2, 776, 0, 0, MipsImpOpBase + 0, 554, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #805 = ADDU16_MMR6 { 804, 3, 1, 2, 739, 0, 0, MipsImpOpBase + 0, 554, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #804 = ADDU16_MM { 803, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #803 = ADDS_U_W { 802, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #802 = ADDS_U_H { 801, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #801 = ADDS_U_D { 800, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #800 = ADDS_U_B { 799, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #799 = ADDS_S_W { 798, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #798 = ADDS_S_H { 797, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #797 = ADDS_S_D { 796, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #796 = ADDS_S_B { 795, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #795 = ADDS_A_W { 794, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #794 = ADDS_A_H { 793, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #793 = ADDS_A_D { 792, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #792 = ADDS_A_B { 791, 3, 1, 4, 1514, 0, 1, MipsImpOpBase + 11, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #791 = ADDSC_MM { 790, 3, 1, 4, 1363, 0, 1, MipsImpOpBase + 11, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #790 = ADDSC { 789, 3, 1, 4, 1212, 0, 0, MipsImpOpBase + 0, 548, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #789 = ADDR_PS64 { 788, 3, 1, 4, 1513, 0, 1, MipsImpOpBase + 10, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #788 = ADDQ_S_W_MM { 787, 3, 1, 4, 1362, 0, 1, MipsImpOpBase + 10, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #787 = ADDQ_S_W { 786, 3, 1, 4, 1512, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #786 = ADDQ_S_PH_MM { 785, 3, 1, 4, 1361, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #785 = ADDQ_S_PH { 784, 3, 1, 4, 1511, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #784 = ADDQ_PH_MM { 783, 3, 1, 4, 1360, 0, 1, MipsImpOpBase + 10, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #783 = ADDQ_PH { 782, 3, 1, 4, 1629, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #782 = ADDQH_W_MMR2 { 781, 3, 1, 4, 1465, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #781 = ADDQH_W { 780, 3, 1, 4, 1628, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #780 = ADDQH_R_W_MMR2 { 779, 3, 1, 4, 1464, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #779 = ADDQH_R_W { 778, 3, 1, 4, 1627, 0, 0, MipsImpOpBase + 0, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #778 = ADDQH_R_PH_MMR2 { 777, 3, 1, 4, 1463, 0, 0, MipsImpOpBase + 0, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #777 = ADDQH_R_PH { 776, 3, 1, 4, 1626, 0, 0, MipsImpOpBase + 0, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #776 = ADDQH_PH_MMR2 { 775, 3, 1, 4, 1462, 0, 0, MipsImpOpBase + 0, 545, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #775 = ADDQH_PH { 774, 3, 1, 4, 775, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #774 = ADDIU_MMR6 { 773, 1, 0, 2, 738, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #773 = ADDIUSP_MM { 772, 3, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 542, 0, 0x0ULL }, // Inst #772 = ADDIUS5_MM { 771, 3, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 539, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #771 = ADDIUR2_MM { 770, 2, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 537, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #770 = ADDIUR1SP_MM { 769, 2, 1, 4, 774, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #769 = ADDIUPC_MMR6 { 768, 2, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 537, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #768 = ADDIUPC_MM { 767, 2, 1, 4, 725, 0, 0, MipsImpOpBase + 0, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #767 = ADDIUPC { 766, 3, 1, 4, 496, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #766 = ADD { 765, 2, 1, 4, 1510, 0, 1, MipsImpOpBase + 10, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #765 = ABSQ_S_W_MM { 764, 2, 1, 4, 1359, 0, 1, MipsImpOpBase + 10, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #764 = ABSQ_S_W { 763, 2, 1, 4, 1625, 0, 1, MipsImpOpBase + 10, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #763 = ABSQ_S_QB_MMR2 { 762, 2, 1, 4, 1461, 0, 1, MipsImpOpBase + 10, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #762 = ABSQ_S_QB { 761, 2, 1, 4, 1509, 0, 1, MipsImpOpBase + 10, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #761 = ABSQ_S_PH_MM { 760, 2, 1, 4, 1358, 0, 1, MipsImpOpBase + 10, 535, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #760 = ABSQ_S_PH { 759, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 160, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #759 = XOR_V_W_PSEUDO { 758, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #758 = XOR_V_H_PSEUDO { 757, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #757 = XOR_V_D_PSEUDO { 756, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #756 = Usw { 755, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #755 = Ush { 754, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #754 = Ulw { 753, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #753 = Ulhu { 752, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #752 = Ulh { 751, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #751 = URemMacro { 750, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #750 = URemIMacro { 749, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #749 = UDivMacro { 748, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #748 = UDivIMacro { 747, 3, 1, 4, 886, 0, 0, MipsImpOpBase + 0, 445, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #747 = UDIV_MM_Pseudo { 746, 0, 0, 4, 982, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #746 = TRAP_MM { 745, 0, 0, 4, 402, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #745 = TRAP { 744, 1, 0, 4, 1007, 0, 1, MipsImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #744 = TAILCALL_MMR6 { 743, 1, 0, 4, 965, 0, 1, MipsImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #743 = TAILCALL_MM { 742, 1, 0, 4, 1006, 0, 1, MipsImpOpBase + 2, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #742 = TAILCALLREG_MMR6 { 741, 1, 0, 4, 964, 0, 1, MipsImpOpBase + 2, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #741 = TAILCALLREG_MM { 740, 1, 0, 4, 1016, 0, 1, MipsImpOpBase + 2, 318, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #740 = TAILCALLREGHB64 { 739, 1, 0, 4, 385, 0, 1, MipsImpOpBase + 2, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #739 = TAILCALLREGHB { 738, 1, 0, 4, 1016, 0, 1, MipsImpOpBase + 2, 318, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #738 = TAILCALLREG64 { 737, 1, 0, 4, 385, 0, 1, MipsImpOpBase + 2, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #737 = TAILCALLREG { 736, 1, 0, 4, 938, 0, 1, MipsImpOpBase + 2, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #736 = TAILCALLR6REG { 735, 1, 0, 4, 938, 0, 1, MipsImpOpBase + 2, 197, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #735 = TAILCALLHBR6REG { 734, 1, 0, 4, 1024, 0, 1, MipsImpOpBase + 2, 318, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #734 = TAILCALLHB64R6REG { 733, 1, 0, 4, 1024, 0, 1, MipsImpOpBase + 2, 318, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #733 = TAILCALL64R6REG { 732, 1, 0, 4, 384, 0, 1, MipsImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #732 = TAILCALL { 731, 3, 1, 2, 736, 0, 1, MipsImpOpBase + 9, 408, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #731 = SltuRxRyRz16 { 730, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 408, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #730 = SltuCCRxRy16 { 729, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 532, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #729 = SltiuCCRxImmX16 { 728, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 532, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #728 = SltiCCRxImmX16 { 727, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 408, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #727 = SltCCRxRy16 { 726, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 522, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #726 = SelTBtneZSltu { 725, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 527, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #725 = SelTBtneZSltiu { 724, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 527, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #724 = SelTBtneZSlti { 723, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 522, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #723 = SelTBtneZSlt { 722, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 527, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #722 = SelTBtneZCmpi { 721, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 522, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #721 = SelTBtneZCmp { 720, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 522, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #720 = SelTBteqZSltu { 719, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 527, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #719 = SelTBteqZSltiu { 718, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 527, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #718 = SelTBteqZSlti { 717, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 522, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #717 = SelTBteqZSlt { 716, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 527, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #716 = SelTBteqZCmpi { 715, 5, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 522, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #715 = SelTBteqZCmp { 714, 4, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 518, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #714 = SelBneZ { 713, 4, 1, 2, 945, 0, 0, MipsImpOpBase + 0, 518, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #713 = SelBeqZ { 712, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #712 = SaadAddr { 711, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 368, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #711 = SaaAddr { 710, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 516, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #710 = SZ_W_PSEUDO { 709, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 510, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #709 = SZ_V_PSEUDO { 708, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 514, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #708 = SZ_H_PSEUDO { 707, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 512, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #707 = SZ_D_PSEUDO { 706, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 510, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #706 = SZ_B_PSEUDO { 705, 3, 0, 4, 1137, 0, 0, MipsImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #705 = SWM_MM { 704, 3, 0, 4, 705, 0, 0, MipsImpOpBase + 0, 328, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #704 = ST_F16 { 703, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 325, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #703 = STR_W { 702, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 322, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #702 = STR_D { 701, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 340, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #701 = STORE_CCOND_DSP { 700, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 337, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #700 = STORE_ACC64DSP { 699, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 334, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #699 = STORE_ACC64 { 698, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 331, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #698 = STORE_ACC128 { 697, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #697 = SRemMacro { 696, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #696 = SRemIMacro { 695, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 516, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #695 = SNZ_W_PSEUDO { 694, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 510, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #694 = SNZ_V_PSEUDO { 693, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 514, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #693 = SNZ_H_PSEUDO { 692, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 512, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #692 = SNZ_D_PSEUDO { 691, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 510, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #691 = SNZ_B_PSEUDO { 690, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #690 = SNEMacro { 689, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #689 = SNEIMacro { 688, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #688 = SLTUImm64 { 687, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #687 = SLTImm64 { 686, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #686 = SLEUImm64 { 685, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #685 = SLEUImm { 684, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #684 = SLEU { 683, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #683 = SLEImm64 { 682, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #682 = SLEImm { 681, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #681 = SLE { 680, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #680 = SGTUImm64 { 679, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #679 = SGTUImm { 678, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #678 = SGTImm64 { 677, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #677 = SGTImm { 676, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #676 = SGEUImm64 { 675, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #675 = SGEUImm { 674, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #674 = SGEU { 673, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #673 = SGEImm64 { 672, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #672 = SGEImm { 671, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #671 = SGE { 670, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #670 = SEQMacro { 669, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #669 = SEQIMacro { 668, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 507, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #668 = SDivMacro { 667, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #667 = SDivIMacro { 666, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #666 = SDMacro { 665, 3, 1, 4, 885, 0, 0, MipsImpOpBase + 0, 445, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #665 = SDIV_MM_Pseudo { 664, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 504, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #664 = SDC1_M1 { 663, 0, 0, 2, 941, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x0ULL }, // Inst #663 = RetRA16 { 662, 0, 0, 4, 382, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #662 = RetRA { 661, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #661 = RORImm { 660, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #660 = ROR { 659, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #659 = ROLImm { 658, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #658 = ROL { 657, 3, 1, 4, 866, 0, 0, MipsImpOpBase + 0, 445, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #657 = PseudoUDIV { 656, 3, 1, 4, 1215, 0, 0, MipsImpOpBase + 0, 501, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #656 = PseudoTRUNC_W_S { 655, 3, 1, 4, 1215, 0, 0, MipsImpOpBase + 0, 498, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #655 = PseudoTRUNC_W_D32 { 654, 3, 1, 4, 1215, 0, 0, MipsImpOpBase + 0, 495, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #654 = PseudoTRUNC_W_D { 653, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 491, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #653 = PseudoSELECT_S { 652, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 487, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #652 = PseudoSELECT_I64 { 651, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 483, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #651 = PseudoSELECT_I { 650, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 479, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #650 = PseudoSELECT_D64 { 649, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 475, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #649 = PseudoSELECT_D32 { 648, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 471, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #648 = PseudoSELECTFP_T_S { 647, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 467, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #647 = PseudoSELECTFP_T_I64 { 646, 4, 1,<TRUNCATED>#ifdef __GNUC__#pragma GCC diagnostic push#pragma GCC diagnostic ignored "-Woverlength-strings"#endif#ifdef __GNUC__#pragma GCC diagnostic pop#endif#endif // GET_INSTRINFO_MC_DESC#ifdef GET_INSTRINFO_HEADER#undef GET_INSTRINFO_HEADER#endif // GET_INSTRINFO_HEADER#ifdef GET_INSTRINFO_HELPER_DECLS#undef GET_INSTRINFO_HELPER_DECLS#endif // GET_INSTRINFO_HELPER_DECLS#ifdef GET_INSTRINFO_HELPERS#undef GET_INSTRINFO_HELPERS#endif // GET_INSTRINFO_HELPERS#ifdef GET_INSTRINFO_CTOR_DTOR#undef GET_INSTRINFO_CTOR_DTOR#endif // GET_INSTRINFO_CTOR_DTOR#ifdef GET_INSTRINFO_OPERAND_ENUM#undef GET_INSTRINFO_OPERAND_ENUM#endif //GET_INSTRINFO_OPERAND_ENUM#ifdef GET_INSTRINFO_NAMED_OPS#undef GET_INSTRINFO_NAMED_OPS#endif //GET_INSTRINFO_NAMED_OPS#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM#undef GET_INSTRINFO_OPERAND_TYPES_ENUM#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM#ifdef GET_INSTRINFO_OPERAND_TYPE#undef GET_INSTRINFO_OPERAND_TYPE#endif // GET_INSTRINFO_OPERAND_TYPE#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE#undef GET_INSTRINFO_MEM_OPERAND_SIZE#endif // GET_INSTRINFO_MEM_OPERAND_SIZE#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP#ifdef GET_INSTRINFO_MC_HELPER_DECLS#undef GET_INSTRINFO_MC_HELPER_DECLSclass MCInstclass FeatureBitsetvoid verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features)#endif // GET_INSTRINFO_MC_HELPER_DECLS#ifdef GET_INSTRINFO_MC_HELPERS#undef GET_INSTRINFO_MC_HELPERS#endif // GET_GENISTRINFO_MC_HELPERS#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\ defined(GET_AVAILABLE_OPCODE_CHECKER)#define GET_COMPUTE_FEATURES#endif#ifdef GET_COMPUTE_FEATURES#undef GET_COMPUTE_FEATURES#endif // GET_COMPUTE_FEATURES#ifdef GET_AVAILABLE_OPCODE_CHECKER#undef GET_AVAILABLE_OPCODE_CHECKER#endif // GET_AVAILABLE_OPCODE_CHECKER#ifdef ENABLE_INSTR_PREDICATE_VERIFIER#undef ENABLE_INSTR_PREDICATE_VERIFIER#include <sstream>#ifndef NDEBUG#endif // NDEBUG#ifndef NDEBUG#endif // NDEBUG#endif // ENABLE_INSTR_PREDICATE_VERIFIER#ifdef GET_INSTRMAP_INFO#undef GET_INSTRMAP_INFO#endif // GET_INSTRMAP_INFO
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