#ifdef GET_GLOBALISEL_PREDICATE_BITSET
const unsigned MAX_SUBTARGET_PREDICATES = …;
PredicateBitset;
#endif
#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
mutable MatcherState State;
typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
static MipsInstructionSelector::CustomRendererFn CustomRenderers[];
bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
const uint8_t *getMatchTable() const override;
bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
bool testSimplePredicate(unsigned PredicateID) const override;
bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
#endif
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
, State(0),
ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
#endif
#ifdef GET_GLOBALISEL_IMPL
enum {
GILLT_s16,
GILLT_s32,
GILLT_s64,
GILLT_v2s16,
GILLT_v2s64,
GILLT_v4s8,
GILLT_v4s32,
GILLT_v8s16,
GILLT_v16s8,
};
const static size_t NumTypeObjects = 9;
const static LLT TypeObjects[] = {
LLT::scalar(16),
LLT::scalar(32),
LLT::scalar(64),
LLT::vector(ElementCount::getFixed(2), 16),
LLT::vector(ElementCount::getFixed(2), 64),
LLT::vector(ElementCount::getFixed(4), 8),
LLT::vector(ElementCount::getFixed(4), 32),
LLT::vector(ElementCount::getFixed(8), 16),
LLT::vector(ElementCount::getFixed(16), 8),
};
enum SubtargetFeatureBits : uint8_t {
Feature_HasMips2Bit = 7,
Feature_HasMips3Bit = 17,
Feature_HasMips4_32Bit = 27,
Feature_NotMips4_32Bit = 28,
Feature_HasMips4_32r2Bit = 18,
Feature_HasMips32Bit = 3,
Feature_HasMips32r2Bit = 6,
Feature_HasMips32r6Bit = 29,
Feature_NotMips32r6Bit = 4,
Feature_IsGP64bitBit = 22,
Feature_IsPTR64bitBit = 24,
Feature_HasMips64Bit = 25,
Feature_HasMips64r2Bit = 23,
Feature_HasMips64r6Bit = 30,
Feature_NotMips64r6Bit = 5,
Feature_InMips16ModeBit = 31,
Feature_NotInMips16ModeBit = 0,
Feature_HasCnMipsBit = 26,
Feature_NotCnMipsBit = 8,
Feature_IsSym32Bit = 38,
Feature_IsSym64Bit = 39,
Feature_IsN64Bit = 40,
Feature_RelocNotPICBit = 9,
Feature_RelocPICBit = 37,
Feature_NoNaNsFPMathBit = 21,
Feature_UseAbsBit = 14,
Feature_HasStdEncBit = 1,
Feature_NotDSPBit = 11,
Feature_InMicroMipsBit = 35,
Feature_NotInMicroMipsBit = 2,
Feature_IsLEBit = 42,
Feature_IsBEBit = 43,
Feature_IsNotNaClBit = 19,
Feature_HasEVABit = 36,
Feature_HasMSABit = 34,
Feature_HasMadd4Bit = 20,
Feature_UseIndirectJumpsHazardBit = 12,
Feature_NoIndirectJumpGuardsBit = 10,
Feature_AllowFPOpFusionBit = 41,
Feature_IsFP64bitBit = 16,
Feature_NotFP64bitBit = 15,
Feature_IsNotSoftFloatBit = 13,
Feature_HasDSPBit = 32,
Feature_HasDSPR2Bit = 33,
};
PredicateBitset MipsInstructionSelector::
computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const {
PredicateBitset Features{};
if (Subtarget->hasMips2())
Features.set(Feature_HasMips2Bit);
if (Subtarget->hasMips3())
Features.set(Feature_HasMips3Bit);
if (Subtarget->hasMips4_32())
Features.set(Feature_HasMips4_32Bit);
if (!Subtarget->hasMips4_32())
Features.set(Feature_NotMips4_32Bit);
if (Subtarget->hasMips4_32r2())
Features.set(Feature_HasMips4_32r2Bit);
if (Subtarget->hasMips32())
Features.set(Feature_HasMips32Bit);
if (Subtarget->hasMips32r2())
Features.set(Feature_HasMips32r2Bit);
if (Subtarget->hasMips32r6())
Features.set(Feature_HasMips32r6Bit);
if (!Subtarget->hasMips32r6())
Features.set(Feature_NotMips32r6Bit);
if (Subtarget->isGP64bit())
Features.set(Feature_IsGP64bitBit);
if (Subtarget->isABI_N64())
Features.set(Feature_IsPTR64bitBit);
if (Subtarget->hasMips64())
Features.set(Feature_HasMips64Bit);
if (Subtarget->hasMips64r2())
Features.set(Feature_HasMips64r2Bit);
if (Subtarget->hasMips64r6())
Features.set(Feature_HasMips64r6Bit);
if (!Subtarget->hasMips64r6())
Features.set(Feature_NotMips64r6Bit);
if (Subtarget->inMips16Mode())
Features.set(Feature_InMips16ModeBit);
if (!Subtarget->inMips16Mode())
Features.set(Feature_NotInMips16ModeBit);
if (Subtarget->hasCnMips())
Features.set(Feature_HasCnMipsBit);
if (!Subtarget->hasCnMips())
Features.set(Feature_NotCnMipsBit);
if (Subtarget->hasSym32())
Features.set(Feature_IsSym32Bit);
if (!Subtarget->hasSym32())
Features.set(Feature_IsSym64Bit);
if (Subtarget->isABI_N64())
Features.set(Feature_IsN64Bit);
if (!TM.isPositionIndependent())
Features.set(Feature_RelocNotPICBit);
if (TM.isPositionIndependent())
Features.set(Feature_RelocPICBit);
if (TM.Options.NoNaNsFPMath)
Features.set(Feature_NoNaNsFPMathBit);
if (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)
Features.set(Feature_UseAbsBit);
if (Subtarget->hasStandardEncoding())
Features.set(Feature_HasStdEncBit);
if (!Subtarget->hasDSP())
Features.set(Feature_NotDSPBit);
if (Subtarget->inMicroMipsMode())
Features.set(Feature_InMicroMipsBit);
if (!Subtarget->inMicroMipsMode())
Features.set(Feature_NotInMicroMipsBit);
if (Subtarget->isLittle())
Features.set(Feature_IsLEBit);
if (!Subtarget->isLittle())
Features.set(Feature_IsBEBit);
if (!Subtarget->isTargetNaCl())
Features.set(Feature_IsNotNaClBit);
if (Subtarget->hasEVA())
Features.set(Feature_HasEVABit);
if (Subtarget->hasMSA())
Features.set(Feature_HasMSABit);
if (!Subtarget->disableMadd4())
Features.set(Feature_HasMadd4Bit);
if (Subtarget->useIndirectJumpsHazard())
Features.set(Feature_UseIndirectJumpsHazardBit);
if (!Subtarget->useIndirectJumpsHazard())
Features.set(Feature_NoIndirectJumpGuardsBit);
if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast)
Features.set(Feature_AllowFPOpFusionBit);
if (Subtarget->isFP64bit())
Features.set(Feature_IsFP64bitBit);
if (!Subtarget->isFP64bit())
Features.set(Feature_NotFP64bitBit);
if (!Subtarget->useSoftFloat())
Features.set(Feature_IsNotSoftFloatBit);
if (Subtarget->hasDSP())
Features.set(Feature_HasDSPBit);
if (Subtarget->hasDSPR2())
Features.set(Feature_HasDSPR2Bit);
return Features;
}
void MipsInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
AvailableFunctionFeatures = computeAvailableFunctionFeatures((const MipsSubtarget *)&MF.getSubtarget(), &MF);
}
PredicateBitset MipsInstructionSelector::
computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const {
PredicateBitset Features{};
return Features;
}
enum {
GIFBS_Invalid,
GIFBS_HasCnMips,
GIFBS_HasDSP,
GIFBS_HasDSPR2,
GIFBS_HasMSA,
GIFBS_InMicroMips,
GIFBS_InMips16Mode,
GIFBS_IsFP64bit,
GIFBS_NotFP64bit,
GIFBS_HasDSP_InMicroMips,
GIFBS_HasDSP_NotInMicroMips,
GIFBS_HasDSPR2_InMicroMips,
GIFBS_HasMSA_HasStdEnc,
GIFBS_HasMSA_IsBE,
GIFBS_HasMSA_IsLE,
GIFBS_HasMips32r6_HasStdEnc,
GIFBS_HasMips32r6_InMicroMips,
GIFBS_HasMips64r2_HasStdEnc,
GIFBS_HasMips64r6_HasStdEnc,
GIFBS_HasStdEnc_IsNotSoftFloat,
GIFBS_HasStdEnc_NotInMicroMips,
GIFBS_HasStdEnc_NotMips4_32,
GIFBS_InMicroMips_IsFP64bit,
GIFBS_InMicroMips_IsNotSoftFloat,
GIFBS_InMicroMips_NotFP64bit,
GIFBS_InMicroMips_NotMips32r6,
GIFBS_IsGP64bit_NotInMips16Mode,
GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
GIFBS_HasMSA_HasMips64_HasStdEnc,
GIFBS_HasMips3_HasStdEnc_IsGP64bit,
GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips,
GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
GIFBS_HasStdEnc_IsFP64bit_NotMips4_32,
GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
GIFBS_HasStdEnc_NotFP64bit_NotMips4_32,
GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
GIFBS_InMicroMips_IsNotSoftFloat_UseAbs,
GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
GIFBS_InMicroMips_NotMips32r6_RelocPIC,
GIFBS_IsFP64bit_IsNotSoftFloat_NotInMips16Mode,
GIFBS_IsNotSoftFloat_NotFP64bit_NotInMips16Mode,
GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6,
GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
GIFBS_HasMips32_HasStdEnc_NotMips32r6_NotMips64r6,
GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips_UseAbs,
GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6,
GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6,
GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_UseAbs,
GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_UseAbs,
GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
};
constexpr static PredicateBitset FeatureBitsets[] {
{},
{Feature_HasCnMipsBit, },
{Feature_HasDSPBit, },
{Feature_HasDSPR2Bit, },
{Feature_HasMSABit, },
{Feature_InMicroMipsBit, },
{Feature_InMips16ModeBit, },
{Feature_IsFP64bitBit, },
{Feature_NotFP64bitBit, },
{Feature_HasDSPBit, Feature_InMicroMipsBit, },
{Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
{Feature_HasDSPR2Bit, Feature_InMicroMipsBit, },
{Feature_HasMSABit, Feature_HasStdEncBit, },
{Feature_HasMSABit, Feature_IsBEBit, },
{Feature_HasMSABit, Feature_IsLEBit, },
{Feature_HasMips32r6Bit, Feature_HasStdEncBit, },
{Feature_HasMips32r6Bit, Feature_InMicroMipsBit, },
{Feature_HasMips64r2Bit, Feature_HasStdEncBit, },
{Feature_HasMips64r6Bit, Feature_HasStdEncBit, },
{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
{Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
{Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
{Feature_InMicroMipsBit, Feature_IsFP64bitBit, },
{Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
{Feature_InMicroMipsBit, Feature_NotFP64bitBit, },
{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
{Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, },
{Feature_AllowFPOpFusionBit, Feature_HasMSABit, Feature_HasStdEncBit, },
{Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, },
{Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
{Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
{Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
{Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
{Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
{Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
{Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, },
{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },
{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
{Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, },
{Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
{Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, },
{Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_UseAbsBit, },
{Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, },
{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, },
{Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMips16ModeBit, },
{Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMips16ModeBit, },
{Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotMips32r6Bit, },
{Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
{Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
{Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
{Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
{Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
{Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
{Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
{Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMips64Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips64r6Bit, },
{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
};
enum {
GICP_Invalid,
};
MipsInstructionSelector::ComplexMatcherMemFn
MipsInstructionSelector::ComplexPredicateFns[] = {
nullptr,
};
bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();
const auto &Operands = State.RecordedOperands;
(void)Operands;
(void)MRI;
llvm_unreachable("Unknown predicate");
return false;
}
enum {
GICXXPred_I64_Predicate_immLi16 = GICXXPred_Invalid + 1,
GICXXPred_I64_Predicate_immSExt6,
GICXXPred_I64_Predicate_immSExt10,
GICXXPred_I64_Predicate_immSExtAddiur2,
GICXXPred_I64_Predicate_immSExtAddius5,
GICXXPred_I64_Predicate_immZExt1,
GICXXPred_I64_Predicate_immZExt1Ptr,
GICXXPred_I64_Predicate_immZExt2,
GICXXPred_I64_Predicate_immZExt2Lsa,
GICXXPred_I64_Predicate_immZExt2Ptr,
GICXXPred_I64_Predicate_immZExt2Shift,
GICXXPred_I64_Predicate_immZExt3,
GICXXPred_I64_Predicate_immZExt3Ptr,
GICXXPred_I64_Predicate_immZExt4,
GICXXPred_I64_Predicate_immZExt4Ptr,
GICXXPred_I64_Predicate_immZExt5,
GICXXPred_I64_Predicate_immZExt5_64,
GICXXPred_I64_Predicate_immZExt6,
GICXXPred_I64_Predicate_immZExt8,
GICXXPred_I64_Predicate_immZExt10,
GICXXPred_I64_Predicate_immZExtAndi16,
GICXXPred_I64_Predicate_immi32Cst7,
GICXXPred_I64_Predicate_immi32Cst15,
GICXXPred_I64_Predicate_immi32Cst31,
GICXXPred_I64_Predicate_timmSExt6,
GICXXPred_I64_Predicate_timmZExt1,
GICXXPred_I64_Predicate_timmZExt1Ptr,
GICXXPred_I64_Predicate_timmZExt2,
GICXXPred_I64_Predicate_timmZExt2Ptr,
GICXXPred_I64_Predicate_timmZExt3,
GICXXPred_I64_Predicate_timmZExt3Ptr,
GICXXPred_I64_Predicate_timmZExt4,
GICXXPred_I64_Predicate_timmZExt4Ptr,
GICXXPred_I64_Predicate_timmZExt5,
GICXXPred_I64_Predicate_timmZExt6,
GICXXPred_I64_Predicate_timmZExt8,
GICXXPred_I64_Predicate_timmZExt10,
};
bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
switch (PredicateID) {
case GICXXPred_I64_Predicate_immLi16: {
return Imm >= -1 && Imm <= 126;
}
case GICXXPred_I64_Predicate_immSExt6: {
return isInt<6>(Imm);
}
case GICXXPred_I64_Predicate_immSExt10: {
return isInt<10>(Imm);
}
case GICXXPred_I64_Predicate_immSExtAddiur2: {
return Imm == 1 || Imm == -1 ||
((Imm % 4 == 0) &&
Imm < 28 && Imm > 0);
}
case GICXXPred_I64_Predicate_immSExtAddius5: {
return Imm >= -8 && Imm <= 7;
}
case GICXXPred_I64_Predicate_immZExt1: {
return isUInt<1>(Imm);
}
case GICXXPred_I64_Predicate_immZExt1Ptr: {
return isUInt<1>(Imm);
}
case GICXXPred_I64_Predicate_immZExt2: {
return isUInt<2>(Imm);
}
case GICXXPred_I64_Predicate_immZExt2Lsa: {
return isUInt<2>(Imm - 1);
}
case GICXXPred_I64_Predicate_immZExt2Ptr: {
return isUInt<2>(Imm);
}
case GICXXPred_I64_Predicate_immZExt2Shift: {
return Imm >= 1 && Imm <= 8;
}
case GICXXPred_I64_Predicate_immZExt3: {
return isUInt<3>(Imm);
}
case GICXXPred_I64_Predicate_immZExt3Ptr: {
return isUInt<3>(Imm);
}
case GICXXPred_I64_Predicate_immZExt4: {
return isUInt<4>(Imm);
}
case GICXXPred_I64_Predicate_immZExt4Ptr: {
return isUInt<4>(Imm);
}
case GICXXPred_I64_Predicate_immZExt5: {
return Imm == (Imm & 0x1f);
}
case GICXXPred_I64_Predicate_immZExt5_64: {
return Imm == (Imm & 0x1f);
}
case GICXXPred_I64_Predicate_immZExt6: {
return Imm == (Imm & 0x3f);
}
case GICXXPred_I64_Predicate_immZExt8: {
return isUInt<8>(Imm);
}
case GICXXPred_I64_Predicate_immZExt10: {
return isUInt<10>(Imm);
}
case GICXXPred_I64_Predicate_immZExtAndi16: {
return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
}
case GICXXPred_I64_Predicate_immi32Cst7: {
return isUInt<32>(Imm) && Imm == 7;
}
case GICXXPred_I64_Predicate_immi32Cst15: {
return isUInt<32>(Imm) && Imm == 15;
}
case GICXXPred_I64_Predicate_immi32Cst31: {
return isUInt<32>(Imm) && Imm == 31;
}
case GICXXPred_I64_Predicate_timmSExt6: {
return isInt<6>(Imm);
}
case GICXXPred_I64_Predicate_timmZExt1: {
return isUInt<1>(Imm);
}
case GICXXPred_I64_Predicate_timmZExt1Ptr: {
return isUInt<1>(Imm);
}
case GICXXPred_I64_Predicate_timmZExt2: {
return isUInt<2>(Imm);
}
case GICXXPred_I64_Predicate_timmZExt2Ptr: {
return isUInt<2>(Imm);
}
case GICXXPred_I64_Predicate_timmZExt3: {
return isUInt<3>(Imm);
}
case GICXXPred_I64_Predicate_timmZExt3Ptr: {
return isUInt<3>(Imm);
}
case GICXXPred_I64_Predicate_timmZExt4: {
return isUInt<4>(Imm);
}
case GICXXPred_I64_Predicate_timmZExt4Ptr: {
return isUInt<4>(Imm);
}
case GICXXPred_I64_Predicate_timmZExt5: {
return Imm == (Imm & 0x1f);
}
case GICXXPred_I64_Predicate_timmZExt6: {
return Imm == (Imm & 0x3f);
}
case GICXXPred_I64_Predicate_timmZExt8: {
return isUInt<8>(Imm);
}
case GICXXPred_I64_Predicate_timmZExt10: {
return isUInt<10>(Imm);
}
}
llvm_unreachable("Unknown predicate");
return false;
}
bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
llvm_unreachable("Unknown predicate");
return false;
}
enum {
GICXXPred_APInt_Predicate_imm32SExt16 = GICXXPred_Invalid + 1,
GICXXPred_APInt_Predicate_imm32ZExt16,
};
bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
switch (PredicateID) {
case GICXXPred_APInt_Predicate_imm32SExt16: {
return isInt<16>(Imm.getSExtValue());
}
case GICXXPred_APInt_Predicate_imm32ZExt16: {
return (uint32_t)Imm.getZExtValue() == (unsigned short)Imm.getZExtValue();
}
}
llvm_unreachable("Unknown predicate");
return false;
}
bool MipsInstructionSelector::testSimplePredicate(unsigned) const {
llvm_unreachable("MipsInstructionSelector does not support simple predicates!");
return false;
}
enum {
GICR_Invalid,
};
MipsInstructionSelector::CustomRendererFn
MipsInstructionSelector::CustomRenderers[] = {
nullptr,
};
bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
const PredicateBitset AvailableFeatures = getAvailableFeatures();
MachineIRBuilder B(I);
State.MIs.clear();
State.MIs.push_back(&I);
if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
return true;
}
return false;
}
bool MipsInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const {
llvm_unreachable("MipsInstructionSelector does not support custom C++ actions!");
}
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
#define GIMT_Encode2 …
#define GIMT_Encode4 …
#define GIMT_Encode8 …
#else
#define GIMT_Encode2 …
#define GIMT_Encode4 …
#define GIMT_Encode8 …
#endif
const uint8_t *MipsInstructionSelector::getMatchTable() const {
constexpr static uint8_t MatchTable0[] = {
GIM_SwitchOpcode, 0, GIMT_Encode2(53), GIMT_Encode2(281), GIMT_Encode4(66635),
GIMT_Encode4(922),
GIMT_Encode4(2220),
GIMT_Encode4(2911),
GIMT_Encode4(3392),
GIMT_Encode4(3661),
GIMT_Encode4(3930),
GIMT_Encode4(4199), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(4468),
GIMT_Encode4(5024),
GIMT_Encode4(5428), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(6320),
GIMT_Encode4(6393), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(6734), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(10925),
GIMT_Encode4(10990),
GIMT_Encode4(11058), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(11126), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(15847),
GIMT_Encode4(30112), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(34770),
GIMT_Encode4(34836),
GIMT_Encode4(34900), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(34961), GIMT_Encode4(0),
GIMT_Encode4(36425),
GIMT_Encode4(36626),
GIMT_Encode4(38423),
GIMT_Encode4(40220), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(41975), GIMT_Encode4(0),
GIMT_Encode4(42263),
GIMT_Encode4(44794), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(46500), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(58538),
GIMT_Encode4(58647), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(58756),
GIMT_Encode4(59669),
GIMT_Encode4(60281),
GIMT_Encode4(60768), GIMT_Encode4(0),
GIMT_Encode4(60874), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(61173), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(61251), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(61329),
GIMT_Encode4(62698),
GIMT_Encode4(62876),
GIMT_Encode4(63039),
GIMT_Encode4(63117),
GIMT_Encode4(63195),
GIMT_Encode4(63448), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(63526), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(63766), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(63840),
GIMT_Encode4(63912), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(63984),
GIMT_Encode4(64152),
GIMT_Encode4(64320),
GIMT_Encode4(64488), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(64656), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(64780),
GIMT_Encode4(65344), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(65396), GIMT_Encode4(0),
GIMT_Encode4(65901),
GIMT_Encode4(66107), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(66271), GIMT_Encode4(0),
GIMT_Encode4(66511), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
GIMT_Encode4(66589),
GIM_SwitchType, 0, 0, GIMT_Encode2(1), GIMT_Encode2(9), GIMT_Encode4(2219),
GIMT_Encode4(965),
GIMT_Encode4(1373),
GIMT_Encode4(1539),
GIMT_Encode4(1571),
GIMT_Encode4(1725),
GIMT_Encode4(1757),
GIMT_Encode4(1911),
GIMT_Encode4(2065),
GIM_Try, GIMT_Encode4(1372),
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_Try, GIMT_Encode4(1043),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RecordInsn, 1, 0, 1,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_SHL),
GIM_CheckType, 1, 1, GILLT_s32,
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckRegBankForClass, 1, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RecordInsn, 2, 1, 2,
GIM_CheckOpcode, 2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 2, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsSafeToFold, 2,
GIR_BuildRootMI, GIMT_Encode2(Mips::LSA),
GIR_RootToRootCopy, 0,
GIR_Copy, 0, 1, 1,
GIR_RootToRootCopy, 2,
GIR_CopyConstantAsSImm, 0, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(1110),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_SHL),
GIM_CheckType, 1, 1, GILLT_s32,
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckRegBankForClass, 1, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RecordInsn, 2, 1, 2,
GIM_CheckOpcode, 2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 2, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
GIM_CheckIsSafeToFold, 2,
GIR_BuildRootMI, GIMT_Encode2(Mips::LSA),
GIR_RootToRootCopy, 0,
GIR_Copy, 0, 1, 1,
GIR_RootToRootCopy, 1,
GIR_CopyConstantAsSImm, 0, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(1152),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckAPIntImmPredicate, 1, GIMT_Encode2(GICXXPred_APInt_Predicate_imm32SExt16),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDiu),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(1194),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immSExtAddiur2),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDIUR2_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(1236),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immSExtAddius5),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDIUS5_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(1263),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::ADDU16_MMR6),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(1290),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::ADDu),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(1317),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::ADDU16_MM),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(1344),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::ADDu_MM),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(1371),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::AdduRxRyRz16),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(1538),
GIM_RootCheckType, 1, GILLT_s64,
GIM_RootCheckType, 2, GILLT_s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_Try, GIMT_Encode4(1451),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc),
GIM_RecordInsn, 1, 0, 1,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_SHL),
GIM_CheckType, 1, 1, GILLT_s64,
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckRegBankForClass, 1, 1, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RecordInsn, 2, 1, 2,
GIM_CheckOpcode, 2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 2, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckIsSafeToFold, 2,
GIR_BuildRootMI, GIMT_Encode2(Mips::DLSA),
GIR_RootToRootCopy, 0,
GIR_Copy, 0, 1, 1,
GIR_RootToRootCopy, 2,
GIR_CopyConstantAsSImm, 0, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(1514),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_SHL),
GIM_CheckType, 1, 1, GILLT_s64,
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckRegBankForClass, 1, 1, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RecordInsn, 2, 1, 2,
GIM_CheckOpcode, 2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 2, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
GIM_CheckIsSafeToFold, 2,
GIR_BuildRootMI, GIMT_Encode2(Mips::DLSA),
GIR_RootToRootCopy, 0,
GIR_Copy, 0, 1, 1,
GIR_RootToRootCopy, 1,
GIR_CopyConstantAsSImm, 0, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(1537),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DADDu),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(1570),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_RootCheckType, 1, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::ADDQ_PH),
GIR_AddImplicitDef, 0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(RegState::Dead),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(1724),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_Try, GIMT_Encode4(1643),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RecordInsn, 1, 0, 1,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_MUL),
GIM_CheckType, 1, 1, GILLT_v2s64,
GIM_CheckType, 1, 2, GILLT_v2s64,
GIM_CheckRegBankForClass, 1, 1, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::MADDV_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_Copy, 0, 1, 1,
GIR_Copy, 0, 1, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(1700),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_MUL),
GIM_CheckType, 1, 1, GILLT_v2s64,
GIM_CheckType, 1, 2, GILLT_v2s64,
GIM_CheckRegBankForClass, 1, 1, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::MADDV_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_Copy, 0, 1, 1,
GIR_Copy, 0, 1, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(1723),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::ADDV_D),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(1756),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_RootCheckType, 1, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::ADDU_QB),
GIR_AddImplicitDef, 0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(RegState::Dead),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(1910),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_Try, GIMT_Encode4(1829),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RecordInsn, 1, 0, 1,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_MUL),
GIM_CheckType, 1, 1, GILLT_v4s32,
GIM_CheckType, 1, 2, GILLT_v4s32,
GIM_CheckRegBankForClass, 1, 1, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::MADDV_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_Copy, 0, 1, 1,
GIR_Copy, 0, 1, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(1886),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_MUL),
GIM_CheckType, 1, 1, GILLT_v4s32,
GIM_CheckType, 1, 2, GILLT_v4s32,
GIM_CheckRegBankForClass, 1, 1, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::MADDV_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_Copy, 0, 1, 1,
GIR_Copy, 0, 1, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(1909),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::ADDV_W),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(2064),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_Try, GIMT_Encode4(1983),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RecordInsn, 1, 0, 1,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_MUL),
GIM_CheckType, 1, 1, GILLT_v8s16,
GIM_CheckType, 1, 2, GILLT_v8s16,
GIM_CheckRegBankForClass, 1, 1, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::MADDV_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_Copy, 0, 1, 1,
GIR_Copy, 0, 1, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(2040),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_MUL),
GIM_CheckType, 1, 1, GILLT_v8s16,
GIM_CheckType, 1, 2, GILLT_v8s16,
GIM_CheckRegBankForClass, 1, 1, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::MADDV_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_Copy, 0, 1, 1,
GIR_Copy, 0, 1, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(2063),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::ADDV_H),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(2218),
GIM_RootCheckType, 1, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_Try, GIMT_Encode4(2137),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RecordInsn, 1, 0, 1,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_MUL),
GIM_CheckType, 1, 1, GILLT_v16s8,
GIM_CheckType, 1, 2, GILLT_v16s8,
GIM_CheckRegBankForClass, 1, 1, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::MADDV_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_Copy, 0, 1, 1,
GIR_Copy, 0, 1, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(2194),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_MUL),
GIM_CheckType, 1, 1, GILLT_v16s8,
GIM_CheckType, 1, 2, GILLT_v16s8,
GIM_CheckRegBankForClass, 1, 1, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::MADDV_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_Copy, 0, 1, 1,
GIR_Copy, 0, 1, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(2217),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::ADDV_B),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Reject,
GIM_SwitchType, 0, 0, GIMT_Encode2(1), GIMT_Encode2(9), GIMT_Encode4(2910),
GIMT_Encode4(2263),
GIMT_Encode4(2440),
GIMT_Encode4(2474),
GIMT_Encode4(2506),
GIMT_Encode4(2599),
GIMT_Encode4(2631),
GIMT_Encode4(2724),
GIMT_Encode4(2817),
GIM_Try, GIMT_Encode4(2439),
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_Try, GIMT_Encode4(2303),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_CheckConstantInt8, 0, 1, 0,
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::NegRxRy16),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(2330),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::SUBU16_MMR6),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(2357),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::SUBu),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(2384),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::SUBU16_MM),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(2411),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::SUBu_MM),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(2438),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::SubuRxRyRz16),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(2473),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
GIM_RootCheckType, 1, GILLT_s64,
GIM_RootCheckType, 2, GILLT_s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DSUBu),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(2505),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_RootCheckType, 1, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::SUBQ_PH),
GIR_AddImplicitDef, 0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(RegState::Dead),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(2598),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_Try, GIMT_Encode4(2578),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_MUL),
GIM_CheckType, 1, 1, GILLT_v2s64,
GIM_CheckType, 1, 2, GILLT_v2s64,
GIM_CheckRegBankForClass, 1, 1, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::MSUBV_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_Copy, 0, 1, 1,
GIR_Copy, 0, 1, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(2597),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::SUBV_D),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(2630),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_RootCheckType, 1, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::SUBU_QB),
GIR_AddImplicitDef, 0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(RegState::Dead),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(2723),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_Try, GIMT_Encode4(2703),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_MUL),
GIM_CheckType, 1, 1, GILLT_v4s32,
GIM_CheckType, 1, 2, GILLT_v4s32,
GIM_CheckRegBankForClass, 1, 1, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::MSUBV_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_Copy, 0, 1, 1,
GIR_Copy, 0, 1, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(2722),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::SUBV_W),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(2816),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_Try, GIMT_Encode4(2796),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_MUL),
GIM_CheckType, 1, 1, GILLT_v8s16,
GIM_CheckType, 1, 2, GILLT_v8s16,
GIM_CheckRegBankForClass, 1, 1, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::MSUBV_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_Copy, 0, 1, 1,
GIR_Copy, 0, 1, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(2815),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::SUBV_H),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(2909),
GIM_RootCheckType, 1, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_Try, GIMT_Encode4(2889),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_MUL),
GIM_CheckType, 1, 1, GILLT_v16s8,
GIM_CheckType, 1, 2, GILLT_v16s8,
GIM_CheckRegBankForClass, 1, 1, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::MSUBV_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_Copy, 0, 1, 1,
GIR_Copy, 0, 1, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(2908),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::SUBV_B),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Reject,
GIM_SwitchType, 0, 0, GIMT_Encode2(1), GIMT_Encode2(9), GIMT_Encode4(3391),
GIMT_Encode4(2954),
GIMT_Encode4(3138),
GIMT_Encode4(3223),
GIMT_Encode4(3255), GIMT_Encode4(0),
GIMT_Encode4(3289),
GIMT_Encode4(3323),
GIMT_Encode4(3357),
GIM_Try, GIMT_Encode4(3137),
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_Try, GIMT_Encode4(3004),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MUL),
GIR_AddImplicitDef, 0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(RegState::Dead),
GIR_AddImplicitDef, 0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(RegState::Dead),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(3031),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MUL_R6),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(3070),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MUL_MM),
GIR_AddImplicitDef, 0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(RegState::Dead),
GIR_AddImplicitDef, 0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(RegState::Dead),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(3097),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MUL_MMR6),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(3136),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MultRxRyRz16),
GIR_AddImplicitDef, 0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(RegState::Dead),
GIR_AddImplicitDef, 0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(RegState::Dead),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(3222),
GIM_RootCheckType, 1, GILLT_s64,
GIM_RootCheckType, 2, GILLT_s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_Try, GIMT_Encode4(3206),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DMUL),
GIR_AddImplicitDef, 0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(RegState::Dead),
GIR_AddImplicitDef, 0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(RegState::Dead),
GIR_AddImplicitDef, 0, GIMT_Encode2(Mips::P0), GIMT_Encode2(RegState::Dead),
GIR_AddImplicitDef, 0, GIMT_Encode2(Mips::P1), GIMT_Encode2(RegState::Dead),
GIR_AddImplicitDef, 0, GIMT_Encode2(Mips::P2), GIMT_Encode2(RegState::Dead),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(3221),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DMUL_R6),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(3254),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_RootCheckType, 1, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MUL_PH),
GIR_AddImplicitDef, 0, GIMT_Encode2(Mips::DSPOutFlag21), GIMT_Encode2(RegState::Dead),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(3288),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MULV_D),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(3322),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MULV_W),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(3356),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MULV_H),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(3390),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MULV_B),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_SwitchType, 0, 0, GIMT_Encode2(1), GIMT_Encode2(9), GIMT_Encode4(3660),
GIMT_Encode4(3435),
GIMT_Encode4(3490), GIMT_Encode4(0),
GIMT_Encode4(3524), GIMT_Encode4(0),
GIMT_Encode4(3558),
GIMT_Encode4(3592),
GIMT_Encode4(3626),
GIM_Try, GIMT_Encode4(3489),
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_Try, GIMT_Encode4(3473),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DIV),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(3488),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DIV_MMR6),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(3523),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
GIM_RootCheckType, 1, GILLT_s64,
GIM_RootCheckType, 2, GILLT_s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DDIV),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(3557),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DIV_S_D),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(3591),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DIV_S_W),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(3625),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DIV_S_H),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(3659),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DIV_S_B),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_SwitchType, 0, 0, GIMT_Encode2(1), GIMT_Encode2(9), GIMT_Encode4(3929),
GIMT_Encode4(3704),
GIMT_Encode4(3759), GIMT_Encode4(0),
GIMT_Encode4(3793), GIMT_Encode4(0),
GIMT_Encode4(3827),
GIMT_Encode4(3861),
GIMT_Encode4(3895),
GIM_Try, GIMT_Encode4(3758),
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_Try, GIMT_Encode4(3742),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DIVU),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(3757),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DIVU_MMR6),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(3792),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
GIM_RootCheckType, 1, GILLT_s64,
GIM_RootCheckType, 2, GILLT_s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DDIVU),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(3826),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DIV_U_D),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(3860),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DIV_U_W),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(3894),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DIV_U_H),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(3928),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DIV_U_B),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_SwitchType, 0, 0, GIMT_Encode2(1), GIMT_Encode2(9), GIMT_Encode4(4198),
GIMT_Encode4(3973),
GIMT_Encode4(4028), GIMT_Encode4(0),
GIMT_Encode4(4062), GIMT_Encode4(0),
GIMT_Encode4(4096),
GIMT_Encode4(4130),
GIMT_Encode4(4164),
GIM_Try, GIMT_Encode4(4027),
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_Try, GIMT_Encode4(4011),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MOD),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(4026),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MOD_MMR6),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(4061),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
GIM_RootCheckType, 1, GILLT_s64,
GIM_RootCheckType, 2, GILLT_s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DMOD),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(4095),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MOD_S_D),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(4129),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MOD_S_W),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(4163),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MOD_S_H),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(4197),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MOD_S_B),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_SwitchType, 0, 0, GIMT_Encode2(1), GIMT_Encode2(9), GIMT_Encode4(4467),
GIMT_Encode4(4242),
GIMT_Encode4(4297), GIMT_Encode4(0),
GIMT_Encode4(4331), GIMT_Encode4(0),
GIMT_Encode4(4365),
GIMT_Encode4(4399),
GIMT_Encode4(4433),
GIM_Try, GIMT_Encode4(4296),
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_Try, GIMT_Encode4(4280),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MODU),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(4295),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MODU_MMR6),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(4330),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
GIM_RootCheckType, 1, GILLT_s64,
GIM_RootCheckType, 2, GILLT_s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DMODU),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(4364),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MOD_U_D),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(4398),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MOD_U_W),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(4432),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MOD_U_H),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(4466),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MOD_U_B),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_SwitchType, 0, 0, GIMT_Encode2(1), GIMT_Encode2(9), GIMT_Encode4(5023),
GIMT_Encode4(4511),
GIMT_Encode4(4785), GIMT_Encode4(0),
GIMT_Encode4(4887), GIMT_Encode4(0),
GIMT_Encode4(4921),
GIMT_Encode4(4955),
GIMT_Encode4(4989),
GIM_Try, GIMT_Encode4(4784),
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_Try, GIMT_Encode4(4564),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckAPIntImmPredicate, 1, GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::ANDi),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(4606),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immZExtAndi16),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::ANDI16_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(4648),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immZExtAndi16),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::ANDI16_MMR6),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(4675),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::AND),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(4702),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::AND16_MM),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(4729),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::AND_MM),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(4756),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::AND_MMR6),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(4783),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::AndRxRxRy16),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(4886),
GIM_RootCheckType, 1, GILLT_s64,
GIM_RootCheckType, 2, GILLT_s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_Try, GIMT_Encode4(4862),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
GIM_RecordInsn, 1, 0, 1,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ADD),
GIM_CheckType, 1, 1, GILLT_s64,
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckRegBankForClass, 1, 1, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckConstantInt, 0, 2, GIMT_Encode8(255),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BADDu),
GIR_RootToRootCopy, 0,
GIR_Copy, 0, 1, 1,
GIR_Copy, 0, 1, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(4885),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::AND64),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(4920),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::AND_V_D_PSEUDO),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(4954),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::AND_V_W_PSEUDO),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(4988),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::AND_V_H_PSEUDO),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(5022),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::AND_V),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_SwitchType, 0, 0, GIMT_Encode2(1), GIMT_Encode2(9), GIMT_Encode4(5427),
GIMT_Encode4(5067),
GIMT_Encode4(5257), GIMT_Encode4(0),
GIMT_Encode4(5291), GIMT_Encode4(0),
GIMT_Encode4(5325),
GIMT_Encode4(5359),
GIMT_Encode4(5393),
GIM_Try, GIMT_Encode4(5256),
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_Try, GIMT_Encode4(5120),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckAPIntImmPredicate, 1, GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::ORi),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(5147),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::OR),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(5174),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::OR16_MM),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(5201),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::OR_MM),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(5228),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::OR_MMR6),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(5255),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::OrRxRxRy16),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(5290),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
GIM_RootCheckType, 1, GILLT_s64,
GIM_RootCheckType, 2, GILLT_s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::OR64),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(5324),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::OR_V_D_PSEUDO),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(5358),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::OR_V_W_PSEUDO),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(5392),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::OR_V_H_PSEUDO),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(5426),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::OR_V),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_SwitchType, 0, 0, GIMT_Encode2(1), GIMT_Encode2(9), GIMT_Encode4(6319),
GIMT_Encode4(5471),
GIMT_Encode4(6088), GIMT_Encode4(0),
GIMT_Encode4(6183), GIMT_Encode4(0),
GIMT_Encode4(6217),
GIMT_Encode4(6251),
GIMT_Encode4(6285),
GIM_Try, GIMT_Encode4(6087),
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_Try, GIMT_Encode4(5541),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RecordInsn, 1, 0, 1,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_OR),
GIM_CheckType, 1, 1, GILLT_s32,
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckRegBankForClass, 1, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckConstantInt8, 0, 2, uint8_t(-1),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::NOR),
GIR_RootToRootCopy, 0,
GIR_Copy, 0, 1, 1,
GIR_Copy, 0, 1, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(5600),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RecordInsn, 1, 0, 1,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_OR),
GIM_CheckType, 1, 1, GILLT_s32,
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckRegBankForClass, 1, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckConstantInt8, 0, 2, uint8_t(-1),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::NOR_MM),
GIR_RootToRootCopy, 0,
GIR_Copy, 0, 1, 1,
GIR_Copy, 0, 1, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(5659),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RecordInsn, 1, 0, 1,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_OR),
GIM_CheckType, 1, 1, GILLT_s32,
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckRegBankForClass, 1, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckConstantInt8, 0, 2, uint8_t(-1),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::NOR_MMR6),
GIR_RootToRootCopy, 0,
GIR_Copy, 0, 1, 1,
GIR_Copy, 0, 1, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(5688),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_CheckConstantInt8, 0, 2, uint8_t(-1),
GIR_BuildRootMI, GIMT_Encode2(Mips::NOT16_MMR6),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(5717),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_CheckConstantInt8, 0, 2, uint8_t(-1),
GIR_BuildRootMI, GIMT_Encode2(Mips::NOT16_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(5752),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckConstantInt8, 0, 2, uint8_t(-1),
GIR_BuildRootMI, GIMT_Encode2(Mips::NOR),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO), GIMT_Encode2(0),
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(5781),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_CheckConstantInt8, 0, 2, uint8_t(-1),
GIR_BuildRootMI, GIMT_Encode2(Mips::NotRxRy16),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(5810),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_CheckConstantInt8, 0, 2, uint8_t(-1),
GIR_BuildRootMI, GIMT_Encode2(Mips::NOT16_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(5845),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckConstantInt8, 0, 2, uint8_t(-1),
GIR_BuildRootMI, GIMT_Encode2(Mips::NOR_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO), GIMT_Encode2(0),
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(5874),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_CheckConstantInt8, 0, 2, uint8_t(-1),
GIR_BuildRootMI, GIMT_Encode2(Mips::NOT16_MMR6),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(5909),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckConstantInt8, 0, 2, uint8_t(-1),
GIR_BuildRootMI, GIMT_Encode2(Mips::NOR_MMR6),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO), GIMT_Encode2(0),
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(5951),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckAPIntImmPredicate, 1, GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::XORi),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(5978),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::XOR),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(6005),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPRMM16RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::XOR16_MM),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(6032),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::XOR_MM),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(6059),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::XOR_MMR6),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(6086),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::XorRxRxRy16),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(6182),
GIM_RootCheckType, 1, GILLT_s64,
GIM_RootCheckType, 2, GILLT_s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_Try, GIMT_Encode4(6158),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
GIM_RecordInsn, 1, 0, 1,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_OR),
GIM_CheckType, 1, 1, GILLT_s64,
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckRegBankForClass, 1, 1, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckConstantInt8, 0, 2, uint8_t(-1),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::NOR64),
GIR_RootToRootCopy, 0,
GIR_Copy, 0, 1, 1,
GIR_Copy, 0, 1, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(6181),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::XOR64),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(6216),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::XOR_V_D_PSEUDO),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(6250),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::XOR_V_W_PSEUDO),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(6284),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::XOR_V_H_PSEUDO),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(6318),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckType, 1, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::XOR_V),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(6392),
GIM_CheckNumOperands, 0, 3,
GIM_RootCheckType, 0, GILLT_s64,
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_Try, GIMT_Encode4(6364),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotSoftFloat_NotFP64bit_NotInMips16Mode),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::AFGR64RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::BuildPairF64),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(6391),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit_IsNotSoftFloat_NotInMips16Mode),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::FGR64RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::BuildPairF64_64),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(6464),
GIM_CheckNumOperands, 0, 3,
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 1, GILLT_s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_Try, GIMT_Encode4(6437),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckIsSameOperand, 0, 2, 0, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::FILL_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(6463),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::FGR64RegClassID),
GIM_CheckIsSameOperand, 0, 2, 0, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::FILL_FD_PSEUDO),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(6555),
GIM_CheckNumOperands, 0, 5,
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_Try, GIMT_Encode4(6518),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsSameOperand, 0, 2, 0, 1,
GIM_CheckIsSameOperand, 0, 3, 0, 1,
GIM_CheckIsSameOperand, 0, 4, 0, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::FILL_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(6554),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::FGR32RegClassID),
GIM_CheckIsSameOperand, 0, 2, 0, 1,
GIM_CheckIsSameOperand, 0, 3, 0, 1,
GIM_CheckIsSameOperand, 0, 4, 0, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::FILL_FW_PSEUDO),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(6624),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckNumOperands, 0, 9,
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsSameOperand, 0, 2, 0, 1,
GIM_CheckIsSameOperand, 0, 3, 0, 1,
GIM_CheckIsSameOperand, 0, 4, 0, 1,
GIM_CheckIsSameOperand, 0, 5, 0, 1,
GIM_CheckIsSameOperand, 0, 6, 0, 1,
GIM_CheckIsSameOperand, 0, 7, 0, 1,
GIM_CheckIsSameOperand, 0, 8, 0, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::FILL_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(6733),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckNumOperands, 0, 17,
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsSameOperand, 0, 2, 0, 1,
GIM_CheckIsSameOperand, 0, 3, 0, 1,
GIM_CheckIsSameOperand, 0, 4, 0, 1,
GIM_CheckIsSameOperand, 0, 5, 0, 1,
GIM_CheckIsSameOperand, 0, 6, 0, 1,
GIM_CheckIsSameOperand, 0, 7, 0, 1,
GIM_CheckIsSameOperand, 0, 8, 0, 1,
GIM_CheckIsSameOperand, 0, 9, 0, 1,
GIM_CheckIsSameOperand, 0, 10, 0, 1,
GIM_CheckIsSameOperand, 0, 11, 0, 1,
GIM_CheckIsSameOperand, 0, 12, 0, 1,
GIM_CheckIsSameOperand, 0, 13, 0, 1,
GIM_CheckIsSameOperand, 0, 14, 0, 1,
GIM_CheckIsSameOperand, 0, 15, 0, 1,
GIM_CheckIsSameOperand, 0, 16, 0, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::FILL_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Reject,
GIM_SwitchType, 0, 0, GIMT_Encode2(1), GIMT_Encode2(9), GIMT_Encode4(10924),
GIMT_Encode4(6777),
GIMT_Encode4(7054),
GIMT_Encode4(7110),
GIMT_Encode4(7170),
GIMT_Encode4(8269),
GIMT_Encode4(8329),
GIMT_Encode4(9368),
GIMT_Encode4(10263),
GIM_Try, GIMT_Encode4(6803),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::FGR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MFC1),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(6829),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::FGR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MTC1),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(6855),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::FGR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MFC1_MM),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(6881),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::FGR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MTC1_MM),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(6907),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::FGR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MTC1_MMR6),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(6933),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::FGR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::MFC1_MMR6),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(6963),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_RootCheckType, 1, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(6993),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_RootCheckType, 1, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(7023),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_RootCheckType, 1, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::FGR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::FGR32RegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(7053),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_RootCheckType, 1, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::FGR32RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::FGR32RegClassID),
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(7109),
GIM_RootCheckType, 1, GILLT_s64,
GIM_Try, GIMT_Encode4(7085),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::FGR64RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR64RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DMTC1),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(7108),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::FGR64RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::DMFC1),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(7169),
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_Try, GIMT_Encode4(7145),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(7168),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::FGR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(7196),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(7222),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(7248),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(7274),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(7300),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(7326),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(7352),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(7378),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(7404),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(7430),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(7456),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(7482),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(7593),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MakeTempReg, 0, GILLT_v4s32,
GIR_MakeTempReg, 1, GILLT_v4s32,
GIR_MakeTempReg, 2, GILLT_v16s8,
GIR_MakeTempReg, 3, GILLT_v16s8,
GIR_BuildMI, 4, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 4, 3, GIMT_Encode2(RegState::Define),
GIR_Copy, 4, 0, 1,
GIR_ConstrainSelectedInstOperands, 4,
GIR_BuildMI, 3, GIMT_Encode2(Mips::SHF_B),
GIR_AddTempRegister, 3, 2, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 3, 3,
GIR_AddImm8, 3, 27,
GIR_ConstrainSelectedInstOperands, 3,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 2, 2,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_W),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(7704),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MakeTempReg, 0, GILLT_v4s32,
GIR_MakeTempReg, 1, GILLT_v4s32,
GIR_MakeTempReg, 2, GILLT_v16s8,
GIR_MakeTempReg, 3, GILLT_v16s8,
GIR_BuildMI, 4, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 4, 3, GIMT_Encode2(RegState::Define),
GIR_Copy, 4, 0, 1,
GIR_ConstrainSelectedInstOperands, 4,
GIR_BuildMI, 3, GIMT_Encode2(Mips::SHF_B),
GIR_AddTempRegister, 3, 2, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 3, 3,
GIR_AddImm8, 3, 27,
GIR_ConstrainSelectedInstOperands, 3,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 2, 2,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_W),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(7771),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MakeTempReg, 0, GILLT_v8s16,
GIR_MakeTempReg, 1, GILLT_v8s16,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_H),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm8, 1, 27,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(7838),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MakeTempReg, 0, GILLT_v8s16,
GIR_MakeTempReg, 1, GILLT_v8s16,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_H),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm8, 1, 27,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(7905),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MakeTempReg, 0, GILLT_v8s16,
GIR_MakeTempReg, 1, GILLT_v8s16,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_H),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm8, 1, 27,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(7972),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MakeTempReg, 0, GILLT_v8s16,
GIR_MakeTempReg, 1, GILLT_v8s16,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_H),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm8, 1, 27,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(8046),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MakeTempReg, 0, GILLT_v4s32,
GIR_MakeTempReg, 1, GILLT_v4s32,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_W),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(8120),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MakeTempReg, 0, GILLT_v4s32,
GIR_MakeTempReg, 1, GILLT_v4s32,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_W),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(8194),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MakeTempReg, 0, GILLT_v4s32,
GIR_MakeTempReg, 1, GILLT_v4s32,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_W),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(8268),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_MakeTempReg, 0, GILLT_v4s32,
GIR_MakeTempReg, 1, GILLT_v4s32,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_W),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(8328),
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_Try, GIMT_Encode4(8304),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(8327),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::FGR32RegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(8355),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(8381),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(8407),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(8433),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(8459),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(8485),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(8511),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(8537),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(8563),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(8589),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(8615),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(8641),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(8708),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MakeTempReg, 0, GILLT_v16s8,
GIR_MakeTempReg, 1, GILLT_v16s8,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_B),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm8, 1, 27,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(8775),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MakeTempReg, 0, GILLT_v16s8,
GIR_MakeTempReg, 1, GILLT_v16s8,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_B),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm8, 1, 27,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(8849),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MakeTempReg, 0, GILLT_v8s16,
GIR_MakeTempReg, 1, GILLT_v8s16,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_H),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(8923),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MakeTempReg, 0, GILLT_v8s16,
GIR_MakeTempReg, 1, GILLT_v8s16,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_H),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(8997),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MakeTempReg, 0, GILLT_v8s16,
GIR_MakeTempReg, 1, GILLT_v8s16,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_H),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(9071),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MakeTempReg, 0, GILLT_v8s16,
GIR_MakeTempReg, 1, GILLT_v8s16,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_H),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(9145),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MakeTempReg, 0, GILLT_v4s32,
GIR_MakeTempReg, 1, GILLT_v4s32,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_W),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(9219),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MakeTempReg, 0, GILLT_v4s32,
GIR_MakeTempReg, 1, GILLT_v4s32,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_W),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(9293),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MakeTempReg, 0, GILLT_v4s32,
GIR_MakeTempReg, 1, GILLT_v4s32,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_W),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(9367),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_MakeTempReg, 0, GILLT_v4s32,
GIR_MakeTempReg, 1, GILLT_v4s32,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_W),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(9394),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(9420),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(9446),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(9472),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(9498),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(9524),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(9550),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(9624),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MakeTempReg, 0, GILLT_v16s8,
GIR_MakeTempReg, 1, GILLT_v16s8,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_B),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(9698),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MakeTempReg, 0, GILLT_v16s8,
GIR_MakeTempReg, 1, GILLT_v16s8,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_B),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(9772),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MakeTempReg, 0, GILLT_v8s16,
GIR_MakeTempReg, 1, GILLT_v8s16,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_H),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(9846),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MakeTempReg, 0, GILLT_v8s16,
GIR_MakeTempReg, 1, GILLT_v8s16,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_H),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(9920),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MakeTempReg, 0, GILLT_v8s16,
GIR_MakeTempReg, 1, GILLT_v8s16,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_H),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(9994),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MakeTempReg, 0, GILLT_v8s16,
GIR_MakeTempReg, 1, GILLT_v8s16,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_H),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(10061),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MakeTempReg, 0, GILLT_v8s16,
GIR_MakeTempReg, 1, GILLT_v8s16,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_H),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm8, 1, 27,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(10128),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MakeTempReg, 0, GILLT_v8s16,
GIR_MakeTempReg, 1, GILLT_v8s16,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_H),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm8, 1, 27,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(10195),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MakeTempReg, 0, GILLT_v8s16,
GIR_MakeTempReg, 1, GILLT_v8s16,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_H),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm8, 1, 27,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(10262),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_MakeTempReg, 0, GILLT_v8s16,
GIR_MakeTempReg, 1, GILLT_v8s16,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_H),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm8, 1, 27,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(10289),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(10315),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(10341),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(10367),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(10393),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(10419),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MutateOpcode, 0, 0, GIMT_Encode2(TargetOpcode::COPY),
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_Done,
GIM_Try, GIMT_Encode4(10493),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MakeTempReg, 0, GILLT_v16s8,
GIR_MakeTempReg, 1, GILLT_v16s8,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_B),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(10567),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MakeTempReg, 0, GILLT_v16s8,
GIR_MakeTempReg, 1, GILLT_v16s8,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_B),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(10634),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MakeTempReg, 0, GILLT_v16s8,
GIR_MakeTempReg, 1, GILLT_v16s8,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_B),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm8, 1, 27,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(10701),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MakeTempReg, 0, GILLT_v16s8,
GIR_MakeTempReg, 1, GILLT_v16s8,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_Copy, 2, 0, 1,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_B),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm8, 1, 27,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(10812),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MakeTempReg, 0, GILLT_v4s32,
GIR_MakeTempReg, 1, GILLT_v4s32,
GIR_MakeTempReg, 2, GILLT_v16s8,
GIR_MakeTempReg, 3, GILLT_v16s8,
GIR_BuildMI, 4, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 4, 3, GIMT_Encode2(RegState::Define),
GIR_Copy, 4, 0, 1,
GIR_ConstrainSelectedInstOperands, 4,
GIR_BuildMI, 3, GIMT_Encode2(Mips::SHF_B),
GIR_AddTempRegister, 3, 2, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 3, 3,
GIR_AddImm8, 3, 27,
GIR_ConstrainSelectedInstOperands, 3,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 2, 2,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_W),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(10923),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
GIM_RootCheckType, 1, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_MakeTempReg, 0, GILLT_v4s32,
GIR_MakeTempReg, 1, GILLT_v4s32,
GIR_MakeTempReg, 2, GILLT_v16s8,
GIR_MakeTempReg, 3, GILLT_v16s8,
GIR_BuildMI, 4, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 4, 3, GIMT_Encode2(RegState::Define),
GIR_Copy, 4, 0, 1,
GIR_ConstrainSelectedInstOperands, 4,
GIR_BuildMI, 3, GIMT_Encode2(Mips::SHF_B),
GIR_AddTempRegister, 3, 2, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 3, 3,
GIR_AddImm8, 3, 27,
GIR_ConstrainSelectedInstOperands, 3,
GIR_BuildMI, 2, GIMT_Encode2(TargetOpcode::COPY),
GIR_AddTempRegister, 2, 1, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 2, 2,
GIR_ConstrainSelectedInstOperands, 2,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SHF_W),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_AddSimpleTempRegister, 1, 1,
GIR_AddImm, 1, GIMT_Encode8(177),
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(TargetOpcode::COPY),
GIR_RootToRootCopy, 0,
GIR_AddSimpleTempRegister, 0, 0,
GIR_ConstrainOperandRC, 0, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_EraseRootFromParent_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(10989),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_RootCheckType, 0, GILLT_s32,
GIM_CheckMemorySizeEqualToLLT, 0, 0, 0,
GIM_CheckAtomicOrdering, 0, (uint8_t)AtomicOrdering::NotAtomic,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckPointerToAny, 0, 1, 32,
GIM_RecordInsn, 1, 0, 1,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ADD),
GIM_CheckType, 1, 1, GILLT_s32,
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::LWX),
GIR_RootToRootCopy, 0,
GIR_Copy, 0, 1, 1,
GIR_Copy, 0, 1, 2,
GIR_MergeMemOperands, 0, 2, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(11057),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_RootCheckType, 0, GILLT_s32,
GIM_CheckMemorySizeEqualTo, 0, 0, GIMT_Encode4(2),
GIM_CheckAtomicOrdering, 0, (uint8_t)AtomicOrdering::NotAtomic,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckPointerToAny, 0, 1, 32,
GIM_RecordInsn, 1, 0, 1,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ADD),
GIM_CheckType, 1, 1, GILLT_s32,
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::LHX),
GIR_RootToRootCopy, 0,
GIR_Copy, 0, 1, 1,
GIR_Copy, 0, 1, 2,
GIR_MergeMemOperands, 0, 2, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(11125),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_RootCheckType, 0, GILLT_s32,
GIM_CheckMemorySizeEqualTo, 0, 0, GIMT_Encode4(1),
GIM_CheckAtomicOrdering, 0, (uint8_t)AtomicOrdering::NotAtomic,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckPointerToAny, 0, 1, 32,
GIM_RecordInsn, 1, 0, 1,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ADD),
GIM_CheckType, 1, 1, GILLT_s32,
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::LBUX),
GIR_RootToRootCopy, 0,
GIR_Copy, 0, 1, 1,
GIR_Copy, 0, 1, 2,
GIR_MergeMemOperands, 0, 2, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Reject,
GIM_SwitchType, 0, 0, GIMT_Encode2(1), GIMT_Encode2(3), GIMT_Encode4(15846),
GIMT_Encode4(11145),
GIMT_Encode4(15812),
GIM_Try, GIMT_Encode4(11253),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_EQ),
GIM_RecordInsn, 2, 1, 2,
GIM_CheckOpcode, 2, GIMT_Encode2(TargetOpcode::G_AND),
GIM_CheckType, 2, 1, GILLT_s64,
GIM_CheckType, 2, 2, GILLT_s64,
GIM_RecordInsn, 3, 2, 1,
GIM_CheckOpcode, 3, GIMT_Encode2(TargetOpcode::G_SHL),
GIM_CheckType, 3, 1, GILLT_s64,
GIM_CheckType, 3, 2, GILLT_s64,
GIM_CheckConstantInt8, 3, 1, 1,
GIM_RecordInsn, 4, 3, 2,
GIM_CheckOpcode, 4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 4, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
GIM_CheckRegBankForClass, 2, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 4,
GIR_BuildRootMI, GIMT_Encode2(Mips::BBIT0),
GIR_Copy, 0, 2, 2,
GIR_CopyConstantAsSImm, 0, 4,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(11368),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_EQ),
GIM_RecordInsn, 2, 1, 2,
GIM_CheckOpcode, 2, GIMT_Encode2(TargetOpcode::G_AND),
GIM_CheckType, 2, 1, GILLT_s64,
GIM_CheckType, 2, 2, GILLT_s64,
GIM_RecordInsn, 3, 2, 1,
GIM_CheckOpcode, 3, GIMT_Encode2(TargetOpcode::G_SHL),
GIM_CheckType, 3, 1, GILLT_s64,
GIM_CheckType, 3, 2, GILLT_s64,
GIM_CheckConstantInt, 3, 1, GIMT_Encode8(4294967296),
GIM_RecordInsn, 4, 3, 2,
GIM_CheckOpcode, 4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 4, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
GIM_CheckRegBankForClass, 2, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 4,
GIR_BuildRootMI, GIMT_Encode2(Mips::BBIT032),
GIR_Copy, 0, 2, 2,
GIR_CopyConstantAsSImm, 0, 4,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(11476),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_NE),
GIM_RecordInsn, 2, 1, 2,
GIM_CheckOpcode, 2, GIMT_Encode2(TargetOpcode::G_AND),
GIM_CheckType, 2, 1, GILLT_s64,
GIM_CheckType, 2, 2, GILLT_s64,
GIM_RecordInsn, 3, 2, 1,
GIM_CheckOpcode, 3, GIMT_Encode2(TargetOpcode::G_SHL),
GIM_CheckType, 3, 1, GILLT_s64,
GIM_CheckType, 3, 2, GILLT_s64,
GIM_CheckConstantInt8, 3, 1, 1,
GIM_RecordInsn, 4, 3, 2,
GIM_CheckOpcode, 4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 4, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
GIM_CheckRegBankForClass, 2, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 4,
GIR_BuildRootMI, GIMT_Encode2(Mips::BBIT1),
GIR_Copy, 0, 2, 2,
GIR_CopyConstantAsSImm, 0, 4,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(11591),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_NE),
GIM_RecordInsn, 2, 1, 2,
GIM_CheckOpcode, 2, GIMT_Encode2(TargetOpcode::G_AND),
GIM_CheckType, 2, 1, GILLT_s64,
GIM_CheckType, 2, 2, GILLT_s64,
GIM_RecordInsn, 3, 2, 1,
GIM_CheckOpcode, 3, GIMT_Encode2(TargetOpcode::G_SHL),
GIM_CheckType, 3, 1, GILLT_s64,
GIM_CheckType, 3, 2, GILLT_s64,
GIM_CheckConstantInt, 3, 1, GIMT_Encode8(4294967296),
GIM_RecordInsn, 4, 3, 2,
GIM_CheckOpcode, 4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 4, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
GIM_CheckRegBankForClass, 2, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 4,
GIR_BuildRootMI, GIMT_Encode2(Mips::BBIT132),
GIR_Copy, 0, 2, 2,
GIR_CopyConstantAsSImm, 0, 4,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(11699),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_EQ),
GIM_RecordInsn, 2, 1, 2,
GIM_CheckOpcode, 2, GIMT_Encode2(TargetOpcode::G_AND),
GIM_CheckType, 2, 1, GILLT_s64,
GIM_CheckType, 2, 2, GILLT_s64,
GIM_CheckRegBankForClass, 2, 1, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RecordInsn, 3, 2, 2,
GIM_CheckOpcode, 3, GIMT_Encode2(TargetOpcode::G_SHL),
GIM_CheckType, 3, 1, GILLT_s64,
GIM_CheckType, 3, 2, GILLT_s64,
GIM_CheckConstantInt8, 3, 1, 1,
GIM_RecordInsn, 4, 3, 2,
GIM_CheckOpcode, 4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 4, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 4,
GIR_BuildRootMI, GIMT_Encode2(Mips::BBIT0),
GIR_Copy, 0, 2, 1,
GIR_CopyConstantAsSImm, 0, 4,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(11814),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_EQ),
GIM_RecordInsn, 2, 1, 2,
GIM_CheckOpcode, 2, GIMT_Encode2(TargetOpcode::G_AND),
GIM_CheckType, 2, 1, GILLT_s64,
GIM_CheckType, 2, 2, GILLT_s64,
GIM_CheckRegBankForClass, 2, 1, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RecordInsn, 3, 2, 2,
GIM_CheckOpcode, 3, GIMT_Encode2(TargetOpcode::G_SHL),
GIM_CheckType, 3, 1, GILLT_s64,
GIM_CheckType, 3, 2, GILLT_s64,
GIM_CheckConstantInt, 3, 1, GIMT_Encode8(4294967296),
GIM_RecordInsn, 4, 3, 2,
GIM_CheckOpcode, 4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 4, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 4,
GIR_BuildRootMI, GIMT_Encode2(Mips::BBIT032),
GIR_Copy, 0, 2, 1,
GIR_CopyConstantAsSImm, 0, 4,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(11922),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_NE),
GIM_RecordInsn, 2, 1, 2,
GIM_CheckOpcode, 2, GIMT_Encode2(TargetOpcode::G_AND),
GIM_CheckType, 2, 1, GILLT_s64,
GIM_CheckType, 2, 2, GILLT_s64,
GIM_CheckRegBankForClass, 2, 1, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RecordInsn, 3, 2, 2,
GIM_CheckOpcode, 3, GIMT_Encode2(TargetOpcode::G_SHL),
GIM_CheckType, 3, 1, GILLT_s64,
GIM_CheckType, 3, 2, GILLT_s64,
GIM_CheckConstantInt8, 3, 1, 1,
GIM_RecordInsn, 4, 3, 2,
GIM_CheckOpcode, 4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 4, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 4,
GIR_BuildRootMI, GIMT_Encode2(Mips::BBIT1),
GIR_Copy, 0, 2, 1,
GIR_CopyConstantAsSImm, 0, 4,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(12037),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_NE),
GIM_RecordInsn, 2, 1, 2,
GIM_CheckOpcode, 2, GIMT_Encode2(TargetOpcode::G_AND),
GIM_CheckType, 2, 1, GILLT_s64,
GIM_CheckType, 2, 2, GILLT_s64,
GIM_CheckRegBankForClass, 2, 1, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_RecordInsn, 3, 2, 2,
GIM_CheckOpcode, 3, GIMT_Encode2(TargetOpcode::G_SHL),
GIM_CheckType, 3, 1, GILLT_s64,
GIM_CheckType, 3, 2, GILLT_s64,
GIM_CheckConstantInt, 3, 1, GIMT_Encode8(4294967296),
GIM_RecordInsn, 4, 3, 2,
GIM_CheckOpcode, 4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 4, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 4,
GIR_BuildRootMI, GIMT_Encode2(Mips::BBIT132),
GIR_Copy, 0, 2, 1,
GIR_CopyConstantAsSImm, 0, 4,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(12094),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SGE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BGEZ),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(12151),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SGT),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BGTZ),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(12208),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SLE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BLEZ),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(12265),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SLT),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BLTZ),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(12322),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SGE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BGEZ64),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(12379),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SGT),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BGTZ64),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(12436),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SLE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BLEZ64),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(12493),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SLT),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BLTZ64),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(12550),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SGE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BGEZ_MM),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(12607),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SGT),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BGTZ_MM),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(12664),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SLE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BLEZ_MM),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(12721),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SLT),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BLTZ_MM),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(12784),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_NE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BNE),
GIR_Copy, 0, 1, 2,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO), GIMT_Encode2(0),
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(12847),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_EQ),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQ),
GIR_Copy, 0, 1, 2,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO), GIMT_Encode2(0),
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(12910),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_NE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BNE64),
GIR_Copy, 0, 1, 2,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO_64), GIMT_Encode2(0),
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(12973),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_EQ),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQ64),
GIR_Copy, 0, 1, 2,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO_64), GIMT_Encode2(0),
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(13027),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_EQ),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BeqzRxImm16),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(13081),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_NE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BnezRxImm16),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(13144),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_NE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BNE_MM),
GIR_Copy, 0, 1, 2,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO), GIMT_Encode2(0),
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(13207),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_EQ),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQ_MM),
GIR_Copy, 0, 1, 2,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO), GIMT_Encode2(0),
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(13264),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_NE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BNEZC_MMR6),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(13321),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_EQ),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckConstantInt8, 1, 3, 0,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQZC_MMR6),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(13373),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SLT),
GIM_CheckConstantInt8, 1, 3, 1,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BLEZ),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(13425),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SGT),
GIM_CheckConstantInt8, 1, 3, uint8_t(-1),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BGEZ),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(13477),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SLT),
GIM_CheckConstantInt8, 1, 3, 1,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BLEZ64),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(13529),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SGT),
GIM_CheckConstantInt8, 1, 3, uint8_t(-1),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BGEZ64),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(13581),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SLT),
GIM_CheckConstantInt8, 1, 3, 1,
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BLEZ_MM),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(13633),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SGT),
GIM_CheckConstantInt8, 1, 3, uint8_t(-1),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BGEZ_MM),
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(13695),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_EQ),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQ),
GIR_Copy, 0, 1, 2,
GIR_Copy, 0, 1, 3,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(13757),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_NE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BNE),
GIR_Copy, 0, 1, 2,
GIR_Copy, 0, 1, 3,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(13819),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_EQ),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQ64),
GIR_Copy, 0, 1, 2,
GIR_Copy, 0, 1, 3,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(13881),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_NE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BNE64),
GIR_Copy, 0, 1, 2,
GIR_Copy, 0, 1, 3,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(13943),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_EQ),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQ_MM),
GIR_Copy, 0, 1, 2,
GIR_Copy, 0, 1, 3,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(14005),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_NE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BNE_MM),
GIR_Copy, 0, 1, 2,
GIR_Copy, 0, 1, 3,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(14090),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SGE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_MakeTempReg, 0, GILLT_s32,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SLT),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_Copy, 1, 1, 2,
GIR_Copy, 1, 1, 3,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQ),
GIR_AddSimpleTempRegister, 0, 0,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO), GIMT_Encode2(0),
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(14175),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_UGE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_MakeTempReg, 0, GILLT_s32,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SLTu),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_Copy, 1, 1, 2,
GIR_Copy, 1, 1, 3,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQ),
GIR_AddSimpleTempRegister, 0, 0,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO), GIMT_Encode2(0),
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(14260),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SLE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_MakeTempReg, 0, GILLT_s32,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SLT),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_Copy, 1, 1, 3,
GIR_Copy, 1, 1, 2,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQ),
GIR_AddSimpleTempRegister, 0, 0,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO), GIMT_Encode2(0),
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(14345),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_ULE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_MakeTempReg, 0, GILLT_s32,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SLTu),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_Copy, 1, 1, 3,
GIR_Copy, 1, 1, 2,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQ),
GIR_AddSimpleTempRegister, 0, 0,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO), GIMT_Encode2(0),
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(14430),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SGE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_MakeTempReg, 0, GILLT_s32,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SLT64),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_Copy, 1, 1, 2,
GIR_Copy, 1, 1, 3,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQ),
GIR_AddSimpleTempRegister, 0, 0,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO), GIMT_Encode2(0),
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(14515),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_UGE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_MakeTempReg, 0, GILLT_s32,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SLTu64),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_Copy, 1, 1, 2,
GIR_Copy, 1, 1, 3,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQ),
GIR_AddSimpleTempRegister, 0, 0,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO), GIMT_Encode2(0),
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(14600),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SLE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_MakeTempReg, 0, GILLT_s32,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SLT64),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_Copy, 1, 1, 3,
GIR_Copy, 1, 1, 2,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQ),
GIR_AddSimpleTempRegister, 0, 0,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO), GIMT_Encode2(0),
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(14685),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s64,
GIM_CheckType, 1, 3, GILLT_s64,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_ULE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_MakeTempReg, 0, GILLT_s32,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SLTu64),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_Copy, 1, 1, 3,
GIR_Copy, 1, 1, 2,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQ),
GIR_AddSimpleTempRegister, 0, 0,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO), GIMT_Encode2(0),
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(14744),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_EQ),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BteqzT8CmpX16),
GIR_Copy, 0, 1, 2,
GIR_Copy, 0, 1, 3,
GIR_RootToRootCopy, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(14803),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SGT),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BtnezT8SltX16),
GIR_Copy, 0, 1, 3,
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(14862),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SGE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BteqzT8SltX16),
GIR_Copy, 0, 1, 2,
GIR_Copy, 0, 1, 3,
GIR_RootToRootCopy, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(14921),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SLT),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BtnezT8SltX16),
GIR_Copy, 0, 1, 2,
GIR_Copy, 0, 1, 3,
GIR_RootToRootCopy, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(14980),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SLE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BteqzT8SltX16),
GIR_Copy, 0, 1, 3,
GIR_Copy, 0, 1, 2,
GIR_RootToRootCopy, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(15039),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_NE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BtnezT8CmpX16),
GIR_Copy, 0, 1, 2,
GIR_Copy, 0, 1, 3,
GIR_RootToRootCopy, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(15124),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SGE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_MakeTempReg, 0, GILLT_s32,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SLT_MM),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_Copy, 1, 1, 2,
GIR_Copy, 1, 1, 3,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQ_MM),
GIR_AddSimpleTempRegister, 0, 0,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO), GIMT_Encode2(0),
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(15209),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_UGE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_MakeTempReg, 0, GILLT_s32,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SLTu_MM),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_Copy, 1, 1, 2,
GIR_Copy, 1, 1, 3,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQ_MM),
GIR_AddSimpleTempRegister, 0, 0,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO), GIMT_Encode2(0),
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(15294),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SLE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_MakeTempReg, 0, GILLT_s32,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SLT_MM),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_Copy, 1, 1, 3,
GIR_Copy, 1, 1, 2,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQ_MM),
GIR_AddSimpleTempRegister, 0, 0,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO), GIMT_Encode2(0),
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(15379),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_ULE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_MakeTempReg, 0, GILLT_s32,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SLTu_MM),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_Copy, 1, 1, 3,
GIR_Copy, 1, 1, 2,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQ_MM),
GIR_AddSimpleTempRegister, 0, 0,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO), GIMT_Encode2(0),
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(15458),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SGE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_MakeTempReg, 0, GILLT_s32,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SLT_MM),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_Copy, 1, 1, 2,
GIR_Copy, 1, 1, 3,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQZC_MMR6),
GIR_AddSimpleTempRegister, 0, 0,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(15537),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_UGE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_MakeTempReg, 0, GILLT_s32,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SLTu_MM),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_Copy, 1, 1, 2,
GIR_Copy, 1, 1, 3,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQZC_MMR6),
GIR_AddSimpleTempRegister, 0, 0,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(15616),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_SLE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_MakeTempReg, 0, GILLT_s32,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SLT_MM),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_Copy, 1, 1, 3,
GIR_Copy, 1, 1, 2,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQZC_MMR6),
GIR_AddSimpleTempRegister, 0, 0,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(15695),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIM_RecordInsn, 1, 0, 0,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_ICMP),
GIM_CheckType, 1, 2, GILLT_s32,
GIM_CheckType, 1, 3, GILLT_s32,
GIM_CheckCmpPredicate, 1, 1, GIMT_Encode2(CmpInst::ICMP_ULE),
GIM_CheckRegBankForClass, 1, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckRegBankForClass, 1, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsMBB, 0, 1,
GIM_CheckIsSafeToFold, 1,
GIR_MakeTempReg, 0, GILLT_s32,
GIR_BuildMI, 1, GIMT_Encode2(Mips::SLTu_MM),
GIR_AddTempRegister, 1, 0, GIMT_Encode2(RegState::Define),
GIR_Copy, 1, 1, 3,
GIR_Copy, 1, 1, 2,
GIR_ConstrainSelectedInstOperands, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BEQZC_MMR6),
GIR_AddSimpleTempRegister, 0, 0,
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(15728),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsMBB, 0, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BNE),
GIR_RootToRootCopy, 0,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO), GIMT_Encode2(0),
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(15750),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::CPU16RegsRegClassID),
GIM_CheckIsMBB, 0, 1,
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::BnezRxImm16),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Try, GIMT_Encode4(15783),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsMBB, 0, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BNE_MM),
GIR_RootToRootCopy, 0,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO), GIMT_Encode2(0),
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(15811),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsMBB, 0, 1,
GIR_MutateOpcode, 0, 0, GIMT_Encode2(Mips::BNEZC_MMR6),
GIR_AddImplicitDef, 0, GIMT_Encode2(Mips::AT), GIMT_Encode2(RegState::Dead),
GIR_RootConstrainSelectedInstOperands,
GIR_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(15845),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR64RegClassID),
GIM_CheckIsMBB, 0, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BNE64),
GIR_RootToRootCopy, 0,
GIR_AddRegister, 0, GIMT_Encode2(Mips::ZERO_64), GIMT_Encode2(0),
GIR_RootToRootCopy, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(17844),
GIM_CheckNumOperands, 0, 3,
GIM_Try, GIMT_Encode4(15902),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_repl_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt8),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::REPL_QB),
GIR_RootToRootCopy, 0,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(15949),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_repl_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immSExt10),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::REPL_PH),
GIR_RootToRootCopy, 0,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(15996),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_repl_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immSExt10),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::REPL_PH_MM),
GIR_RootToRootCopy, 0,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16043),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_repl_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RecordInsn, 1, 0, 2,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt8),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::REPL_QB_MM),
GIR_RootToRootCopy, 0,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16079),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_raddu_w_qb),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::RADDU_W_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16115),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_preceq_w_phl),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECEQ_W_PHL),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16151),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_preceq_w_phr),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECEQ_W_PHR),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16187),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbl),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECEQU_PH_QBL),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16223),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbr),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECEQU_PH_QBR),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16259),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbla),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECEQU_PH_QBLA),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16295),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbra),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECEQU_PH_QBRA),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16331),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbl),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECEU_PH_QBL),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16367),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbr),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECEU_PH_QBR),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16403),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbla),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECEU_PH_QBLA),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16439),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbra),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECEU_PH_QBRA),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16475),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_bitrev),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::BITREV),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16511),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_repl_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::REPLV_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16547),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_repl_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::REPLV_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16583),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fclass_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FCLASS_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16619),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fclass_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FCLASS_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16655),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fexupl_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FEXUPL_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16691),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fexupl_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FEXUPL_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16727),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fexupr_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FEXUPR_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16763),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fexupr_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FEXUPR_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16799),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_ffql_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FFQL_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16835),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_ffql_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FFQL_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16871),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_ffqr_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FFQR_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16907),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_ffqr_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FFQR_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16943),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_frcp_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FRCP_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(16979),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_frcp_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FRCP_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17015),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_frsqrt_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FRSQRT_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17051),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_frsqrt_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FRSQRT_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17087),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_ftint_s_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FTINT_S_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17123),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_ftint_s_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FTINT_S_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17159),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_ftint_u_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FTINT_U_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17195),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_ftint_u_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FTINT_U_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17231),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_nloc_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::NLOC_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17267),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_nloc_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::NLOC_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17303),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_nloc_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::NLOC_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17339),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_nloc_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::NLOC_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17375),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_preceq_w_phl),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECEQ_W_PHL_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17411),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_preceq_w_phr),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECEQ_W_PHR_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17447),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbl),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECEQU_PH_QBL_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17483),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbla),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECEQU_PH_QBLA_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17519),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbr),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECEQU_PH_QBR_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17555),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbra),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECEQU_PH_QBRA_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17591),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbl),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECEU_PH_QBL_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17627),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbla),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECEU_PH_QBLA_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17663),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbr),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECEU_PH_QBR_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17699),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbra),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECEU_PH_QBRA_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17735),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_raddu_w_qb),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::RADDU_W_QB_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17771),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_repl_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::REPLV_PH_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17807),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_repl_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::REPLV_QB_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17843),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_bitrev),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::BITREV_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(27597),
GIM_CheckNumOperands, 0, 4,
GIM_Try, GIMT_Encode4(17898),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_sat_s_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_CheckIsImm, 0, 3,
GIM_CheckImmOperandPredicate, 0, 3, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
GIR_BuildRootMI, GIMT_Encode2(Mips::SAT_S_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17944),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_sat_s_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_CheckIsImm, 0, 3,
GIM_CheckImmOperandPredicate, 0, 3, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
GIR_BuildRootMI, GIMT_Encode2(Mips::SAT_S_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(17990),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_sat_s_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_CheckIsImm, 0, 3,
GIM_CheckImmOperandPredicate, 0, 3, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
GIR_BuildRootMI, GIMT_Encode2(Mips::SAT_S_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(18036),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_sat_s_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_CheckIsImm, 0, 3,
GIM_CheckImmOperandPredicate, 0, 3, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
GIR_BuildRootMI, GIMT_Encode2(Mips::SAT_S_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(18082),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_sat_u_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_CheckIsImm, 0, 3,
GIM_CheckImmOperandPredicate, 0, 3, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
GIR_BuildRootMI, GIMT_Encode2(Mips::SAT_U_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(18128),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_sat_u_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_CheckIsImm, 0, 3,
GIM_CheckImmOperandPredicate, 0, 3, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
GIR_BuildRootMI, GIMT_Encode2(Mips::SAT_U_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(18174),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_sat_u_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_CheckIsImm, 0, 3,
GIM_CheckImmOperandPredicate, 0, 3, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
GIR_BuildRootMI, GIMT_Encode2(Mips::SAT_U_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(18220),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_sat_u_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_CheckIsImm, 0, 3,
GIM_CheckImmOperandPredicate, 0, 3, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
GIR_BuildRootMI, GIMT_Encode2(Mips::SAT_U_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(18266),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_srari_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_CheckIsImm, 0, 3,
GIM_CheckImmOperandPredicate, 0, 3, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
GIR_BuildRootMI, GIMT_Encode2(Mips::SRARI_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(18312),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_srari_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_CheckIsImm, 0, 3,
GIM_CheckImmOperandPredicate, 0, 3, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
GIR_BuildRootMI, GIMT_Encode2(Mips::SRARI_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(18358),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_srari_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_CheckIsImm, 0, 3,
GIM_CheckImmOperandPredicate, 0, 3, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
GIR_BuildRootMI, GIMT_Encode2(Mips::SRARI_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(18404),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_srari_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_CheckIsImm, 0, 3,
GIM_CheckImmOperandPredicate, 0, 3, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
GIR_BuildRootMI, GIMT_Encode2(Mips::SRARI_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(18450),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_srlri_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_CheckIsImm, 0, 3,
GIM_CheckImmOperandPredicate, 0, 3, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
GIR_BuildRootMI, GIMT_Encode2(Mips::SRLRI_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(18496),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_srlri_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_CheckIsImm, 0, 3,
GIM_CheckImmOperandPredicate, 0, 3, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
GIR_BuildRootMI, GIMT_Encode2(Mips::SRLRI_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(18542),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_srlri_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_CheckIsImm, 0, 3,
GIM_CheckImmOperandPredicate, 0, 3, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
GIR_BuildRootMI, GIMT_Encode2(Mips::SRLRI_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(18588),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_srlri_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_CheckIsImm, 0, 3,
GIM_CheckImmOperandPredicate, 0, 3, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
GIR_BuildRootMI, GIMT_Encode2(Mips::SRLRI_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(18644),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RecordInsn, 1, 0, 3,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRA_R_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(18700),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RecordInsn, 1, 0, 3,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRA_R_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(18756),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RecordInsn, 1, 0, 3,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRA_R_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(18812),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RecordInsn, 1, 0, 3,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRA_R_PH_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(18868),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RecordInsn, 1, 0, 3,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRA_R_W_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(18924),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RecordInsn, 1, 0, 3,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRA_R_QB_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(18976),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shra_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RecordInsn, 1, 0, 3,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRA_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19028),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RecordInsn, 1, 0, 3,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRL_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19080),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shra_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RecordInsn, 1, 0, 3,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRA_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19132),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RecordInsn, 1, 0, 3,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRL_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19180),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_addu_s_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDU_S_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19228),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subu_s_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBU_S_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19276),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_addq_s_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDQ_S_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19324),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subq_s_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBQ_S_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19369),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_modsub),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MODSUB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19414),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_precrq_qb_ph),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECRQ_QB_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19459),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_precrq_ph_w),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECRQ_PH_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19504),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRLV_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19549),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shra_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRAV_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19594),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRAV_R_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19639),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRAV_R_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19684),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_packrl_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PACKRL_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19729),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_adduh_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDUH_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19774),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_adduh_r_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDUH_R_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19819),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subuh_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBUH_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19864),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subuh_r_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBUH_R_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19909),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_addqh_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDQH_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19954),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_addqh_r_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDQH_R_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(19999),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subqh_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBQH_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20044),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subqh_r_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBQH_R_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20089),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_addqh_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDQH_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20134),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_addqh_r_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDQH_R_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20179),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subqh_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBQH_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20224),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subqh_r_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBQH_R_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20269),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shra_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRAV_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20314),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRAV_R_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20359),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRLV_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20404),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_add_a_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADD_A_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20449),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_add_a_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADD_A_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20494),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_add_a_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADD_A_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20539),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_add_a_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADD_A_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20584),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_adds_a_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDS_A_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20629),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_adds_a_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDS_A_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20674),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_adds_a_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDS_A_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20719),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_adds_a_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDS_A_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20764),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_adds_s_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDS_S_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20809),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_adds_s_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDS_S_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20854),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_adds_s_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDS_S_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20899),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_adds_s_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDS_S_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20944),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_adds_u_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDS_U_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(20989),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_adds_u_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDS_U_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21034),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_adds_u_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDS_U_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21079),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_adds_u_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDS_U_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21124),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_asub_s_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ASUB_S_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21169),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_asub_s_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ASUB_S_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21214),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_asub_s_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ASUB_S_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21259),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_asub_s_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ASUB_S_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21304),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_asub_u_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ASUB_U_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21349),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_asub_u_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ASUB_U_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21394),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_asub_u_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ASUB_U_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21439),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_asub_u_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ASUB_U_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21484),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_ave_s_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::AVE_S_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21529),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_ave_s_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::AVE_S_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21574),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_ave_s_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::AVE_S_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21619),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_ave_s_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::AVE_S_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21664),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_ave_u_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::AVE_U_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21709),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_ave_u_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::AVE_U_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21754),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_ave_u_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::AVE_U_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21799),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_ave_u_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::AVE_U_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21844),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_aver_s_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::AVER_S_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21889),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_aver_s_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::AVER_S_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21934),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_aver_s_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::AVER_S_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(21979),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_aver_s_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::AVER_S_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22024),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_aver_u_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::AVER_U_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22069),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_aver_u_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::AVER_U_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22114),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_aver_u_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::AVER_U_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22159),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_aver_u_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::AVER_U_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22204),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_dotp_s_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::DOTP_S_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22249),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_dotp_s_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::DOTP_S_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22294),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_dotp_s_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::DOTP_S_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22339),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_dotp_u_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::DOTP_U_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22384),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_dotp_u_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::DOTP_U_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22429),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_dotp_u_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::DOTP_U_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22474),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fcaf_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FCAF_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22519),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fcaf_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FCAF_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22564),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fexdo_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FEXDO_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22609),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fexdo_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FEXDO_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22654),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fmax_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FMAX_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22699),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fmax_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FMAX_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22744),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fmax_a_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FMAX_A_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22789),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fmax_a_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FMAX_A_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22834),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fmin_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FMIN_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22879),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fmin_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FMIN_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22924),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fmin_a_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FMIN_A_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(22969),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fmin_a_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FMIN_A_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23014),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fsaf_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSAF_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23059),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fsaf_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSAF_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23104),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fseq_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSEQ_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23149),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fseq_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSEQ_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23194),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fsle_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSLE_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23239),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fsle_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSLE_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23284),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fslt_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSLT_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23329),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fslt_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSLT_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23374),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fsne_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSNE_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23419),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fsne_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSNE_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23464),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fsor_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSOR_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23509),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fsor_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSOR_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23554),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fsueq_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSUEQ_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23599),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fsueq_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSUEQ_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23644),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fsule_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSULE_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23689),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fsule_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSULE_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23734),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fsult_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSULT_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23779),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fsult_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSULT_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23824),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fsun_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSUN_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23869),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fsun_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSUN_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23914),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fsune_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSUNE_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(23959),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_fsune_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FSUNE_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24004),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_ftq_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FTQ_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24049),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_ftq_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::FTQ_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24094),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_hadd_s_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::HADD_S_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24139),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_hadd_s_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::HADD_S_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24184),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_hadd_s_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::HADD_S_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24229),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_hadd_u_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::HADD_U_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24274),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_hadd_u_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::HADD_U_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24319),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_hadd_u_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::HADD_U_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24364),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_hsub_s_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::HSUB_S_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24409),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_hsub_s_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::HSUB_S_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24454),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_hsub_s_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::HSUB_S_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24499),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_hsub_u_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::HSUB_U_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24544),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_hsub_u_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::HSUB_U_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24589),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_hsub_u_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::HSUB_U_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24634),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_max_a_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MAX_A_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24679),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_max_a_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MAX_A_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24724),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_max_a_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MAX_A_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24769),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_max_a_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MAX_A_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24814),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_min_a_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MIN_A_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24859),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_min_a_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MIN_A_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24904),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_min_a_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MIN_A_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24949),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_min_a_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MIN_A_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(24994),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_mul_q_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MUL_Q_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25039),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_mul_q_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MUL_Q_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25084),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_mulr_q_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MULR_Q_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25129),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_mulr_q_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MULR_Q_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25174),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_srar_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SRAR_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25219),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_srar_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SRAR_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25264),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_srar_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SRAR_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25309),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_srar_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SRAR_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25354),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_srlr_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SRLR_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25399),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_srlr_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SRLR_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25444),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_srlr_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SRLR_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25489),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_srlr_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SRLR_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25534),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subs_s_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBS_S_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25579),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subs_s_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBS_S_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25624),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subs_s_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBS_S_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25669),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subs_s_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBS_S_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25714),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subs_u_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBS_U_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25759),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subs_u_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBS_U_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25804),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subs_u_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBS_U_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25849),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subs_u_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBS_U_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25894),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subsus_u_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBSUS_U_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25939),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subsus_u_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBSUS_U_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(25984),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subsus_u_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBSUS_U_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26029),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subsus_u_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBSUS_U_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26074),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subsuu_s_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBSUU_S_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26119),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subsuu_s_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBSUU_S_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26164),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subsuu_s_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBSUU_S_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26209),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subsuu_s_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBSUU_S_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26257),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_addq_s_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDQ_S_PH_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26305),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_addu_s_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDU_S_QB_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26350),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shra_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRAV_PH_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26395),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRAV_R_PH_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26440),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRAV_R_W_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26485),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRLV_QB_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26533),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subq_s_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBQ_S_PH_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26581),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subu_s_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBU_S_QB_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26626),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_precrq_ph_w),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECRQ_PH_W_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26671),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_precrq_qb_ph),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECRQ_QB_PH_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26716),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_packrl_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PACKRL_PH_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26761),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_modsub),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MODSUB_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26806),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_addqh_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDQH_PH_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26851),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_addqh_r_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDQH_R_PH_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26896),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_addqh_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDQH_W_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26941),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_addqh_r_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDQH_R_W_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(26986),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_adduh_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDUH_QB_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(27031),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_adduh_r_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDUH_R_QB_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(27076),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shra_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRAV_QB_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(27121),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRAV_R_QB_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(27166),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHRLV_PH_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(27211),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subqh_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBQH_PH_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(27256),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subqh_r_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBQH_R_PH_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(27301),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subqh_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBQH_W_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(27346),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subqh_r_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBQH_R_W_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(27391),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subuh_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBUH_QB_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(27436),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subuh_r_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBUH_R_QB_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(27476),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_addq_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDQ_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(27516),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subq_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBQ_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(27556),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_addu_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDU_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(27596),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subu_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBU_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(30111),
GIM_CheckNumOperands, 0, 5,
GIM_Try, GIMT_Encode4(27660),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_precr_sra_ph_w),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsImm, 0, 4,
GIM_CheckImmOperandPredicate, 0, 4, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECR_SRA_PH_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(27715),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_precr_sra_r_ph_w),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsImm, 0, 4,
GIM_CheckImmOperandPredicate, 0, 4, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECR_SRA_R_PH_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(27770),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_append),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsImm, 0, 4,
GIM_CheckImmOperandPredicate, 0, 4, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
GIR_BuildRootMI, GIMT_Encode2(Mips::APPEND),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(27825),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_balign),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsImm, 0, 4,
GIM_CheckImmOperandPredicate, 0, 4, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt2),
GIR_BuildRootMI, GIMT_Encode2(Mips::BALIGN),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(27880),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_prepend),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsImm, 0, 4,
GIM_CheckImmOperandPredicate, 0, 4, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
GIR_BuildRootMI, GIMT_Encode2(Mips::PREPEND),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(27935),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_sldi_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_CheckIsImm, 0, 4,
GIM_CheckImmOperandPredicate, 0, 4, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
GIR_BuildRootMI, GIMT_Encode2(Mips::SLDI_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(27990),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_sldi_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_CheckIsImm, 0, 4,
GIM_CheckImmOperandPredicate, 0, 4, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
GIR_BuildRootMI, GIMT_Encode2(Mips::SLDI_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(28045),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_sldi_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_CheckIsImm, 0, 4,
GIM_CheckImmOperandPredicate, 0, 4, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt2),
GIR_BuildRootMI, GIMT_Encode2(Mips::SLDI_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(28100),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_sldi_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_CheckIsImm, 0, 4,
GIM_CheckImmOperandPredicate, 0, 4, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt1),
GIR_BuildRootMI, GIMT_Encode2(Mips::SLDI_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(28155),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_precr_sra_ph_w),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsImm, 0, 4,
GIM_CheckImmOperandPredicate, 0, 4, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECR_SRA_PH_W_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(28210),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_precr_sra_r_ph_w),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsImm, 0, 4,
GIM_CheckImmOperandPredicate, 0, 4, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECR_SRA_R_PH_W_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(28265),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_prepend),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsImm, 0, 4,
GIM_CheckImmOperandPredicate, 0, 4, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
GIR_BuildRootMI, GIMT_Encode2(Mips::PREPEND_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(28320),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_append),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsImm, 0, 4,
GIM_CheckImmOperandPredicate, 0, 4, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
GIR_BuildRootMI, GIMT_Encode2(Mips::APPEND_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(28382),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_balign),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RecordInsn, 1, 0, 4,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::BALIGN_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 3,
GIR_CopyConstantAsSImm, 0, 1,
GIR_RootToRootCopy, 2,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(28436),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_binsl_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckType, 4, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::BINSL_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(28490),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_binsl_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckType, 4, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::BINSL_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(28544),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_binsl_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckType, 4, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::BINSL_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(28598),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_binsl_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckType, 4, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::BINSL_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(28652),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_binsr_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckType, 4, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::BINSR_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(28706),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_binsr_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckType, 4, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::BINSR_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(28760),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_binsr_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckType, 4, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::BINSR_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(28814),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_binsr_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckType, 4, GILLT_v2s64,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128DRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::BINSR_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(28868),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_dpadd_s_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckType, 4, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::DPADD_S_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(28922),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_dpadd_s_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckType, 4, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::DPADD_S_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(28976),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_dpadd_s_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckType, 4, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::DPADD_S_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(29030),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_dpadd_u_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckType, 4, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::DPADD_U_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(29084),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_dpadd_u_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckType, 4, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::DPADD_U_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(29138),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_dpadd_u_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckType, 4, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::DPADD_U_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(29192),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_dpsub_s_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckType, 4, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::DPSUB_S_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(29246),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_dpsub_s_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckType, 4, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::DPSUB_S_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(29300),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_dpsub_s_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckType, 4, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::DPSUB_S_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(29354),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_dpsub_u_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckType, 4, GILLT_v16s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128BRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::DPSUB_U_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(29408),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_dpsub_u_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckType, 4, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::DPSUB_U_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(29462),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_dpsub_u_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckType, 4, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::DPSUB_U_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(29516),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_madd_q_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckType, 4, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MADD_Q_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(29570),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_madd_q_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckType, 4, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MADD_Q_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(29624),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_maddr_q_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckType, 4, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MADDR_Q_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(29678),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_maddr_q_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckType, 4, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MADDR_Q_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(29732),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_msub_q_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckType, 4, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MSUB_Q_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(29786),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_msub_q_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckType, 4, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MSUB_Q_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(29840),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_msubr_q_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckType, 4, GILLT_v8s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128HRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MSUBR_Q_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(29894),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_msubr_q_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckType, 4, GILLT_v4s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::MSA128WRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MSUBR_Q_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(29948),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_sld_b),
GIM_RootCheckType, 0, GILLT_v16s8,
GIM_RootCheckType, 2, GILLT_v16s8,
GIM_RootCheckType, 3, GILLT_v16s8,
GIM_RootCheckType, 4, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128BRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SLD_B),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30002),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_sld_h),
GIM_RootCheckType, 0, GILLT_v8s16,
GIM_RootCheckType, 2, GILLT_v8s16,
GIM_RootCheckType, 3, GILLT_v8s16,
GIM_RootCheckType, 4, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128HRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SLD_H),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30056),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_sld_w),
GIM_RootCheckType, 0, GILLT_v4s32,
GIM_RootCheckType, 2, GILLT_v4s32,
GIM_RootCheckType, 3, GILLT_v4s32,
GIM_RootCheckType, 4, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128WRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SLD_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30110),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_sld_d),
GIM_RootCheckType, 0, GILLT_v2s64,
GIM_RootCheckType, 2, GILLT_v2s64,
GIM_RootCheckType, 3, GILLT_v2s64,
GIM_RootCheckType, 4, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::MSA128DRegClassID),
GIM_RootCheckRegBankForClass, 4, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SLD_D),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_RootToRootCopy, 4,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Reject,
GIM_Reject,
GIM_Try, GIMT_Encode4(30143),
GIM_CheckNumOperands, 0, 2,
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_bposge32),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::BPOSGE32_PSEUDO),
GIR_RootToRootCopy, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(31080),
GIM_CheckNumOperands, 0, 3,
GIM_Try, GIMT_Encode4(30192),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_rddsp),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsImm, 0, 2,
GIM_CheckImmOperandPredicate, 0, 2, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt10),
GIR_BuildRootMI, GIMT_Encode2(Mips::RDDSP),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30228),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_rddsp),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsImm, 0, 2,
GIR_BuildRootMI, GIMT_Encode2(Mips::RDDSP_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30269),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_NotInMicroMips),
GIM_CheckIntrinsicID, 0, 0, GIMT_Encode2(Intrinsic::mips_wrdsp),
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsImm, 0, 2,
GIM_CheckImmOperandPredicate, 0, 2, GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt10),
GIR_BuildRootMI, GIMT_Encode2(Mips::WRDSP),
GIR_RootToRootCopy, 1,
GIR_RootToRootCopy, 2,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30305),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 0, GIMT_Encode2(Intrinsic::mips_wrdsp),
GIM_RootCheckType, 1, GILLT_s32,
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_CheckIsImm, 0, 2,
GIR_BuildRootMI, GIMT_Encode2(Mips::WRDSP_MM),
GIR_RootToRootCopy, 1,
GIR_RootToRootCopy, 2,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30348),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_absq_s_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ABSQ_S_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30391),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_absq_s_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ABSQ_S_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30434),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_absq_s_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ABSQ_S_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30477),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_absq_s_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ABSQ_S_PH_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30520),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_absq_s_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ABSQ_S_W_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30563),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_absq_s_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ABSQ_S_QB_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30606),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 0, GIMT_Encode2(Intrinsic::mips_cmpu_eq_qb),
GIM_RootCheckType, 1, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMPU_EQ_QB),
GIR_RootToRootCopy, 1,
GIR_RootToRootCopy, 2,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30649),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 0, GIMT_Encode2(Intrinsic::mips_cmpu_lt_qb),
GIM_RootCheckType, 1, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMPU_LT_QB),
GIR_RootToRootCopy, 1,
GIR_RootToRootCopy, 2,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30692),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 0, GIMT_Encode2(Intrinsic::mips_cmpu_le_qb),
GIM_RootCheckType, 1, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMPU_LE_QB),
GIR_RootToRootCopy, 1,
GIR_RootToRootCopy, 2,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30735),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 0, GIMT_Encode2(Intrinsic::mips_cmp_eq_ph),
GIM_RootCheckType, 1, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMP_EQ_PH),
GIR_RootToRootCopy, 1,
GIR_RootToRootCopy, 2,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30778),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 0, GIMT_Encode2(Intrinsic::mips_cmp_lt_ph),
GIM_RootCheckType, 1, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMP_LT_PH),
GIR_RootToRootCopy, 1,
GIR_RootToRootCopy, 2,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30821),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 0, GIMT_Encode2(Intrinsic::mips_cmp_le_ph),
GIM_RootCheckType, 1, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMP_LE_PH),
GIR_RootToRootCopy, 1,
GIR_RootToRootCopy, 2,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30864),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 0, GIMT_Encode2(Intrinsic::mips_cmp_eq_ph),
GIM_RootCheckType, 1, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMP_EQ_PH_MM),
GIR_RootToRootCopy, 1,
GIR_RootToRootCopy, 2,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30907),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 0, GIMT_Encode2(Intrinsic::mips_cmp_lt_ph),
GIM_RootCheckType, 1, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMP_LT_PH_MM),
GIR_RootToRootCopy, 1,
GIR_RootToRootCopy, 2,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30950),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 0, GIMT_Encode2(Intrinsic::mips_cmp_le_ph),
GIM_RootCheckType, 1, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMP_LE_PH_MM),
GIR_RootToRootCopy, 1,
GIR_RootToRootCopy, 2,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(30993),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 0, GIMT_Encode2(Intrinsic::mips_cmpu_eq_qb),
GIM_RootCheckType, 1, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMPU_EQ_QB_MM),
GIR_RootToRootCopy, 1,
GIR_RootToRootCopy, 2,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(31036),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 0, GIMT_Encode2(Intrinsic::mips_cmpu_lt_qb),
GIM_RootCheckType, 1, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMPU_LT_QB_MM),
GIR_RootToRootCopy, 1,
GIR_RootToRootCopy, 2,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(31079),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 0, GIMT_Encode2(Intrinsic::mips_cmpu_le_qb),
GIM_RootCheckType, 1, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 1, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMPU_LE_QB_MM),
GIR_RootToRootCopy, 1,
GIR_RootToRootCopy, 2,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Reject,
GIM_Try, GIMT_Encode4(34769),
GIM_CheckNumOperands, 0, 4,
GIM_Try, GIMT_Encode4(31152),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RecordInsn, 1, 0, 3,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::SHLL_S_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_CopyConstantAsSImm, 0, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 2, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(31216),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RecordInsn, 1, 0, 3,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::SHLL_S_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_CopyConstantAsSImm, 0, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 2, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(31280),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RecordInsn, 1, 0, 3,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::SHLL_S_PH_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_CopyConstantAsSImm, 0, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 2, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(31344),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RecordInsn, 1, 0, 3,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::SHLL_S_W_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_CopyConstantAsSImm, 0, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 2, 0, 1,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(31399),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shll_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RecordInsn, 1, 0, 3,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::SHLL_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_CopyConstantAsSImm, 0, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(31454),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shll_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RecordInsn, 1, 0, 3,
GIM_CheckOpcode, 1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
GIM_CheckI64ImmPredicate, 1, GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
GIM_CheckIsSafeToFold, 1,
GIR_BuildRootMI, GIMT_Encode2(Mips::SHLL_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_CopyConstantAsSImm, 0, 1,
GIR_SetImplicitDefDead, 0, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(31506),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_addq_s_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDQ_S_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(31558),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subq_s_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBQ_S_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(31610),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_precrq_rs_ph_w),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECRQ_RS_PH_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(31662),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_precrqu_s_qb_ph),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECRQU_S_QB_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(31714),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shll_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHLLV_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(31766),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shll_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHLLV_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(31818),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHLLV_S_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(31870),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHLLV_S_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(31922),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbl),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MULEU_S_PH_QBL),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(31974),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbr),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MULEU_S_PH_QBR),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(32026),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phl),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MULEQ_S_W_PHL),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(32078),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phr),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MULEQ_S_W_PHR),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(32130),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_mulq_rs_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MULQ_RS_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(32179),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_cmpgu_eq_qb),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMPGU_EQ_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(32228),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_cmpgu_lt_qb),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMPGU_LT_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(32277),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_cmpgu_le_qb),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMPGU_LE_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(32326),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_pick_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PICK_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(32375),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_pick_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PICK_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(32424),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_insv),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::INSV),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(32476),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_addu_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDU_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(32528),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_addu_s_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDU_S_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(32580),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subu_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBU_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(32632),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subu_s_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBU_S_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(32684),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_cmpgdu_eq_qb),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMPGDU_EQ_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(32736),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_cmpgdu_lt_qb),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMPGDU_LT_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(32788),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_cmpgdu_le_qb),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMPGDU_LE_QB),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(32840),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_mul_s_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MUL_S_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(32892),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_mulq_s_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MULQ_S_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(32944),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_mulq_rs_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MULQ_RS_W),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(32996),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_mulq_s_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MULQ_S_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(33045),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_precr_qb_ph),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECR_QB_PH),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(33097),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_addq_s_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDQ_S_W_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(33146),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_insv),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::INSV_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(33198),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shll_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHLLV_PH_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(33250),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHLLV_S_PH_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(33302),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shll_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHLLV_QB_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(33354),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SHLLV_S_W_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(33406),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_subq_s_w),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::SUBQ_S_W_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(33458),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phl),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MULEQ_S_W_PHL_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(33510),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phr),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MULEQ_S_W_PHR_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(33562),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbl),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MULEU_S_PH_QBL_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(33614),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbr),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MULEU_S_PH_QBR_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(33666),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_mulq_rs_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::MULQ_RS_PH_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(33718),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_precrqu_s_qb_ph),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECRQU_S_QB_PH_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(33770),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_precrq_rs_ph_w),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_s32,
GIM_RootCheckType, 3, GILLT_s32,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::GPR32RegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PRECRQ_RS_PH_W_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(33819),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_pick_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PICK_PH_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(33868),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_pick_qb),
GIM_RootCheckType, 0, GILLT_v4s8,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::PICK_QB_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(33917),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_cmpgu_eq_qb),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMPGU_EQ_QB_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(33966),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_cmpgu_lt_qb),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMPGU_LT_QB_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(34015),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_cmpgu_le_qb),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMPGU_LE_QB_MM),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(34067),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_addu_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDU_PH_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(34119),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_addu_s_ph),
GIM_RootCheckType, 0, GILLT_v2s16,
GIM_RootCheckType, 2, GILLT_v2s16,
GIM_RootCheckType, 3, GILLT_v2s16,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::ADDU_S_PH_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(34171),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_cmpgdu_eq_qb),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMPGDU_EQ_QB_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(34223),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_cmpgdu_lt_qb),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMPGDU_LT_QB_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(34275),
GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
GIM_CheckIntrinsicID, 0, 1, GIMT_Encode2(Intrinsic::mips_cmpgdu_le_qb),
GIM_RootCheckType, 0, GILLT_s32,
GIM_RootCheckType, 2, GILLT_v4s8,
GIM_RootCheckType, 3, GILLT_v4s8,
GIM_RootCheckRegBankForClass, 0, GIMT_Encode2(Mips::GPR32RegClassID),
GIM_RootCheckRegBankForClass, 2, GIMT_Encode2(Mips::DSPRRegClassID),
GIM_RootCheckRegBankForClass, 3, GIMT_Encode2(Mips::DSPRRegClassID),
GIR_BuildRootMI, GIMT_Encode2(Mips::CMPGDU_LE_QB_MMR2),
GIR_RootToRootCopy, 0,
GIR_RootToRootCopy, 2,
GIR_RootToRootCopy, 3,
GIR_SetImplicitDefDead, 0, 0,
GIR_MergeMemOperands, 0, 1, 0,
GIR_RootConstrainSelectedInstOperands,
GIR_EraseRootFromParent_Done,
GIM_Try, GIMT_Encode4(34327)#undef GIMT_Encode2#undef GIMT_Encode4#undef GIMT_Encode8#endif #ifdef GET_GLOBALISEL_PREDICATES_DECL#endif #ifdef GET_GLOBALISEL_PREDICATES_INIT#endif