llvm/llvm/lib/Target/Mips/MipsSubtarget.cpp

//===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file implements the Mips specific subclass of TargetSubtargetInfo.
//
//===----------------------------------------------------------------------===//

#include "MipsSubtarget.h"
#include "Mips.h"
#include "MipsCallLowering.h"
#include "MipsLegalizerInfo.h"
#include "MipsMachineFunction.h"
#include "MipsRegisterBankInfo.h"
#include "MipsRegisterInfo.h"
#include "MipsTargetMachine.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"

usingnamespacellvm;

#define DEBUG_TYPE …

#define GET_SUBTARGETINFO_TARGET_DESC
#define GET_SUBTARGETINFO_CTOR
#include "MipsGenSubtargetInfo.inc"

// FIXME: Maybe this should be on by default when Mips16 is specified
//
static cl::opt<bool>
    Mixed16_32("mips-mixed-16-32", cl::init(false),
               cl::desc("Allow for a mixture of Mips16 "
                        "and Mips32 code in a single output file"),
               cl::Hidden);

static cl::opt<bool> Mips_Os16("mips-os16", cl::init(false),
                               cl::desc("Compile all functions that don't use "
                                        "floating point as Mips 16"),
                               cl::Hidden);

static cl::opt<bool> Mips16HardFloat("mips16-hard-float", cl::NotHidden,
                                     cl::desc("Enable mips16 hard float."),
                                     cl::init(false));

static cl::opt<bool>
    Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden,
                          cl::desc("Enable mips16 constant islands."),
                          cl::init(true));

static cl::opt<bool>
    GPOpt("mgpopt", cl::Hidden,
          cl::desc("Enable gp-relative addressing of mips small data items"));

bool MipsSubtarget::DspWarningPrinted = …;
bool MipsSubtarget::MSAWarningPrinted = …;
bool MipsSubtarget::VirtWarningPrinted = …;
bool MipsSubtarget::CRCWarningPrinted = …;
bool MipsSubtarget::GINVWarningPrinted = …;
bool MipsSubtarget::MIPS1WarningPrinted = …;

void MipsSubtarget::anchor() { … }

MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
                             bool little, const MipsTargetMachine &TM,
                             MaybeAlign StackAlignOverride)
    : … { … }

bool MipsSubtarget::isPositionIndependent() const { … }

/// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
bool MipsSubtarget::enablePostRAScheduler() const { … }

void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { … }

CodeGenOptLevel MipsSubtarget::getOptLevelToEnablePostRAScheduler() const { … }

MipsSubtarget &
MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
                                               const TargetMachine &TM) { … }

bool MipsSubtarget::useConstantIslands() { … }

Reloc::Model MipsSubtarget::getRelocationModel() const { … }

bool MipsSubtarget::isABI_N64() const { … }
bool MipsSubtarget::isABI_N32() const { … }
bool MipsSubtarget::isABI_O32() const { … }
const MipsABIInfo &MipsSubtarget::getABI() const { … }

const CallLowering *MipsSubtarget::getCallLowering() const { … }

const LegalizerInfo *MipsSubtarget::getLegalizerInfo() const { … }

const RegisterBankInfo *MipsSubtarget::getRegBankInfo() const { … }

InstructionSelector *MipsSubtarget::getInstructionSelector() const { … }