llvm/lib/Target/Mips/MipsGenMCCodeEmitter.inc

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Machine Code Emitter                                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

uint64_t MipsMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
    SmallVectorImpl<MCFixup> &Fixups,
    const MCSubtargetInfo &STI) const { … }

#ifdef GET_OPERAND_BIT_OFFSET
#undef GET_OPERAND_BIT_OFFSET

uint32_t MipsMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
    unsigned OpNum,
    const MCSubtargetInfo &STI) const {
  switch (MI.getOpcode()) {
    case Mips::Break16:
    case Mips::DERET:
    case Mips::DERET_MM:
    case Mips::DERET_MMR6:
    case Mips::EHB:
    case Mips::EHB_MM:
    case Mips::EHB_MMR6:
    case Mips::ERET:
    case Mips::ERETNC:
    case Mips::ERETNC_MMR6:
    case Mips::ERET_MM:
    case Mips::ERET_MMR6:
    case Mips::JrRa16:
    case Mips::JrcRa16:
    case Mips::JrcRx16:
    case Mips::NAL:
    case Mips::PAUSE:
    case Mips::PAUSE_MM:
    case Mips::PAUSE_MMR6:
    case Mips::Restore16:
    case Mips::RestoreX16:
    case Mips::SSNOP:
    case Mips::SSNOP_MM:
    case Mips::SSNOP_MMR6:
    case Mips::Save16:
    case Mips::SaveX16:
    case Mips::TLBGINV:
    case Mips::TLBGINVF:
    case Mips::TLBGINVF_MM:
    case Mips::TLBGINV_MM:
    case Mips::TLBGP:
    case Mips::TLBGP_MM:
    case Mips::TLBGR:
    case Mips::TLBGR_MM:
    case Mips::TLBGWI:
    case Mips::TLBGWI_MM:
    case Mips::TLBGWR:
    case Mips::TLBGWR_MM:
    case Mips::TLBINV:
    case Mips::TLBINVF:
    case Mips::TLBINVF_MMR6:
    case Mips::TLBINV_MMR6:
    case Mips::TLBP:
    case Mips::TLBP_MM:
    case Mips::TLBR:
    case Mips::TLBR_MM:
    case Mips::TLBWI:
    case Mips::TLBWI_MM:
    case Mips::TLBWR:
    case Mips::TLBWR_MM:
    case Mips::WAIT: {
      break;
    }
    case Mips::DPAQX_SA_W_PH:
    case Mips::DPAQX_S_W_PH:
    case Mips::DPAQ_SA_L_W:
    case Mips::DPAQ_S_W_PH:
    case Mips::DPAU_H_QBL:
    case Mips::DPAU_H_QBR:
    case Mips::DPAX_W_PH:
    case Mips::DPA_W_PH:
    case Mips::DPSQX_SA_W_PH:
    case Mips::DPSQX_S_W_PH:
    case Mips::DPSQ_SA_L_W:
    case Mips::DPSQ_S_W_PH:
    case Mips::DPSU_H_QBL:
    case Mips::DPSU_H_QBR:
    case Mips::DPSX_W_PH:
    case Mips::DPS_W_PH:
    case Mips::MADDU_DSP:
    case Mips::MADD_DSP:
    case Mips::MAQ_SA_W_PHL:
    case Mips::MAQ_SA_W_PHR:
    case Mips::MAQ_S_W_PHL:
    case Mips::MAQ_S_W_PHR:
    case Mips::MSUBU_DSP:
    case Mips::MSUB_DSP:
    case Mips::MULSAQ_S_W_PH:
    case Mips::MULSA_W_PH:
    case Mips::MULTU_DSP:
    case Mips::MULT_DSP: {
      switch (OpNum) {
      case 0:
        // op: ac
        return 11;
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: rt
        return 16;
      }
      break;
    }
    case Mips::MTHLIP:
    case Mips::SHILOV: {
      switch (OpNum) {
      case 0:
        // op: ac
        return 11;
      case 1:
        // op: rs
        return 21;
      }
      break;
    }
    case Mips::SHILO: {
      switch (OpNum) {
      case 0:
        // op: ac
        return 11;
      case 1:
        // op: shift
        return 20;
      }
      break;
    }
    case Mips::CACHE:
    case Mips::PREF: {
      switch (OpNum) {
      case 0:
        // op: addr
        return 0;
      case 2:
        // op: hint
        return 16;
      }
      break;
    }
    case Mips::CACHEE_MM:
    case Mips::CACHE_MM:
    case Mips::CACHE_MMR6:
    case Mips::PREFE_MM:
    case Mips::PREF_MM:
    case Mips::PREF_MMR6: {
      switch (OpNum) {
      case 0:
        // op: addr
        return 0;
      case 2:
        // op: hint
        return 21;
      }
      break;
    }
    case Mips::SYNCI:
    case Mips::SYNCI_MM:
    case Mips::SYNCI_MMR6: {
      switch (OpNum) {
      case 0:
        // op: addr
        return 0;
      }
      break;
    }
    case Mips::CACHEE:
    case Mips::CACHE_R6:
    case Mips::PREFE:
    case Mips::PREF_R6: {
      switch (OpNum) {
      case 0:
        // op: addr
        return 7;
      case 2:
        // op: hint
        return 16;
      }
      break;
    }
    case Mips::BREAK16_MM:
    case Mips::SDBBP16_MM:
    case Mips::SIGRIE: {
      switch (OpNum) {
      case 0:
        // op: code_
        return 0;
      }
      break;
    }
    case Mips::HYPCALL: {
      switch (OpNum) {
      case 0:
        // op: code_
        return 11;
      }
      break;
    }
    case Mips::HYPCALL_MM:
    case Mips::SDBBP_MM:
    case Mips::SDBBP_MMR6:
    case Mips::SYSCALL_MM:
    case Mips::WAIT_MM:
    case Mips::WAIT_MMR6: {
      switch (OpNum) {
      case 0:
        // op: code_
        return 16;
      }
      break;
    }
    case Mips::BREAK16_MMR6:
    case Mips::SDBBP:
    case Mips::SDBBP16_MMR6:
    case Mips::SDBBP_R6:
    case Mips::SIGRIE_MMR6:
    case Mips::SYSCALL: {
      switch (OpNum) {
      case 0:
        // op: code_
        return 6;
      }
      break;
    }
    case Mips::BREAK:
    case Mips::BREAK_MM:
    case Mips::BREAK_MMR6: {
      switch (OpNum) {
      case 0:
        // op: code_1
        return 16;
      case 1:
        // op: code_2
        return 6;
      }
      break;
    }
    case Mips::BC2EQZ:
    case Mips::BC2NEZ: {
      switch (OpNum) {
      case 0:
        // op: ct
        return 16;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::BC1F:
    case Mips::BC1FL:
    case Mips::BC1F_MM:
    case Mips::BC1T:
    case Mips::BC1TL:
    case Mips::BC1T_MM: {
      switch (OpNum) {
      case 0:
        // op: fcc
        return 18;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::LUXC1_MM:
    case Mips::LWXC1_MM: {
      switch (OpNum) {
      case 0:
        // op: fd
        return 11;
      case 1:
        // op: base
        return 16;
      case 2:
        // op: index
        return 21;
      }
      break;
    }
    case Mips::MOVN_I_D32_MM:
    case Mips::MOVN_I_S_MM:
    case Mips::MOVZ_I_D32_MM:
    case Mips::MOVZ_I_S_MM: {
      switch (OpNum) {
      case 0:
        // op: fd
        return 11;
      case 1:
        // op: fs
        return 16;
      case 2:
        // op: rt
        return 21;
      }
      break;
    }
    case Mips::MOVF_D32_MM:
    case Mips::MOVF_S_MM:
    case Mips::MOVT_D32_MM:
    case Mips::MOVT_S_MM: {
      switch (OpNum) {
      case 0:
        // op: fd
        return 21;
      case 1:
        // op: fs
        return 16;
      case 2:
        // op: fcc
        return 13;
      }
      break;
    }
    case Mips::CEIL_W_MM:
    case Mips::CEIL_W_S_MM:
    case Mips::CVT_D32_S_MM:
    case Mips::CVT_D32_W_MM:
    case Mips::CVT_D64_S_MM:
    case Mips::CVT_D64_W_MM:
    case Mips::CVT_L_D64_MM:
    case Mips::CVT_L_S_MM:
    case Mips::CVT_S_D32_MM:
    case Mips::CVT_S_D64_MM:
    case Mips::CVT_S_W_MM:
    case Mips::CVT_W_D32_MM:
    case Mips::CVT_W_D64_MM:
    case Mips::CVT_W_S_MM:
    case Mips::FABS_D32_MM:
    case Mips::FABS_D64_MM:
    case Mips::FABS_S_MM:
    case Mips::FLOOR_W_MM:
    case Mips::FLOOR_W_S_MM:
    case Mips::FMOV_D32_MM:
    case Mips::FMOV_D64_MM:
    case Mips::FMOV_S_MM:
    case Mips::FNEG_D32_MM:
    case Mips::FNEG_D64_MM:
    case Mips::FNEG_S_MM:
    case Mips::FSQRT_D32_MM:
    case Mips::FSQRT_D64_MM:
    case Mips::FSQRT_S_MM:
    case Mips::RECIP_D32_MM:
    case Mips::RECIP_D64_MM:
    case Mips::RECIP_S_MM:
    case Mips::ROUND_W_MM:
    case Mips::ROUND_W_S_MM:
    case Mips::RSQRT_D32_MM:
    case Mips::RSQRT_D64_MM:
    case Mips::RSQRT_S_MM:
    case Mips::TRUNC_W_MM:
    case Mips::TRUNC_W_S_MM: {
      switch (OpNum) {
      case 0:
        // op: fd
        return 21;
      case 1:
        // op: fs
        return 16;
      }
      break;
    }
    case Mips::LDXC1:
    case Mips::LDXC164:
    case Mips::LUXC1:
    case Mips::LUXC164:
    case Mips::LWXC1: {
      switch (OpNum) {
      case 0:
        // op: fd
        return 6;
      case 1:
        // op: base
        return 21;
      case 2:
        // op: index
        return 16;
      }
      break;
    }
    case Mips::MADD_D32:
    case Mips::MADD_D64:
    case Mips::MADD_S:
    case Mips::MSUB_D32:
    case Mips::MSUB_D64:
    case Mips::MSUB_S:
    case Mips::NMADD_D32:
    case Mips::NMADD_D64:
    case Mips::NMADD_S:
    case Mips::NMSUB_D32:
    case Mips::NMSUB_D64:
    case Mips::NMSUB_S: {
      switch (OpNum) {
      case 0:
        // op: fd
        return 6;
      case 1:
        // op: fr
        return 21;
      case 2:
        // op: fs
        return 11;
      case 3:
        // op: ft
        return 16;
      }
      break;
    }
    case Mips::MOVF_D32:
    case Mips::MOVF_D64:
    case Mips::MOVF_S:
    case Mips::MOVT_D32:
    case Mips::MOVT_D64:
    case Mips::MOVT_S: {
      switch (OpNum) {
      case 0:
        // op: fd
        return 6;
      case 1:
        // op: fs
        return 11;
      case 2:
        // op: fcc
        return 18;
      }
      break;
    }
    case Mips::ADDR_PS64:
    case Mips::CMP_EQ_D:
    case Mips::CMP_EQ_S:
    case Mips::CMP_F_D:
    case Mips::CMP_F_S:
    case Mips::CMP_LE_D:
    case Mips::CMP_LE_S:
    case Mips::CMP_LT_D:
    case Mips::CMP_LT_S:
    case Mips::CMP_SAF_D:
    case Mips::CMP_SAF_S:
    case Mips::CMP_SEQ_D:
    case Mips::CMP_SEQ_S:
    case Mips::CMP_SLE_D:
    case Mips::CMP_SLE_S:
    case Mips::CMP_SLT_D:
    case Mips::CMP_SLT_S:
    case Mips::CMP_SUEQ_D:
    case Mips::CMP_SUEQ_S:
    case Mips::CMP_SULE_D:
    case Mips::CMP_SULE_S:
    case Mips::CMP_SULT_D:
    case Mips::CMP_SULT_S:
    case Mips::CMP_SUN_D:
    case Mips::CMP_SUN_S:
    case Mips::CMP_UEQ_D:
    case Mips::CMP_UEQ_S:
    case Mips::CMP_ULE_D:
    case Mips::CMP_ULE_S:
    case Mips::CMP_ULT_D:
    case Mips::CMP_ULT_S:
    case Mips::CMP_UN_D:
    case Mips::CMP_UN_S:
    case Mips::CVT_PS_S64:
    case Mips::FADD_D32:
    case Mips::FADD_D64:
    case Mips::FADD_PS64:
    case Mips::FADD_S:
    case Mips::FDIV_D32:
    case Mips::FDIV_D64:
    case Mips::FDIV_S:
    case Mips::FMUL_D32:
    case Mips::FMUL_D64:
    case Mips::FMUL_PS64:
    case Mips::FMUL_S:
    case Mips::FSUB_D32:
    case Mips::FSUB_D64:
    case Mips::FSUB_PS64:
    case Mips::FSUB_S:
    case Mips::MULR_PS64:
    case Mips::PLL_PS64:
    case Mips::PLU_PS64:
    case Mips::PUL_PS64:
    case Mips::PUU_PS64: {
      switch (OpNum) {
      case 0:
        // op: fd
        return 6;
      case 1:
        // op: fs
        return 11;
      case 2:
        // op: ft
        return 16;
      }
      break;
    }
    case Mips::MOVN_I64_D64:
    case Mips::MOVN_I64_S:
    case Mips::MOVN_I_D32:
    case Mips::MOVN_I_D64:
    case Mips::MOVN_I_S:
    case Mips::MOVZ_I64_D64:
    case Mips::MOVZ_I64_S:
    case Mips::MOVZ_I_D32:
    case Mips::MOVZ_I_D64:
    case Mips::MOVZ_I_S: {
      switch (OpNum) {
      case 0:
        // op: fd
        return 6;
      case 1:
        // op: fs
        return 11;
      case 2:
        // op: rt
        return 16;
      }
      break;
    }
    case Mips::CEIL_L_D64:
    case Mips::CEIL_L_S:
    case Mips::CEIL_W_D32:
    case Mips::CEIL_W_D64:
    case Mips::CEIL_W_S:
    case Mips::CVT_D32_S:
    case Mips::CVT_D32_W:
    case Mips::CVT_D64_L:
    case Mips::CVT_D64_S:
    case Mips::CVT_D64_W:
    case Mips::CVT_L_D64:
    case Mips::CVT_L_S:
    case Mips::CVT_PS_PW64:
    case Mips::CVT_PW_PS64:
    case Mips::CVT_S_D32:
    case Mips::CVT_S_D64:
    case Mips::CVT_S_L:
    case Mips::CVT_S_PL64:
    case Mips::CVT_S_PU64:
    case Mips::CVT_S_W:
    case Mips::CVT_W_D32:
    case Mips::CVT_W_D64:
    case Mips::CVT_W_S:
    case Mips::FABS_D32:
    case Mips::FABS_D64:
    case Mips::FABS_S:
    case Mips::FLOOR_L_D64:
    case Mips::FLOOR_L_S:
    case Mips::FLOOR_W_D32:
    case Mips::FLOOR_W_D64:
    case Mips::FLOOR_W_S:
    case Mips::FMOV_D32:
    case Mips::FMOV_D64:
    case Mips::FMOV_S:
    case Mips::FNEG_D32:
    case Mips::FNEG_D64:
    case Mips::FNEG_S:
    case Mips::FSQRT_D32:
    case Mips::FSQRT_D64:
    case Mips::FSQRT_S:
    case Mips::RECIP_D32:
    case Mips::RECIP_D64:
    case Mips::RECIP_S:
    case Mips::ROUND_L_D64:
    case Mips::ROUND_L_S:
    case Mips::ROUND_W_D32:
    case Mips::ROUND_W_D64:
    case Mips::ROUND_W_S:
    case Mips::RSQRT_D32:
    case Mips::RSQRT_D64:
    case Mips::RSQRT_S:
    case Mips::TRUNC_L_D64:
    case Mips::TRUNC_L_S:
    case Mips::TRUNC_W_D32:
    case Mips::TRUNC_W_D64:
    case Mips::TRUNC_W_S: {
      switch (OpNum) {
      case 0:
        // op: fd
        return 6;
      case 1:
        // op: fs
        return 11;
      }
      break;
    }
    case Mips::SUXC1_MM:
    case Mips::SWXC1_MM: {
      switch (OpNum) {
      case 0:
        // op: fs
        return 11;
      case 1:
        // op: base
        return 16;
      case 2:
        // op: index
        return 21;
      }
      break;
    }
    case Mips::SDXC1:
    case Mips::SDXC164:
    case Mips::SUXC1:
    case Mips::SUXC164:
    case Mips::SWXC1: {
      switch (OpNum) {
      case 0:
        // op: fs
        return 11;
      case 1:
        // op: base
        return 21;
      case 2:
        // op: index
        return 16;
      }
      break;
    }
    case Mips::FCMP_D32:
    case Mips::FCMP_D64:
    case Mips::FCMP_S32: {
      switch (OpNum) {
      case 0:
        // op: fs
        return 11;
      case 1:
        // op: ft
        return 16;
      case 2:
        // op: cond
        return 0;
      }
      break;
    }
    case Mips::FCMP_D32_MM:
    case Mips::FCMP_S32_MM: {
      switch (OpNum) {
      case 0:
        // op: fs
        return 16;
      case 1:
        // op: ft
        return 21;
      case 2:
        // op: cond
        return 6;
      }
      break;
    }
    case Mips::BC1EQZ:
    case Mips::BC1NEZ: {
      switch (OpNum) {
      case 0:
        // op: ft
        return 16;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::LDC1_D64_MMR6:
    case Mips::SDC1_D64_MMR6: {
      switch (OpNum) {
      case 0:
        // op: ft
        return 21;
      case 1:
        // op: addr
        return 0;
      }
      break;
    }
    case Mips::CEIL_L_D_MMR6:
    case Mips::CEIL_L_S_MMR6:
    case Mips::CEIL_W_D_MMR6:
    case Mips::CEIL_W_S_MMR6:
    case Mips::CVT_D_L_MMR6:
    case Mips::CVT_L_D_MMR6:
    case Mips::CVT_L_S_MMR6:
    case Mips::CVT_S_L_MMR6:
    case Mips::CVT_S_W_MMR6:
    case Mips::CVT_W_S_MMR6:
    case Mips::FLOOR_L_D_MMR6:
    case Mips::FLOOR_L_S_MMR6:
    case Mips::FLOOR_W_D_MMR6:
    case Mips::FLOOR_W_S_MMR6:
    case Mips::FMOV_D_MMR6:
    case Mips::FMOV_S_MMR6:
    case Mips::FNEG_S_MMR6:
    case Mips::ROUND_L_D_MMR6:
    case Mips::ROUND_L_S_MMR6:
    case Mips::ROUND_W_D_MMR6:
    case Mips::ROUND_W_S_MMR6:
    case Mips::TRUNC_L_D_MMR6:
    case Mips::TRUNC_L_S_MMR6:
    case Mips::TRUNC_W_D_MMR6:
    case Mips::TRUNC_W_S_MMR6: {
      switch (OpNum) {
      case 0:
        // op: ft
        return 21;
      case 1:
        // op: fs
        return 16;
      }
      break;
    }
    case Mips::JRADDIUSP: {
      switch (OpNum) {
      case 0:
        // op: imm
        return 0;
      }
      break;
    }
    case Mips::ADDIUSP_MM: {
      switch (OpNum) {
      case 0:
        // op: imm
        return 1;
      }
      break;
    }
    case Mips::JRCADDIUSP_MMR6: {
      switch (OpNum) {
      case 0:
        // op: imm
        return 5;
      }
      break;
    }
    case Mips::Bimm16: {
      switch (OpNum) {
      case 0:
        // op: imm11
        return 0;
      }
      break;
    }
    case Mips::AddiuSpImmX16:
    case Mips::BimmX16:
    case Mips::BteqzX16:
    case Mips::BtnezX16: {
      switch (OpNum) {
      case 0:
        // op: imm16
        return 0;
      }
      break;
    }
    case Mips::Jal16:
    case Mips::JalB16: {
      switch (OpNum) {
      case 0:
        // op: imm26
        return 0;
      }
      break;
    }
    case Mips::AddiuSpImm16:
    case Mips::Bteqz16:
    case Mips::Btnez16: {
      switch (OpNum) {
      case 0:
        // op: imm8
        return 0;
      }
      break;
    }
    case Mips::B16_MM:
    case Mips::BAL:
    case Mips::BALC:
    case Mips::BALC_MMR6:
    case Mips::BC:
    case Mips::BC16_MMR6:
    case Mips::BC_MMR6:
    case Mips::BPOSGE32:
    case Mips::BPOSGE32C_MMR3:
    case Mips::BPOSGE32_MM: {
      switch (OpNum) {
      case 0:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::Move32R16: {
      switch (OpNum) {
      case 0:
        // op: r32
        return 3;
      case 1:
        // op: rz
        return 0;
      }
      break;
    }
    case Mips::MFHI16_MM:
    case Mips::MFLO16_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case Mips::MFHI_DSP:
    case Mips::MFLO_DSP: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: ac
        return 21;
      }
      break;
    }
    case Mips::LWXS_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: base
        return 16;
      case 2:
        // op: index
        return 21;
      }
      break;
    }
    case Mips::LBUX:
    case Mips::LHX:
    case Mips::LWX: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: base
        return 21;
      case 2:
        // op: index
        return 16;
      }
      break;
    }
    case Mips::REPL_PH:
    case Mips::REPL_PH_MM:
    case Mips::REPL_QB: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: imm
        return 16;
      }
      break;
    }
    case Mips::RDDSP: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: mask
        return 16;
      }
      break;
    }
    case Mips::LSA_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: rt
        return 21;
      case 3:
        // op: imm2
        return 9;
      }
      break;
    }
    case Mips::ADDQH_PH_MMR2:
    case Mips::ADDQH_R_PH_MMR2:
    case Mips::ADDQH_R_W_MMR2:
    case Mips::ADDQH_W_MMR2:
    case Mips::ADDQ_PH_MM:
    case Mips::ADDQ_S_PH_MM:
    case Mips::ADDQ_S_W_MM:
    case Mips::ADDSC_MM:
    case Mips::ADDUH_QB_MMR2:
    case Mips::ADDUH_R_QB_MMR2:
    case Mips::ADDU_PH_MMR2:
    case Mips::ADDU_QB_MM:
    case Mips::ADDU_S_PH_MMR2:
    case Mips::ADDU_S_QB_MM:
    case Mips::ADDWC_MM:
    case Mips::CMPGDU_EQ_QB_MMR2:
    case Mips::CMPGDU_LE_QB_MMR2:
    case Mips::CMPGDU_LT_QB_MMR2:
    case Mips::MODSUB_MM:
    case Mips::MULEQ_S_W_PHL_MM:
    case Mips::MULEQ_S_W_PHR_MM:
    case Mips::MULEU_S_PH_QBL_MM:
    case Mips::MULEU_S_PH_QBR_MM:
    case Mips::MULQ_RS_PH_MM:
    case Mips::MULQ_RS_W_MMR2:
    case Mips::MULQ_S_PH_MMR2:
    case Mips::MULQ_S_W_MMR2:
    case Mips::MUL_PH_MMR2:
    case Mips::MUL_S_PH_MMR2:
    case Mips::PACKRL_PH_MM:
    case Mips::PICK_PH_MM:
    case Mips::PICK_QB_MM:
    case Mips::PRECRQU_S_QB_PH_MM:
    case Mips::PRECRQ_PH_W_MM:
    case Mips::PRECRQ_QB_PH_MM:
    case Mips::PRECRQ_RS_PH_W_MM:
    case Mips::PRECR_QB_PH_MMR2:
    case Mips::SELEQZ_MMR6:
    case Mips::SELNEZ_MMR6:
    case Mips::SUBQH_PH_MMR2:
    case Mips::SUBQH_R_PH_MMR2:
    case Mips::SUBQH_R_W_MMR2:
    case Mips::SUBQH_W_MMR2:
    case Mips::SUBQ_PH_MM:
    case Mips::SUBQ_S_PH_MM:
    case Mips::SUBQ_S_W_MM:
    case Mips::SUBUH_QB_MMR2:
    case Mips::SUBUH_R_QB_MMR2:
    case Mips::SUBU_PH_MMR2:
    case Mips::SUBU_QB_MM:
    case Mips::SUBU_S_PH_MMR2:
    case Mips::SUBU_S_QB_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: rt
        return 21;
      }
      break;
    }
    case Mips::MOVF_I:
    case Mips::MOVF_I64:
    case Mips::MOVT_I:
    case Mips::MOVT_I64: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: fcc
        return 18;
      }
      break;
    }
    case Mips::ALIGN:
    case Mips::DALIGN: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: rt
        return 16;
      case 3:
        // op: bp
        return 6;
      }
      break;
    }
    case Mips::ALIGN_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: rt
        return 16;
      case 3:
        // op: bp
        return 9;
      }
      break;
    }
    case Mips::DLSA_R6:
    case Mips::LSA_R6: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: rt
        return 16;
      case 3:
        // op: imm2
        return 6;
      }
      break;
    }
    case Mips::ADD:
    case Mips::ADDQH_PH:
    case Mips::ADDQH_R_PH:
    case Mips::ADDQH_R_W:
    case Mips::ADDQH_W:
    case Mips::ADDQ_PH:
    case Mips::ADDQ_S_PH:
    case Mips::ADDQ_S_W:
    case Mips::ADDSC:
    case Mips::ADDUH_QB:
    case Mips::ADDUH_R_QB:
    case Mips::ADDU_PH:
    case Mips::ADDU_QB:
    case Mips::ADDU_S_PH:
    case Mips::ADDU_S_QB:
    case Mips::ADDWC:
    case Mips::ADDu:
    case Mips::AND:
    case Mips::AND64:
    case Mips::BADDu:
    case Mips::DADD:
    case Mips::DADDu:
    case Mips::DDIV:
    case Mips::DDIVU:
    case Mips::DIV:
    case Mips::DIVU:
    case Mips::DMOD:
    case Mips::DMODU:
    case Mips::DMUH:
    case Mips::DMUHU:
    case Mips::DMUL:
    case Mips::DMULU:
    case Mips::DMUL_R6:
    case Mips::DSUB:
    case Mips::DSUBu:
    case Mips::MOD:
    case Mips::MODSUB:
    case Mips::MODU:
    case Mips::MOVN_I64_I:
    case Mips::MOVN_I64_I64:
    case Mips::MOVN_I_I:
    case Mips::MOVN_I_I64:
    case Mips::MOVZ_I64_I:
    case Mips::MOVZ_I64_I64:
    case Mips::MOVZ_I_I:
    case Mips::MOVZ_I_I64:
    case Mips::MUH:
    case Mips::MUHU:
    case Mips::MUL:
    case Mips::MULEQ_S_W_PHL:
    case Mips::MULEQ_S_W_PHR:
    case Mips::MULEU_S_PH_QBL:
    case Mips::MULEU_S_PH_QBR:
    case Mips::MULQ_RS_PH:
    case Mips::MULQ_RS_W:
    case Mips::MULQ_S_PH:
    case Mips::MULQ_S_W:
    case Mips::MULU:
    case Mips::MUL_PH:
    case Mips::MUL_R6:
    case Mips::MUL_S_PH:
    case Mips::NOR:
    case Mips::NOR64:
    case Mips::OR:
    case Mips::OR64:
    case Mips::SELEQZ:
    case Mips::SELEQZ64:
    case Mips::SELNEZ:
    case Mips::SELNEZ64:
    case Mips::SEQ:
    case Mips::SLT:
    case Mips::SLT64:
    case Mips::SLTu:
    case Mips::SLTu64:
    case Mips::SNE:
    case Mips::SUB:
    case Mips::SUBQH_PH:
    case Mips::SUBQH_R_PH:
    case Mips::SUBQH_R_W:
    case Mips::SUBQH_W:
    case Mips::SUBQ_PH:
    case Mips::SUBQ_S_PH:
    case Mips::SUBQ_S_W:
    case Mips::SUBUH_QB:
    case Mips::SUBUH_R_QB:
    case Mips::SUBU_PH:
    case Mips::SUBU_QB:
    case Mips::SUBU_S_PH:
    case Mips::SUBU_S_QB:
    case Mips::SUBu:
    case Mips::V3MULU:
    case Mips::VMM0:
    case Mips::VMULU:
    case Mips::XOR:
    case Mips::XOR64: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: rt
        return 16;
      }
      break;
    }
    case Mips::CLO:
    case Mips::CLO_R6:
    case Mips::CLZ:
    case Mips::CLZ_R6:
    case Mips::DCLO:
    case Mips::DCLO_R6:
    case Mips::DCLZ:
    case Mips::DCLZ_R6:
    case Mips::DPOP:
    case Mips::JALR:
    case Mips::JALR64:
    case Mips::JALR_HB:
    case Mips::JALR_HB64:
    case Mips::POP:
    case Mips::RADDU_W_QB: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rs
        return 21;
      }
      break;
    }
    case Mips::DROTRV:
    case Mips::DSLLV:
    case Mips::DSRAV:
    case Mips::DSRLV:
    case Mips::ROTRV:
    case Mips::SLLV:
    case Mips::SRAV:
    case Mips::SRLV: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rt
        return 16;
      case 2:
        // op: rs
        return 21;
      }
      break;
    }
    case Mips::SHLLV_PH:
    case Mips::SHLLV_QB:
    case Mips::SHLLV_S_PH:
    case Mips::SHLLV_S_W:
    case Mips::SHLL_PH:
    case Mips::SHLL_QB:
    case Mips::SHLL_S_PH:
    case Mips::SHLL_S_W:
    case Mips::SHRAV_PH:
    case Mips::SHRAV_QB:
    case Mips::SHRAV_R_PH:
    case Mips::SHRAV_R_QB:
    case Mips::SHRAV_R_W:
    case Mips::SHRA_PH:
    case Mips::SHRA_QB:
    case Mips::SHRA_R_PH:
    case Mips::SHRA_R_QB:
    case Mips::SHRA_R_W:
    case Mips::SHRLV_PH:
    case Mips::SHRLV_QB:
    case Mips::SHRL_PH:
    case Mips::SHRL_QB: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rt
        return 16;
      case 2:
        // op: rs_sa
        return 21;
      }
      break;
    }
    case Mips::DROTR:
    case Mips::DROTR32:
    case Mips::DSLL:
    case Mips::DSLL32:
    case Mips::DSRA:
    case Mips::DSRA32:
    case Mips::DSRL:
    case Mips::DSRL32:
    case Mips::ROTR:
    case Mips::SLL:
    case Mips::SRA:
    case Mips::SRL: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rt
        return 16;
      case 2:
        // op: shamt
        return 6;
      }
      break;
    }
    case Mips::ABSQ_S_PH:
    case Mips::ABSQ_S_QB:
    case Mips::ABSQ_S_W:
    case Mips::BITREV:
    case Mips::BITSWAP:
    case Mips::DBITSWAP:
    case Mips::DSBH:
    case Mips::DSHD:
    case Mips::DSLL64_32:
    case Mips::PRECEQU_PH_QBL:
    case Mips::PRECEQU_PH_QBLA:
    case Mips::PRECEQU_PH_QBR:
    case Mips::PRECEQU_PH_QBRA:
    case Mips::PRECEQ_W_PHL:
    case Mips::PRECEQ_W_PHR:
    case Mips::PRECEU_PH_QBL:
    case Mips::PRECEU_PH_QBLA:
    case Mips::PRECEU_PH_QBR:
    case Mips::PRECEU_PH_QBRA:
    case Mips::REPLV_PH:
    case Mips::REPLV_QB:
    case Mips::SEB:
    case Mips::SEB64:
    case Mips::SEH:
    case Mips::SEH64:
    case Mips::SLL64_32:
    case Mips::SLL64_64:
    case Mips::WSBH: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rt
        return 16;
      }
      break;
    }
    case Mips::ROTRV_MM:
    case Mips::SLLV_MM:
    case Mips::SRAV_MM:
    case Mips::SRLV_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 1:
        // op: rt
        return 21;
      case 2:
        // op: rs
        return 16;
      }
      break;
    }
    case Mips::SHLLV_PH_MM:
    case Mips::SHLLV_QB_MM:
    case Mips::SHLLV_S_PH_MM:
    case Mips::SHLLV_S_W_MM:
    case Mips::SHRAV_PH_MM:
    case Mips::SHRAV_QB_MMR2:
    case Mips::SHRAV_R_PH_MM:
    case Mips::SHRAV_R_QB_MMR2:
    case Mips::SHRAV_R_W_MM:
    case Mips::SHRLV_PH_MMR2:
    case Mips::SHRLV_QB_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 2:
        // op: rs
        return 16;
      case 1:
        // op: rt
        return 21;
      }
      break;
    }
    case Mips::ADDU_MMR6:
    case Mips::ADD_MMR6:
    case Mips::AND_MMR6:
    case Mips::DIVU_MMR6:
    case Mips::DIV_MMR6:
    case Mips::MODU_MMR6:
    case Mips::MOD_MMR6:
    case Mips::MUHU_MMR6:
    case Mips::MUH_MMR6:
    case Mips::MULU_MMR6:
    case Mips::MUL_MMR6:
    case Mips::NOR_MMR6:
    case Mips::OR_MMR6:
    case Mips::SUBU_MMR6:
    case Mips::SUB_MMR6:
    case Mips::XOR_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      case 2:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      }
      break;
    }
    case Mips::MFHI:
    case Mips::MFHI64:
    case Mips::MFLO:
    case Mips::MFLO64: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 11;
      }
      break;
    }
    case Mips::BITSWAP_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 16;
      case 1:
        // op: rt
        return 21;
      }
      break;
    }
    case Mips::MFHI_MM:
    case Mips::MFLO_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 16;
      }
      break;
    }
    case Mips::MOVF_I_MM:
    case Mips::MOVT_I_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 21;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: fcc
        return 13;
      }
      break;
    }
    case Mips::CLO_MM:
    case Mips::CLZ_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 21;
      case 1:
        // op: rs
        return 16;
      }
      break;
    }
    case Mips::ROTR_MM:
    case Mips::SLL_MM:
    case Mips::SLL_MMR6:
    case Mips::SRA_MM:
    case Mips::SRL_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 21;
      case 1:
        // op: rt
        return 16;
      case 2:
        // op: shamt
        return 11;
      }
      break;
    }
    case Mips::SEB_MM:
    case Mips::SEH_MM:
    case Mips::WSBH_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 21;
      case 1:
        // op: rt
        return 16;
      }
      break;
    }
    case Mips::CFCMSA: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 6;
      case 1:
        // op: cs
        return 11;
      }
      break;
    }
    case Mips::LI16_MM:
    case Mips::LI16_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 7;
      case 1:
        // op: imm
        return 0;
      }
      break;
    }
    case Mips::ADDIUR1SP_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 7;
      case 1:
        // op: imm
        return 1;
      }
      break;
    }
    case Mips::ANDI16_MM:
    case Mips::ANDI16_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 7;
      case 1:
        // op: rs
        return 4;
      case 2:
        // op: imm
        return 0;
      }
      break;
    }
    case Mips::ADDIUR2_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 7;
      case 1:
        // op: rs
        return 4;
      case 2:
        // op: imm
        return 1;
      }
      break;
    }
    case Mips::SLL16_MM:
    case Mips::SLL16_MMR6:
    case Mips::SRL16_MM:
    case Mips::SRL16_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 7;
      case 1:
        // op: rt
        return 4;
      case 2:
        // op: shamt
        return 1;
      }
      break;
    }
    case Mips::ADDU16_MM:
    case Mips::SUBU16_MM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 7;
      case 2:
        // op: rt
        return 4;
      case 1:
        // op: rs
        return 1;
      }
      break;
    }
    case Mips::JALR16_MM:
    case Mips::JALRS16_MM:
    case Mips::JR16_MM:
    case Mips::JRC16_MM: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 0;
      }
      break;
    }
    case Mips::MFHI_DSP_MM:
    case Mips::MFLO_DSP_MM: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 16;
      case 1:
        // op: ac
        return 14;
      }
      break;
    }
    case Mips::TEQI_MM:
    case Mips::TGEIU_MM:
    case Mips::TGEI_MM:
    case Mips::TLTIU_MM:
    case Mips::TLTI_MM:
    case Mips::TNEI_MM: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 16;
      case 1:
        // op: imm16
        return 0;
      }
      break;
    }
    case Mips::BEQZC_MM:
    case Mips::BGEZALS_MM:
    case Mips::BGEZAL_MM:
    case Mips::BGEZ_MM:
    case Mips::BGTZ_MM:
    case Mips::BLEZ_MM:
    case Mips::BLTZALS_MM:
    case Mips::BLTZAL_MM:
    case Mips::BLTZ_MM:
    case Mips::BNEZC_MM: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 16;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::TEQ_MM:
    case Mips::TGEU_MM:
    case Mips::TGE_MM:
    case Mips::TLTU_MM:
    case Mips::TLT_MM:
    case Mips::TNE_MM: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 16;
      case 1:
        // op: rt
        return 21;
      case 2:
        // op: code_
        return 12;
      }
      break;
    }
    case Mips::BEQ_MM:
    case Mips::BNE_MM: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 16;
      case 1:
        // op: rt
        return 21;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::MADDU_MM:
    case Mips::MADD_MM:
    case Mips::MSUBU_MM:
    case Mips::MSUB_MM:
    case Mips::MULT_MM:
    case Mips::MULTu_MM:
    case Mips::SDIV_MM:
    case Mips::UDIV_MM: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 16;
      case 1:
        // op: rt
        return 21;
      }
      break;
    }
    case Mips::GINVT_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 16;
      case 1:
        // op: type
        return 9;
      }
      break;
    }
    case Mips::DVP_MMR6:
    case Mips::EVP_MMR6:
    case Mips::GINVI_MMR6:
    case Mips::JR_MM:
    case Mips::MTHI_MM:
    case Mips::MTLO_MM: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 16;
      }
      break;
    }
    case Mips::ADDIUPC:
    case Mips::ALUIPC:
    case Mips::AUIPC:
    case Mips::LDPC:
    case Mips::LWPC:
    case Mips::LWUPC: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 1:
        // op: imm
        return 0;
      }
      break;
    }
    case Mips::TEQI:
    case Mips::TGEI:
    case Mips::TGEIU:
    case Mips::TLTI:
    case Mips::TNEI:
    case Mips::TTLTIU: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 1:
        // op: imm16
        return 0;
      }
      break;
    }
    case Mips::WRDSP: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 1:
        // op: mask
        return 11;
      }
      break;
    }
    case Mips::BEQZC:
    case Mips::BEQZC64:
    case Mips::BEQZC_MMR6:
    case Mips::BGEZ:
    case Mips::BGEZ64:
    case Mips::BGEZAL:
    case Mips::BGEZALL:
    case Mips::BGEZL:
    case Mips::BGTZ:
    case Mips::BGTZ64:
    case Mips::BGTZL:
    case Mips::BLEZ:
    case Mips::BLEZ64:
    case Mips::BLEZL:
    case Mips::BLTZ:
    case Mips::BLTZ64:
    case Mips::BLTZAL:
    case Mips::BLTZALL:
    case Mips::BLTZL:
    case Mips::BNEZC:
    case Mips::BNEZC64:
    case Mips::BNEZC_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::BBIT0:
    case Mips::BBIT1:
    case Mips::BBIT032:
    case Mips::BBIT132: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 1:
        // op: p
        return 16;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::TEQ:
    case Mips::TGE:
    case Mips::TGEU:
    case Mips::TLT:
    case Mips::TLTU:
    case Mips::TNE: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 1:
        // op: rt
        return 16;
      case 2:
        // op: code_
        return 6;
      }
      break;
    }
    case Mips::BEQ:
    case Mips::BEQ64:
    case Mips::BEQC:
    case Mips::BEQC64:
    case Mips::BEQL:
    case Mips::BGEC:
    case Mips::BGEC64:
    case Mips::BGEUC:
    case Mips::BGEUC64:
    case Mips::BLTC:
    case Mips::BLTC64:
    case Mips::BLTUC:
    case Mips::BLTUC64:
    case Mips::BNE:
    case Mips::BNE64:
    case Mips::BNEC:
    case Mips::BNEC64:
    case Mips::BNEL:
    case Mips::BNVC:
    case Mips::BOVC: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 1:
        // op: rt
        return 16;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::CMPU_EQ_QB:
    case Mips::CMPU_LE_QB:
    case Mips::CMPU_LT_QB:
    case Mips::CMP_EQ_PH:
    case Mips::CMP_LE_PH:
    case Mips::CMP_LT_PH:
    case Mips::DMULT:
    case Mips::DMULTu:
    case Mips::DSDIV:
    case Mips::DUDIV:
    case Mips::MADD:
    case Mips::MADDU:
    case Mips::MSUB:
    case Mips::MSUBU:
    case Mips::MULT:
    case Mips::MULTu:
    case Mips::SDIV:
    case Mips::UDIV: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 1:
        // op: rt
        return 16;
      }
      break;
    }
    case Mips::GINVT: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 1:
        // op: type_
        return 8;
      }
      break;
    }
    case Mips::DAHI:
    case Mips::DATI: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 2:
        // op: imm
        return 0;
      }
      break;
    }
    case Mips::FORK: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      case 2:
        // op: rt
        return 16;
      case 1:
        // op: rd
        return 11;
      }
      break;
    }
    case Mips::GINVI:
    case Mips::JR:
    case Mips::JR64:
    case Mips::JR_HB:
    case Mips::JR_HB64:
    case Mips::JR_HB64_R6:
    case Mips::JR_HB_R6:
    case Mips::MTHI:
    case Mips::MTHI64:
    case Mips::MTLO:
    case Mips::MTLO64:
    case Mips::MTM0:
    case Mips::MTM1:
    case Mips::MTM2:
    case Mips::MTP0:
    case Mips::MTP1:
    case Mips::MTP2: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 21;
      }
      break;
    }
    case Mips::ADDIUPC_MM: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 23;
      case 1:
        // op: imm
        return 0;
      }
      break;
    }
    case Mips::JALRC16_MMR6:
    case Mips::JRC16_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 5;
      }
      break;
    }
    case Mips::BEQZ16_MM:
    case Mips::BEQZC16_MMR6:
    case Mips::BNEZ16_MM:
    case Mips::BNEZC16_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rs
        return 7;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::EXTP:
    case Mips::EXTPDP:
    case Mips::EXTPDPV:
    case Mips::EXTPV:
    case Mips::EXTRV_RS_W:
    case Mips::EXTRV_R_W:
    case Mips::EXTRV_S_H:
    case Mips::EXTRV_W:
    case Mips::EXTR_RS_W:
    case Mips::EXTR_R_W:
    case Mips::EXTR_S_H:
    case Mips::EXTR_W: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: ac
        return 11;
      case 2:
        // op: shift_rs
        return 21;
      }
      break;
    }
    case Mips::LB:
    case Mips::LB64:
    case Mips::LBu:
    case Mips::LBu64:
    case Mips::LD:
    case Mips::LDC1:
    case Mips::LDC2:
    case Mips::LDC2_R6:
    case Mips::LDC3:
    case Mips::LDC164:
    case Mips::LDL:
    case Mips::LDR:
    case Mips::LEA_ADDiu:
    case Mips::LEA_ADDiu64:
    case Mips::LH:
    case Mips::LH64:
    case Mips::LHu:
    case Mips::LHu64:
    case Mips::LL:
    case Mips::LL64:
    case Mips::LLD:
    case Mips::LW:
    case Mips::LW64:
    case Mips::LWC1:
    case Mips::LWC2:
    case Mips::LWC2_R6:
    case Mips::LWC3:
    case Mips::LWDSP:
    case Mips::LWL:
    case Mips::LWL64:
    case Mips::LWR:
    case Mips::LWR64:
    case Mips::LWu:
    case Mips::SB:
    case Mips::SB64:
    case Mips::SD:
    case Mips::SDC1:
    case Mips::SDC2:
    case Mips::SDC2_R6:
    case Mips::SDC3:
    case Mips::SDC164:
    case Mips::SDL:
    case Mips::SDR:
    case Mips::SH:
    case Mips::SH64:
    case Mips::SW:
    case Mips::SW64:
    case Mips::SWC1:
    case Mips::SWC2:
    case Mips::SWC2_R6:
    case Mips::SWC3:
    case Mips::SWDSP:
    case Mips::SWL:
    case Mips::SWL64:
    case Mips::SWR:
    case Mips::SWR64: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: addr
        return 0;
      }
      break;
    }
    case Mips::LL64_R6:
    case Mips::LLD_R6:
    case Mips::LL_R6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: addr
        return 7;
      }
      break;
    }
    case Mips::CFC1:
    case Mips::DMFC1:
    case Mips::MFC1:
    case Mips::MFC1_D64:
    case Mips::MFHC1_D32:
    case Mips::MFHC1_D64: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: fs
        return 11;
      }
      break;
    }
    case Mips::DMFC2_OCTEON:
    case Mips::DMTC2_OCTEON:
    case Mips::LUi:
    case Mips::LUi64:
    case Mips::LUi_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: imm16
        return 0;
      }
      break;
    }
    case Mips::BC1EQZC_MMR6:
    case Mips::BC1NEZC_MMR6:
    case Mips::BC2EQZC_MMR6:
    case Mips::BC2NEZC_MMR6:
    case Mips::BEQZALC:
    case Mips::BGEZALC:
    case Mips::BGEZALC_MMR6:
    case Mips::BGEZC:
    case Mips::BGEZC64:
    case Mips::BGEZC_MMR6:
    case Mips::BGTZALC:
    case Mips::BGTZC:
    case Mips::BGTZC64:
    case Mips::BLEZALC:
    case Mips::BLEZC:
    case Mips::BLEZC64:
    case Mips::BLTZALC:
    case Mips::BLTZALC_MMR6:
    case Mips::BLTZC:
    case Mips::BLTZC64:
    case Mips::BLTZC_MMR6:
    case Mips::BNEZALC:
    case Mips::JIALC:
    case Mips::JIALC64:
    case Mips::JIALC_MMR6:
    case Mips::JIC:
    case Mips::JIC64:
    case Mips::JIC_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::DMFC0:
    case Mips::DMFC2:
    case Mips::DMFGC0:
    case Mips::MFC0:
    case Mips::MFC2:
    case Mips::MFGC0:
    case Mips::MFHGC0: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: rd
        return 11;
      case 2:
        // op: sel
        return 0;
      }
      break;
    }
    case Mips::RDHWR:
    case Mips::RDHWR64: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: rd
        return 11;
      case 2:
        // op: sel
        return 6;
      }
      break;
    }
    case Mips::SLTi:
    case Mips::SLTi64:
    case Mips::SLTiu:
    case Mips::SLTiu64: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: imm16
        return 0;
      }
      break;
    }
    case Mips::CINS:
    case Mips::CINS32:
    case Mips::CINS64_32:
    case Mips::CINS_i32:
    case Mips::EXTS:
    case Mips::EXTS32: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: pos
        return 6;
      case 3:
        // op: lenm1
        return 11;
      }
      break;
    }
    case Mips::DEXT:
    case Mips::DEXT64_32:
    case Mips::DEXTM:
    case Mips::DEXTU:
    case Mips::DINS:
    case Mips::DINSM:
    case Mips::DINSU:
    case Mips::EXT:
    case Mips::INS: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: pos
        return 6;
      case 3:
        // op: size
        return 11;
      }
      break;
    }
    case Mips::APPEND:
    case Mips::BALIGN:
    case Mips::PREPEND: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: sa
        return 11;
      }
      break;
    }
    case Mips::SAA:
    case Mips::SAAD: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 1:
        // op: rs
        return 21;
      }
      break;
    }
    case Mips::INSV: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      case 2:
        // op: rs
        return 21;
      }
      break;
    }
    case Mips::DI:
    case Mips::DI_MM:
    case Mips::DI_MMR6:
    case Mips::DMT:
    case Mips::DVP:
    case Mips::DVPE:
    case Mips::EI:
    case Mips::EI_MM:
    case Mips::EI_MMR6:
    case Mips::EMT:
    case Mips::EVP:
    case Mips::EVPE: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 16;
      }
      break;
    }
    case Mips::LBE_MM:
    case Mips::LB_MM:
    case Mips::LBuE_MM:
    case Mips::LBu_MM:
    case Mips::LDC1_MM_D32:
    case Mips::LDC1_MM_D64:
    case Mips::LDC2_MMR6:
    case Mips::LEA_ADDiu_MM:
    case Mips::LHE_MM:
    case Mips::LH_MM:
    case Mips::LHuE_MM:
    case Mips::LHu_MM:
    case Mips::LLE_MM:
    case Mips::LL_MM:
    case Mips::LL_MMR6:
    case Mips::LWC1_MM:
    case Mips::LWC2_MMR6:
    case Mips::LWDSP_MM:
    case Mips::LWE_MM:
    case Mips::LWLE_MM:
    case Mips::LWL_MM:
    case Mips::LWM32_MM:
    case Mips::LWRE_MM:
    case Mips::LWR_MM:
    case Mips::LWU_MM:
    case Mips::LW_MM:
    case Mips::LW_MMR6:
    case Mips::SBE_MM:
    case Mips::SB_MM:
    case Mips::SB_MMR6:
    case Mips::SDC1_MM_D32:
    case Mips::SDC1_MM_D64:
    case Mips::SDC2_MMR6:
    case Mips::SHE_MM:
    case Mips::SH_MM:
    case Mips::SH_MMR6:
    case Mips::SWC1_MM:
    case Mips::SWC2_MMR6:
    case Mips::SWDSP_MM:
    case Mips::SWE_MM:
    case Mips::SWLE_MM:
    case Mips::SWL_MM:
    case Mips::SWM32_MM:
    case Mips::SWRE_MM:
    case Mips::SWR_MM:
    case Mips::SW_MM:
    case Mips::SW_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: addr
        return 0;
      }
      break;
    }
    case Mips::CFC1_MM:
    case Mips::MFC1_MM:
    case Mips::MFC1_MMR6:
    case Mips::MFHC1_D32_MM:
    case Mips::MFHC1_D64_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: fs
        return 16;
      }
      break;
    }
    case Mips::ADDIUPC_MMR6:
    case Mips::ALUIPC_MMR6:
    case Mips::AUIPC_MMR6:
    case Mips::LWPC_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: imm
        return 0;
      }
      break;
    }
    case Mips::REPL_QB_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: imm
        return 13;
      }
      break;
    }
    case Mips::LUI_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: imm16
        return 0;
      }
      break;
    }
    case Mips::CFC2_MM:
    case Mips::MFC2_MMR6:
    case Mips::MFHC2_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: impl
        return 16;
      }
      break;
    }
    case Mips::RDDSP_MM:
    case Mips::WRDSP_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: mask
        return 14;
      }
      break;
    }
    case Mips::BEQZALC_MMR6:
    case Mips::BGTZALC_MMR6:
    case Mips::BGTZC_MMR6:
    case Mips::BLEZALC_MMR6:
    case Mips::BLEZC_MMR6:
    case Mips::BNEZALC_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::RDHWR_MM:
    case Mips::RDPGPR_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rd
        return 16;
      }
      break;
    }
    case Mips::BALIGN_MMR2: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: bp
        return 14;
      }
      break;
    }
    case Mips::ADDIU_MMR6:
    case Mips::ANDI_MMR6:
    case Mips::ORI_MMR6:
    case Mips::SLTi_MM:
    case Mips::SLTiu_MM:
    case Mips::XORI_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: imm16
        return 0;
      }
      break;
    }
    case Mips::BNVC_MMR6:
    case Mips::BOVC_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::EXT_MM:
    case Mips::INS_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: pos
        return 6;
      case 3:
        // op: size
        return 11;
      }
      break;
    }
    case Mips::APPEND_MMR2:
    case Mips::PRECR_SRA_PH_W_MMR2:
    case Mips::PRECR_SRA_R_PH_W_MMR2:
    case Mips::PREPEND_MMR2:
    case Mips::SHLL_S_W_MM:
    case Mips::SHRA_R_W_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: sa
        return 11;
      }
      break;
    }
    case Mips::SHLL_PH_MM:
    case Mips::SHLL_S_PH_MM:
    case Mips::SHRA_PH_MM:
    case Mips::SHRA_R_PH_MM:
    case Mips::SHRL_PH_MMR2: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: sa
        return 12;
      }
      break;
    }
    case Mips::SHLL_QB_MM:
    case Mips::SHRA_QB_MMR2:
    case Mips::SHRA_R_QB_MMR2:
    case Mips::SHRL_QB_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: sa
        return 13;
      }
      break;
    }
    case Mips::MFC0_MMR6:
    case Mips::MFGC0_MM:
    case Mips::MFHC0_MMR6:
    case Mips::MFHGC0_MM:
    case Mips::RDHWR_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 2:
        // op: sel
        return 11;
      }
      break;
    }
    case Mips::EXT_MMR6:
    case Mips::INS_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 3:
        // op: size
        return 11;
      case 2:
        // op: pos
        return 6;
      }
      break;
    }
    case Mips::ABSQ_S_PH_MM:
    case Mips::ABSQ_S_QB_MMR2:
    case Mips::ABSQ_S_W_MM:
    case Mips::BITREV_MM:
    case Mips::JALRC_HB_MMR6:
    case Mips::JALRC_MMR6:
    case Mips::PRECEQU_PH_QBLA_MM:
    case Mips::PRECEQU_PH_QBL_MM:
    case Mips::PRECEQU_PH_QBRA_MM:
    case Mips::PRECEQU_PH_QBR_MM:
    case Mips::PRECEQ_W_PHL_MM:
    case Mips::PRECEQ_W_PHR_MM:
    case Mips::PRECEU_PH_QBLA_MM:
    case Mips::PRECEU_PH_QBL_MM:
    case Mips::PRECEU_PH_QBRA_MM:
    case Mips::PRECEU_PH_QBR_MM:
    case Mips::RADDU_W_QB_MM:
    case Mips::REPLV_PH_MM:
    case Mips::REPLV_QB_MM:
    case Mips::WRPGPR_MMR6:
    case Mips::WSBH_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      }
      break;
    }
    case Mips::LWP_MM:
    case Mips::SWP_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 2:
        // op: addr
        return 0;
      }
      break;
    }
    case Mips::EXTPDP_MM:
    case Mips::EXTP_MM:
    case Mips::EXTR_RS_W_MM:
    case Mips::EXTR_R_W_MM:
    case Mips::EXTR_S_H_MM:
    case Mips::EXTR_W_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 2:
        // op: imm
        return 16;
      case 1:
        // op: ac
        return 14;
      }
      break;
    }
    case Mips::EXTPDPV_MM:
    case Mips::EXTPV_MM:
    case Mips::EXTRV_RS_W_MM:
    case Mips::EXTRV_R_W_MM:
    case Mips::EXTRV_S_H_MM:
    case Mips::EXTRV_W_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 2:
        // op: rs
        return 16;
      case 1:
        // op: ac
        return 14;
      }
      break;
    }
    case Mips::INSV_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 21;
      case 2:
        // op: rs
        return 16;
      }
      break;
    }
    case Mips::NOT16_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 3;
      case 1:
        // op: rs
        return 0;
      }
      break;
    }
    case Mips::LWM16_MM:
    case Mips::SWM16_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 4;
      case 1:
        // op: addr
        return 0;
      }
      break;
    }
    case Mips::LWSP_MM:
    case Mips::SWSP_MM:
    case Mips::SWSP_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 5;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::LBU16_MM:
    case Mips::LHU16_MM:
    case Mips::LW16_MM:
    case Mips::SB16_MM:
    case Mips::SB16_MMR6:
    case Mips::SH16_MM:
    case Mips::SH16_MMR6:
    case Mips::SW16_MM:
    case Mips::SW16_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 7;
      case 1:
        // op: addr
        return 0;
      }
      break;
    }
    case Mips::LWGP_MM: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 7;
      case 1:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::NOT16_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 7;
      case 1:
        // op: rs
        return 4;
      }
      break;
    }
    case Mips::LWM16_MMR6:
    case Mips::SWM16_MMR6: {
      switch (OpNum) {
      case 0:
        // op: rt
        return 8;
      case 1:
        // op: addr
        return 4;
      }
      break;
    }
    case Mips::BeqzRxImm16:
    case Mips::BnezRxImm16:
    case Mips::CmpiRxImm16:
    case Mips::LiRxImm16:
    case Mips::LwRxPcTcp16:
    case Mips::SltiRxImm16:
    case Mips::SltiuRxImm16: {
      switch (OpNum) {
      case 0:
        // op: rx
        return 8;
      case 1:
        // op: imm8
        return 0;
      }
      break;
    }
    case Mips::CmpRxRy16:
    case Mips::DivRxRy16:
    case Mips::DivuRxRy16:
    case Mips::NegRxRy16:
    case Mips::NotRxRy16:
    case Mips::SltRxRy16:
    case Mips::SltuRxRy16: {
      switch (OpNum) {
      case 0:
        // op: rx
        return 8;
      case 1:
        // op: ry
        return 5;
      }
      break;
    }
    case Mips::AddiuRxRxImm16: {
      switch (OpNum) {
      case 0:
        // op: rx
        return 8;
      case 2:
        // op: imm8
        return 0;
      }
      break;
    }
    case Mips::JumpLinkReg16:
    case Mips::Mfhi16:
    case Mips::Mflo16:
    case Mips::SebRx16:
    case Mips::SehRx16: {
      switch (OpNum) {
      case 0:
        // op: rx
        return 8;
      }
      break;
    }
    case Mips::MoveR3216: {
      switch (OpNum) {
      case 0:
        // op: ry
        return 4;
      case 1:
        // op: r32
        return 0;
      }
      break;
    }
    case Mips::SYNC_MM:
    case Mips::SYNC_MMR6: {
      switch (OpNum) {
      case 0:
        // op: stype
        return 16;
      }
      break;
    }
    case Mips::SYNC: {
      switch (OpNum) {
      case 0:
        // op: stype
        return 6;
      }
      break;
    }
    case Mips::J:
    case Mips::JAL:
    case Mips::JALS_MM:
    case Mips::JALX:
    case Mips::JALX_MM:
    case Mips::JAL_MM:
    case Mips::J_MM: {
      switch (OpNum) {
      case 0:
        // op: target
        return 0;
      }
      break;
    }
    case Mips::LBU_MMR6:
    case Mips::LB_MMR6: {
      switch (OpNum) {
      case 1:
        // op: addr
        return 0;
      case 0:
        // op: rt
        return 21;
      }
      break;
    }
    case Mips::LD_B:
    case Mips::LD_D:
    case Mips::LD_H:
    case Mips::LD_W:
    case Mips::ST_B:
    case Mips::ST_D:
    case Mips::ST_H:
    case Mips::ST_W: {
      switch (OpNum) {
      case 1:
        // op: addr
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::LBE:
    case Mips::LBuE:
    case Mips::LHE:
    case Mips::LHuE:
    case Mips::LLE:
    case Mips::LWE:
    case Mips::LWLE:
    case Mips::LWRE:
    case Mips::SBE:
    case Mips::SHE:
    case Mips::SWE:
    case Mips::SWLE:
    case Mips::SWRE: {
      switch (OpNum) {
      case 1:
        // op: addr
        return 7;
      case 0:
        // op: rt
        return 16;
      }
      break;
    }
    case Mips::CLASS_D:
    case Mips::CLASS_S:
    case Mips::RINT_D:
    case Mips::RINT_S: {
      switch (OpNum) {
      case 1:
        // op: fs
        return 11;
      case 0:
        // op: fd
        return 6;
      }
      break;
    }
    case Mips::C_EQ_D32:
    case Mips::C_EQ_D64:
    case Mips::C_EQ_S:
    case Mips::C_F_D32:
    case Mips::C_F_D64:
    case Mips::C_F_S:
    case Mips::C_LE_D32:
    case Mips::C_LE_D64:
    case Mips::C_LE_S:
    case Mips::C_LT_D32:
    case Mips::C_LT_D64:
    case Mips::C_LT_S:
    case Mips::C_NGE_D32:
    case Mips::C_NGE_D64:
    case Mips::C_NGE_S:
    case Mips::C_NGLE_D32:
    case Mips::C_NGLE_D64:
    case Mips::C_NGLE_S:
    case Mips::C_NGL_D32:
    case Mips::C_NGL_D64:
    case Mips::C_NGL_S:
    case Mips::C_NGT_D32:
    case Mips::C_NGT_D64:
    case Mips::C_NGT_S:
    case Mips::C_OLE_D32:
    case Mips::C_OLE_D64:
    case Mips::C_OLE_S:
    case Mips::C_OLT_D32:
    case Mips::C_OLT_D64:
    case Mips::C_OLT_S:
    case Mips::C_SEQ_D32:
    case Mips::C_SEQ_D64:
    case Mips::C_SEQ_S:
    case Mips::C_SF_D32:
    case Mips::C_SF_D64:
    case Mips::C_SF_S:
    case Mips::C_UEQ_D32:
    case Mips::C_UEQ_D64:
    case Mips::C_UEQ_S:
    case Mips::C_ULE_D32:
    case Mips::C_ULE_D64:
    case Mips::C_ULE_S:
    case Mips::C_ULT_D32:
    case Mips::C_ULT_D64:
    case Mips::C_ULT_S:
    case Mips::C_UN_D32:
    case Mips::C_UN_D64:
    case Mips::C_UN_S: {
      switch (OpNum) {
      case 1:
        // op: fs
        return 11;
      case 2:
        // op: ft
        return 16;
      case 0:
        // op: fcc
        return 8;
      }
      break;
    }
    case Mips::C_EQ_D32_MM:
    case Mips::C_EQ_D64_MM:
    case Mips::C_EQ_S_MM:
    case Mips::C_F_D32_MM:
    case Mips::C_F_D64_MM:
    case Mips::C_F_S_MM:
    case Mips::C_LE_D32_MM:
    case Mips::C_LE_D64_MM:
    case Mips::C_LE_S_MM:
    case Mips::C_LT_D32_MM:
    case Mips::C_LT_D64_MM:
    case Mips::C_LT_S_MM:
    case Mips::C_NGE_D32_MM:
    case Mips::C_NGE_D64_MM:
    case Mips::C_NGE_S_MM:
    case Mips::C_NGLE_D32_MM:
    case Mips::C_NGLE_D64_MM:
    case Mips::C_NGLE_S_MM:
    case Mips::C_NGL_D32_MM:
    case Mips::C_NGL_D64_MM:
    case Mips::C_NGL_S_MM:
    case Mips::C_NGT_D32_MM:
    case Mips::C_NGT_D64_MM:
    case Mips::C_NGT_S_MM:
    case Mips::C_OLE_D32_MM:
    case Mips::C_OLE_D64_MM:
    case Mips::C_OLE_S_MM:
    case Mips::C_OLT_D32_MM:
    case Mips::C_OLT_D64_MM:
    case Mips::C_OLT_S_MM:
    case Mips::C_SEQ_D32_MM:
    case Mips::C_SEQ_D64_MM:
    case Mips::C_SEQ_S_MM:
    case Mips::C_SF_D32_MM:
    case Mips::C_SF_D64_MM:
    case Mips::C_SF_S_MM:
    case Mips::C_UEQ_D32_MM:
    case Mips::C_UEQ_D64_MM:
    case Mips::C_UEQ_S_MM:
    case Mips::C_ULE_D32_MM:
    case Mips::C_ULE_D64_MM:
    case Mips::C_ULE_S_MM:
    case Mips::C_ULT_D32_MM:
    case Mips::C_ULT_D64_MM:
    case Mips::C_ULT_S_MM:
    case Mips::C_UN_D32_MM:
    case Mips::C_UN_D64_MM:
    case Mips::C_UN_S_MM: {
      switch (OpNum) {
      case 1:
        // op: fs
        return 16;
      case 2:
        // op: ft
        return 21;
      case 0:
        // op: fcc
        return 13;
      }
      break;
    }
    case Mips::CLASS_D_MMR6:
    case Mips::CLASS_S_MMR6:
    case Mips::RINT_D_MMR6:
    case Mips::RINT_S_MMR6: {
      switch (OpNum) {
      case 1:
        // op: fs
        return 21;
      case 0:
        // op: fd
        return 16;
      }
      break;
    }
    case Mips::FADD_S_MMR6:
    case Mips::FDIV_S_MMR6:
    case Mips::FMUL_S_MMR6:
    case Mips::FSUB_S_MMR6: {
      switch (OpNum) {
      case 1:
        // op: ft
        return 21;
      case 2:
        // op: fs
        return 16;
      case 0:
        // op: fd
        return 11;
      }
      break;
    }
    case Mips::AddiuRxImmX16:
    case Mips::AddiuRxPcImmX16:
    case Mips::BeqzRxImmX16:
    case Mips::BnezRxImmX16:
    case Mips::CmpiRxImmX16:
    case Mips::LiRxImmAlignX16:
    case Mips::LiRxImmX16:
    case Mips::LwRxPcTcpX16:
    case Mips::SltiRxImmX16:
    case Mips::SltiuRxImmX16: {
      switch (OpNum) {
      case 1:
        // op: imm16
        return 0;
      case 0:
        // op: rx
        return 8;
      }
      break;
    }
    case Mips::PREFX_MM: {
      switch (OpNum) {
      case 1:
        // op: index
        return 21;
      case 0:
        // op: base
        return 16;
      case 2:
        // op: hint
        return 11;
      }
      break;
    }
    case Mips::BNZ_B:
    case Mips::BNZ_D:
    case Mips::BNZ_H:
    case Mips::BNZ_V:
    case Mips::BNZ_W:
    case Mips::BZ_B:
    case Mips::BZ_D:
    case Mips::BZ_H:
    case Mips::BZ_V:
    case Mips::BZ_W: {
      switch (OpNum) {
      case 1:
        // op: offset
        return 0;
      case 0:
        // op: wt
        return 16;
      }
      break;
    }
    case Mips::ADDIUS5_MM: {
      switch (OpNum) {
      case 1:
        // op: rd
        return 5;
      case 2:
        // op: imm
        return 1;
      }
      break;
    }
    case Mips::MOVE16_MM:
    case Mips::MOVE16_MMR6: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 0;
      case 0:
        // op: rd
        return 5;
      }
      break;
    }
    case Mips::CTCMSA: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 11;
      case 0:
        // op: cd
        return 6;
      }
      break;
    }
    case Mips::FILL_B:
    case Mips::FILL_D:
    case Mips::FILL_H:
    case Mips::FILL_W: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::MTHI_DSP_MM:
    case Mips::MTHLIP_MM:
    case Mips::MTLO_DSP_MM:
    case Mips::SHILOV_MM: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 16;
      case 0:
        // op: ac
        return 14;
      }
      break;
    }
    case Mips::JALRS_MM:
    case Mips::JALR_MM: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 16;
      case 0:
        // op: rd
        return 21;
      }
      break;
    }
    case Mips::AUI_MMR6: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 16;
      case 0:
        // op: rt
        return 21;
      case 2:
        // op: imm
        return 0;
      }
      break;
    }
    case Mips::ADDi_MM:
    case Mips::ADDiu_MM:
    case Mips::ANDi_MM:
    case Mips::ORi_MM:
    case Mips::XORi_MM: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 16;
      case 0:
        // op: rt
        return 21;
      case 2:
        // op: imm16
        return 0;
      }
      break;
    }
    case Mips::CLO_MMR6: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 16;
      case 0:
        // op: rt
        return 21;
      }
      break;
    }
    case Mips::MTHI_DSP:
    case Mips::MTLO_DSP: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 21;
      case 0:
        // op: ac
        return 11;
      }
      break;
    }
    case Mips::YIELD: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 21;
      case 0:
        // op: rd
        return 11;
      }
      break;
    }
    case Mips::CLZ_MMR6: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 21;
      case 0:
        // op: rt
        return 11;
      }
      break;
    }
    case Mips::AUI:
    case Mips::DAUI: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 21;
      case 0:
        // op: rt
        return 16;
      case 2:
        // op: imm
        return 0;
      }
      break;
    }
    case Mips::SEQi:
    case Mips::SNEi: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 21;
      case 0:
        // op: rt
        return 16;
      case 2:
        // op: imm10
        return 6;
      }
      break;
    }
    case Mips::ADDi:
    case Mips::ADDiu:
    case Mips::ANDi:
    case Mips::ANDi64:
    case Mips::DADDi:
    case Mips::DADDiu:
    case Mips::ORi:
    case Mips::ORi64:
    case Mips::XORi:
    case Mips::XORi64: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 21;
      case 0:
        // op: rt
        return 16;
      case 2:
        // op: imm16
        return 0;
      }
      break;
    }
    case Mips::PRECR_SRA_PH_W:
    case Mips::PRECR_SRA_R_PH_W: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 21;
      case 0:
        // op: rt
        return 16;
      case 2:
        // op: sa
        return 11;
      }
      break;
    }
    case Mips::DLSA:
    case Mips::LSA: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: rt
        return 16;
      case 0:
        // op: rd
        return 11;
      case 3:
        // op: sa
        return 6;
      }
      break;
    }
    case Mips::CMPGDU_EQ_QB:
    case Mips::CMPGDU_LE_QB:
    case Mips::CMPGDU_LT_QB:
    case Mips::CMPGU_EQ_QB:
    case Mips::CMPGU_LE_QB:
    case Mips::CMPGU_LT_QB:
    case Mips::PACKRL_PH:
    case Mips::PICK_PH:
    case Mips::PICK_QB:
    case Mips::PRECRQU_S_QB_PH:
    case Mips::PRECRQ_PH_W:
    case Mips::PRECRQ_QB_PH:
    case Mips::PRECRQ_RS_PH_W:
    case Mips::PRECR_QB_PH: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: rt
        return 16;
      case 0:
        // op: rd
        return 11;
      }
      break;
    }
    case Mips::CRC32B:
    case Mips::CRC32CB:
    case Mips::CRC32CD:
    case Mips::CRC32CH:
    case Mips::CRC32CW:
    case Mips::CRC32D:
    case Mips::CRC32H:
    case Mips::CRC32W: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 21;
      case 2:
        // op: rt
        return 16;
      }
      break;
    }
    case Mips::ADDU16_MMR6:
    case Mips::SUBU16_MMR6: {
      switch (OpNum) {
      case 1:
        // op: rs
        return 7;
      case 2:
        // op: rt
        return 4;
      case 0:
        // op: rd
        return 1;
      }
      break;
    }
    case Mips::CTC1:
    case Mips::DMTC1:
    case Mips::MTC1:
    case Mips::MTC1_D64: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 16;
      case 0:
        // op: fs
        return 11;
      }
      break;
    }
    case Mips::DMTC0:
    case Mips::DMTC2:
    case Mips::DMTGC0:
    case Mips::MTC0:
    case Mips::MTC2:
    case Mips::MTGC0:
    case Mips::MTHGC0: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 16;
      case 0:
        // op: rd
        return 11;
      case 2:
        // op: sel
        return 0;
      }
      break;
    }
    case Mips::MFTR:
    case Mips::MTTR: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 16;
      case 0:
        // op: rd
        return 11;
      case 2:
        // op: u
        return 5;
      case 4:
        // op: h
        return 4;
      case 3:
        // op: sel
        return 0;
      }
      break;
    }
    case Mips::SC:
    case Mips::SC64:
    case Mips::SCD: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 16;
      case 2:
        // op: addr
        return 0;
      }
      break;
    }
    case Mips::SC64_R6:
    case Mips::SCD_R6:
    case Mips::SC_R6: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 16;
      case 2:
        // op: addr
        return 7;
      }
      break;
    }
    case Mips::CTC1_MM:
    case Mips::MTC1_D64_MM:
    case Mips::MTC1_MM:
    case Mips::MTC1_MMR6: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 21;
      case 0:
        // op: fs
        return 16;
      }
      break;
    }
    case Mips::CTC2_MM:
    case Mips::MTC2_MMR6:
    case Mips::MTHC2_MMR6: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 21;
      case 0:
        // op: impl
        return 16;
      }
      break;
    }
    case Mips::BEQC_MMR6:
    case Mips::BGEC_MMR6:
    case Mips::BGEUC_MMR6:
    case Mips::BLTC_MMR6:
    case Mips::BLTUC_MMR6:
    case Mips::BNEC_MMR6: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 21;
      case 0:
        // op: rs
        return 16;
      case 2:
        // op: offset
        return 0;
      }
      break;
    }
    case Mips::MTC0_MMR6:
    case Mips::MTGC0_MM:
    case Mips::MTHC0_MMR6:
    case Mips::MTHGC0_MM: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 21;
      case 0:
        // op: rs
        return 16;
      case 2:
        // op: sel
        return 11;
      }
      break;
    }
    case Mips::CMPU_EQ_QB_MM:
    case Mips::CMPU_LE_QB_MM:
    case Mips::CMPU_LT_QB_MM:
    case Mips::CMP_EQ_PH_MM:
    case Mips::CMP_LE_PH_MM:
    case Mips::CMP_LT_PH_MM: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 21;
      case 0:
        // op: rs
        return 16;
      }
      break;
    }
    case Mips::SCE_MM:
    case Mips::SC_MM:
    case Mips::SC_MMR6: {
      switch (OpNum) {
      case 1:
        // op: rt
        return 21;
      case 2:
        // op: addr
        return 0;
      }
      break;
    }
    case Mips::AdduRxRyRz16:
    case Mips::SubuRxRyRz16: {
      switch (OpNum) {
      case 1:
        // op: rx
        return 8;
      case 2:
        // op: ry
        return 5;
      case 0:
        // op: rz
        return 2;
      }
      break;
    }
    case Mips::AndRxRxRy16:
    case Mips::OrRxRxRy16:
    case Mips::SllvRxRy16:
    case Mips::SravRxRy16:
    case Mips::SrlvRxRy16:
    case Mips::XorRxRxRy16: {
      switch (OpNum) {
      case 1:
        // op: rx
        return 8;
      case 2:
        // op: ry
        return 5;
      }
      break;
    }
    case Mips::LDI_B:
    case Mips::LDI_D:
    case Mips::LDI_H:
    case Mips::LDI_W: {
      switch (OpNum) {
      case 1:
        // op: s10
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::SHILO_MM: {
      switch (OpNum) {
      case 1:
        // op: shift
        return 16;
      case 0:
        // op: ac
        return 14;
      }
      break;
    }
    case Mips::BCLRI_B:
    case Mips::BCLRI_D:
    case Mips::BCLRI_H:
    case Mips::BCLRI_W:
    case Mips::BNEGI_B:
    case Mips::BNEGI_D:
    case Mips::BNEGI_H:
    case Mips::BNEGI_W:
    case Mips::BSETI_B:
    case Mips::BSETI_D:
    case Mips::BSETI_H:
    case Mips::BSETI_W:
    case Mips::SAT_S_B:
    case Mips::SAT_S_D:
    case Mips::SAT_S_H:
    case Mips::SAT_S_W:
    case Mips::SAT_U_B:
    case Mips::SAT_U_D:
    case Mips::SAT_U_H:
    case Mips::SAT_U_W:
    case Mips::SLLI_B:
    case Mips::SLLI_D:
    case Mips::SLLI_H:
    case Mips::SLLI_W:
    case Mips::SRAI_B:
    case Mips::SRAI_D:
    case Mips::SRAI_H:
    case Mips::SRAI_W:
    case Mips::SRARI_B:
    case Mips::SRARI_D:
    case Mips::SRARI_H:
    case Mips::SRARI_W:
    case Mips::SRLI_B:
    case Mips::SRLI_D:
    case Mips::SRLI_H:
    case Mips::SRLI_W:
    case Mips::SRLRI_B:
    case Mips::SRLRI_D:
    case Mips::SRLRI_H:
    case Mips::SRLRI_W: {
      switch (OpNum) {
      case 1:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      case 2:
        // op: m
        return 16;
      }
      break;
    }
    case Mips::FCLASS_D:
    case Mips::FCLASS_W:
    case Mips::FEXUPL_D:
    case Mips::FEXUPL_W:
    case Mips::FEXUPR_D:
    case Mips::FEXUPR_W:
    case Mips::FFINT_S_D:
    case Mips::FFINT_S_W:
    case Mips::FFINT_U_D:
    case Mips::FFINT_U_W:
    case Mips::FFQL_D:
    case Mips::FFQL_W:
    case Mips::FFQR_D:
    case Mips::FFQR_W:
    case Mips::FLOG2_D:
    case Mips::FLOG2_W:
    case Mips::FRCP_D:
    case Mips::FRCP_W:
    case Mips::FRINT_D:
    case Mips::FRINT_W:
    case Mips::FRSQRT_D:
    case Mips::FRSQRT_W:
    case Mips::FSQRT_D:
    case Mips::FSQRT_W:
    case Mips::FTINT_S_D:
    case Mips::FTINT_S_W:
    case Mips::FTINT_U_D:
    case Mips::FTINT_U_W:
    case Mips::FTRUNC_S_D:
    case Mips::FTRUNC_S_W:
    case Mips::FTRUNC_U_D:
    case Mips::FTRUNC_U_W:
    case Mips::MOVE_V:
    case Mips::NLOC_B:
    case Mips::NLOC_D:
    case Mips::NLOC_H:
    case Mips::NLOC_W:
    case Mips::NLZC_B:
    case Mips::NLZC_D:
    case Mips::NLZC_H:
    case Mips::NLZC_W:
    case Mips::PCNT_B:
    case Mips::PCNT_D:
    case Mips::PCNT_H:
    case Mips::PCNT_W: {
      switch (OpNum) {
      case 1:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::SCE: {
      switch (OpNum) {
      case 2:
        // op: addr
        return 7;
      case 1:
        // op: rt
        return 16;
      }
      break;
    }
    case Mips::MAXA_D:
    case Mips::MAXA_S:
    case Mips::MAX_D:
    case Mips::MAX_S:
    case Mips::MINA_D:
    case Mips::MINA_S:
    case Mips::MIN_D:
    case Mips::MIN_S:
    case Mips::SELEQZ_D:
    case Mips::SELEQZ_S:
    case Mips::SELNEZ_D:
    case Mips::SELNEZ_S: {
      switch (OpNum) {
      case 2:
        // op: ft
        return 16;
      case 1:
        // op: fs
        return 11;
      case 0:
        // op: fd
        return 6;
      }
      break;
    }
    case Mips::CMP_AF_D_MMR6:
    case Mips::CMP_AF_S_MMR6:
    case Mips::CMP_EQ_D_MMR6:
    case Mips::CMP_EQ_S_MMR6:
    case Mips::CMP_LE_D_MMR6:
    case Mips::CMP_LE_S_MMR6:
    case Mips::CMP_LT_D_MMR6:
    case Mips::CMP_LT_S_MMR6:
    case Mips::CMP_SAF_D_MMR6:
    case Mips::CMP_SAF_S_MMR6:
    case Mips::CMP_SEQ_D_MMR6:
    case Mips::CMP_SEQ_S_MMR6:
    case Mips::CMP_SLE_D_MMR6:
    case Mips::CMP_SLE_S_MMR6:
    case Mips::CMP_SLT_D_MMR6:
    case Mips::CMP_SLT_S_MMR6:
    case Mips::CMP_SUEQ_D_MMR6:
    case Mips::CMP_SUEQ_S_MMR6:
    case Mips::CMP_SULE_D_MMR6:
    case Mips::CMP_SULE_S_MMR6:
    case Mips::CMP_SULT_D_MMR6:
    case Mips::CMP_SULT_S_MMR6:
    case Mips::CMP_SUN_D_MMR6:
    case Mips::CMP_SUN_S_MMR6:
    case Mips::CMP_UEQ_D_MMR6:
    case Mips::CMP_UEQ_S_MMR6:
    case Mips::CMP_ULE_D_MMR6:
    case Mips::CMP_ULE_S_MMR6:
    case Mips::CMP_ULT_D_MMR6:
    case Mips::CMP_ULT_S_MMR6:
    case Mips::CMP_UN_D_MMR6:
    case Mips::CMP_UN_S_MMR6:
    case Mips::FADD_D32_MM:
    case Mips::FADD_D64_MM:
    case Mips::FADD_S_MM:
    case Mips::FDIV_D32_MM:
    case Mips::FDIV_D64_MM:
    case Mips::FDIV_S_MM:
    case Mips::FMUL_D32_MM:
    case Mips::FMUL_D64_MM:
    case Mips::FMUL_S_MM:
    case Mips::FSUB_D32_MM:
    case Mips::FSUB_D64_MM:
    case Mips::FSUB_S_MM:
    case Mips::MAXA_D_MMR6:
    case Mips::MAXA_S_MMR6:
    case Mips::MAX_D_MMR6:
    case Mips::MAX_S_MMR6:
    case Mips::MINA_D_MMR6:
    case Mips::MINA_S_MMR6:
    case Mips::MIN_D_MMR6:
    case Mips::MIN_S_MMR6:
    case Mips::SELEQZ_D_MMR6:
    case Mips::SELEQZ_S_MMR6:
    case Mips::SELNEZ_D_MMR6:
    case Mips::SELNEZ_S_MMR6: {
      switch (OpNum) {
      case 2:
        // op: ft
        return 21;
      case 1:
        // op: fs
        return 16;
      case 0:
        // op: fd
        return 11;
      }
      break;
    }
    case Mips::ADDVI_B:
    case Mips::ADDVI_D:
    case Mips::ADDVI_H:
    case Mips::ADDVI_W:
    case Mips::CEQI_B:
    case Mips::CEQI_D:
    case Mips::CEQI_H:
    case Mips::CEQI_W:
    case Mips::CLEI_S_B:
    case Mips::CLEI_S_D:
    case Mips::CLEI_S_H:
    case Mips::CLEI_S_W:
    case Mips::CLEI_U_B:
    case Mips::CLEI_U_D:
    case Mips::CLEI_U_H:
    case Mips::CLEI_U_W:
    case Mips::CLTI_S_B:
    case Mips::CLTI_S_D:
    case Mips::CLTI_S_H:
    case Mips::CLTI_S_W:
    case Mips::CLTI_U_B:
    case Mips::CLTI_U_D:
    case Mips::CLTI_U_H:
    case Mips::CLTI_U_W:
    case Mips::MAXI_S_B:
    case Mips::MAXI_S_D:
    case Mips::MAXI_S_H:
    case Mips::MAXI_S_W:
    case Mips::MAXI_U_B:
    case Mips::MAXI_U_D:
    case Mips::MAXI_U_H:
    case Mips::MAXI_U_W:
    case Mips::MINI_S_B:
    case Mips::MINI_S_D:
    case Mips::MINI_S_H:
    case Mips::MINI_S_W:
    case Mips::MINI_U_B:
    case Mips::MINI_U_D:
    case Mips::MINI_U_H:
    case Mips::MINI_U_W:
    case Mips::SUBVI_B:
    case Mips::SUBVI_D:
    case Mips::SUBVI_H:
    case Mips::SUBVI_W: {
      switch (OpNum) {
      case 2:
        // op: imm
        return 16;
      case 1:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::AddiuRxRyOffMemX16: {
      switch (OpNum) {
      case 2:
        // op: imm15
        return 0;
      case 1:
        // op: rx
        return 8;
      case 0:
        // op: ry
        return 5;
      }
      break;
    }
    case Mips::AddiuRxRxImmX16: {
      switch (OpNum) {
      case 2:
        // op: imm16
        return 0;
      case 0:
        // op: rx
        return 8;
      }
      break;
    }
    case Mips::LbRxRyOffMemX16:
    case Mips::LbuRxRyOffMemX16:
    case Mips::LhRxRyOffMemX16:
    case Mips::LhuRxRyOffMemX16:
    case Mips::LwRxRyOffMemX16:
    case Mips::LwRxSpImmX16:
    case Mips::SbRxRyOffMemX16:
    case Mips::ShRxRyOffMemX16:
    case Mips::SwRxRyOffMemX16:
    case Mips::SwRxSpImmX16: {
      switch (OpNum) {
      case 2:
        // op: imm16
        return 0;
      case 1:
        // op: rx
        return 8;
      case 0:
        // op: ry
        return 5;
      }
      break;
    }
    case Mips::LBUX_MM:
    case Mips::LHX_MM:
    case Mips::LWX_MM: {
      switch (OpNum) {
      case 2:
        // op: index
        return 21;
      case 1:
        // op: base
        return 16;
      case 0:
        // op: rd
        return 11;
      }
      break;
    }
    case Mips::COPY_S_B:
    case Mips::COPY_S_D:
    case Mips::COPY_S_H:
    case Mips::COPY_S_W:
    case Mips::COPY_U_B:
    case Mips::COPY_U_H:
    case Mips::COPY_U_W: {
      switch (OpNum) {
      case 2:
        // op: n
        return 16;
      case 1:
        // op: ws
        return 11;
      case 0:
        // op: rd
        return 6;
      }
      break;
    }
    case Mips::SPLATI_B:
    case Mips::SPLATI_D:
    case Mips::SPLATI_H:
    case Mips::SPLATI_W: {
      switch (OpNum) {
      case 2:
        // op: n
        return 16;
      case 1:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::INSVE_B:
    case Mips::INSVE_D:
    case Mips::INSVE_H:
    case Mips::INSVE_W: {
      switch (OpNum) {
      case 2:
        // op: n
        return 16;
      case 3:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::MTHC1_D32:
    case Mips::MTHC1_D64: {
      switch (OpNum) {
      case 2:
        // op: rt
        return 16;
      case 0:
        // op: fs
        return 11;
      }
      break;
    }
    case Mips::SPLAT_B:
    case Mips::SPLAT_D:
    case Mips::SPLAT_H:
    case Mips::SPLAT_W: {
      switch (OpNum) {
      case 2:
        // op: rt
        return 16;
      case 1:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::MTHC1_D32_MM:
    case Mips::MTHC1_D64_MM: {
      switch (OpNum) {
      case 2:
        // op: rt
        return 21;
      case 0:
        // op: fs
        return 16;
      }
      break;
    }
    case Mips::DPAQX_SA_W_PH_MMR2:
    case Mips::DPAQX_S_W_PH_MMR2:
    case Mips::DPAQ_SA_L_W_MM:
    case Mips::DPAQ_S_W_PH_MM:
    case Mips::DPAU_H_QBL_MM:
    case Mips::DPAU_H_QBR_MM:
    case Mips::DPAX_W_PH_MMR2:
    case Mips::DPA_W_PH_MMR2:
    case Mips::DPSQX_SA_W_PH_MMR2:
    case Mips::DPSQX_S_W_PH_MMR2:
    case Mips::DPSQ_SA_L_W_MM:
    case Mips::DPSQ_S_W_PH_MM:
    case Mips::DPSU_H_QBL_MM:
    case Mips::DPSU_H_QBR_MM:
    case Mips::DPSX_W_PH_MMR2:
    case Mips::DPS_W_PH_MMR2:
    case Mips::MADDU_DSP_MM:
    case Mips::MADD_DSP_MM:
    case Mips::MAQ_SA_W_PHL_MM:
    case Mips::MAQ_SA_W_PHR_MM:
    case Mips::MAQ_S_W_PHL_MM:
    case Mips::MAQ_S_W_PHR_MM:
    case Mips::MSUBU_DSP_MM:
    case Mips::MSUB_DSP_MM:
    case Mips::MULSAQ_S_W_PH_MM:
    case Mips::MULSA_W_PH_MMR2:
    case Mips::MULTU_DSP_MM:
    case Mips::MULT_DSP_MM: {
      switch (OpNum) {
      case 2:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 0:
        // op: ac
        return 14;
      }
      break;
    }
    case Mips::ADD_MM:
    case Mips::ADDu_MM:
    case Mips::AND_MM:
    case Mips::CMPGU_EQ_QB_MM:
    case Mips::CMPGU_LE_QB_MM:
    case Mips::CMPGU_LT_QB_MM:
    case Mips::MOVN_I_MM:
    case Mips::MOVZ_I_MM:
    case Mips::MUL_MM:
    case Mips::NOR_MM:
    case Mips::OR_MM:
    case Mips::SLT_MM:
    case Mips::SLTu_MM:
    case Mips::SUB_MM:
    case Mips::SUBu_MM:
    case Mips::XOR_MM: {
      switch (OpNum) {
      case 2:
        // op: rt
        return 21;
      case 1:
        // op: rs
        return 16;
      case 0:
        // op: rd
        return 11;
      }
      break;
    }
    case Mips::AND16_MM:
    case Mips::OR16_MM:
    case Mips::XOR16_MM: {
      switch (OpNum) {
      case 2:
        // op: rt
        return 3;
      case 1:
        // op: rs
        return 0;
      }
      break;
    }
    case Mips::AND16_MMR6:
    case Mips::OR16_MMR6:
    case Mips::XOR16_MMR6: {
      switch (OpNum) {
      case 2:
        // op: rt
        return 7;
      case 1:
        // op: rs
        return 4;
      }
      break;
    }
    case Mips::SllX16:
    case Mips::SraX16:
    case Mips::SrlX16: {
      switch (OpNum) {
      case 2:
        // op: sa6
        return 21;
      case 0:
        // op: rx
        return 8;
      case 1:
        // op: ry
        return 5;
      }
      break;
    }
    case Mips::ANDI_B:
    case Mips::NORI_B:
    case Mips::ORI_B:
    case Mips::SHF_B:
    case Mips::SHF_H:
    case Mips::SHF_W:
    case Mips::XORI_B: {
      switch (OpNum) {
      case 2:
        // op: u8
        return 16;
      case 1:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::BINSLI_B:
    case Mips::BINSLI_D:
    case Mips::BINSLI_H:
    case Mips::BINSLI_W:
    case Mips::BINSRI_B:
    case Mips::BINSRI_D:
    case Mips::BINSRI_H:
    case Mips::BINSRI_W: {
      switch (OpNum) {
      case 2:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      case 3:
        // op: m
        return 16;
      }
      break;
    }
    case Mips::ADDS_A_B:
    case Mips::ADDS_A_D:
    case Mips::ADDS_A_H:
    case Mips::ADDS_A_W:
    case Mips::ADDS_S_B:
    case Mips::ADDS_S_D:
    case Mips::ADDS_S_H:
    case Mips::ADDS_S_W:
    case Mips::ADDS_U_B:
    case Mips::ADDS_U_D:
    case Mips::ADDS_U_H:
    case Mips::ADDS_U_W:
    case Mips::ADDV_B:
    case Mips::ADDV_D:
    case Mips::ADDV_H:
    case Mips::ADDV_W:
    case Mips::ADD_A_B:
    case Mips::ADD_A_D:
    case Mips::ADD_A_H:
    case Mips::ADD_A_W:
    case Mips::AND_V:
    case Mips::ASUB_S_B:
    case Mips::ASUB_S_D:
    case Mips::ASUB_S_H:
    case Mips::ASUB_S_W:
    case Mips::ASUB_U_B:
    case Mips::ASUB_U_D:
    case Mips::ASUB_U_H:
    case Mips::ASUB_U_W:
    case Mips::AVER_S_B:
    case Mips::AVER_S_D:
    case Mips::AVER_S_H:
    case Mips::AVER_S_W:
    case Mips::AVER_U_B:
    case Mips::AVER_U_D:
    case Mips::AVER_U_H:
    case Mips::AVER_U_W:
    case Mips::AVE_S_B:
    case Mips::AVE_S_D:
    case Mips::AVE_S_H:
    case Mips::AVE_S_W:
    case Mips::AVE_U_B:
    case Mips::AVE_U_D:
    case Mips::AVE_U_H:
    case Mips::AVE_U_W:
    case Mips::BCLR_B:
    case Mips::BCLR_D:
    case Mips::BCLR_H:
    case Mips::BCLR_W:
    case Mips::BNEG_B:
    case Mips::BNEG_D:
    case Mips::BNEG_H:
    case Mips::BNEG_W:
    case Mips::BSET_B:
    case Mips::BSET_D:
    case Mips::BSET_H:
    case Mips::BSET_W:
    case Mips::CEQ_B:
    case Mips::CEQ_D:
    case Mips::CEQ_H:
    case Mips::CEQ_W:
    case Mips::CLE_S_B:
    case Mips::CLE_S_D:
    case Mips::CLE_S_H:
    case Mips::CLE_S_W:
    case Mips::CLE_U_B:
    case Mips::CLE_U_D:
    case Mips::CLE_U_H:
    case Mips::CLE_U_W:
    case Mips::CLT_S_B:
    case Mips::CLT_S_D:
    case Mips::CLT_S_H:
    case Mips::CLT_S_W:
    case Mips::CLT_U_B:
    case Mips::CLT_U_D:
    case Mips::CLT_U_H:
    case Mips::CLT_U_W:
    case Mips::DIV_S_B:
    case Mips::DIV_S_D:
    case Mips::DIV_S_H:
    case Mips::DIV_S_W:
    case Mips::DIV_U_B:
    case Mips::DIV_U_D:
    case Mips::DIV_U_H:
    case Mips::DIV_U_W:
    case Mips::DOTP_S_D:
    case Mips::DOTP_S_H:
    case Mips::DOTP_S_W:
    case Mips::DOTP_U_D:
    case Mips::DOTP_U_H:
    case Mips::DOTP_U_W:
    case Mips::FADD_D:
    case Mips::FADD_W:
    case Mips::FCAF_D:
    case Mips::FCAF_W:
    case Mips::FCEQ_D:
    case Mips::FCEQ_W:
    case Mips::FCLE_D:
    case Mips::FCLE_W:
    case Mips::FCLT_D:
    case Mips::FCLT_W:
    case Mips::FCNE_D:
    case Mips::FCNE_W:
    case Mips::FCOR_D:
    case Mips::FCOR_W:
    case Mips::FCUEQ_D:
    case Mips::FCUEQ_W:
    case Mips::FCULE_D:
    case Mips::FCULE_W:
    case Mips::FCULT_D:
    case Mips::FCULT_W:
    case Mips::FCUNE_D:
    case Mips::FCUNE_W:
    case Mips::FCUN_D:
    case Mips::FCUN_W:
    case Mips::FDIV_D:
    case Mips::FDIV_W:
    case Mips::FEXDO_H:
    case Mips::FEXDO_W:
    case Mips::FEXP2_D:
    case Mips::FEXP2_W:
    case Mips::FMAX_A_D:
    case Mips::FMAX_A_W:
    case Mips::FMAX_D:
    case Mips::FMAX_W:
    case Mips::FMIN_A_D:
    case Mips::FMIN_A_W:
    case Mips::FMIN_D:
    case Mips::FMIN_W:
    case Mips::FMUL_D:
    case Mips::FMUL_W:
    case Mips::FSAF_D:
    case Mips::FSAF_W:
    case Mips::FSEQ_D:
    case Mips::FSEQ_W:
    case Mips::FSLE_D:
    case Mips::FSLE_W:
    case Mips::FSLT_D:
    case Mips::FSLT_W:
    case Mips::FSNE_D:
    case Mips::FSNE_W:
    case Mips::FSOR_D:
    case Mips::FSOR_W:
    case Mips::FSUB_D:
    case Mips::FSUB_W:
    case Mips::FSUEQ_D:
    case Mips::FSUEQ_W:
    case Mips::FSULE_D:
    case Mips::FSULE_W:
    case Mips::FSULT_D:
    case Mips::FSULT_W:
    case Mips::FSUNE_D:
    case Mips::FSUNE_W:
    case Mips::FSUN_D:
    case Mips::FSUN_W:
    case Mips::FTQ_H:
    case Mips::FTQ_W:
    case Mips::HADD_S_D:
    case Mips::HADD_S_H:
    case Mips::HADD_S_W:
    case Mips::HADD_U_D:
    case Mips::HADD_U_H:
    case Mips::HADD_U_W:
    case Mips::HSUB_S_D:
    case Mips::HSUB_S_H:
    case Mips::HSUB_S_W:
    case Mips::HSUB_U_D:
    case Mips::HSUB_U_H:
    case Mips::HSUB_U_W:
    case Mips::ILVEV_B:
    case Mips::ILVEV_D:
    case Mips::ILVEV_H:
    case Mips::ILVEV_W:
    case Mips::ILVL_B:
    case Mips::ILVL_D:
    case Mips::ILVL_H:
    case Mips::ILVL_W:
    case Mips::ILVOD_B:
    case Mips::ILVOD_D:
    case Mips::ILVOD_H:
    case Mips::ILVOD_W:
    case Mips::ILVR_B:
    case Mips::ILVR_D:
    case Mips::ILVR_H:
    case Mips::ILVR_W:
    case Mips::MAX_A_B:
    case Mips::MAX_A_D:
    case Mips::MAX_A_H:
    case Mips::MAX_A_W:
    case Mips::MAX_S_B:
    case Mips::MAX_S_D:
    case Mips::MAX_S_H:
    case Mips::MAX_S_W:
    case Mips::MAX_U_B:
    case Mips::MAX_U_D:
    case Mips::MAX_U_H:
    case Mips::MAX_U_W:
    case Mips::MIN_A_B:
    case Mips::MIN_A_D:
    case Mips::MIN_A_H:
    case Mips::MIN_A_W:
    case Mips::MIN_S_B:
    case Mips::MIN_S_D:
    case Mips::MIN_S_H:
    case Mips::MIN_S_W:
    case Mips::MIN_U_B:
    case Mips::MIN_U_D:
    case Mips::MIN_U_H:
    case Mips::MIN_U_W:
    case Mips::MOD_S_B:
    case Mips::MOD_S_D:
    case Mips::MOD_S_H:
    case Mips::MOD_S_W:
    case Mips::MOD_U_B:
    case Mips::MOD_U_D:
    case Mips::MOD_U_H:
    case Mips::MOD_U_W:
    case Mips::MULR_Q_H:
    case Mips::MULR_Q_W:
    case Mips::MULV_B:
    case Mips::MULV_D:
    case Mips::MULV_H:
    case Mips::MULV_W:
    case Mips::MUL_Q_H:
    case Mips::MUL_Q_W:
    case Mips::NOR_V:
    case Mips::OR_V:
    case Mips::PCKEV_B:
    case Mips::PCKEV_D:
    case Mips::PCKEV_H:
    case Mips::PCKEV_W:
    case Mips::PCKOD_B:
    case Mips::PCKOD_D:
    case Mips::PCKOD_H:
    case Mips::PCKOD_W:
    case Mips::SLL_B:
    case Mips::SLL_D:
    case Mips::SLL_H:
    case Mips::SLL_W:
    case Mips::SRAR_B:
    case Mips::SRAR_D:
    case Mips::SRAR_H:
    case Mips::SRAR_W:
    case Mips::SRA_B:
    case Mips::SRA_D:
    case Mips::SRA_H:
    case Mips::SRA_W:
    case Mips::SRLR_B:
    case Mips::SRLR_D:
    case Mips::SRLR_H:
    case Mips::SRLR_W:
    case Mips::SRL_B:
    case Mips::SRL_D:
    case Mips::SRL_H:
    case Mips::SRL_W:
    case Mips::SUBSUS_U_B:
    case Mips::SUBSUS_U_D:
    case Mips::SUBSUS_U_H:
    case Mips::SUBSUS_U_W:
    case Mips::SUBSUU_S_B:
    case Mips::SUBSUU_S_D:
    case Mips::SUBSUU_S_H:
    case Mips::SUBSUU_S_W:
    case Mips::SUBS_S_B:
    case Mips::SUBS_S_D:
    case Mips::SUBS_S_H:
    case Mips::SUBS_S_W:
    case Mips::SUBS_U_B:
    case Mips::SUBS_U_D:
    case Mips::SUBS_U_H:
    case Mips::SUBS_U_W:
    case Mips::SUBV_B:
    case Mips::SUBV_D:
    case Mips::SUBV_H:
    case Mips::SUBV_W:
    case Mips::XOR_V: {
      switch (OpNum) {
      case 2:
        // op: wt
        return 16;
      case 1:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::MADDF_D:
    case Mips::MADDF_S:
    case Mips::MSUBF_D:
    case Mips::MSUBF_S:
    case Mips::SEL_D:
    case Mips::SEL_S: {
      switch (OpNum) {
      case 3:
        // op: ft
        return 16;
      case 2:
        // op: fs
        return 11;
      case 0:
        // op: fd
        return 6;
      }
      break;
    }
    case Mips::MADD_D32_MM:
    case Mips::MADD_S_MM:
    case Mips::MSUB_D32_MM:
    case Mips::MSUB_S_MM:
    case Mips::NMADD_D32_MM:
    case Mips::NMADD_S_MM:
    case Mips::NMSUB_D32_MM:
    case Mips::NMSUB_S_MM: {
      switch (OpNum) {
      case 3:
        // op: ft
        return 21;
      case 2:
        // op: fs
        return 16;
      case 0:
        // op: fd
        return 11;
      case 1:
        // op: fr
        return 6;
      }
      break;
    }
    case Mips::MADDF_D_MMR6:
    case Mips::MADDF_S_MMR6:
    case Mips::MSUBF_D_MMR6:
    case Mips::MSUBF_S_MMR6:
    case Mips::SEL_D_MMR6:
    case Mips::SEL_S_MMR6: {
      switch (OpNum) {
      case 3:
        // op: ft
        return 21;
      case 2:
        // op: fs
        return 16;
      case 0:
        // op: fd
        return 11;
      }
      break;
    }
    case Mips::INSERT_B:
    case Mips::INSERT_D:
    case Mips::INSERT_H:
    case Mips::INSERT_W: {
      switch (OpNum) {
      case 3:
        // op: n
        return 16;
      case 2:
        // op: rs
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::SLDI_B:
    case Mips::SLDI_D:
    case Mips::SLDI_H:
    case Mips::SLDI_W: {
      switch (OpNum) {
      case 3:
        // op: n
        return 16;
      case 2:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::SLD_B:
    case Mips::SLD_D:
    case Mips::SLD_H:
    case Mips::SLD_W: {
      switch (OpNum) {
      case 3:
        // op: rt
        return 16;
      case 2:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::MOVEP_MMR6: {
      switch (OpNum) {
      case 3:
        // op: rt
        return 4;
      case 2:
        // op: rs
        return 0;
      }
      break;
    }
    case Mips::MOVEP_MM: {
      switch (OpNum) {
      case 3:
        // op: rt
        return 4;
      case 2:
        // op: rs
        return 1;
      }
      break;
    }
    case Mips::BMNZI_B:
    case Mips::BMZI_B:
    case Mips::BSELI_B: {
      switch (OpNum) {
      case 3:
        // op: u8
        return 16;
      case 2:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
    case Mips::BINSL_B:
    case Mips::BINSL_D:
    case Mips::BINSL_H:
    case Mips::BINSL_W:
    case Mips::BINSR_B:
    case Mips::BINSR_D:
    case Mips::BINSR_H:
    case Mips::BINSR_W:
    case Mips::BMNZ_V:
    case Mips::BMZ_V:
    case Mips::BSEL_V:
    case Mips::DPADD_S_D:
    case Mips::DPADD_S_H:
    case Mips::DPADD_S_W:
    case Mips::DPADD_U_D:
    case Mips::DPADD_U_H:
    case Mips::DPADD_U_W:
    case Mips::DPSUB_S_D:
    case Mips::DPSUB_S_H:
    case Mips::DPSUB_S_W:
    case Mips::DPSUB_U_D:
    case Mips::DPSUB_U_H:
    case Mips::DPSUB_U_W:
    case Mips::FMADD_D:
    case Mips::FMADD_W:
    case Mips::FMSUB_D:
    case Mips::FMSUB_W:
    case Mips::MADDR_Q_H:
    case Mips::MADDR_Q_W:
    case Mips::MADDV_B:
    case Mips::MADDV_D:
    case Mips::MADDV_H:
    case Mips::MADDV_W:
    case Mips::MADD_Q_H:
    case Mips::MADD_Q_W:
    case Mips::MSUBR_Q_H:
    case Mips::MSUBR_Q_W:
    case Mips::MSUBV_B:
    case Mips::MSUBV_D:
    case Mips::MSUBV_H:
    case Mips::MSUBV_W:
    case Mips::MSUB_Q_H:
    case Mips::MSUB_Q_W:
    case Mips::VSHF_B:
    case Mips::VSHF_D:
    case Mips::VSHF_H:
    case Mips::VSHF_W: {
      switch (OpNum) {
      case 3:
        // op: wt
        return 16;
      case 2:
        // op: ws
        return 11;
      case 0:
        // op: wd
        return 6;
      }
      break;
    }
  }
  std::string msg;
  raw_string_ostream Msg(msg);
  Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
  report_fatal_error(Msg.str().c_str());
}

#endif // GET_OPERAND_BIT_OFFSET