#ifdef GET_ASSEMBLER_HEADER
#undef GET_ASSEMBLER_HEADER
FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;
void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
const OperandVector &Operands,
const SmallBitVector &OptionalOperandsMask,
ArrayRef<unsigned> DefaultsOffset);
void convertToMapAndConstraints(unsigned Kind,
const OperandVector &Operands) override;
unsigned MatchInstructionImpl(const OperandVector &Operands,
MCInst &Inst,
uint64_t &ErrorInfo,
FeatureBitset &MissingFeatures,
bool matchingInlineAsm,
unsigned VariantID = 0);
unsigned MatchInstructionImpl(const OperandVector &Operands,
MCInst &Inst,
uint64_t &ErrorInfo,
bool matchingInlineAsm,
unsigned VariantID = 0) {
FeatureBitset MissingFeatures;
return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
matchingInlineAsm, VariantID);
}
ParseStatus MatchOperandParserImpl(
OperandVector &Operands,
StringRef Mnemonic,
bool ParseForAllFeatures = false);
ParseStatus tryCustomParseOperand(
OperandVector &Operands,
unsigned MCK);
#endif
#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
#undef GET_OPERAND_DIAGNOSTIC_TYPES
Match_InvalidBareSymbol,
Match_InvalidCLUIImm,
Match_InvalidCSRSystemRegister,
Match_InvalidCallSymbol,
Match_InvalidImmXLenLI,
Match_InvalidImmXLenLI_Restricted,
Match_InvalidImmZero,
Match_InvalidLoadFPImm,
Match_InvalidPseudoJumpSymbol,
Match_InvalidRTZArg,
Match_InvalidRegReg,
Match_InvalidRlist,
Match_InvalidRnumArg,
Match_InvalidSImm10Lsb0000NonZero,
Match_InvalidSImm12,
Match_InvalidSImm12Lsb0,
Match_InvalidSImm12Lsb00000,
Match_InvalidSImm13Lsb0,
Match_InvalidSImm21Lsb0JAL,
Match_InvalidSImm5,
Match_InvalidSImm5Plus1,
Match_InvalidSImm6,
Match_InvalidSImm6NonZero,
Match_InvalidSImm9Lsb0,
Match_InvalidStackAdj,
Match_InvalidTLSDESCCallSymbol,
Match_InvalidTPRelAddSymbol,
Match_InvalidUImm1,
Match_InvalidUImm10Lsb00NonZero,
Match_InvalidUImm16,
Match_InvalidUImm2,
Match_InvalidUImm20,
Match_InvalidUImm20AUIPC,
Match_InvalidUImm20LUI,
Match_InvalidUImm2Lsb0,
Match_InvalidUImm3,
Match_InvalidUImm32,
Match_InvalidUImm4,
Match_InvalidUImm5,
Match_InvalidUImm5Lsb0,
Match_InvalidUImm6,
Match_InvalidUImm6Lsb0,
Match_InvalidUImm7,
Match_InvalidUImm7Lsb00,
Match_InvalidUImm8,
Match_InvalidUImm8GE32,
Match_InvalidUImm8Lsb00,
Match_InvalidUImm8Lsb000,
Match_InvalidUImm9Lsb000,
Match_InvalidUImmLog2XLen,
Match_InvalidUImmLog2XLenNonZero,
Match_InvalidVMaskRegister,
Match_InvalidVTypeI,
END_OPERAND_DIAGNOSTIC_TYPES
#endif
#ifdef GET_REGISTER_MATCHER
#undef GET_REGISTER_MATCHER
enum SubtargetFeatureBits : uint8_t { … };
static MCRegister MatchRegisterName(StringRef Name) { … }
static MCRegister MatchRegisterAltName(StringRef Name) { … }
#endif
#ifdef GET_SUBTARGET_FEATURE_NAME
#undef GET_SUBTARGET_FEATURE_NAME
static const char *getSubtargetFeatureName(uint64_t Val) {
switch(Val) {
case Feature_HasStdExtZicbomBit: return "'Zicbom' (Cache-Block Management Instructions)";
case Feature_HasStdExtZicbopBit: return "'Zicbop' (Cache-Block Prefetch Instructions)";
case Feature_HasStdExtZicbozBit: return "'Zicboz' (Cache-Block Zero Instructions)";
case Feature_HasStdExtZicsrBit: return "'Zicsr' (CSRs)";
case Feature_HasStdExtZicondBit: return "'Zicond' (Integer Conditional Operations)";
case Feature_HasStdExtZifenceiBit: return "'Zifencei' (fence.i)";
case Feature_HasStdExtZihintpauseBit: return "'Zihintpause' (Pause Hint)";
case Feature_HasStdExtZihintntlBit: return "'Zihintntl' (Non-Temporal Locality Hints)";
case Feature_HasStdExtZimopBit: return "'Zimop' (May-Be-Operations)";
case Feature_HasStdExtZicfilpBit: return "'Zicfilp' (Landing pad)";
case Feature_NoStdExtZicfilpBit: return "";
case Feature_HasStdExtZicfissBit: return "'Zicfiss' (Shadow stack)";
case Feature_HasStdExtZmmulBit: return "'Zmmul' (Integer Multiplication)";
case Feature_HasStdExtMBit: return "'M' (Integer Multiplication and Division)";
case Feature_HasStdExtABit: return "'A' (Atomic Instructions)";
case Feature_HasStdExtZtsoBit: return "'Ztso' (Memory Model - Total Store Order)";
case Feature_HasStdExtAOrZaamoBit: return "'A' (Atomic Instructions) or 'Zaamo' (Atomic Memory Operations)";
case Feature_HasStdExtZabhaBit: return "'Zabha' (Byte and Halfword Atomic Memory Operations)";
case Feature_HasStdExtZacasBit: return "'Zacas' (Atomic Compare-And-Swap Instructions)";
case Feature_HasStdExtZalasrBit: return "'Zalasr' (Load-Acquire and Store-Release Instructions)";
case Feature_HasStdExtAOrZalrscBit: return "'A' (Atomic Instructions) or 'Zalrsc' (Load-Reserved/Store-Conditional)";
case Feature_HasStdExtZawrsBit: return "'Zawrs' (Wait on Reservation Set)";
case Feature_HasStdExtFBit: return "'F' (Single-Precision Floating-Point)";
case Feature_HasStdExtDBit: return "'D' (Double-Precision Floating-Point)";
case Feature_HasStdExtZfhminBit: return "'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal)";
case Feature_HasStdExtZfhBit: return "'Zfh' (Half-Precision Floating-Point)";
case Feature_HasStdExtZfbfminBit: return "'Zfbfmin' (Scalar BF16 Converts)";
case Feature_HasHalfFPLoadStoreMoveBit: return "'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts)";
case Feature_HasStdExtZfaBit: return "'Zfa' (Additional Floating-Point)";
case Feature_HasStdExtZfinxBit: return "'Zfinx' (Float in Integer)";
case Feature_HasStdExtFOrZfinxBit: return "'F' (Single-Precision Floating-Point) or 'Zfinx' (Float in Integer)";
case Feature_HasStdExtZdinxBit: return "'Zdinx' (Double in Integer)";
case Feature_HasStdExtZhinxminBit: return "'Zhinx' (Half Float in Integer) or 'Zhinxmin' (Half Float in Integer Minimal)";
case Feature_HasStdExtZhinxBit: return "'Zhinx' (Half Float in Integer)";
case Feature_HasStdExtCBit: return "'C' (Compressed Instructions)";
case Feature_HasRVCHintsBit: return "RVC Hint Instructions";
case Feature_HasStdExtCOrZcaBit: return "'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores)";
case Feature_HasStdExtZcbBit: return "'Zcb' (Compressed basic bit manipulation instructions)";
case Feature_HasStdExtCOrZcdBit: return "'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions)";
case Feature_HasStdExtZcmpBit: return "'Zcmp' (sequenced instructions for code-size reduction)";
case Feature_HasStdExtZcmtBit: return "'Zcmt' (table jump instructions for code-size reduction)";
case Feature_HasStdExtCOrZcfOrZceBit: return "'C' (Compressed Instructions) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions)";
case Feature_HasStdExtZcmopBit: return "'Zcmop' (Compressed May-Be-Operations)";
case Feature_HasStdExtZbaBit: return "'Zba' (Address Generation Instructions)";
case Feature_HasStdExtZbbBit: return "'Zbb' (Basic Bit-Manipulation)";
case Feature_NoStdExtZbbBit: return "";
case Feature_HasStdExtZbcBit: return "'Zbc' (Carry-Less Multiplication)";
case Feature_HasStdExtZbsBit: return "'Zbs' (Single-Bit Instructions)";
case Feature_HasStdExtZbkbBit: return "'Zbkb' (Bitmanip instructions for Cryptography)";
case Feature_HasStdExtZbkxBit: return "'Zbkx' (Crossbar permutation instructions)";
case Feature_HasStdExtZbbOrZbkbBit: return "'Zbb' (Basic Bit-Manipulation) or 'Zbkb' (Bitmanip instructions for Cryptography)";
case Feature_HasStdExtZbkcBit: return "'Zbkc' (Carry-less multiply instructions for Cryptography)";
case Feature_HasStdExtZbcOrZbkcBit: return "'Zbc' (Carry-Less Multiplication) or 'Zbkc' (Carry-less multiply instructions for Cryptography)";
case Feature_HasStdExtZkndBit: return "'Zknd' (NIST Suite: AES Decryption)";
case Feature_HasStdExtZkneBit: return "'Zkne' (NIST Suite: AES Encryption)";
case Feature_HasStdExtZkndOrZkneBit: return "'Zknd' (NIST Suite: AES Decryption) or 'Zkne' (NIST Suite: AES Encryption)";
case Feature_HasStdExtZknhBit: return "'Zknh' (NIST Suite: Hash Function Instructions)";
case Feature_HasStdExtZksedBit: return "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)";
case Feature_HasStdExtZkshBit: return "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)";
case Feature_HasStdExtZkrBit: return "'Zkr' (Entropy Source Extension)";
case Feature_HasStdExtZvfbfminBit: return "'Zvfbfmin' (Vector BF16 Converts)";
case Feature_HasStdExtZvfbfwmaBit: return "'Zvfbfwma' (Vector BF16 widening mul-add)";
case Feature_HasStdExtZfhOrZvfhBit: return "'Zfh' (Half-Precision Floating-Point) or 'Zvfh' (Vector Half-Precision Floating-Point)";
case Feature_HasStdExtZvkbBit: return "'Zvkb' (Vector Bit-manipulation used in Cryptography)";
case Feature_HasStdExtZvbbBit: return "'Zvbb' (Vector basic bit-manipulation instructions)";
case Feature_HasStdExtZvbcBit: return "'Zvbc' (Vector Carryless Multiplication)";
case Feature_HasStdExtZvbcOrZvbc32eBit: return "'Zvbc' or 'Zvbc32e' (Vector Carryless Multiplication)";
case Feature_HasStdExtZvkgBit: return "'Zvkg' (Vector GCM instructions for Cryptography)";
case Feature_HasStdExtZvkgsBit: return "'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)";
case Feature_HasStdExtZvknedBit: return "'Zvkned' (Vector AES Encryption & Decryption (Single Round))";
case Feature_HasStdExtZvknhaBit: return "'Zvknha' (Vector SHA-2 (SHA-256 only))";
case Feature_HasStdExtZvknhbBit: return "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))";
case Feature_HasStdExtZvknhaOrZvknhbBit: return "'Zvknha' or 'Zvknhb' (Vector SHA-2)";
case Feature_HasStdExtZvksedBit: return "'Zvksed' (SM4 Block Cipher Instructions)";
case Feature_HasStdExtZvkshBit: return "'Zvksh' (SM3 Hash Function Instructions)";
case Feature_HasVInstructionsBit: return "'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors)";
case Feature_HasVInstructionsI64Bit: return "'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors)";
case Feature_HasVInstructionsAnyFBit: return "'V' (Vector Extension for Application Processors), 'Zve32f' (Vector Extensions for Embedded Processors)";
case Feature_HasVInstructionsF16MinimalBit: return "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) or 'Zvfh' (Vector Half-Precision Floating-Point)";
case Feature_HasStdExtHBit: return "'H' (Hypervisor)";
case Feature_HasStdExtSvinvalBit: return "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)";
case Feature_HasStdExtSmctrOrSsctrBit: return "'Smctr' (Control Transfer Records Machine Level) or 'Ssctr' (Control Transfer Records Supervisor Level)";
case Feature_HasVendorXVentanaCondOpsBit: return "'XVentanaCondOps' (Ventana Conditional Ops)";
case Feature_HasVendorXTHeadBaBit: return "'XTHeadBa' (T-Head address calculation instructions)";
case Feature_HasVendorXTHeadBbBit: return "'XTHeadBb' (T-Head basic bit-manipulation instructions)";
case Feature_HasVendorXTHeadBsBit: return "'XTHeadBs' (T-Head single-bit instructions)";
case Feature_HasVendorXTHeadCondMovBit: return "'XTHeadCondMov' (T-Head conditional move instructions)";
case Feature_HasVendorXTHeadCmoBit: return "'XTHeadCmo' (T-Head cache management instructions)";
case Feature_HasVendorXTHeadFMemIdxBit: return "'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations)";
case Feature_HasVendorXTHeadMacBit: return "'XTHeadMac' (T-Head Multiply-Accumulate Instructions)";
case Feature_HasVendorXTHeadMemIdxBit: return "'XTHeadMemIdx' (T-Head Indexed Memory Operations)";
case Feature_HasVendorXTHeadMemPairBit: return "'XTHeadMemPair' (T-Head two-GPR Memory Operations)";
case Feature_HasVendorXTHeadSyncBit: return "'XTHeadSync' (T-Head multicore synchronization instructions)";
case Feature_HasVendorXTHeadVdotBit: return "'XTHeadVdot' (T-Head Vector Extensions for Dot)";
case Feature_HasVendorXSfvcpBit: return "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)";
case Feature_HasVendorXSfvqmaccdodBit: return "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))";
case Feature_HasVendorXSfvqmaccqoqBit: return "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))";
case Feature_HasVendorXSfvfwmaccqqqBit: return "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))";
case Feature_HasVendorXSfvfnrclipxfqfBit: return "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)";
case Feature_HasVendorXSiFivecdiscarddloneBit: return "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)";
case Feature_HasVendorXSiFivecflushdloneBit: return "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)";
case Feature_HasVendorXSfceaseBit: return "'XSfcease' (SiFive sf.cease Instruction)";
case Feature_HasVendorXCVelwBit: return "'XCVelw' (CORE-V Event Load Word)";
case Feature_HasVendorXCVbitmanipBit: return "'XCVbitmanip' (CORE-V Bit Manipulation)";
case Feature_HasVendorXCVmacBit: return "'XCVmac' (CORE-V Multiply-Accumulate)";
case Feature_HasVendorXCVmemBit: return "'XCVmem' (CORE-V Post-incrementing Load & Store)";
case Feature_HasVendorXCValuBit: return "'XCValu' (CORE-V ALU Operations)";
case Feature_HasVendorXCVsimdBit: return "'XCVsimd' (CORE-V SIMD ALU)";
case Feature_HasVendorXCVbiBit: return "'XCVbi' (CORE-V Immediate Branching)";
case Feature_HasVendorXwchcBit: return "'Xwchc' (WCH/QingKe additional compressed opcodes)";
case Feature_IsRV64Bit: return "RV64I Base Instruction Set";
case Feature_IsRV32Bit: return "RV32I Base Instruction Set";
default: return "(unknown)";
}
}
#endif
#ifdef GET_MATCHER_IMPLEMENTATION
#undef GET_MATCHER_IMPLEMENTATION
static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) {
switch (Mnemonic.size()) {
default: break;
case 4:
if (memcmp(Mnemonic.data()+0, "move", 4) != 0)
break;
Mnemonic = "mv";
return;
case 5:
if (memcmp(Mnemonic.data()+0, "scall", 5) != 0)
break;
Mnemonic = "ecall";
return;
case 6:
if (memcmp(Mnemonic.data()+0, "sbreak", 6) != 0)
break;
Mnemonic = "ebreak";
return;
case 7:
switch (Mnemonic[0]) {
default: break;
case 'c':
if (memcmp(Mnemonic.data()+1, "v.slet", 6) != 0)
break;
if (Features.test(Feature_HasVendorXCValuBit) && Features.test(Feature_IsRV32Bit))
Mnemonic = "cv.sle";
return;
case 'f':
if (memcmp(Mnemonic.data()+1, "mv.", 3) != 0)
break;
switch (Mnemonic[4]) {
default: break;
case 's':
if (memcmp(Mnemonic.data()+5, ".x", 2) != 0)
break;
if (Features.test(Feature_HasStdExtFBit))
Mnemonic = "fmv.w.x";
return;
case 'x':
if (memcmp(Mnemonic.data()+5, ".s", 2) != 0)
break;
if (Features.test(Feature_HasStdExtFBit))
Mnemonic = "fmv.x.w";
return;
}
break;
}
break;
case 8:
if (memcmp(Mnemonic.data()+0, "cv.sletu", 8) != 0)
break;
if (Features.test(Feature_HasVendorXCValuBit) && Features.test(Feature_IsRV32Bit))
Mnemonic = "cv.sleu";
return;
}
}
enum {
Tie0_1_1,
Tie0_2_2,
Tie0_3_3,
Tie1_3_3,
};
static const uint8_t TiedAsmOperandTable[][3] = {
{ 0, 1, 1 },
{ 0, 2, 2 },
{ 0, 3, 3 },
{ 1, 3, 3 },
};
namespace {
enum OperatorConversionKind {
CVT_Done,
CVT_Reg,
CVT_Tied,
CVT_95_addImmOperands,
CVT_95_addRegOperands,
CVT_imm_95_0,
CVT_95_Reg,
CVT_regX0,
CVT_regX5,
CVT_regX2,
CVT_regX3,
CVT_regX4,
CVT_95_addRlistOperands,
CVT_95_addSpimmOperands,
CVT_95_addCSRSystemRegisterOperands,
CVT_95_addRegRegOperands,
CVT_95_addFRMArgOperands_95_defaultFRMArgOp,
CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp,
CVT_95_addFRMArgOperands,
CVT_imm_95_15,
CVT_95_addFenceArgOperands,
CVT_95_addFPImmOperands,
CVT_imm_95_3,
CVT_imm_95_1,
CVT_imm_95_2,
CVT_regX1,
CVT_imm_95__MINUS_1,
CVT_imm_95_3072,
CVT_imm_95_3200,
CVT_imm_95_3074,
CVT_imm_95_3202,
CVT_imm_95_3073,
CVT_imm_95_3201,
CVT_95_addRegOperands_95_defaultMaskRegOp,
CVT_reg0,
CVT_95_addVTypeIOperands,
CVT_imm_95_255,
CVT_NUM_CONVERTERS
};
enum InstructionConversionKind {
Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_3__SImm13Lsb01_4,
Convert__AnyRegCOperand1_3__InsnCDirectiveOpcode1_0__UImm61_1__UImm21_2__AnyRegCOperand1_4,
Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__SImm9Lsb01_3,
Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__SImm61_3,
Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__UImm81_3,
Convert__InsnCDirectiveOpcode1_0__UImm31_1__SImm12Lsb01_2,
Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_4__imm_95_0,
Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_5__UImm51_3,
Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm41_1__AnyRegOperand1_3,
Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_4__imm_95_0,
Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_5__UImm51_3,
Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__UImm61_3,
Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_3__SImm121_4,
Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_4__imm_95_0,
Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_5__SImm121_3,
Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__SImm21Lsb0JAL1_2,
Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm71_2__AnyRegOperand1_4__AnyRegOperand1_5,
Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__AnyRegOperand1_5__AnyRegOperand1_6,
Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_4__imm_95_0,
Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_5__SImm121_3,
Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__UImm20LUI1_2,
Convert__Reg1_0__Reg1_1__Reg1_2,
Convert__Reg1_0__Reg1_1__SImm121_2,
Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3,
Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3,
Convert__Reg1_0__Reg1_1,
Convert__Reg1_0__Reg1_1__RnumArg1_2,
Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1,
Convert__Reg1_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__Reg1_1,
Convert__GPRPairRV321_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__GPRPairRV321_1,
Convert__GPRPairRV641_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__GPRPairRV641_1,
Convert__Reg1_0__UImm20AUIPC1_1,
Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2,
Convert__Reg1_0__Reg1_1__SImm13Lsb01_2,
Convert__Reg1_0__regX0__SImm13Lsb01_1,
Convert__Reg1_1__Reg1_0__SImm13Lsb01_2,
Convert__regX0__Reg1_0__SImm13Lsb01_1,
Convert__Reg1_0__Tie0_1_1__Reg1_1,
Convert__Reg1_0__Tie0_1_1__ImmZero1_1,
Convert__SImm6NonZero1_1,
Convert__Reg1_0__Tie0_1_1__SImm6NonZero1_1,
Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1,
Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2,
Convert__Reg1_0__Tie0_1_1__SImm61_1,
Convert__Reg1_0__SImm9Lsb01_1,
Convert_NoOperands,
Convert__Reg1_0__Reg1_2__imm_95_0,
Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1,
Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1,
Convert__Reg1_0__Reg1_3__UImm7Lsb001_1,
Convert__Reg1_0__Reg1_3__UImm8Lsb001_1,
Convert__SImm12Lsb01_0,
Convert__Reg1_0,
Convert__Reg1_0__Reg1_3__UImm21_1,
Convert__Reg1_0__Reg1_3__UImm2Lsb01_1,
Convert__Reg1_0__SImm61_1,
Convert__Reg1_0__CLUIImm1_1,
Convert__SImm6NonZero1_0,
Convert__Reg1_0__Tie0_1_1,
Convert__regX0__Tie0_1_1__regX5,
Convert__regX0__Tie0_1_1__regX2,
Convert__regX0__Tie0_1_1__regX3,
Convert__regX0__Tie0_1_1__regX4,
Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1,
Convert__CallSymbol1_0,
Convert__Reg1_0__CallSymbol1_1,
Convert__ZeroOffsetMemOpOperand1_0,
Convert__UImm8GE321_0,
Convert__UImm51_0,
Convert__Rlist1_0__StackAdj1_1,
Convert__Rlist1_0__NegStackAdj1_1,
Convert__regX0__CSRSystemRegister1_0__Reg1_1,
Convert__regX0__CSRSystemRegister1_0__UImm51_1,
Convert__Reg1_0__CSRSystemRegister1_1__regX0,
Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2,
Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2,
Convert__Reg1_0__Reg1_1__SImm61_2,
Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3,
Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2,
Convert__Reg1_0__Reg1_1__UImm61_2,
Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3,
Convert__Reg1_0__SImm51_1__SImm13Lsb01_2,
Convert__Reg1_0__Reg1_1__UImm21_2__UImm51_3,
Convert__Reg1_0__Reg1_1__UImm51_2,
Convert__Reg1_0__Reg1_3__SImm121_1,
Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__UImm51_3,
Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2,
Convert__Reg1_0__RegReg2_1,
Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4,
Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm121_4,
Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3,
Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0,
Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4,
Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm121_4,
Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2,
Convert__Reg1_0__Reg1_1__UImm31_2,
Convert__Reg1_0__Reg1_1__UImm41_2,
Convert__Reg1_0__Reg1_1__Reg1_1,
Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1,
Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1,
Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1,
Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1,
Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3,
Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3,
Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3,
Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3,
Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3,
Convert__Reg1_0__GPRF64AsFPR1_1,
Convert__Reg1_0__GPRPairAsFPR1_1,
Convert__Reg1_0__GPRAsFPR161_1,
Convert__Reg1_0__GPRAsFPR321_1,
Convert__Reg1_0__Reg1_1__FRMArg1_2,
Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2,
Convert__GPRF64AsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2,
Convert__GPRPairAsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2,
Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2,
Convert__GPRF64AsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2,
Convert__GPRPairAsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2,
Convert__GPRF64AsFPR1_0__Reg1_1__FRMArgLegacy1_2,
Convert__GPRPairAsFPR1_0__Reg1_1__FRMArgLegacy1_2,
Convert__GPRAsFPR161_0__GPRF64AsFPR1_1__FRMArg1_2,
Convert__GPRAsFPR161_0__GPRPairAsFPR1_1__FRMArg1_2,
Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2,
Convert__GPRAsFPR161_0__GPRAsFPR321_1__FRMArg1_2,
Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2,
Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2,
Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2,
Convert__GPRAsFPR321_0__GPRF64AsFPR1_1__FRMArg1_2,
Convert__GPRAsFPR321_0__GPRPairAsFPR1_1__FRMArg1_2,
Convert__GPRAsFPR321_0__GPRAsFPR161_1__FRMArgLegacy1_2,
Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2,
Convert__Reg1_0__GPRPairAsFPR1_1__FRMArg1_2,
Convert__Reg1_0__Reg1_1__RTZArg1_2,
Convert__imm_95_15__imm_95_15,
Convert__FenceArg1_0__FenceArg1_1,
Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2,
Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2,
Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2,
Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2,
Convert__Reg1_0__Reg1_2__Reg1_1,
Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1,
Convert__Reg1_0__GPRPairAsFPR1_2__GPRPairAsFPR1_1,
Convert__Reg1_0__GPRAsFPR161_2__GPRAsFPR161_1,
Convert__Reg1_0__GPRAsFPR321_2__GPRAsFPR321_1,
Convert__Reg1_2__Reg1_0__BareSymbol1_1,
Convert__Reg1_0__LoadFPImm1_1,
Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4,
Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4,
Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4,
Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4,
Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4,
Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2,
Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2,
Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2,
Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2,
Convert__Reg1_0__imm_95_3__regX0,
Convert__Reg1_0__imm_95_1__regX0,
Convert__Reg1_0__imm_95_2__regX0,
Convert__regX0__imm_95_3__Reg1_0,
Convert__Reg1_0__imm_95_3__Reg1_1,
Convert__regX0__imm_95_1__Reg1_0,
Convert__Reg1_0__imm_95_1__Reg1_1,
Convert__regX0__imm_95_1__UImm51_0,
Convert__Reg1_0__imm_95_1__UImm51_1,
Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2,
Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__FRMArg1_2,
Convert__GPRAsFPR161_0__GPRAsFPR161_1__FRMArg1_2,
Convert__GPRAsFPR321_0__GPRAsFPR321_1__FRMArg1_2,
Convert__regX0__imm_95_2__Reg1_0,
Convert__Reg1_0__imm_95_2__Reg1_1,
Convert__regX0__imm_95_2__UImm51_0,
Convert__Reg1_0__imm_95_2__UImm51_1,
Convert__regX0__regX0,
Convert__Reg1_0__regX0,
Convert__Reg1_0__ZeroOffsetMemOpOperand1_1,
Convert__regX0__SImm21Lsb0JAL1_0,
Convert__regX1__SImm21Lsb0JAL1_0,
Convert__Reg1_0__SImm21Lsb0JAL1_1,
Convert__regX1__Reg1_0__imm_95_0,
Convert__Reg1_0__Reg1_1__imm_95_0,
Convert__regX1__Reg1_0__SImm121_1,
Convert__regX1__Reg1_1__imm_95_0,
Convert__regX1__Reg1_2__SImm121_0,
Convert__Reg1_0__Reg1_3__SImm121_1__TLSDESCCallSymbol1_5,
Convert__regX0__Reg1_0__imm_95_0,
Convert__regX0__Reg1_0__SImm121_1,
Convert__regX0__Reg1_1__imm_95_0,
Convert__regX0__Reg1_2__SImm121_0,
Convert__Reg1_1__PseudoJumpSymbol1_0,
Convert__Reg1_0__BareSymbol1_1,
Convert__Reg1_0__ImmXLenLI_Restricted1_1,
Convert__Reg1_0__regX0__SImm121_1,
Convert__Reg1_0__ImmXLenLI1_1,
Convert__regX0__UImm201_0,
Convert__Reg1_0__UImm20LUI1_1,
Convert__Reg1_0__regX0__Reg1_1,
Convert__regX0__regX0__imm_95_0,
Convert__Reg1_0__Reg1_1__imm_95__MINUS_1,
Convert__regX0__regX0__regX5,
Convert__regX0__regX0__regX2,
Convert__regX0__regX0__regX3,
Convert__regX0__regX0__regX4,
Convert__imm_95_1__imm_95_0,
Convert__Reg1_2__SImm12Lsb000001_0,
Convert__Reg1_0__Reg1_3__UImm51_1,
Convert__Reg1_0__Reg1_3__UImm41_1,
Convert__Reg1_0__Reg1_3__UImm6Lsb01_1,
Convert__Reg1_0__Reg1_3__UImm5Lsb01_1,
Convert__Reg1_0__imm_95_3072__regX0,
Convert__Reg1_0__imm_95_3200__regX0,
Convert__Reg1_0__imm_95_3074__regX0,
Convert__Reg1_0__imm_95_3202__regX0,
Convert__Reg1_0__imm_95_3073__regX0,
Convert__Reg1_0__imm_95_3201__regX0,
Convert__regX0__regX1__imm_95_0,
Convert__ZeroOffsetMemOpOperand1_1__Reg1_0,
Convert__Reg1_0__Reg1_1__imm_95_1,
Convert__regX0,
Convert__UImm11_0__UImm51_1__Reg1_2__Reg1_3,
Convert__UImm11_0__Reg1_1__Reg1_2__Reg1_3,
Convert__UImm21_0__UImm51_1__UImm51_2__SImm51_3,
Convert__UImm21_0__UImm51_1__Reg1_2__SImm51_3,
Convert__UImm21_0__Reg1_1__Reg1_2__SImm51_3,
Convert__Reg1_1__UImm11_0__Reg1_2__Reg1_3,
Convert__Reg1_1__UImm11_0__Tie0_2_2__Reg1_2__Reg1_3,
Convert__Reg1_2__UImm21_0__UImm51_1__SImm51_3,
Convert__Reg1_1__UImm21_0__Reg1_2__SImm51_3,
Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__SImm51_3,
Convert__Reg1_1__UImm21_0__Reg1_2__Reg1_3,
Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3,
Convert__Reg1_2__UImm21_0__UImm51_1__Reg1_3,
Convert__UImm21_0__UImm51_1__Reg1_2__Reg1_3,
Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3,
Convert__UImm21_0__UImm51_1__UImm51_2__Reg1_3,
Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3,
Convert__Reg1_0__Reg1_1__regX0,
Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3,
Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5,
Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__UImm71_6,
Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5,
Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3,
Convert__Reg1_0__Reg1_1__SImm51_2__imm_95_0,
Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3,
Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2,
Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2,
Convert__Reg1_0__Reg1_1__Reg1_1__reg0,
Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2,
Convert__Reg1_0__RVVMaskRegOpOperand1_1,
Convert__Reg1_0__Reg1_2,
Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2,
Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3,
Convert__Reg1_0__Reg1_1__SImm51_2,
Convert__Reg1_0__Reg1_0__Reg1_0,
Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3,
Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3,
Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3,
Convert__Reg1_0__SImm51_1,
Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3,
Convert__Reg1_0__Reg1_1__regX0__reg0,
Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2,
Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__reg0,
Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__RVVMaskRegOpOperand1_2,
Convert__Reg1_0__Reg1_1__UImm61_2__RVVMaskRegOpOperand1_3,
Convert__Reg1_0__UImm51_1__VTypeI101_2,
Convert__Reg1_0__Reg1_1__VTypeI111_2,
Convert__Reg1_0__Reg1_1__imm_95_255,
CVT_NUM_SIGNATURES
};
}
static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][15] = {
{ CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
{ CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 5, CVT_Done },
{ CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
{ CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
{ CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 4, CVT_Done },
{ CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
{ CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
{ CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
{ CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 3, CVT_Done },
{ CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_Done },
{ CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_95_addRegOperands, 7, CVT_Done },
{ CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
{ CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_Reg, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 3, CVT_95_Reg, 2, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_Done },
{ CVT_regX0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_addImmOperands, 1, CVT_Done },
{ CVT_95_Reg, 1, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_addImmOperands, 1, CVT_Done },
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
{ CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX5, 0, CVT_Done },
{ CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX2, 0, CVT_Done },
{ CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX3, 0, CVT_Done },
{ CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX4, 0, CVT_Done },
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_addImmOperands, 1, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_Done },
{ CVT_95_addImmOperands, 1, CVT_Done },
{ CVT_95_addImmOperands, 1, CVT_Done },
{ CVT_95_addRlistOperands, 1, CVT_95_addSpimmOperands, 2, CVT_Done },
{ CVT_95_addRlistOperands, 1, CVT_95_addSpimmOperands, 2, CVT_Done },
{ CVT_regX0, 0, CVT_95_addCSRSystemRegisterOperands, 1, CVT_95_Reg, 2, CVT_Done },
{ CVT_regX0, 0, CVT_95_addCSRSystemRegisterOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_regX0, 0, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_95_Reg, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegRegOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie1_3_3, CVT_95_Reg, 5, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie1_3_3, CVT_95_addImmOperands, 5, CVT_Done },
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
{ CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
{ CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_Done },
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 4, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp, 3, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands, 3, CVT_Done },
{ CVT_imm_95_15, 0, CVT_imm_95_15, 0, CVT_Done },
{ CVT_95_addFenceArgOperands, 1, CVT_95_addFenceArgOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
{ CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addFPImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 5, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_imm_95_3, 0, CVT_regX0, 0, CVT_Done },
{ CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_regX0, 0, CVT_Done },
{ CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_regX0, 0, CVT_Done },
{ CVT_regX0, 0, CVT_imm_95_3, 0, CVT_95_Reg, 1, CVT_Done },
{ CVT_95_Reg, 1, CVT_imm_95_3, 0, CVT_95_Reg, 2, CVT_Done },
{ CVT_regX0, 0, CVT_imm_95_1, 0, CVT_95_Reg, 1, CVT_Done },
{ CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_95_Reg, 2, CVT_Done },
{ CVT_regX0, 0, CVT_imm_95_1, 0, CVT_95_addImmOperands, 1, CVT_Done },
{ CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands_95_defaultFRMArgOp, 3, CVT_Done },
{ CVT_regX0, 0, CVT_imm_95_2, 0, CVT_95_Reg, 1, CVT_Done },
{ CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_95_Reg, 2, CVT_Done },
{ CVT_regX0, 0, CVT_imm_95_2, 0, CVT_95_addImmOperands, 1, CVT_Done },
{ CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_regX0, 0, CVT_regX0, 0, CVT_Done },
{ CVT_95_Reg, 1, CVT_regX0, 0, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
{ CVT_regX0, 0, CVT_95_addImmOperands, 1, CVT_Done },
{ CVT_regX1, 0, CVT_95_addImmOperands, 1, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_regX1, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
{ CVT_regX1, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_regX1, 0, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
{ CVT_regX1, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 6, CVT_Done },
{ CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
{ CVT_regX0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_regX0, 0, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
{ CVT_regX0, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
{ CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_regX0, 0, CVT_95_addImmOperands, 1, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_Reg, 2, CVT_Done },
{ CVT_regX0, 0, CVT_regX0, 0, CVT_imm_95_0, 0, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_Done },
{ CVT_regX0, 0, CVT_regX0, 0, CVT_regX5, 0, CVT_Done },
{ CVT_regX0, 0, CVT_regX0, 0, CVT_regX2, 0, CVT_Done },
{ CVT_regX0, 0, CVT_regX0, 0, CVT_regX3, 0, CVT_Done },
{ CVT_regX0, 0, CVT_regX0, 0, CVT_regX4, 0, CVT_Done },
{ CVT_imm_95_1, 0, CVT_imm_95_0, 0, CVT_Done },
{ CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_imm_95_3072, 0, CVT_regX0, 0, CVT_Done },
{ CVT_95_Reg, 1, CVT_imm_95_3200, 0, CVT_regX0, 0, CVT_Done },
{ CVT_95_Reg, 1, CVT_imm_95_3074, 0, CVT_regX0, 0, CVT_Done },
{ CVT_95_Reg, 1, CVT_imm_95_3202, 0, CVT_regX0, 0, CVT_Done },
{ CVT_95_Reg, 1, CVT_imm_95_3073, 0, CVT_regX0, 0, CVT_Done },
{ CVT_95_Reg, 1, CVT_imm_95_3201, 0, CVT_regX0, 0, CVT_Done },
{ CVT_regX0, 0, CVT_regX1, 0, CVT_imm_95_0, 0, CVT_Done },
{ CVT_95_addRegOperands, 2, CVT_95_Reg, 1, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_1, 0, CVT_Done },
{ CVT_regX0, 0, CVT_Done },
{ CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
{ CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
{ CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
{ CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
{ CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
{ CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
{ CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 4, CVT_Done },
{ CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
{ CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
{ CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie1_3_3, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
{ CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_reg0, 0, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegOperands_95_defaultMaskRegOp, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_reg0, 0, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_reg0, 0, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addVTypeIOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addVTypeIOperands, 3, CVT_Done },
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_255, 0, CVT_Done },
};
void RISCVAsmParser::
convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
const OperandVector &Operands,
const SmallBitVector &OptionalOperandsMask,
ArrayRef<unsigned> DefaultsOffset) {
assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
const uint8_t *Converter = ConversionTable[Kind];
Inst.setOpcode(Opcode);
for (const uint8_t *p = Converter; *p; p += 2) {
unsigned OpIdx = *(p + 1) - DefaultsOffset[*(p + 1)];
switch (*p) {
default: llvm_unreachable("invalid conversion entry!");
case CVT_Reg:
static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
break;
case CVT_Tied: {
assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) -
std::begin(TiedAsmOperandTable)) &&
"Tied operand not found");
unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0];
if (TiedResOpnd != (uint8_t)-1)
Inst.addOperand(Inst.getOperand(TiedResOpnd));
break;
}
case CVT_95_addImmOperands:
static_cast<RISCVOperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
break;
case CVT_95_addRegOperands:
static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
break;
case CVT_imm_95_0:
Inst.addOperand(MCOperand::createImm(0));
break;
case CVT_95_Reg:
static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
break;
case CVT_regX0:
Inst.addOperand(MCOperand::createReg(RISCV::X0));
break;
case CVT_regX5:
Inst.addOperand(MCOperand::createReg(RISCV::X5));
break;
case CVT_regX2:
Inst.addOperand(MCOperand::createReg(RISCV::X2));
break;
case CVT_regX3:
Inst.addOperand(MCOperand::createReg(RISCV::X3));
break;
case CVT_regX4:
Inst.addOperand(MCOperand::createReg(RISCV::X4));
break;
case CVT_95_addRlistOperands:
static_cast<RISCVOperand &>(*Operands[OpIdx]).addRlistOperands(Inst, 1);
break;
case CVT_95_addSpimmOperands:
static_cast<RISCVOperand &>(*Operands[OpIdx]).addSpimmOperands(Inst, 1);
break;
case CVT_95_addCSRSystemRegisterOperands:
static_cast<RISCVOperand &>(*Operands[OpIdx]).addCSRSystemRegisterOperands(Inst, 1);
break;
case CVT_95_addRegRegOperands:
static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegRegOperands(Inst, 2);
break;
case CVT_95_addFRMArgOperands_95_defaultFRMArgOp:
if (OptionalOperandsMask[*(p + 1) - 1]) {
defaultFRMArgOp()->addFRMArgOperands(Inst, 1);
} else {
static_cast<RISCVOperand &>(*Operands[OpIdx]).addFRMArgOperands(Inst, 1);
}
break;
case CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp:
if (OptionalOperandsMask[*(p + 1) - 1]) {
defaultFRMArgLegacyOp()->addFRMArgOperands(Inst, 1);
} else {
static_cast<RISCVOperand &>(*Operands[OpIdx]).addFRMArgOperands(Inst, 1);
}
break;
case CVT_95_addFRMArgOperands:
static_cast<RISCVOperand &>(*Operands[OpIdx]).addFRMArgOperands(Inst, 1);
break;
case CVT_imm_95_15:
Inst.addOperand(MCOperand::createImm(15));
break;
case CVT_95_addFenceArgOperands:
static_cast<RISCVOperand &>(*Operands[OpIdx]).addFenceArgOperands(Inst, 1);
break;
case CVT_95_addFPImmOperands:
static_cast<RISCVOperand &>(*Operands[OpIdx]).addFPImmOperands(Inst, 1);
break;
case CVT_imm_95_3:
Inst.addOperand(MCOperand::createImm(3));
break;
case CVT_imm_95_1:
Inst.addOperand(MCOperand::createImm(1));
break;
case CVT_imm_95_2:
Inst.addOperand(MCOperand::createImm(2));
break;
case CVT_regX1:
Inst.addOperand(MCOperand::createReg(RISCV::X1));
break;
case CVT_imm_95__MINUS_1:
Inst.addOperand(MCOperand::createImm(-1));
break;
case CVT_imm_95_3072:
Inst.addOperand(MCOperand::createImm(3072));
break;
case CVT_imm_95_3200:
Inst.addOperand(MCOperand::createImm(3200));
break;
case CVT_imm_95_3074:
Inst.addOperand(MCOperand::createImm(3074));
break;
case CVT_imm_95_3202:
Inst.addOperand(MCOperand::createImm(3202));
break;
case CVT_imm_95_3073:
Inst.addOperand(MCOperand::createImm(3073));
break;
case CVT_imm_95_3201:
Inst.addOperand(MCOperand::createImm(3201));
break;
case CVT_95_addRegOperands_95_defaultMaskRegOp:
if (OptionalOperandsMask[*(p + 1) - 1]) {
defaultMaskRegOp()->addRegOperands(Inst, 1);
} else {
static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
}
break;
case CVT_reg0:
Inst.addOperand(MCOperand::createReg(0));
break;
case CVT_95_addVTypeIOperands:
static_cast<RISCVOperand &>(*Operands[OpIdx]).addVTypeIOperands(Inst, 1);
break;
case CVT_imm_95_255:
Inst.addOperand(MCOperand::createImm(255));
break;
}
}
}
void RISCVAsmParser::
convertToMapAndConstraints(unsigned Kind,
const OperandVector &Operands) {
assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
unsigned NumMCOperands = 0;
const uint8_t *Converter = ConversionTable[Kind];
for (const uint8_t *p = Converter; *p; p += 2) {
switch (*p) {
default: llvm_unreachable("invalid conversion entry!");
case CVT_Reg:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("r");
++NumMCOperands;
break;
case CVT_Tied:
++NumMCOperands;
break;
case CVT_95_addImmOperands:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
NumMCOperands += 1;
break;
case CVT_95_addRegOperands:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
NumMCOperands += 1;
break;
case CVT_imm_95_0:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_95_Reg:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("r");
NumMCOperands += 1;
break;
case CVT_regX0:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
++NumMCOperands;
break;
case CVT_regX5:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
++NumMCOperands;
break;
case CVT_regX2:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
++NumMCOperands;
break;
case CVT_regX3:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
++NumMCOperands;
break;
case CVT_regX4:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
++NumMCOperands;
break;
case CVT_95_addRlistOperands:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
NumMCOperands += 1;
break;
case CVT_95_addSpimmOperands:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
NumMCOperands += 1;
break;
case CVT_95_addCSRSystemRegisterOperands:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
NumMCOperands += 1;
break;
case CVT_95_addRegRegOperands:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
NumMCOperands += 2;
break;
case CVT_95_addFRMArgOperands_95_defaultFRMArgOp:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
NumMCOperands += 1;
break;
case CVT_95_addFRMArgOperands_95_defaultFRMArgLegacyOp:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
NumMCOperands += 1;
break;
case CVT_95_addFRMArgOperands:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
NumMCOperands += 1;
break;
case CVT_imm_95_15:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_95_addFenceArgOperands:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
NumMCOperands += 1;
break;
case CVT_95_addFPImmOperands:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
NumMCOperands += 1;
break;
case CVT_imm_95_3:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_imm_95_1:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_imm_95_2:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_regX1:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
++NumMCOperands;
break;
case CVT_imm_95__MINUS_1:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_imm_95_3072:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_imm_95_3200:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_imm_95_3074:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_imm_95_3202:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_imm_95_3073:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_imm_95_3201:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_95_addRegOperands_95_defaultMaskRegOp:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
NumMCOperands += 1;
break;
case CVT_reg0:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
++NumMCOperands;
break;
case CVT_95_addVTypeIOperands:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
NumMCOperands += 1;
break;
case CVT_imm_95_255:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
}
}
}
namespace {
enum MatchClassKind {
InvalidMatchClass = 0,
OptionalMatchClass = 1,
MCK__40_,
MCK__41_,
MCK_LAST_TOKEN = MCK__41_,
MCK_Reg89,
MCK_Reg86,
MCK_Reg83,
MCK_Reg80,
MCK_Reg77,
MCK_Reg74,
MCK_Reg71,
MCK_Reg68,
MCK_Reg65,
MCK_Reg62,
MCK_Reg59,
MCK_Reg50,
MCK_Reg47,
MCK_Reg45,
MCK_Reg43,
MCK_Reg41,
MCK_Reg37,
MCK_Reg34,
MCK_Reg31,
MCK_GPRX0,
MCK_GPRX1,
MCK_GPRX5,
MCK_GPRX7,
MCK_SP,
MCK_VMV0,
MCK_anonymous_8771,
MCK_Reg19,
MCK_GPRX1X5,
MCK_Reg54,
MCK_VCSR,
MCK_VRM8NoV0,
MCK_Reg53,
MCK_Reg51,
MCK_VRM8,
MCK_Reg55,
MCK_Reg22,
MCK_VRN2M4NoV0,
MCK_Reg49,
MCK_VRM4NoV0,
MCK_VRN2M4,
MCK_FPR32C,
MCK_FPR64C,
MCK_GPRC,
MCK_GPRF16C,
MCK_GPRF32C,
MCK_SR07,
MCK_VRM4,
MCK_Reg52,
MCK_VRN4M2NoV0,
MCK_Reg48,
MCK_GPRTCNonX7,
MCK_VRN3M2NoV0,
MCK_VRN4M2,
MCK_Reg46,
MCK_GPRTC,
MCK_VRN2M2NoV0,
MCK_VRN3M2,
MCK_Reg44,
MCK_VRM2NoV0,
MCK_VRN2M2,
MCK_GPRPair,
MCK_VRM2,
MCK_VRN8M1NoV0,
MCK_GPRJALRNonX7,
MCK_VRN7M1NoV0,
MCK_VRN8M1,
MCK_GPRJALR,
MCK_VRN6M1NoV0,
MCK_VRN7M1,
MCK_VRN5M1NoV0,
MCK_VRN6M1,
MCK_VRN4M1NoV0,
MCK_VRN5M1,
MCK_VRN3M1NoV0,
MCK_VRN4M1,
MCK_GPRNoX0X2,
MCK_VRN2M1NoV0,
MCK_VRN3M1,
MCK_GPRF32NoX0,
MCK_GPRNoX0,
MCK_VRN2M1,
MCK_VRNoV0,
MCK_FPR16,
MCK_FPR32,
MCK_FPR64,
MCK_GPR,
MCK_GPRF16,
MCK_GPRF32,
MCK_VM,
MCK_GPRAll,
MCK_LAST_REGISTER = MCK_GPRAll,
MCK_AnyRegCOperand,
MCK_AnyRegOperand,
MCK_BareSymbol,
MCK_CLUIImm,
MCK_CSRSystemRegister,
MCK_RegReg,
MCK_CallSymbol,
MCK_FRMArg,
MCK_FRMArgLegacy,
MCK_FenceArg,
MCK_GPRAsFPR16,
MCK_GPRAsFPR32,
MCK_GPRF64AsFPR,
MCK_GPRPairAsFPR,
MCK_GPRPairRV32,
MCK_GPRPairRV64,
MCK_Imm,
MCK_ImmZero,
MCK_InsnCDirectiveOpcode,
MCK_InsnDirectiveOpcode,
MCK_LoadFPImm,
MCK_NegStackAdj,
MCK_PseudoJumpSymbol,
MCK_RTZArg,
MCK_Rlist,
MCK_RnumArg,
MCK_SImm5Plus1,
MCK_SImm21Lsb0JAL,
MCK_StackAdj,
MCK_TLSDESCCallSymbol,
MCK_TPRelAddSymbol,
MCK_UImmLog2XLen,
MCK_UImmLog2XLenNonZero,
MCK_RVVMaskRegOpOperand,
MCK_ZeroOffsetMemOpOperand,
MCK_VTypeI10,
MCK_VTypeI11,
MCK_SImm5,
MCK_SImm6,
MCK_SImm6NonZero,
MCK_UImm7Lsb00,
MCK_UImm8Lsb00,
MCK_UImm8Lsb000,
MCK_SImm9Lsb0,
MCK_UImm9Lsb000,
MCK_UImm10Lsb00NonZero,
MCK_SImm10Lsb0000NonZero,
MCK_SImm12Lsb0,
MCK_UImm2Lsb0,
MCK_UImm8GE32,
MCK_SImm12Lsb00000,
MCK_UImm5Lsb0,
MCK_UImm6Lsb0,
MCK_UImm1,
MCK_UImm2,
MCK_UImm3,
MCK_UImm4,
MCK_UImm5,
MCK_UImm6,
MCK_UImm7,
MCK_UImm8,
MCK_UImm16,
MCK_UImm32,
MCK_SImm12,
MCK_SImm13Lsb0,
MCK_UImm20LUI,
MCK_UImm20AUIPC,
MCK_UImm20,
MCK_ImmXLenLI,
MCK_ImmXLenLI_Restricted,
NumMatchClassKinds
};
}
static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
return MCTargetAsmParser::Match_InvalidOperand;
}
static MatchClassKind matchTokenString(StringRef Name) {
switch (Name.size()) {
default: break;
case 1:
switch (Name[0]) {
default: break;
case '(':
return MCK__40_;
case ')':
return MCK__41_;
}
break;
}
return InvalidMatchClass;
}
static bool isSubclass(MatchClassKind A, MatchClassKind B) {
if (A == B)
return true;
switch (A) {
default:
return false;
case MCK_Reg89:
return B == MCK_VRN8M1;
case MCK_Reg86:
return B == MCK_VRN7M1;
case MCK_Reg83:
return B == MCK_VRN6M1;
case MCK_Reg80:
return B == MCK_VRN5M1;
case MCK_Reg77:
return B == MCK_VRN4M2;
case MCK_Reg74:
return B == MCK_VRN4M1;
case MCK_Reg71:
return B == MCK_VRN3M2;
case MCK_Reg68:
return B == MCK_VRN3M1;
case MCK_Reg65:
return B == MCK_VRN2M4;
case MCK_Reg62:
return B == MCK_VRN2M2;
case MCK_Reg59:
return B == MCK_VRN2M1;
case MCK_Reg50:
switch (B) {
default: return false;
case MCK_Reg53: return true;
case MCK_Reg51: return true;
case MCK_Reg52: return true;
case MCK_Reg48: return true;
case MCK_Reg46: return true;
case MCK_Reg44: return true;
case MCK_GPRPair: return true;
}
case MCK_Reg47:
switch (B) {
default: return false;
case MCK_Reg49: return true;
case MCK_Reg48: return true;
case MCK_Reg46: return true;
case MCK_Reg44: return true;
case MCK_GPRPair: return true;
}
case MCK_Reg45:
switch (B) {
default: return false;
case MCK_Reg46: return true;
case MCK_Reg44: return true;
case MCK_GPRPair: return true;
}
case MCK_Reg43:
switch (B) {
default: return false;
case MCK_Reg44: return true;
case MCK_GPRPair: return true;
}
case MCK_Reg41:
return B == MCK_GPRPair;
case MCK_Reg37:
return B == MCK_VRM8;
case MCK_Reg34:
return B == MCK_VRM4;
case MCK_Reg31:
return B == MCK_VRM2;
case MCK_GPRX0:
switch (B) {
default: return false;
case MCK_GPR: return true;
case MCK_GPRAll: return true;
}
case MCK_GPRX1:
switch (B) {
default: return false;
case MCK_GPRX1X5: return true;
case MCK_GPRNoX0X2: return true;
case MCK_GPRNoX0: return true;
case MCK_GPR: return true;
case MCK_GPRAll: return true;
}
case MCK_GPRX5:
switch (B) {
default: return false;
case MCK_GPRX1X5: return true;
case MCK_GPRNoX0X2: return true;
case MCK_GPRNoX0: return true;
case MCK_GPR: return true;
case MCK_GPRAll: return true;
}
case MCK_GPRX7:
switch (B) {
default: return false;
case MCK_GPRTC: return true;
case MCK_GPRJALR: return true;
case MCK_GPRNoX0X2: return true;
case MCK_GPRNoX0: return true;
case MCK_GPR: return true;
case MCK_GPRAll: return true;
}
case MCK_SP:
switch (B) {
default: return false;
case MCK_GPRNoX0: return true;
case MCK_GPR: return true;
case MCK_GPRAll: return true;
}
case MCK_VMV0:
return B == MCK_VM;
case MCK_Reg19:
switch (B) {
default: return false;
case MCK_GPRC: return true;
case MCK_SR07: return true;
case MCK_GPRJALRNonX7: return true;
case MCK_GPRJALR: return true;
case MCK_GPRNoX0X2: return true;
case MCK_GPRNoX0: return true;
case MCK_GPR: return true;
case MCK_GPRAll: return true;
}
case MCK_GPRX1X5:
switch (B) {
default: return false;
case MCK_GPRNoX0X2: return true;
case MCK_GPRNoX0: return true;
case MCK_GPR: return true;
case MCK_GPRAll: return true;
}
case MCK_Reg54:
switch (B) {
default: return false;
case MCK_Reg51: return true;
case MCK_Reg55: return true;
case MCK_Reg49: return true;
case MCK_Reg52: return true;
case MCK_Reg48: return true;
case MCK_Reg46: return true;
case MCK_Reg44: return true;
case MCK_GPRPair: return true;
}
case MCK_VRM8NoV0:
return B == MCK_VRM8;
case MCK_Reg53:
switch (B) {
default: return false;
case MCK_Reg52: return true;
case MCK_Reg48: return true;
case MCK_Reg46: return true;
case MCK_Reg44: return true;
case MCK_GPRPair: return true;
}
case MCK_Reg51:
switch (B) {
default: return false;
case MCK_Reg52: return true;
case MCK_Reg48: return true;
case MCK_Reg46: return true;
case MCK_Reg44: return true;
case MCK_GPRPair: return true;
}
case MCK_Reg55:
switch (B) {
default: return false;
case MCK_Reg49: return true;
case MCK_Reg52: return true;
case MCK_Reg48: return true;
case MCK_Reg46: return true;
case MCK_Reg44: return true;
case MCK_GPRPair: return true;
}
case MCK_Reg22:
switch (B) {
default: return false;
case MCK_GPRC: return true;
case MCK_GPRTCNonX7: return true;
case MCK_GPRTC: return true;
case MCK_GPRJALRNonX7: return true;
case MCK_GPRJALR: return true;
case MCK_GPRNoX0X2: return true;
case MCK_GPRNoX0: return true;
case MCK_GPR: return true;
case MCK_GPRAll: return true;
}
case MCK_VRN2M4NoV0:
return B == MCK_VRN2M4;
case MCK_Reg49:
switch (B) {
default: return false;
case MCK_Reg48: return true;
case MCK_Reg46: return true;
case MCK_Reg44: return true;
case MCK_GPRPair: return true;
}
case MCK_VRM4NoV0:
return B == MCK_VRM4;
case MCK_FPR32C:
return B == MCK_FPR32;
case MCK_FPR64C:
return B == MCK_FPR64;
case MCK_GPRC:
switch (B) {
default: return false;
case MCK_GPRJALRNonX7: return true;
case MCK_GPRJALR: return true;
case MCK_GPRNoX0X2: return true;
case MCK_GPRNoX0: return true;
case MCK_GPR: return true;
case MCK_GPRAll: return true;
}
case MCK_GPRF16C:
return B == MCK_GPRF16;
case MCK_GPRF32C:
switch (B) {
default: return false;
case MCK_GPRF32NoX0: return true;
case MCK_GPRF32: return true;
}
case MCK_SR07:
switch (B) {
default: return false;
case MCK_GPRJALRNonX7: return true;
case MCK_GPRJALR: return true;
case MCK_GPRNoX0X2: return true;
case MCK_GPRNoX0: return true;
case MCK_GPR: return true;
case MCK_GPRAll: return true;
}
case MCK_Reg52:
switch (B) {
default: return false;
case MCK_Reg48: return true;
case MCK_Reg46: return true;
case MCK_Reg44: return true;
case MCK_GPRPair: return true;
}
case MCK_VRN4M2NoV0:
return B == MCK_VRN4M2;
case MCK_Reg48:
switch (B) {
default: return false;
case MCK_Reg46: return true;
case MCK_Reg44: return true;
case MCK_GPRPair: return true;
}
case MCK_GPRTCNonX7:
switch (B) {
default: return false;
case MCK_GPRTC: return true;
case MCK_GPRJALRNonX7: return true;
case MCK_GPRJALR: return true;
case MCK_GPRNoX0X2: return true;
case MCK_GPRNoX0: return true;
case MCK_GPR: return true;
case MCK_GPRAll: return true;
}
case MCK_VRN3M2NoV0:
return B == MCK_VRN3M2;
case MCK_Reg46:
switch (B) {
default: return false;
case MCK_Reg44: return true;
case MCK_GPRPair: return true;
}
case MCK_GPRTC:
switch (B) {
default: return false;
case MCK_GPRJALR: return true;
case MCK_GPRNoX0X2: return true;
case MCK_GPRNoX0: return true;
case MCK_GPR: return true;
case MCK_GPRAll: return true;
}
case MCK_VRN2M2NoV0:
return B == MCK_VRN2M2;
case MCK_Reg44:
return B == MCK_GPRPair;
case MCK_VRM2NoV0:
return B == MCK_VRM2;
case MCK_VRN8M1NoV0:
return B == MCK_VRN8M1;
case MCK_GPRJALRNonX7:
switch (B) {
default: return false;
case MCK_GPRJALR: return true;
case MCK_GPRNoX0X2: return true;
case MCK_GPRNoX0: return true;
case MCK_GPR: return true;
case MCK_GPRAll: return true;
}
case MCK_VRN7M1NoV0:
return B == MCK_VRN7M1;
case MCK_GPRJALR:
switch (B) {
default: return false;
case MCK_GPRNoX0X2: return true;
case MCK_GPRNoX0: return true;
case MCK_GPR: return true;
case MCK_GPRAll: return true;
}
case MCK_VRN6M1NoV0:
return B == MCK_VRN6M1;
case MCK_VRN5M1NoV0:
return B == MCK_VRN5M1;
case MCK_VRN4M1NoV0:
return B == MCK_VRN4M1;
case MCK_VRN3M1NoV0:
return B == MCK_VRN3M1;
case MCK_GPRNoX0X2:
switch (B) {
default: return false;
case MCK_GPRNoX0: return true;
case MCK_GPR: return true;
case MCK_GPRAll: return true;
}
case MCK_VRN2M1NoV0:
return B == MCK_VRN2M1;
case MCK_GPRF32NoX0:
return B == MCK_GPRF32;
case MCK_GPRNoX0:
switch (B) {
default: return false;
case MCK_GPR: return true;
case MCK_GPRAll: return true;
}
case MCK_VRNoV0:
return B == MCK_VM;
case MCK_GPR:
return B == MCK_GPRAll;
case MCK_FRMArg:
return B == OptionalMatchClass;
case MCK_FRMArgLegacy:
return B == OptionalMatchClass;
case MCK_RVVMaskRegOpOperand:
return B == OptionalMatchClass;
}
}
static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
RISCVOperand &Operand = (RISCVOperand &)GOp;
if (Kind == InvalidMatchClass)
return MCTargetAsmParser::Match_InvalidOperand;
if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
MCTargetAsmParser::Match_Success :
MCTargetAsmParser::Match_InvalidOperand;
switch (Kind) {
default: break;
case MCK_AnyRegCOperand: {
DiagnosticPredicate DP(Operand.isAnyRegC());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
break;
}
case MCK_AnyRegOperand: {
DiagnosticPredicate DP(Operand.isAnyReg());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
break;
}
case MCK_BareSymbol: {
DiagnosticPredicate DP(Operand.isBareSymbol());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidBareSymbol;
break;
}
case MCK_CLUIImm: {
DiagnosticPredicate DP(Operand.isCLUIImm());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidCLUIImm;
break;
}
case MCK_CSRSystemRegister: {
DiagnosticPredicate DP(Operand.isCSRSystemRegister());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidCSRSystemRegister;
break;
}
case MCK_RegReg: {
DiagnosticPredicate DP(Operand.isRegReg());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidRegReg;
break;
}
case MCK_CallSymbol: {
DiagnosticPredicate DP(Operand.isCallSymbol());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidCallSymbol;
break;
}
case MCK_FRMArg: {
DiagnosticPredicate DP(Operand.isFRMArg());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
break;
}
case MCK_FRMArgLegacy: {
DiagnosticPredicate DP(Operand.isFRMArgLegacy());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
break;
}
case MCK_FenceArg: {
DiagnosticPredicate DP(Operand.isFenceArg());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
break;
}
case MCK_GPRAsFPR16: {
DiagnosticPredicate DP(Operand.isGPRAsFPR16());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
break;
}
case MCK_GPRAsFPR32: {
DiagnosticPredicate DP(Operand.isGPRAsFPR32());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
break;
}
case MCK_GPRF64AsFPR: {
DiagnosticPredicate DP(Operand.isGPRAsFPR());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
break;
}
case MCK_GPRPairAsFPR: {
DiagnosticPredicate DP(Operand.isGPRPairAsFPR());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
break;
}
case MCK_GPRPairRV32: {
DiagnosticPredicate DP(Operand.isGPRPair());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
break;
}
case MCK_GPRPairRV64: {
DiagnosticPredicate DP(Operand.isGPRPair());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
break;
}
case MCK_Imm: {
DiagnosticPredicate DP(Operand.isImm());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
break;
}
case MCK_ImmZero: {
DiagnosticPredicate DP(Operand.isImmZero());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidImmZero;
break;
}
case MCK_InsnCDirectiveOpcode: {
DiagnosticPredicate DP(Operand.isImm());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
break;
}
case MCK_InsnDirectiveOpcode: {
DiagnosticPredicate DP(Operand.isImm());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
break;
}
case MCK_LoadFPImm: {
DiagnosticPredicate DP(Operand.isLoadFPImm());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidLoadFPImm;
break;
}
case MCK_NegStackAdj: {
DiagnosticPredicate DP(Operand.isSpimm());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidStackAdj;
break;
}
case MCK_PseudoJumpSymbol: {
DiagnosticPredicate DP(Operand.isPseudoJumpSymbol());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidPseudoJumpSymbol;
break;
}
case MCK_RTZArg: {
DiagnosticPredicate DP(Operand.isRTZArg());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidRTZArg;
break;
}
case MCK_Rlist: {
DiagnosticPredicate DP(Operand.isRlist());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidRlist;
break;
}
case MCK_RnumArg: {
DiagnosticPredicate DP(Operand.isRnumArg());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidRnumArg;
break;
}
case MCK_SImm5Plus1: {
DiagnosticPredicate DP(Operand.isSImm5Plus1());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidSImm5Plus1;
break;
}
case MCK_SImm21Lsb0JAL: {
DiagnosticPredicate DP(Operand.isSImm21Lsb0JAL());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidSImm21Lsb0JAL;
break;
}
case MCK_StackAdj: {
DiagnosticPredicate DP(Operand.isSpimm());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidStackAdj;
break;
}
case MCK_TLSDESCCallSymbol: {
DiagnosticPredicate DP(Operand.isTLSDESCCallSymbol());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidTLSDESCCallSymbol;
break;
}
case MCK_TPRelAddSymbol: {
DiagnosticPredicate DP(Operand.isTPRelAddSymbol());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidTPRelAddSymbol;
break;
}
case MCK_UImmLog2XLen: {
DiagnosticPredicate DP(Operand.isUImmLog2XLen());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImmLog2XLen;
break;
}
case MCK_UImmLog2XLenNonZero: {
DiagnosticPredicate DP(Operand.isUImmLog2XLenNonZero());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImmLog2XLenNonZero;
break;
}
case MCK_RVVMaskRegOpOperand: {
DiagnosticPredicate DP(Operand.isV0Reg());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidVMaskRegister;
break;
}
case MCK_ZeroOffsetMemOpOperand: {
DiagnosticPredicate DP(Operand.isGPR());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
break;
}
case MCK_VTypeI10: {
DiagnosticPredicate DP(Operand.isVTypeI10());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidVTypeI;
break;
}
case MCK_VTypeI11: {
DiagnosticPredicate DP(Operand.isVTypeI11());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidVTypeI;
break;
}
case MCK_SImm5: {
DiagnosticPredicate DP(Operand.isSImm5());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidSImm5;
break;
}
case MCK_SImm6: {
DiagnosticPredicate DP(Operand.isSImm6());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidSImm6;
break;
}
case MCK_SImm6NonZero: {
DiagnosticPredicate DP(Operand.isSImm6NonZero());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidSImm6NonZero;
break;
}
case MCK_UImm7Lsb00: {
DiagnosticPredicate DP(Operand.isUImm7Lsb00());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm7Lsb00;
break;
}
case MCK_UImm8Lsb00: {
DiagnosticPredicate DP(Operand.isUImm8Lsb00());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm8Lsb00;
break;
}
case MCK_UImm8Lsb000: {
DiagnosticPredicate DP(Operand.isUImm8Lsb000());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm8Lsb000;
break;
}
case MCK_SImm9Lsb0: {
DiagnosticPredicate DP(Operand.isSImm9Lsb0());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidSImm9Lsb0;
break;
}
case MCK_UImm9Lsb000: {
DiagnosticPredicate DP(Operand.isUImm9Lsb000());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm9Lsb000;
break;
}
case MCK_UImm10Lsb00NonZero: {
DiagnosticPredicate DP(Operand.isUImm10Lsb00NonZero());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm10Lsb00NonZero;
break;
}
case MCK_SImm10Lsb0000NonZero: {
DiagnosticPredicate DP(Operand.isSImm10Lsb0000NonZero());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidSImm10Lsb0000NonZero;
break;
}
case MCK_SImm12Lsb0: {
DiagnosticPredicate DP(Operand.isSImm12Lsb0());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidSImm12Lsb0;
break;
}
case MCK_UImm2Lsb0: {
DiagnosticPredicate DP(Operand.isUImm2Lsb0());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm2Lsb0;
break;
}
case MCK_UImm8GE32: {
DiagnosticPredicate DP(Operand.isUImm8GE32());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm8GE32;
break;
}
case MCK_SImm12Lsb00000: {
DiagnosticPredicate DP(Operand.isSImm12Lsb00000());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidSImm12Lsb00000;
break;
}
case MCK_UImm5Lsb0: {
DiagnosticPredicate DP(Operand.isUImm5Lsb0());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm5Lsb0;
break;
}
case MCK_UImm6Lsb0: {
DiagnosticPredicate DP(Operand.isUImm6Lsb0());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm6Lsb0;
break;
}
case MCK_UImm1: {
DiagnosticPredicate DP(Operand.isUImm1());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm1;
break;
}
case MCK_UImm2: {
DiagnosticPredicate DP(Operand.isUImm2());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm2;
break;
}
case MCK_UImm3: {
DiagnosticPredicate DP(Operand.isUImm3());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm3;
break;
}
case MCK_UImm4: {
DiagnosticPredicate DP(Operand.isUImm4());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm4;
break;
}
case MCK_UImm5: {
DiagnosticPredicate DP(Operand.isUImm5());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm5;
break;
}
case MCK_UImm6: {
DiagnosticPredicate DP(Operand.isUImm6());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm6;
break;
}
case MCK_UImm7: {
DiagnosticPredicate DP(Operand.isUImm7());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm7;
break;
}
case MCK_UImm8: {
DiagnosticPredicate DP(Operand.isUImm8());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm8;
break;
}
case MCK_UImm16: {
DiagnosticPredicate DP(Operand.isUImm16());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm16;
break;
}
case MCK_UImm32: {
DiagnosticPredicate DP(Operand.isUImm32());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm32;
break;
}
case MCK_SImm12: {
DiagnosticPredicate DP(Operand.isSImm12());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidSImm12;
break;
}
case MCK_SImm13Lsb0: {
DiagnosticPredicate DP(Operand.isSImm13Lsb0());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidSImm13Lsb0;
break;
}
case MCK_UImm20LUI: {
DiagnosticPredicate DP(Operand.isUImm20LUI());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm20LUI;
break;
}
case MCK_UImm20AUIPC: {
DiagnosticPredicate DP(Operand.isUImm20AUIPC());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm20AUIPC;
break;
}
case MCK_UImm20: {
DiagnosticPredicate DP(Operand.isUImm20());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm20;
break;
}
case MCK_ImmXLenLI: {
DiagnosticPredicate DP(Operand.isImmXLenLI());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidImmXLenLI;
break;
}
case MCK_ImmXLenLI_Restricted: {
DiagnosticPredicate DP(Operand.isImmXLenLI_Restricted());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidImmXLenLI_Restricted;
break;
}
}
if (Operand.isReg()) {
MatchClassKind OpKind;
switch (Operand.getReg().id()) {
default: OpKind = InvalidMatchClass; break;
case RISCV::X0_H: OpKind = MCK_GPRF16; break;
case RISCV::X1_H: OpKind = MCK_GPRF16; break;
case RISCV::X2_H: OpKind = MCK_GPRF16; break;
case RISCV::X3_H: OpKind = MCK_GPRF16; break;
case RISCV::X4_H: OpKind = MCK_GPRF16; break;
case RISCV::X5_H: OpKind = MCK_GPRF16; break;
case RISCV::X6_H: OpKind = MCK_GPRF16; break;
case RISCV::X7_H: OpKind = MCK_GPRF16; break;
case RISCV::X8_H: OpKind = MCK_GPRF16C; break;
case RISCV::X9_H: OpKind = MCK_GPRF16C; break;
case RISCV::X10_H: OpKind = MCK_GPRF16C; break;
case RISCV::X11_H: OpKind = MCK_GPRF16C; break;
case RISCV::X12_H: OpKind = MCK_GPRF16C; break;
case RISCV::X13_H: OpKind = MCK_GPRF16C; break;
case RISCV::X14_H: OpKind = MCK_GPRF16C; break;
case RISCV::X15_H: OpKind = MCK_GPRF16C; break;
case RISCV::X16_H: OpKind = MCK_GPRF16; break;
case RISCV::X17_H: OpKind = MCK_GPRF16; break;
case RISCV::X18_H: OpKind = MCK_GPRF16; break;
case RISCV::X19_H: OpKind = MCK_GPRF16; break;
case RISCV::X20_H: OpKind = MCK_GPRF16; break;
case RISCV::X21_H: OpKind = MCK_GPRF16; break;
case RISCV::X22_H: OpKind = MCK_GPRF16; break;
case RISCV::X23_H: OpKind = MCK_GPRF16; break;
case RISCV::X24_H: OpKind = MCK_GPRF16; break;
case RISCV::X25_H: OpKind = MCK_GPRF16; break;
case RISCV::X26_H: OpKind = MCK_GPRF16; break;
case RISCV::X27_H: OpKind = MCK_GPRF16; break;
case RISCV::X28_H: OpKind = MCK_GPRF16; break;
case RISCV::X29_H: OpKind = MCK_GPRF16; break;
case RISCV::X30_H: OpKind = MCK_GPRF16; break;
case RISCV::X31_H: OpKind = MCK_GPRF16; break;
case RISCV::X0_W: OpKind = MCK_GPRF32; break;
case RISCV::X1_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X2_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X3_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X4_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X5_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X6_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X7_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X8_W: OpKind = MCK_GPRF32C; break;
case RISCV::X9_W: OpKind = MCK_GPRF32C; break;
case RISCV::X10_W: OpKind = MCK_GPRF32C; break;
case RISCV::X11_W: OpKind = MCK_GPRF32C; break;
case RISCV::X12_W: OpKind = MCK_GPRF32C; break;
case RISCV::X13_W: OpKind = MCK_GPRF32C; break;
case RISCV::X14_W: OpKind = MCK_GPRF32C; break;
case RISCV::X15_W: OpKind = MCK_GPRF32C; break;
case RISCV::X16_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X17_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X18_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X19_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X20_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X21_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X22_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X23_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X24_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X25_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X26_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X27_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X28_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X29_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X30_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X31_W: OpKind = MCK_GPRF32NoX0; break;
case RISCV::X0: OpKind = MCK_GPRX0; break;
case RISCV::X1: OpKind = MCK_GPRX1; break;
case RISCV::X2: OpKind = MCK_SP; break;
case RISCV::X3: OpKind = MCK_GPRNoX0X2; break;
case RISCV::X4: OpKind = MCK_GPRNoX0X2; break;
case RISCV::X5: OpKind = MCK_GPRX5; break;
case RISCV::X6: OpKind = MCK_GPRTCNonX7; break;
case RISCV::X7: OpKind = MCK_GPRX7; break;
case RISCV::X8: OpKind = MCK_Reg19; break;
case RISCV::X9: OpKind = MCK_Reg19; break;
case RISCV::X10: OpKind = MCK_Reg22; break;
case RISCV::X11: OpKind = MCK_Reg22; break;
case RISCV::X12: OpKind = MCK_Reg22; break;
case RISCV::X13: OpKind = MCK_Reg22; break;
case RISCV::X14: OpKind = MCK_Reg22; break;
case RISCV::X15: OpKind = MCK_Reg22; break;
case RISCV::X16: OpKind = MCK_GPRTCNonX7; break;
case RISCV::X17: OpKind = MCK_GPRTCNonX7; break;
case RISCV::X18: OpKind = MCK_SR07; break;
case RISCV::X19: OpKind = MCK_SR07; break;
case RISCV::X20: OpKind = MCK_SR07; break;
case RISCV::X21: OpKind = MCK_SR07; break;
case RISCV::X22: OpKind = MCK_SR07; break;
case RISCV::X23: OpKind = MCK_SR07; break;
case RISCV::X24: OpKind = MCK_GPRJALRNonX7; break;
case RISCV::X25: OpKind = MCK_GPRJALRNonX7; break;
case RISCV::X26: OpKind = MCK_GPRJALRNonX7; break;
case RISCV::X27: OpKind = MCK_GPRJALRNonX7; break;
case RISCV::X28: OpKind = MCK_GPRTCNonX7; break;
case RISCV::X29: OpKind = MCK_GPRTCNonX7; break;
case RISCV::X30: OpKind = MCK_GPRTCNonX7; break;
case RISCV::X31: OpKind = MCK_GPRTCNonX7; break;
case RISCV::F0_H: OpKind = MCK_FPR16; break;
case RISCV::F1_H: OpKind = MCK_FPR16; break;
case RISCV::F2_H: OpKind = MCK_FPR16; break;
case RISCV::F3_H: OpKind = MCK_FPR16; break;
case RISCV::F4_H: OpKind = MCK_FPR16; break;
case RISCV::F5_H: OpKind = MCK_FPR16; break;
case RISCV::F6_H: OpKind = MCK_FPR16; break;
case RISCV::F7_H: OpKind = MCK_FPR16; break;
case RISCV::F8_H: OpKind = MCK_FPR16; break;
case RISCV::F9_H: OpKind = MCK_FPR16; break;
case RISCV::F10_H: OpKind = MCK_FPR16; break;
case RISCV::F11_H: OpKind = MCK_FPR16; break;
case RISCV::F12_H: OpKind = MCK_FPR16; break;
case RISCV::F13_H: OpKind = MCK_FPR16; break;
case RISCV::F14_H: OpKind = MCK_FPR16; break;
case RISCV::F15_H: OpKind = MCK_FPR16; break;
case RISCV::F16_H: OpKind = MCK_FPR16; break;
case RISCV::F17_H: OpKind = MCK_FPR16; break;
case RISCV::F18_H: OpKind = MCK_FPR16; break;
case RISCV::F19_H: OpKind = MCK_FPR16; break;
case RISCV::F20_H: OpKind = MCK_FPR16; break;
case RISCV::F21_H: OpKind = MCK_FPR16; break;
case RISCV::F22_H: OpKind = MCK_FPR16; break;
case RISCV::F23_H: OpKind = MCK_FPR16; break;
case RISCV::F24_H: OpKind = MCK_FPR16; break;
case RISCV::F25_H: OpKind = MCK_FPR16; break;
case RISCV::F26_H: OpKind = MCK_FPR16; break;
case RISCV::F27_H: OpKind = MCK_FPR16; break;
case RISCV::F28_H: OpKind = MCK_FPR16; break;
case RISCV::F29_H: OpKind = MCK_FPR16; break;
case RISCV::F30_H: OpKind = MCK_FPR16; break;
case RISCV::F31_H: OpKind = MCK_FPR16; break;
case RISCV::F0_F: OpKind = MCK_FPR32; break;
case RISCV::F1_F: OpKind = MCK_FPR32; break;
case RISCV::F2_F: OpKind = MCK_FPR32; break;
case RISCV::F3_F: OpKind = MCK_FPR32; break;
case RISCV::F4_F: OpKind = MCK_FPR32; break;
case RISCV::F5_F: OpKind = MCK_FPR32; break;
case RISCV::F6_F: OpKind = MCK_FPR32; break;
case RISCV::F7_F: OpKind = MCK_FPR32; break;
case RISCV::F8_F: OpKind = MCK_FPR32C; break;
case RISCV::F9_F: OpKind = MCK_FPR32C; break;
case RISCV::F10_F: OpKind = MCK_FPR32C; break;
case RISCV::F11_F: OpKind = MCK_FPR32C; break;
case RISCV::F12_F: OpKind = MCK_FPR32C; break;
case RISCV::F13_F: OpKind = MCK_FPR32C; break;
case RISCV::F14_F: OpKind = MCK_FPR32C; break;
case RISCV::F15_F: OpKind = MCK_FPR32C; break;
case RISCV::F16_F: OpKind = MCK_FPR32; break;
case RISCV::F17_F: OpKind = MCK_FPR32; break;
case RISCV::F18_F: OpKind = MCK_FPR32; break;
case RISCV::F19_F: OpKind = MCK_FPR32; break;
case RISCV::F20_F: OpKind = MCK_FPR32; break;
case RISCV::F21_F: OpKind = MCK_FPR32; break;
case RISCV::F22_F: OpKind = MCK_FPR32; break;
case RISCV::F23_F: OpKind = MCK_FPR32; break;
case RISCV::F24_F: OpKind = MCK_FPR32; break;
case RISCV::F25_F: OpKind = MCK_FPR32; break;
case RISCV::F26_F: OpKind = MCK_FPR32; break;
case RISCV::F27_F: OpKind = MCK_FPR32; break;
case RISCV::F28_F: OpKind = MCK_FPR32; break;
case RISCV::F29_F: OpKind = MCK_FPR32; break;
case RISCV::F30_F: OpKind = MCK_FPR32; break;
case RISCV::F31_F: OpKind = MCK_FPR32; break;
case RISCV::F0_D: OpKind = MCK_FPR64; break;
case RISCV::F1_D: OpKind = MCK_FPR64; break;
case RISCV::F2_D: OpKind = MCK_FPR64; break;
case RISCV::F3_D: OpKind = MCK_FPR64; break;
case RISCV::F4_D: OpKind = MCK_FPR64; break;
case RISCV::F5_D: OpKind = MCK_FPR64; break;
case RISCV::F6_D: OpKind = MCK_FPR64; break;
case RISCV::F7_D: OpKind = MCK_FPR64; break;
case RISCV::F8_D: OpKind = MCK_FPR64C; break;
case RISCV::F9_D: OpKind = MCK_FPR64C; break;
case RISCV::F10_D: OpKind = MCK_FPR64C; break;
case RISCV::F11_D: OpKind = MCK_FPR64C; break;
case RISCV::F12_D: OpKind = MCK_FPR64C; break;
case RISCV::F13_D: OpKind = MCK_FPR64C; break;
case RISCV::F14_D: OpKind = MCK_FPR64C; break;
case RISCV::F15_D: OpKind = MCK_FPR64C; break;
case RISCV::F16_D: OpKind = MCK_FPR64; break;
case RISCV::F17_D: OpKind = MCK_FPR64; break;
case RISCV::F18_D: OpKind = MCK_FPR64; break;
case RISCV::F19_D: OpKind = MCK_FPR64; break;
case RISCV::F20_D: OpKind = MCK_FPR64; break;
case RISCV::F21_D: OpKind = MCK_FPR64; break;
case RISCV::F22_D: OpKind = MCK_FPR64; break;
case RISCV::F23_D: OpKind = MCK_FPR64; break;
case RISCV::F24_D: OpKind = MCK_FPR64; break;
case RISCV::F25_D: OpKind = MCK_FPR64; break;
case RISCV::F26_D: OpKind = MCK_FPR64; break;
case RISCV::F27_D: OpKind = MCK_FPR64; break;
case RISCV::F28_D: OpKind = MCK_FPR64; break;
case RISCV::F29_D: OpKind = MCK_FPR64; break;
case RISCV::F30_D: OpKind = MCK_FPR64; break;
case RISCV::F31_D: OpKind = MCK_FPR64; break;
case RISCV::V0: OpKind = MCK_VMV0; break;
case RISCV::V1: OpKind = MCK_VRNoV0; break;
case RISCV::V2: OpKind = MCK_VRNoV0; break;
case RISCV::V3: OpKind = MCK_VRNoV0; break;
case RISCV::V4: OpKind = MCK_VRNoV0; break;
case RISCV::V5: OpKind = MCK_VRNoV0; break;
case RISCV::V6: OpKind = MCK_VRNoV0; break;
case RISCV::V7: OpKind = MCK_VRNoV0; break;
case RISCV::V8: OpKind = MCK_VRNoV0; break;
case RISCV::V9: OpKind = MCK_VRNoV0; break;
case RISCV::V10: OpKind = MCK_VRNoV0; break;
case RISCV::V11: OpKind = MCK_VRNoV0; break;
case RISCV::V12: OpKind = MCK_VRNoV0; break;
case RISCV::V13: OpKind = MCK_VRNoV0; break;
case RISCV::V14: OpKind = MCK_VRNoV0; break;
case RISCV::V15: OpKind = MCK_VRNoV0; break;
case RISCV::V16: OpKind = MCK_VRNoV0; break;
case RISCV::V17: OpKind = MCK_VRNoV0; break;
case RISCV::V18: OpKind = MCK_VRNoV0; break;
case RISCV::V19: OpKind = MCK_VRNoV0; break;
case RISCV::V20: OpKind = MCK_VRNoV0; break;
case RISCV::V21: OpKind = MCK_VRNoV0; break;
case RISCV::V22: OpKind = MCK_VRNoV0; break;
case RISCV::V23: OpKind = MCK_VRNoV0; break;
case RISCV::V24: OpKind = MCK_VRNoV0; break;
case RISCV::V25: OpKind = MCK_VRNoV0; break;
case RISCV::V26: OpKind = MCK_VRNoV0; break;
case RISCV::V27: OpKind = MCK_VRNoV0; break;
case RISCV::V28: OpKind = MCK_VRNoV0; break;
case RISCV::V29: OpKind = MCK_VRNoV0; break;
case RISCV::V30: OpKind = MCK_VRNoV0; break;
case RISCV::V31: OpKind = MCK_VRNoV0; break;
case RISCV::V0M2: OpKind = MCK_Reg31; break;
case RISCV::V2M2: OpKind = MCK_VRM2NoV0; break;
case RISCV::V4M2: OpKind = MCK_VRM2NoV0; break;
case RISCV::V6M2: OpKind = MCK_VRM2NoV0; break;
case RISCV::V8M2: OpKind = MCK_VRM2NoV0; break;
case RISCV::V10M2: OpKind = MCK_VRM2NoV0; break;
case RISCV::V12M2: OpKind = MCK_VRM2NoV0; break;
case RISCV::V14M2: OpKind = MCK_VRM2NoV0; break;
case RISCV::V16M2: OpKind = MCK_VRM2NoV0; break;
case RISCV::V18M2: OpKind = MCK_VRM2NoV0; break;
case RISCV::V20M2: OpKind = MCK_VRM2NoV0; break;
case RISCV::V22M2: OpKind = MCK_VRM2NoV0; break;
case RISCV::V24M2: OpKind = MCK_VRM2NoV0; break;
case RISCV::V26M2: OpKind = MCK_VRM2NoV0; break;
case RISCV::V28M2: OpKind = MCK_VRM2NoV0; break;
case RISCV::V30M2: OpKind = MCK_VRM2NoV0; break;
case RISCV::V0M4: OpKind = MCK_Reg34; break;
case RISCV::V4M4: OpKind = MCK_VRM4NoV0; break;
case RISCV::V8M4: OpKind = MCK_VRM4NoV0; break;
case RISCV::V12M4: OpKind = MCK_VRM4NoV0; break;
case RISCV::V16M4: OpKind = MCK_VRM4NoV0; break;
case RISCV::V20M4: OpKind = MCK_VRM4NoV0; break;
case RISCV::V24M4: OpKind = MCK_VRM4NoV0; break;
case RISCV::V28M4: OpKind = MCK_VRM4NoV0; break;
case RISCV::V0M8: OpKind = MCK_Reg37; break;
case RISCV::V8M8: OpKind = MCK_VRM8NoV0; break;
case RISCV::V16M8: OpKind = MCK_VRM8NoV0; break;
case RISCV::V24M8: OpKind = MCK_VRM8NoV0; break;
case RISCV::VTYPE: OpKind = MCK_VCSR; break;
case RISCV::VL: OpKind = MCK_VCSR; break;
case RISCV::VLENB: OpKind = MCK_VCSR; break;
case RISCV::DUMMY_REG_PAIR_WITH_X0: OpKind = MCK_GPRAll; break;
case RISCV::X0_Pair: OpKind = MCK_Reg41; break;
case RISCV::X2_X3: OpKind = MCK_Reg43; break;
case RISCV::X4_X5: OpKind = MCK_Reg45; break;
case RISCV::X6_X7: OpKind = MCK_Reg47; break;
case RISCV::X8_X9: OpKind = MCK_Reg50; break;
case RISCV::X10_X11: OpKind = MCK_Reg54; break;
case RISCV::X12_X13: OpKind = MCK_Reg54; break;
case RISCV::X14_X15: OpKind = MCK_Reg54; break;
case RISCV::X16_X17: OpKind = MCK_Reg55; break;
case RISCV::X18_X19: OpKind = MCK_Reg53; break;
case RISCV::X20_X21: OpKind = MCK_Reg53; break;
case RISCV::X22_X23: OpKind = MCK_Reg53; break;
case RISCV::X24_X25: OpKind = MCK_Reg52; break;
case RISCV::X26_X27: OpKind = MCK_Reg52; break;
case RISCV::X28_X29: OpKind = MCK_Reg55; break;
case RISCV::X30_X31: OpKind = MCK_Reg55; break;
case RISCV::SF_VCIX_STATE: OpKind = MCK_anonymous_8771; break;
case RISCV::V8_V9: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V9_V10: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V10_V11: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V11_V12: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V12_V13: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V13_V14: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V14_V15: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V15_V16: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V16_V17: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V17_V18: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V18_V19: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V19_V20: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V20_V21: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V21_V22: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V22_V23: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V23_V24: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V24_V25: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V25_V26: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V26_V27: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V27_V28: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V28_V29: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V29_V30: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V30_V31: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V1_V2: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V2_V3: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V3_V4: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V4_V5: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V5_V6: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V6_V7: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V7_V8: OpKind = MCK_VRN2M1NoV0; break;
case RISCV::V0_V1: OpKind = MCK_Reg59; break;
case RISCV::V8M2_V10M2: OpKind = MCK_VRN2M2NoV0; break;
case RISCV::V10M2_V12M2: OpKind = MCK_VRN2M2NoV0; break;
case RISCV::V12M2_V14M2: OpKind = MCK_VRN2M2NoV0; break;
case RISCV::V14M2_V16M2: OpKind = MCK_VRN2M2NoV0; break;
case RISCV::V16M2_V18M2: OpKind = MCK_VRN2M2NoV0; break;
case RISCV::V18M2_V20M2: OpKind = MCK_VRN2M2NoV0; break;
case RISCV::V20M2_V22M2: OpKind = MCK_VRN2M2NoV0; break;
case RISCV::V22M2_V24M2: OpKind = MCK_VRN2M2NoV0; break;
case RISCV::V24M2_V26M2: OpKind = MCK_VRN2M2NoV0; break;
case RISCV::V26M2_V28M2: OpKind = MCK_VRN2M2NoV0; break;
case RISCV::V28M2_V30M2: OpKind = MCK_VRN2M2NoV0; break;
case RISCV::V2M2_V4M2: OpKind = MCK_VRN2M2NoV0; break;
case RISCV::V4M2_V6M2: OpKind = MCK_VRN2M2NoV0; break;
case RISCV::V6M2_V8M2: OpKind = MCK_VRN2M2NoV0; break;
case RISCV::V0M2_V2M2: OpKind = MCK_Reg62; break;
case RISCV::V8M4_V12M4: OpKind = MCK_VRN2M4NoV0; break;
case RISCV::V12M4_V16M4: OpKind = MCK_VRN2M4NoV0; break;
case RISCV::V16M4_V20M4: OpKind = MCK_VRN2M4NoV0; break;
case RISCV::V20M4_V24M4: OpKind = MCK_VRN2M4NoV0; break;
case RISCV::V24M4_V28M4: OpKind = MCK_VRN2M4NoV0; break;
case RISCV::V4M4_V8M4: OpKind = MCK_VRN2M4NoV0; break;
case RISCV::V0M4_V4M4: OpKind = MCK_Reg65; break;
case RISCV::V8_V9_V10: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V9_V10_V11: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V10_V11_V12: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V11_V12_V13: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V12_V13_V14: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V13_V14_V15: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V14_V15_V16: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V15_V16_V17: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V16_V17_V18: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V17_V18_V19: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V18_V19_V20: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V19_V20_V21: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V20_V21_V22: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V21_V22_V23: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V22_V23_V24: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V23_V24_V25: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V24_V25_V26: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V25_V26_V27: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V26_V27_V28: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V27_V28_V29: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V28_V29_V30: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V29_V30_V31: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V1_V2_V3: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V2_V3_V4: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V3_V4_V5: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V4_V5_V6: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V5_V6_V7: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V6_V7_V8: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V7_V8_V9: OpKind = MCK_VRN3M1NoV0; break;
case RISCV::V0_V1_V2: OpKind = MCK_Reg68; break;
case RISCV::V8M2_V10M2_V12M2: OpKind = MCK_VRN3M2NoV0; break;
case RISCV::V10M2_V12M2_V14M2: OpKind = MCK_VRN3M2NoV0; break;
case RISCV::V12M2_V14M2_V16M2: OpKind = MCK_VRN3M2NoV0; break;
case RISCV::V14M2_V16M2_V18M2: OpKind = MCK_VRN3M2NoV0; break;
case RISCV::V16M2_V18M2_V20M2: OpKind = MCK_VRN3M2NoV0; break;
case RISCV::V18M2_V20M2_V22M2: OpKind = MCK_VRN3M2NoV0; break;
case RISCV::V20M2_V22M2_V24M2: OpKind = MCK_VRN3M2NoV0; break;
case RISCV::V22M2_V24M2_V26M2: OpKind = MCK_VRN3M2NoV0; break;
case RISCV::V24M2_V26M2_V28M2: OpKind = MCK_VRN3M2NoV0; break;
case RISCV::V26M2_V28M2_V30M2: OpKind = MCK_VRN3M2NoV0; break;
case RISCV::V2M2_V4M2_V6M2: OpKind = MCK_VRN3M2NoV0; break;
case RISCV::V4M2_V6M2_V8M2: OpKind = MCK_VRN3M2NoV0; break;
case RISCV::V6M2_V8M2_V10M2: OpKind = MCK_VRN3M2NoV0; break;
case RISCV::V0M2_V2M2_V4M2: OpKind = MCK_Reg71; break;
case RISCV::V8_V9_V10_V11: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V9_V10_V11_V12: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V10_V11_V12_V13: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V11_V12_V13_V14: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V12_V13_V14_V15: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V13_V14_V15_V16: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V14_V15_V16_V17: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V15_V16_V17_V18: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V16_V17_V18_V19: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V17_V18_V19_V20: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V18_V19_V20_V21: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V19_V20_V21_V22: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V20_V21_V22_V23: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V21_V22_V23_V24: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V22_V23_V24_V25: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V23_V24_V25_V26: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V24_V25_V26_V27: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V25_V26_V27_V28: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V26_V27_V28_V29: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V27_V28_V29_V30: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V28_V29_V30_V31: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V1_V2_V3_V4: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V2_V3_V4_V5: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V3_V4_V5_V6: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V4_V5_V6_V7: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V5_V6_V7_V8: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V6_V7_V8_V9: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V7_V8_V9_V10: OpKind = MCK_VRN4M1NoV0; break;
case RISCV::V0_V1_V2_V3: OpKind = MCK_Reg74; break;
case RISCV::V8M2_V10M2_V12M2_V14M2: OpKind = MCK_VRN4M2NoV0; break;
case RISCV::V10M2_V12M2_V14M2_V16M2: OpKind = MCK_VRN4M2NoV0; break;
case RISCV::V12M2_V14M2_V16M2_V18M2: OpKind = MCK_VRN4M2NoV0; break;
case RISCV::V14M2_V16M2_V18M2_V20M2: OpKind = MCK_VRN4M2NoV0; break;
case RISCV::V16M2_V18M2_V20M2_V22M2: OpKind = MCK_VRN4M2NoV0; break;
case RISCV::V18M2_V20M2_V22M2_V24M2: OpKind = MCK_VRN4M2NoV0; break;
case RISCV::V20M2_V22M2_V24M2_V26M2: OpKind = MCK_VRN4M2NoV0; break;
case RISCV::V22M2_V24M2_V26M2_V28M2: OpKind = MCK_VRN4M2NoV0; break;
case RISCV::V24M2_V26M2_V28M2_V30M2: OpKind = MCK_VRN4M2NoV0; break;
case RISCV::V2M2_V4M2_V6M2_V8M2: OpKind = MCK_VRN4M2NoV0; break;
case RISCV::V4M2_V6M2_V8M2_V10M2: OpKind = MCK_VRN4M2NoV0; break;
case RISCV::V6M2_V8M2_V10M2_V12M2: OpKind = MCK_VRN4M2NoV0; break;
case RISCV::V0M2_V2M2_V4M2_V6M2: OpKind = MCK_Reg77; break;
case RISCV::V8_V9_V10_V11_V12: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V9_V10_V11_V12_V13: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V10_V11_V12_V13_V14: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V11_V12_V13_V14_V15: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V12_V13_V14_V15_V16: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V13_V14_V15_V16_V17: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V14_V15_V16_V17_V18: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V15_V16_V17_V18_V19: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V16_V17_V18_V19_V20: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V17_V18_V19_V20_V21: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V18_V19_V20_V21_V22: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V19_V20_V21_V22_V23: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V20_V21_V22_V23_V24: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V21_V22_V23_V24_V25: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V22_V23_V24_V25_V26: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V23_V24_V25_V26_V27: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V24_V25_V26_V27_V28: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V25_V26_V27_V28_V29: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V26_V27_V28_V29_V30: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V27_V28_V29_V30_V31: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V1_V2_V3_V4_V5: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V2_V3_V4_V5_V6: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V3_V4_V5_V6_V7: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V4_V5_V6_V7_V8: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V5_V6_V7_V8_V9: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V6_V7_V8_V9_V10: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V7_V8_V9_V10_V11: OpKind = MCK_VRN5M1NoV0; break;
case RISCV::V0_V1_V2_V3_V4: OpKind = MCK_Reg80; break;
case RISCV::V8_V9_V10_V11_V12_V13: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V9_V10_V11_V12_V13_V14: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V10_V11_V12_V13_V14_V15: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V11_V12_V13_V14_V15_V16: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V12_V13_V14_V15_V16_V17: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V13_V14_V15_V16_V17_V18: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V14_V15_V16_V17_V18_V19: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V15_V16_V17_V18_V19_V20: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V16_V17_V18_V19_V20_V21: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V17_V18_V19_V20_V21_V22: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V18_V19_V20_V21_V22_V23: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V19_V20_V21_V22_V23_V24: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V20_V21_V22_V23_V24_V25: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V21_V22_V23_V24_V25_V26: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V22_V23_V24_V25_V26_V27: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V23_V24_V25_V26_V27_V28: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V24_V25_V26_V27_V28_V29: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V25_V26_V27_V28_V29_V30: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V26_V27_V28_V29_V30_V31: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V1_V2_V3_V4_V5_V6: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V2_V3_V4_V5_V6_V7: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V3_V4_V5_V6_V7_V8: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V4_V5_V6_V7_V8_V9: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V5_V6_V7_V8_V9_V10: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V6_V7_V8_V9_V10_V11: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V7_V8_V9_V10_V11_V12: OpKind = MCK_VRN6M1NoV0; break;
case RISCV::V0_V1_V2_V3_V4_V5: OpKind = MCK_Reg83; break;
case RISCV::V8_V9_V10_V11_V12_V13_V14: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V9_V10_V11_V12_V13_V14_V15: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V10_V11_V12_V13_V14_V15_V16: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V11_V12_V13_V14_V15_V16_V17: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V12_V13_V14_V15_V16_V17_V18: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V13_V14_V15_V16_V17_V18_V19: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V14_V15_V16_V17_V18_V19_V20: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V15_V16_V17_V18_V19_V20_V21: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V16_V17_V18_V19_V20_V21_V22: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V17_V18_V19_V20_V21_V22_V23: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V18_V19_V20_V21_V22_V23_V24: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V19_V20_V21_V22_V23_V24_V25: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V20_V21_V22_V23_V24_V25_V26: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V21_V22_V23_V24_V25_V26_V27: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V22_V23_V24_V25_V26_V27_V28: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V23_V24_V25_V26_V27_V28_V29: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V24_V25_V26_V27_V28_V29_V30: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V25_V26_V27_V28_V29_V30_V31: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V1_V2_V3_V4_V5_V6_V7: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V2_V3_V4_V5_V6_V7_V8: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V3_V4_V5_V6_V7_V8_V9: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V4_V5_V6_V7_V8_V9_V10: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V5_V6_V7_V8_V9_V10_V11: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V6_V7_V8_V9_V10_V11_V12: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V7_V8_V9_V10_V11_V12_V13: OpKind = MCK_VRN7M1NoV0; break;
case RISCV::V0_V1_V2_V3_V4_V5_V6: OpKind = MCK_Reg86; break;
case RISCV::V8_V9_V10_V11_V12_V13_V14_V15: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V9_V10_V11_V12_V13_V14_V15_V16: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V10_V11_V12_V13_V14_V15_V16_V17: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V11_V12_V13_V14_V15_V16_V17_V18: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V12_V13_V14_V15_V16_V17_V18_V19: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V13_V14_V15_V16_V17_V18_V19_V20: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V14_V15_V16_V17_V18_V19_V20_V21: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V15_V16_V17_V18_V19_V20_V21_V22: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V16_V17_V18_V19_V20_V21_V22_V23: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V17_V18_V19_V20_V21_V22_V23_V24: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V18_V19_V20_V21_V22_V23_V24_V25: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V19_V20_V21_V22_V23_V24_V25_V26: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V20_V21_V22_V23_V24_V25_V26_V27: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V21_V22_V23_V24_V25_V26_V27_V28: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V22_V23_V24_V25_V26_V27_V28_V29: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V23_V24_V25_V26_V27_V28_V29_V30: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V24_V25_V26_V27_V28_V29_V30_V31: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V1_V2_V3_V4_V5_V6_V7_V8: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V2_V3_V4_V5_V6_V7_V8_V9: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V3_V4_V5_V6_V7_V8_V9_V10: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V4_V5_V6_V7_V8_V9_V10_V11: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V5_V6_V7_V8_V9_V10_V11_V12: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V6_V7_V8_V9_V10_V11_V12_V13: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V7_V8_V9_V10_V11_V12_V13_V14: OpKind = MCK_VRN8M1NoV0; break;
case RISCV::V0_V1_V2_V3_V4_V5_V6_V7: OpKind = MCK_Reg89; break;
}
return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
getDiagKindFromRegisterClass(Kind);
}
if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
return getDiagKindFromRegisterClass(Kind);
return MCTargetAsmParser::Match_InvalidOperand;
}
#ifndef NDEBUG
const char *getMatchClassName(MatchClassKind Kind) {
switch (Kind) {
case InvalidMatchClass: return "InvalidMatchClass";
case OptionalMatchClass: return "OptionalMatchClass";
case MCK__40_: return "MCK__40_";
case MCK__41_: return "MCK__41_";
case MCK_Reg89: return "MCK_Reg89";
case MCK_Reg86: return "MCK_Reg86";
case MCK_Reg83: return "MCK_Reg83";
case MCK_Reg80: return "MCK_Reg80";
case MCK_Reg77: return "MCK_Reg77";
case MCK_Reg74: return "MCK_Reg74";
case MCK_Reg71: return "MCK_Reg71";
case MCK_Reg68: return "MCK_Reg68";
case MCK_Reg65: return "MCK_Reg65";
case MCK_Reg62: return "MCK_Reg62";
case MCK_Reg59: return "MCK_Reg59";
case MCK_Reg50: return "MCK_Reg50";
case MCK_Reg47: return "MCK_Reg47";
case MCK_Reg45: return "MCK_Reg45";
case MCK_Reg43: return "MCK_Reg43";
case MCK_Reg41: return "MCK_Reg41";
case MCK_Reg37: return "MCK_Reg37";
case MCK_Reg34: return "MCK_Reg34";
case MCK_Reg31: return "MCK_Reg31";
case MCK_GPRX0: return "MCK_GPRX0";
case MCK_GPRX1: return "MCK_GPRX1";
case MCK_GPRX5: return "MCK_GPRX5";
case MCK_GPRX7: return "MCK_GPRX7";
case MCK_SP: return "MCK_SP";
case MCK_VMV0: return "MCK_VMV0";
case MCK_anonymous_8771: return "MCK_anonymous_8771";
case MCK_Reg19: return "MCK_Reg19";
case MCK_GPRX1X5: return "MCK_GPRX1X5";
case MCK_Reg54: return "MCK_Reg54";
case MCK_VCSR: return "MCK_VCSR";
case MCK_VRM8NoV0: return "MCK_VRM8NoV0";
case MCK_Reg53: return "MCK_Reg53";
case MCK_Reg51: return "MCK_Reg51";
case MCK_VRM8: return "MCK_VRM8";
case MCK_Reg55: return "MCK_Reg55";
case MCK_Reg22: return "MCK_Reg22";
case MCK_VRN2M4NoV0: return "MCK_VRN2M4NoV0";
case MCK_Reg49: return "MCK_Reg49";
case MCK_VRM4NoV0: return "MCK_VRM4NoV0";
case MCK_VRN2M4: return "MCK_VRN2M4";
case MCK_FPR32C: return "MCK_FPR32C";
case MCK_FPR64C: return "MCK_FPR64C";
case MCK_GPRC: return "MCK_GPRC";
case MCK_GPRF16C: return "MCK_GPRF16C";
case MCK_GPRF32C: return "MCK_GPRF32C";
case MCK_SR07: return "MCK_SR07";
case MCK_VRM4: return "MCK_VRM4";
case MCK_Reg52: return "MCK_Reg52";
case MCK_VRN4M2NoV0: return "MCK_VRN4M2NoV0";
case MCK_Reg48: return "MCK_Reg48";
case MCK_GPRTCNonX7: return "MCK_GPRTCNonX7";
case MCK_VRN3M2NoV0: return "MCK_VRN3M2NoV0";
case MCK_VRN4M2: return "MCK_VRN4M2";
case MCK_Reg46: return "MCK_Reg46";
case MCK_GPRTC: return "MCK_GPRTC";
case MCK_VRN2M2NoV0: return "MCK_VRN2M2NoV0";
case MCK_VRN3M2: return "MCK_VRN3M2";
case MCK_Reg44: return "MCK_Reg44";
case MCK_VRM2NoV0: return "MCK_VRM2NoV0";
case MCK_VRN2M2: return "MCK_VRN2M2";
case MCK_GPRPair: return "MCK_GPRPair";
case MCK_VRM2: return "MCK_VRM2";
case MCK_VRN8M1NoV0: return "MCK_VRN8M1NoV0";
case MCK_GPRJALRNonX7: return "MCK_GPRJALRNonX7";
case MCK_VRN7M1NoV0: return "MCK_VRN7M1NoV0";
case MCK_VRN8M1: return "MCK_VRN8M1";
case MCK_GPRJALR: return "MCK_GPRJALR";
case MCK_VRN6M1NoV0: return "MCK_VRN6M1NoV0";
case MCK_VRN7M1: return "MCK_VRN7M1";
case MCK_VRN5M1NoV0: return "MCK_VRN5M1NoV0";
case MCK_VRN6M1: return "MCK_VRN6M1";
case MCK_VRN4M1NoV0: return "MCK_VRN4M1NoV0";
case MCK_VRN5M1: return "MCK_VRN5M1";
case MCK_VRN3M1NoV0: return "MCK_VRN3M1NoV0";
case MCK_VRN4M1: return "MCK_VRN4M1";
case MCK_GPRNoX0X2: return "MCK_GPRNoX0X2";
case MCK_VRN2M1NoV0: return "MCK_VRN2M1NoV0";
case MCK_VRN3M1: return "MCK_VRN3M1";
case MCK_GPRF32NoX0: return "MCK_GPRF32NoX0";
case MCK_GPRNoX0: return "MCK_GPRNoX0";
case MCK_VRN2M1: return "MCK_VRN2M1";
case MCK_VRNoV0: return "MCK_VRNoV0";
case MCK_FPR16: return "MCK_FPR16";
case MCK_FPR32: return "MCK_FPR32";
case MCK_FPR64: return "MCK_FPR64";
case MCK_GPR: return "MCK_GPR";
case MCK_GPRF16: return "MCK_GPRF16";
case MCK_GPRF32: return "MCK_GPRF32";
case MCK_VM: return "MCK_VM";
case MCK_GPRAll: return "MCK_GPRAll";
case MCK_AnyRegCOperand: return "MCK_AnyRegCOperand";
case MCK_AnyRegOperand: return "MCK_AnyRegOperand";
case MCK_BareSymbol: return "MCK_BareSymbol";
case MCK_CLUIImm: return "MCK_CLUIImm";
case MCK_CSRSystemRegister: return "MCK_CSRSystemRegister";
case MCK_RegReg: return "MCK_RegReg";
case MCK_CallSymbol: return "MCK_CallSymbol";
case MCK_FRMArg: return "MCK_FRMArg";
case MCK_FRMArgLegacy: return "MCK_FRMArgLegacy";
case MCK_FenceArg: return "MCK_FenceArg";
case MCK_GPRAsFPR16: return "MCK_GPRAsFPR16";
case MCK_GPRAsFPR32: return "MCK_GPRAsFPR32";
case MCK_GPRF64AsFPR: return "MCK_GPRF64AsFPR";
case MCK_GPRPairAsFPR: return "MCK_GPRPairAsFPR";
case MCK_GPRPairRV32: return "MCK_GPRPairRV32";
case MCK_GPRPairRV64: return "MCK_GPRPairRV64";
case MCK_Imm: return "MCK_Imm";
case MCK_ImmZero: return "MCK_ImmZero";
case MCK_InsnCDirectiveOpcode: return "MCK_InsnCDirectiveOpcode";
case MCK_InsnDirectiveOpcode: return "MCK_InsnDirectiveOpcode";
case MCK_LoadFPImm: return "MCK_LoadFPImm";
case MCK_NegStackAdj: return "MCK_NegStackAdj";
case MCK_PseudoJumpSymbol: return "MCK_PseudoJumpSymbol";
case MCK_RTZArg: return "MCK_RTZArg";
case MCK_Rlist: return "MCK_Rlist";
case MCK_RnumArg: return "MCK_RnumArg";
case MCK_SImm5Plus1: return "MCK_SImm5Plus1";
case MCK_SImm21Lsb0JAL: return "MCK_SImm21Lsb0JAL";
case MCK_StackAdj: return "MCK_StackAdj";
case MCK_TLSDESCCallSymbol: return "MCK_TLSDESCCallSymbol";
case MCK_TPRelAddSymbol: return "MCK_TPRelAddSymbol";
case MCK_UImmLog2XLen: return "MCK_UImmLog2XLen";
case MCK_UImmLog2XLenNonZero: return "MCK_UImmLog2XLenNonZero";
case MCK_RVVMaskRegOpOperand: return "MCK_RVVMaskRegOpOperand";
case MCK_ZeroOffsetMemOpOperand: return "MCK_ZeroOffsetMemOpOperand";
case MCK_VTypeI10: return "MCK_VTypeI10";
case MCK_VTypeI11: return "MCK_VTypeI11";
case MCK_SImm5: return "MCK_SImm5";
case MCK_SImm6: return "MCK_SImm6";
case MCK_SImm6NonZero: return "MCK_SImm6NonZero";
case MCK_UImm7Lsb00: return "MCK_UImm7Lsb00";
case MCK_UImm8Lsb00: return "MCK_UImm8Lsb00";
case MCK_UImm8Lsb000: return "MCK_UImm8Lsb000";
case MCK_SImm9Lsb0: return "MCK_SImm9Lsb0";
case MCK_UImm9Lsb000: return "MCK_UImm9Lsb000";
case MCK_UImm10Lsb00NonZero: return "MCK_UImm10Lsb00NonZero";
case MCK_SImm10Lsb0000NonZero: return "MCK_SImm10Lsb0000NonZero";
case MCK_SImm12Lsb0: return "MCK_SImm12Lsb0";
case MCK_UImm2Lsb0: return "MCK_UImm2Lsb0";
case MCK_UImm8GE32: return "MCK_UImm8GE32";
case MCK_SImm12Lsb00000: return "MCK_SImm12Lsb00000";
case MCK_UImm5Lsb0: return "MCK_UImm5Lsb0";
case MCK_UImm6Lsb0: return "MCK_UImm6Lsb0";
case MCK_UImm1: return "MCK_UImm1";
case MCK_UImm2: return "MCK_UImm2";
case MCK_UImm3: return "MCK_UImm3";
case MCK_UImm4: return "MCK_UImm4";
case MCK_UImm5: return "MCK_UImm5";
case MCK_UImm6: return "MCK_UImm6";
case MCK_UImm7: return "MCK_UImm7";
case MCK_UImm8: return "MCK_UImm8";
case MCK_UImm16: return "MCK_UImm16";
case MCK_UImm32: return "MCK_UImm32";
case MCK_SImm12: return "MCK_SImm12";
case MCK_SImm13Lsb0: return "MCK_SImm13Lsb0";
case MCK_UImm20LUI: return "MCK_UImm20LUI";
case MCK_UImm20AUIPC: return "MCK_UImm20AUIPC";
case MCK_UImm20: return "MCK_UImm20";
case MCK_ImmXLenLI: return "MCK_ImmXLenLI";
case MCK_ImmXLenLI_Restricted: return "MCK_ImmXLenLI_Restricted";
case NumMatchClassKinds: return "NumMatchClassKinds";
}
llvm_unreachable("unhandled MatchClassKind!");
}
#endif
FeatureBitset RISCVAsmParser::
ComputeAvailableFeatures(const FeatureBitset &FB) const {
FeatureBitset Features;
if (FB[RISCV::FeatureStdExtZicbom])
Features.set(Feature_HasStdExtZicbomBit);
if (FB[RISCV::FeatureStdExtZicbop])
Features.set(Feature_HasStdExtZicbopBit);
if (FB[RISCV::FeatureStdExtZicboz])
Features.set(Feature_HasStdExtZicbozBit);
if (FB[RISCV::FeatureStdExtZicsr])
Features.set(Feature_HasStdExtZicsrBit);
if (FB[RISCV::FeatureStdExtZicond])
Features.set(Feature_HasStdExtZicondBit);
if (FB[RISCV::FeatureStdExtZifencei])
Features.set(Feature_HasStdExtZifenceiBit);
if (FB[RISCV::FeatureStdExtZihintpause])
Features.set(Feature_HasStdExtZihintpauseBit);
if (FB[RISCV::FeatureStdExtZihintntl])
Features.set(Feature_HasStdExtZihintntlBit);
if (FB[RISCV::FeatureStdExtZimop])
Features.set(Feature_HasStdExtZimopBit);
if (FB[RISCV::FeatureStdExtZicfilp])
Features.set(Feature_HasStdExtZicfilpBit);
if (!FB[RISCV::FeatureStdExtZicfilp])
Features.set(Feature_NoStdExtZicfilpBit);
if (FB[RISCV::FeatureStdExtZicfiss])
Features.set(Feature_HasStdExtZicfissBit);
if (FB[RISCV::FeatureStdExtZmmul])
Features.set(Feature_HasStdExtZmmulBit);
if (FB[RISCV::FeatureStdExtM])
Features.set(Feature_HasStdExtMBit);
if (FB[RISCV::FeatureStdExtA])
Features.set(Feature_HasStdExtABit);
if (FB[RISCV::FeatureStdExtZtso])
Features.set(Feature_HasStdExtZtsoBit);
if (FB[RISCV::FeatureStdExtA] || FB[RISCV::FeatureStdExtZaamo])
Features.set(Feature_HasStdExtAOrZaamoBit);
if (FB[RISCV::FeatureStdExtZabha])
Features.set(Feature_HasStdExtZabhaBit);
if (FB[RISCV::FeatureStdExtZacas])
Features.set(Feature_HasStdExtZacasBit);
if (FB[RISCV::FeatureStdExtZalasr])
Features.set(Feature_HasStdExtZalasrBit);
if (FB[RISCV::FeatureStdExtA] || FB[RISCV::FeatureStdExtZalrsc])
Features.set(Feature_HasStdExtAOrZalrscBit);
if (FB[RISCV::FeatureStdExtZawrs])
Features.set(Feature_HasStdExtZawrsBit);
if (FB[RISCV::FeatureStdExtF])
Features.set(Feature_HasStdExtFBit);
if (FB[RISCV::FeatureStdExtD])
Features.set(Feature_HasStdExtDBit);
if (FB[RISCV::FeatureStdExtZfhmin])
Features.set(Feature_HasStdExtZfhminBit);
if (FB[RISCV::FeatureStdExtZfh])
Features.set(Feature_HasStdExtZfhBit);
if (FB[RISCV::FeatureStdExtZfbfmin])
Features.set(Feature_HasStdExtZfbfminBit);
if (FB[RISCV::FeatureStdExtZfh] || FB[RISCV::FeatureStdExtZfhmin] || FB[RISCV::FeatureStdExtZfbfmin])
Features.set(Feature_HasHalfFPLoadStoreMoveBit);
if (FB[RISCV::FeatureStdExtZfa])
Features.set(Feature_HasStdExtZfaBit);
if (FB[RISCV::FeatureStdExtZfinx])
Features.set(Feature_HasStdExtZfinxBit);
if (FB[RISCV::FeatureStdExtF] || FB[RISCV::FeatureStdExtZfinx])
Features.set(Feature_HasStdExtFOrZfinxBit);
if (FB[RISCV::FeatureStdExtZdinx])
Features.set(Feature_HasStdExtZdinxBit);
if (FB[RISCV::FeatureStdExtZhinxmin])
Features.set(Feature_HasStdExtZhinxminBit);
if (FB[RISCV::FeatureStdExtZhinx])
Features.set(Feature_HasStdExtZhinxBit);
if (FB[RISCV::FeatureStdExtC])
Features.set(Feature_HasStdExtCBit);
if (!FB[RISCV::FeatureNoRVCHints])
Features.set(Feature_HasRVCHintsBit);
if (FB[RISCV::FeatureStdExtC] || FB[RISCV::FeatureStdExtZca])
Features.set(Feature_HasStdExtCOrZcaBit);
if (FB[RISCV::FeatureStdExtZcb])
Features.set(Feature_HasStdExtZcbBit);
if (FB[RISCV::FeatureStdExtC] || FB[RISCV::FeatureStdExtZcd])
Features.set(Feature_HasStdExtCOrZcdBit);
if (FB[RISCV::FeatureStdExtZcmp])
Features.set(Feature_HasStdExtZcmpBit);
if (FB[RISCV::FeatureStdExtZcmt])
Features.set(Feature_HasStdExtZcmtBit);
if (FB[RISCV::FeatureStdExtC] || FB[RISCV::FeatureStdExtZcf] || FB[RISCV::FeatureStdExtZce])
Features.set(Feature_HasStdExtCOrZcfOrZceBit);
if (FB[RISCV::FeatureStdExtZcmop])
Features.set(Feature_HasStdExtZcmopBit);
if (FB[RISCV::FeatureStdExtZba])
Features.set(Feature_HasStdExtZbaBit);
if (FB[RISCV::FeatureStdExtZbb])
Features.set(Feature_HasStdExtZbbBit);
if (!FB[RISCV::FeatureStdExtZbb])
Features.set(Feature_NoStdExtZbbBit);
if (FB[RISCV::FeatureStdExtZbc])
Features.set(Feature_HasStdExtZbcBit);
if (FB[RISCV::FeatureStdExtZbs])
Features.set(Feature_HasStdExtZbsBit);
if (FB[RISCV::FeatureStdExtZbkb])
Features.set(Feature_HasStdExtZbkbBit);
if (FB[RISCV::FeatureStdExtZbkx])
Features.set(Feature_HasStdExtZbkxBit);
if (FB[RISCV::FeatureStdExtZbb] || FB[RISCV::FeatureStdExtZbkb])
Features.set(Feature_HasStdExtZbbOrZbkbBit);
if (FB[RISCV::FeatureStdExtZbkc])
Features.set(Feature_HasStdExtZbkcBit);
if (FB[RISCV::FeatureStdExtZbc] || FB[RISCV::FeatureStdExtZbkc])
Features.set(Feature_HasStdExtZbcOrZbkcBit);
if (FB[RISCV::FeatureStdExtZknd])
Features.set(Feature_HasStdExtZkndBit);
if (FB[RISCV::FeatureStdExtZkne])
Features.set(Feature_HasStdExtZkneBit);
if (FB[RISCV::FeatureStdExtZknd] || FB[RISCV::FeatureStdExtZkne])
Features.set(Feature_HasStdExtZkndOrZkneBit);
if (FB[RISCV::FeatureStdExtZknh])
Features.set(Feature_HasStdExtZknhBit);
if (FB[RISCV::FeatureStdExtZksed])
Features.set(Feature_HasStdExtZksedBit);
if (FB[RISCV::FeatureStdExtZksh])
Features.set(Feature_HasStdExtZkshBit);
if (FB[RISCV::FeatureStdExtZkr])
Features.set(Feature_HasStdExtZkrBit);
if (FB[RISCV::FeatureStdExtZvfbfmin])
Features.set(Feature_HasStdExtZvfbfminBit);
if (FB[RISCV::FeatureStdExtZvfbfwma])
Features.set(Feature_HasStdExtZvfbfwmaBit);
if (FB[RISCV::FeatureStdExtZfh] || FB[RISCV::FeatureStdExtZvfh])
Features.set(Feature_HasStdExtZfhOrZvfhBit);
if (FB[RISCV::FeatureStdExtZvkb])
Features.set(Feature_HasStdExtZvkbBit);
if (FB[RISCV::FeatureStdExtZvbb])
Features.set(Feature_HasStdExtZvbbBit);
if (FB[RISCV::FeatureStdExtZvbc])
Features.set(Feature_HasStdExtZvbcBit);
if (FB[RISCV::FeatureStdExtZvbc] || FB[RISCV::FeatureStdExtZvbc32e])
Features.set(Feature_HasStdExtZvbcOrZvbc32eBit);
if (FB[RISCV::FeatureStdExtZvkg])
Features.set(Feature_HasStdExtZvkgBit);
if (FB[RISCV::FeatureStdExtZvkgs])
Features.set(Feature_HasStdExtZvkgsBit);
if (FB[RISCV::FeatureStdExtZvkned])
Features.set(Feature_HasStdExtZvknedBit);
if (FB[RISCV::FeatureStdExtZvknha])
Features.set(Feature_HasStdExtZvknhaBit);
if (FB[RISCV::FeatureStdExtZvknhb])
Features.set(Feature_HasStdExtZvknhbBit);
if (FB[RISCV::FeatureStdExtZvknha] || FB[RISCV::FeatureStdExtZvknhb])
Features.set(Feature_HasStdExtZvknhaOrZvknhbBit);
if (FB[RISCV::FeatureStdExtZvksed])
Features.set(Feature_HasStdExtZvksedBit);
if (FB[RISCV::FeatureStdExtZvksh])
Features.set(Feature_HasStdExtZvkshBit);
if (FB[RISCV::FeatureStdExtZve32x])
Features.set(Feature_HasVInstructionsBit);
if (FB[RISCV::FeatureStdExtZve64x])
Features.set(Feature_HasVInstructionsI64Bit);
if (FB[RISCV::FeatureStdExtZve32f])
Features.set(Feature_HasVInstructionsAnyFBit);
if (FB[RISCV::FeatureStdExtZvfhmin] || FB[RISCV::FeatureStdExtZvfh])
Features.set(Feature_HasVInstructionsF16MinimalBit);
if (FB[RISCV::FeatureStdExtH])
Features.set(Feature_HasStdExtHBit);
if (FB[RISCV::FeatureStdExtSvinval])
Features.set(Feature_HasStdExtSvinvalBit);
if (FB[RISCV::FeatureStdExtSmctr] || FB[RISCV::FeatureStdExtSsctr])
Features.set(Feature_HasStdExtSmctrOrSsctrBit);
if (FB[RISCV::FeatureVendorXVentanaCondOps])
Features.set(Feature_HasVendorXVentanaCondOpsBit);
if (FB[RISCV::FeatureVendorXTHeadBa])
Features.set(Feature_HasVendorXTHeadBaBit);
if (FB[RISCV::FeatureVendorXTHeadBb])
Features.set(Feature_HasVendorXTHeadBbBit);
if (FB[RISCV::FeatureVendorXTHeadBs])
Features.set(Feature_HasVendorXTHeadBsBit);
if (FB[RISCV::FeatureVendorXTHeadCondMov])
Features.set(Feature_HasVendorXTHeadCondMovBit);
if (FB[RISCV::FeatureVendorXTHeadCmo])
Features.set(Feature_HasVendorXTHeadCmoBit);
if (FB[RISCV::FeatureVendorXTHeadFMemIdx])
Features.set(Feature_HasVendorXTHeadFMemIdxBit);
if (FB[RISCV::FeatureVendorXTHeadMac])
Features.set(Feature_HasVendorXTHeadMacBit);
if (FB[RISCV::FeatureVendorXTHeadMemIdx])
Features.set(Feature_HasVendorXTHeadMemIdxBit);
if (FB[RISCV::FeatureVendorXTHeadMemPair])
Features.set(Feature_HasVendorXTHeadMemPairBit);
if (FB[RISCV::FeatureVendorXTHeadSync])
Features.set(Feature_HasVendorXTHeadSyncBit);
if (FB[RISCV::FeatureVendorXTHeadVdot])
Features.set(Feature_HasVendorXTHeadVdotBit);
if (FB[RISCV::FeatureVendorXSfvcp])
Features.set(Feature_HasVendorXSfvcpBit);
if (FB[RISCV::FeatureVendorXSfvqmaccdod])
Features.set(Feature_HasVendorXSfvqmaccdodBit);
if (FB[RISCV::FeatureVendorXSfvqmaccqoq])
Features.set(Feature_HasVendorXSfvqmaccqoqBit);
if (FB[RISCV::FeatureVendorXSfvfwmaccqqq])
Features.set(Feature_HasVendorXSfvfwmaccqqqBit);
if (FB[RISCV::FeatureVendorXSfvfnrclipxfqf])
Features.set(Feature_HasVendorXSfvfnrclipxfqfBit);
if (FB[RISCV::FeatureVendorXSiFivecdiscarddlone])
Features.set(Feature_HasVendorXSiFivecdiscarddloneBit);
if (FB[RISCV::FeatureVendorXSiFivecflushdlone])
Features.set(Feature_HasVendorXSiFivecflushdloneBit);
if (FB[RISCV::FeatureVendorXSfcease])
Features.set(Feature_HasVendorXSfceaseBit);
if (FB[RISCV::FeatureVendorXCVelw])
Features.set(Feature_HasVendorXCVelwBit);
if (FB[RISCV::FeatureVendorXCVbitmanip])
Features.set(Feature_HasVendorXCVbitmanipBit);
if (FB[RISCV::FeatureVendorXCVmac])
Features.set(Feature_HasVendorXCVmacBit);
if (FB[RISCV::FeatureVendorXCVmem])
Features.set(Feature_HasVendorXCVmemBit);
if (FB[RISCV::FeatureVendorXCValu])
Features.set(Feature_HasVendorXCValuBit);
if (FB[RISCV::FeatureVendorXCVsimd])
Features.set(Feature_HasVendorXCVsimdBit);
if (FB[RISCV::FeatureVendorXCVbi])
Features.set(Feature_HasVendorXCVbiBit);
if (FB[RISCV::FeatureVendorXwchc])
Features.set(Feature_HasVendorXwchcBit);
if (FB[RISCV::Feature64Bit])
Features.set(Feature_IsRV64Bit);
if (!FB[RISCV::Feature64Bit])
Features.set(Feature_IsRV32Bit);
return Features;
}
static bool checkAsmTiedOperandConstraints(const RISCVAsmParser&AsmParser,
unsigned Kind, const OperandVector &Operands,
ArrayRef<unsigned> DefaultsOffset,
uint64_t &ErrorInfo) {
assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
const uint8_t *Converter = ConversionTable[Kind];
for (const uint8_t *p = Converter; *p; p += 2) {
switch (*p) {
case CVT_Tied: {
unsigned OpIdx = *(p + 1);
assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
std::begin(TiedAsmOperandTable)) &&
"Tied operand not found");
unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
OpndNum1 = OpndNum1 - DefaultsOffset[OpndNum1];
OpndNum2 = OpndNum2 - DefaultsOffset[OpndNum2];
if (OpndNum1 != OpndNum2) {
auto &SrcOp1 = Operands[OpndNum1];
auto &SrcOp2 = Operands[OpndNum2];
if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) {
ErrorInfo = OpndNum2;
return false;
}
}
break;
}
default:
break;
}
}
return true;
}
static const char MnemonicTable[] =
"\007.insn_b\010.insn_ca\010.insn_cb\010.insn_ci\t.insn_ciw\010.insn_cj\010"
".insn_cl\010.insn_cr\010.insn_cs\t.insn_css\007.insn_i\007.insn_j\007.i"
"nsn_r\010.insn_r4\007.insn_s\010.insn_sb\007.insn_u\010.insn_uj\003add\006"
"add.uw\004addi\005addiw\004addw\010aes32dsi\taes32dsmi\010aes32esi\taes"
"32esmi\007aes64ds\010aes64dsm\007aes64es\010aes64esm\007aes64im\taes64k"
"s1i\010aes64ks2\010amoadd.b\013amoadd.b.aq\015amoadd.b.aqrl\013amoadd.b"
".rl\010amoadd.d\013amoadd.d.aq\015amoadd.d.aqrl\013amoadd.d.rl\010amoad"
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".v\016vluxseg7ei16.v\016vluxseg7ei32.v\016vluxseg7ei64.v\015vluxseg7ei8"
".v\016vluxseg8ei16.v\016vluxseg8ei32.v\016vluxseg8ei64.v\015vluxseg8ei8"
".v\010vmacc.vv\010vmacc.vx\010vmadc.vi\tvmadc.vim\010vmadc.vv\tvmadc.vv"
"m\010vmadc.vx\tvmadc.vxm\010vmadd.vv\010vmadd.vx\010vmand.mm\tvmandn.mm"
"\013vmandnot.mm\007vmax.vv\007vmax.vx\010vmaxu.vv\010vmaxu.vx\007vmclr."
"m\nvmerge.vim\nvmerge.vvm\nvmerge.vxm\010vmfeq.vf\010vmfeq.vv\010vmfge."
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".vf\010vmflt.vv\010vmfne.vf\010vmfne.vv\007vmin.vv\007vmin.vx\010vminu."
"vv\010vminu.vx\006vmmv.m\tvmnand.mm\010vmnor.mm\007vmnot.m\007vmor.mm\010"
"vmorn.mm\nvmornot.mm\010vmsbc.vv\tvmsbc.vvm\010vmsbc.vx\tvmsbc.vxm\007v"
"msbf.m\010vmseq.vi\010vmseq.vv\010vmseq.vx\007vmset.m\010vmsge.vi\010vm"
"sge.vv\010vmsge.vx\tvmsgeu.vi\tvmsgeu.vv\tvmsgeu.vx\010vmsgt.vi\010vmsg"
"t.vv\010vmsgt.vx\tvmsgtu.vi\tvmsgtu.vv\tvmsgtu.vx\007vmsif.m\010vmsle.v"
"i\010vmsle.vv\010vmsle.vx\tvmsleu.vi\tvmsleu.vv\tvmsleu.vx\010vmslt.vi\010"
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"h.vx\nvmulhsu.vv\nvmulhsu.vx\tvmulhu.vv\tvmulhu.vx\007vmv.s.x\007vmv.v."
"i\007vmv.v.v\007vmv.v.x\007vmv.x.s\007vmv1r.v\007vmv2r.v\007vmv4r.v\007"
"vmv8r.v\tvmxnor.mm\010vmxor.mm\tvnclip.wi\tvnclip.wv\tvnclip.wx\nvnclip"
"u.wi\nvnclipu.wv\nvnclipu.wx\013vncvt.x.x.w\006vneg.v\tvnmsac.vv\tvnmsa"
"c.vx\tvnmsub.vv\tvnmsub.vx\006vnot.v\010vnsra.wi\010vnsra.wv\010vnsra.w"
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"\010vremu.vx\007vrev8.v\013vrgather.vi\013vrgather.vv\013vrgather.vx\017"
"vrgatherei16.vv\007vrol.vv\007vrol.vx\007vror.vi\007vror.vv\007vror.vx\010"
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"li\006vsetvl\007vsetvli\tvsext.vf2\tvsext.vf4\tvsext.vf8\nvsha2ch.vv\nv"
"sha2cl.vv\nvsha2ms.vv\016vslide1down.vx\014vslide1up.vx\015vslidedown.v"
"i\015vslidedown.vx\013vslideup.vi\013vslideup.vx\007vsll.vi\007vsll.vv\007"
"vsll.vx\005vsm.v\010vsm3c.vi\tvsm3me.vv\010vsm4k.vi\010vsm4r.vs\010vsm4"
"r.vv\010vsmul.vv\010vsmul.vx\nvsoxei16.v\nvsoxei32.v\nvsoxei64.v\tvsoxe"
"i8.v\016vsoxseg2ei16.v\016vsoxseg2ei32.v\016vsoxseg2ei64.v\015vsoxseg2e"
"i8.v\016vsoxseg3ei16.v\016vsoxseg3ei32.v\016vsoxseg3ei64.v\015vsoxseg3e"
"i8.v\016vsoxseg4ei16.v\016vsoxseg4ei32.v\016vsoxseg4ei64.v\015vsoxseg4e"
"i8.v\016vsoxseg5ei16.v\016vsoxseg5ei32.v\016vsoxseg5ei64.v\015vsoxseg5e"
"i8.v\016vsoxseg6ei16.v\016vsoxseg6ei32.v\016vsoxseg6ei64.v\015vsoxseg6e"
"i8.v\016vsoxseg7ei16.v\016vsoxseg7ei32.v\016vsoxseg7ei64.v\015vsoxseg7e"
"i8.v\016vsoxseg8ei16.v\016vsoxseg8ei32.v\016vsoxseg8ei64.v\015vsoxseg8e"
"i8.v\007vsra.vi\007vsra.vv\007vsra.vx\007vsrl.vi\007vsrl.vv\007vsrl.vx\010"
"vsse16.v\010vsse32.v\010vsse64.v\007vsse8.v\013vsseg2e16.v\013vsseg2e32"
".v\013vsseg2e64.v\nvsseg2e8.v\013vsseg3e16.v\013vsseg3e32.v\013vsseg3e6"
"4.v\nvsseg3e8.v\013vsseg4e16.v\013vsseg4e32.v\013vsseg4e64.v\nvsseg4e8."
"v\013vsseg5e16.v\013vsseg5e32.v\013vsseg5e64.v\nvsseg5e8.v\013vsseg6e16"
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"2.v\013vsseg7e64.v\nvsseg7e8.v\013vsseg8e16.v\013vsseg8e32.v\013vsseg8e"
"64.v\nvsseg8e8.v\010vssra.vi\010vssra.vv\010vssra.vx\010vssrl.vi\010vss"
"rl.vv\010vssrl.vx\014vssseg2e16.v\014vssseg2e32.v\014vssseg2e64.v\013vs"
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"v\014vssseg4e16.v\014vssseg4e32.v\014vssseg4e64.v\013vssseg4e8.v\014vss"
"seg5e16.v\014vssseg5e32.v\014vssseg5e64.v\013vssseg5e8.v\014vssseg6e16."
"v\014vssseg6e32.v\014vssseg6e64.v\013vssseg6e8.v\014vssseg7e16.v\014vss"
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"v\014vssseg8e64.v\013vssseg8e8.v\010vssub.vv\010vssub.vx\tvssubu.vv\tvs"
"subu.vx\007vsub.vv\007vsub.vx\nvsuxei16.v\nvsuxei32.v\nvsuxei64.v\tvsux"
"ei8.v\016vsuxseg2ei16.v\016vsuxseg2ei32.v\016vsuxseg2ei64.v\015vsuxseg2"
"ei8.v\016vsuxseg3ei16.v\016vsuxseg3ei32.v\016vsuxseg3ei64.v\015vsuxseg3"
"ei8.v\016vsuxseg4ei16.v\016vsuxseg4ei32.v\016vsuxseg4ei64.v\015vsuxseg4"
"ei8.v\016vsuxseg5ei16.v\016vsuxseg5ei32.v\016vsuxseg5ei64.v\015vsuxseg5"
"ei8.v\016vsuxseg6ei16.v\016vsuxseg6ei32.v\016vsuxseg6ei64.v\015vsuxseg6"
"ei8.v\016vsuxseg7ei16.v\016vsuxseg7ei32.v\016vsuxseg7ei64.v\015vsuxseg7"
"ei8.v\016vsuxseg8ei16.v\016vsuxseg8ei32.v\016vsuxseg8ei64.v\015vsuxseg8"
"ei8.v\010vt.maskc\tvt.maskcn\010vwadd.vv\010vwadd.vx\010vwadd.wv\010vwa"
"dd.wx\tvwaddu.vv\tvwaddu.vx\tvwaddu.wv\tvwaddu.wx\013vwcvt.x.x.v\014vwc"
"vtu.x.x.v\tvwmacc.vv\tvwmacc.vx\013vwmaccsu.vv\013vwmaccsu.vx\nvwmaccu."
"vv\nvwmaccu.vx\013vwmaccus.vx\010vwmul.vv\010vwmul.vx\nvwmulsu.vv\nvwmu"
"lsu.vx\tvwmulu.vv\tvwmulu.vx\013vwredsum.vs\014vwredsumu.vs\010vwsll.vi"
"\010vwsll.vv\010vwsll.vx\010vwsub.vv\010vwsub.vx\010vwsub.wv\010vwsub.w"
"x\tvwsubu.vv\tvwsubu.vx\tvwsubu.wv\tvwsubu.wx\007vxor.vi\007vxor.vv\007"
"vxor.vx\tvzext.vf2\tvzext.vf4\tvzext.vf8\003wfi\007wrs.nto\007wrs.sto\004"
"xnor\003xor\004xori\006xperm4\006xperm8\006zext.b\006zext.h\006zext.w\003"
"zip";
enum : uint8_t {
AMFBS_None,
AMFBS_HasHalfFPLoadStoreMove,
AMFBS_HasStdExtAOrZaamo,
AMFBS_HasStdExtAOrZalrsc,
AMFBS_HasStdExtCOrZca,
AMFBS_HasStdExtD,
AMFBS_HasStdExtF,
AMFBS_HasStdExtFOrZfinx,
AMFBS_HasStdExtH,
AMFBS_HasStdExtM,
AMFBS_HasStdExtSmctrOrSsctr,
AMFBS_HasStdExtSvinval,
AMFBS_HasStdExtZabha,
AMFBS_HasStdExtZacas,
AMFBS_HasStdExtZalasr,
AMFBS_HasStdExtZawrs,
AMFBS_HasStdExtZba,
AMFBS_HasStdExtZbb,
AMFBS_HasStdExtZbbOrZbkb,
AMFBS_HasStdExtZbc,
AMFBS_HasStdExtZbcOrZbkc,
AMFBS_HasStdExtZbkb,
AMFBS_HasStdExtZbkx,
AMFBS_HasStdExtZbs,
AMFBS_HasStdExtZcb,
AMFBS_HasStdExtZcmop,
AMFBS_HasStdExtZcmp,
AMFBS_HasStdExtZcmt,
AMFBS_HasStdExtZfa,
AMFBS_HasStdExtZfbfmin,
AMFBS_HasStdExtZfh,
AMFBS_HasStdExtZfhmin,
AMFBS_HasStdExtZfinx,
AMFBS_HasStdExtZhinx,
AMFBS_HasStdExtZhinxmin,
AMFBS_HasStdExtZicbom,
AMFBS_HasStdExtZicbop,
AMFBS_HasStdExtZicboz,
AMFBS_HasStdExtZicfilp,
AMFBS_HasStdExtZicfiss,
AMFBS_HasStdExtZicond,
AMFBS_HasStdExtZihintntl,
AMFBS_HasStdExtZihintpause,
AMFBS_HasStdExtZimop,
AMFBS_HasStdExtZknh,
AMFBS_HasStdExtZksed,
AMFBS_HasStdExtZksh,
AMFBS_HasStdExtZmmul,
AMFBS_HasStdExtZvbb,
AMFBS_HasStdExtZvbcOrZvbc32e,
AMFBS_HasStdExtZvfbfmin,
AMFBS_HasStdExtZvfbfwma,
AMFBS_HasStdExtZvkb,
AMFBS_HasStdExtZvkg,
AMFBS_HasStdExtZvkgs,
AMFBS_HasStdExtZvkned,
AMFBS_HasStdExtZvknhaOrZvknhb,
AMFBS_HasStdExtZvksed,
AMFBS_HasStdExtZvksh,
AMFBS_HasVInstructions,
AMFBS_HasVInstructionsAnyF,
AMFBS_HasVInstructionsI64,
AMFBS_HasVendorXSfcease,
AMFBS_HasVendorXSfvcp,
AMFBS_HasVendorXSfvfnrclipxfqf,
AMFBS_HasVendorXSfvfwmaccqqq,
AMFBS_HasVendorXSfvqmaccdod,
AMFBS_HasVendorXSfvqmaccqoq,
AMFBS_HasVendorXSiFivecdiscarddlone,
AMFBS_HasVendorXSiFivecflushdlone,
AMFBS_HasVendorXTHeadBa,
AMFBS_HasVendorXTHeadBb,
AMFBS_HasVendorXTHeadBs,
AMFBS_HasVendorXTHeadCmo,
AMFBS_HasVendorXTHeadCondMov,
AMFBS_HasVendorXTHeadMac,
AMFBS_HasVendorXTHeadMemIdx,
AMFBS_HasVendorXTHeadMemPair,
AMFBS_HasVendorXTHeadSync,
AMFBS_HasVendorXTHeadVdot,
AMFBS_HasVendorXVentanaCondOps,
AMFBS_HasVendorXwchc,
AMFBS_IsRV32,
AMFBS_IsRV64,
AMFBS_HasStdExtAOrZaamo_IsRV64,
AMFBS_HasStdExtAOrZalrsc_IsRV64,
AMFBS_HasStdExtCOrZca_HasRVCHints,
AMFBS_HasStdExtCOrZca_IsRV32,
AMFBS_HasStdExtCOrZca_IsRV64,
AMFBS_HasStdExtCOrZcd_HasStdExtD,
AMFBS_HasStdExtD_IsRV64,
AMFBS_HasStdExtF_IsRV64,
AMFBS_HasStdExtM_IsRV64,
AMFBS_HasStdExtZabha_HasStdExtZacas,
AMFBS_HasStdExtZacas_IsRV32,
AMFBS_HasStdExtZacas_IsRV64,
AMFBS_HasStdExtZalasr_IsRV64,
AMFBS_HasStdExtZba_IsRV64,
AMFBS_HasStdExtZbb_IsRV32,
AMFBS_HasStdExtZbb_IsRV64,
AMFBS_HasStdExtZbbOrZbkb_IsRV32,
AMFBS_HasStdExtZbbOrZbkb_IsRV64,
AMFBS_HasStdExtZbkb_IsRV32,
AMFBS_HasStdExtZbkb_IsRV64,
AMFBS_HasStdExtZcb_HasStdExtZbb,
AMFBS_HasStdExtZcb_HasStdExtZmmul,
AMFBS_HasStdExtZdinx_IsRV32,
AMFBS_HasStdExtZdinx_IsRV64,
AMFBS_HasStdExtZfa_HasStdExtD,
AMFBS_HasStdExtZfa_HasStdExtZfh,
AMFBS_HasStdExtZfa_HasStdExtZfhOrZvfh,
AMFBS_HasStdExtZfh_IsRV64,
AMFBS_HasStdExtZfhmin_HasStdExtD,
AMFBS_HasStdExtZfinx_IsRV64,
AMFBS_HasStdExtZhinx_IsRV64,
AMFBS_HasStdExtZicfiss_HasStdExtZcmop,
AMFBS_HasStdExtZicfiss_IsRV64,
AMFBS_HasStdExtZknd_IsRV32,
AMFBS_HasStdExtZknd_IsRV64,
AMFBS_HasStdExtZkndOrZkne_IsRV64,
AMFBS_HasStdExtZkne_IsRV32,
AMFBS_HasStdExtZkne_IsRV64,
AMFBS_HasStdExtZknh_IsRV32,
AMFBS_HasStdExtZknh_IsRV64,
AMFBS_HasStdExtZmmul_IsRV64,
AMFBS_HasVInstructionsI64_IsRV64,
AMFBS_HasVendorXCValu_IsRV32,
AMFBS_HasVendorXCVbi_IsRV32,
AMFBS_HasVendorXCVbitmanip_IsRV32,
AMFBS_HasVendorXCVelw_IsRV32,
AMFBS_HasVendorXCVmac_IsRV32,
AMFBS_HasVendorXCVmem_IsRV32,
AMFBS_HasVendorXCVsimd_IsRV32,
AMFBS_HasVendorXTHeadBb_IsRV64,
AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD,
AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF,
AMFBS_HasVendorXTHeadMac_IsRV64,
AMFBS_HasVendorXTHeadMemIdx_IsRV64,
AMFBS_HasVendorXTHeadMemPair_IsRV64,
AMFBS_IsRV64_HasStdExtH,
AMFBS_IsRV64_HasVInstructionsI64,
AMFBS_HasStdExtC_HasRVCHints_HasStdExtZihintntl,
AMFBS_HasStdExtCOrZcfOrZce_HasStdExtF_IsRV32,
AMFBS_HasStdExtZbkb_NoStdExtZbb_IsRV32,
AMFBS_HasStdExtZbkb_NoStdExtZbb_IsRV64,
AMFBS_HasStdExtZcb_HasStdExtZba_IsRV64,
AMFBS_HasStdExtZdinx_IsRV64_IsRV64,
AMFBS_HasStdExtZfa_HasStdExtD_IsRV32,
AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32,
AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64,
AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD_IsRV64,
AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF_IsRV64,
};
static constexpr FeatureBitset FeatureBitsets[] = {
{},
{Feature_HasHalfFPLoadStoreMoveBit, },
{Feature_HasStdExtAOrZaamoBit, },
{Feature_HasStdExtAOrZalrscBit, },
{Feature_HasStdExtCOrZcaBit, },
{Feature_HasStdExtDBit, },
{Feature_HasStdExtFBit, },
{Feature_HasStdExtFOrZfinxBit, },
{Feature_HasStdExtHBit, },
{Feature_HasStdExtMBit, },
{Feature_HasStdExtSmctrOrSsctrBit, },
{Feature_HasStdExtSvinvalBit, },
{Feature_HasStdExtZabhaBit, },
{Feature_HasStdExtZacasBit, },
{Feature_HasStdExtZalasrBit, },
{Feature_HasStdExtZawrsBit, },
{Feature_HasStdExtZbaBit, },
{Feature_HasStdExtZbbBit, },
{Feature_HasStdExtZbbOrZbkbBit, },
{Feature_HasStdExtZbcBit, },
{Feature_HasStdExtZbcOrZbkcBit, },
{Feature_HasStdExtZbkbBit, },
{Feature_HasStdExtZbkxBit, },
{Feature_HasStdExtZbsBit, },
{Feature_HasStdExtZcbBit, },
{Feature_HasStdExtZcmopBit, },
{Feature_HasStdExtZcmpBit, },
{Feature_HasStdExtZcmtBit, },
{Feature_HasStdExtZfaBit, },
{Feature_HasStdExtZfbfminBit, },
{Feature_HasStdExtZfhBit, },
{Feature_HasStdExtZfhminBit, },
{Feature_HasStdExtZfinxBit, },
{Feature_HasStdExtZhinxBit, },
{Feature_HasStdExtZhinxminBit, },
{Feature_HasStdExtZicbomBit, },
{Feature_HasStdExtZicbopBit, },
{Feature_HasStdExtZicbozBit, },
{Feature_HasStdExtZicfilpBit, },
{Feature_HasStdExtZicfissBit, },
{Feature_HasStdExtZicondBit, },
{Feature_HasStdExtZihintntlBit, },
{Feature_HasStdExtZihintpauseBit, },
{Feature_HasStdExtZimopBit, },
{Feature_HasStdExtZknhBit, },
{Feature_HasStdExtZksedBit, },
{Feature_HasStdExtZkshBit, },
{Feature_HasStdExtZmmulBit, },
{Feature_HasStdExtZvbbBit, },
{Feature_HasStdExtZvbcOrZvbc32eBit, },
{Feature_HasStdExtZvfbfminBit, },
{Feature_HasStdExtZvfbfwmaBit, },
{Feature_HasStdExtZvkbBit, },
{Feature_HasStdExtZvkgBit, },
{Feature_HasStdExtZvkgsBit, },
{Feature_HasStdExtZvknedBit, },
{Feature_HasStdExtZvknhaOrZvknhbBit, },
{Feature_HasStdExtZvksedBit, },
{Feature_HasStdExtZvkshBit, },
{Feature_HasVInstructionsBit, },
{Feature_HasVInstructionsAnyFBit, },
{Feature_HasVInstructionsI64Bit, },
{Feature_HasVendorXSfceaseBit, },
{Feature_HasVendorXSfvcpBit, },
{Feature_HasVendorXSfvfnrclipxfqfBit, },
{Feature_HasVendorXSfvfwmaccqqqBit, },
{Feature_HasVendorXSfvqmaccdodBit, },
{Feature_HasVendorXSfvqmaccqoqBit, },
{Feature_HasVendorXSiFivecdiscarddloneBit, },
{Feature_HasVendorXSiFivecflushdloneBit, },
{Feature_HasVendorXTHeadBaBit, },
{Feature_HasVendorXTHeadBbBit, },
{Feature_HasVendorXTHeadBsBit, },
{Feature_HasVendorXTHeadCmoBit, },
{Feature_HasVendorXTHeadCondMovBit, },
{Feature_HasVendorXTHeadMacBit, },
{Feature_HasVendorXTHeadMemIdxBit, },
{Feature_HasVendorXTHeadMemPairBit, },
{Feature_HasVendorXTHeadSyncBit, },
{Feature_HasVendorXTHeadVdotBit, },
{Feature_HasVendorXVentanaCondOpsBit, },
{Feature_HasVendorXwchcBit, },
{Feature_IsRV32Bit, },
{Feature_IsRV64Bit, },
{Feature_HasStdExtAOrZaamoBit, Feature_IsRV64Bit, },
{Feature_HasStdExtAOrZalrscBit, Feature_IsRV64Bit, },
{Feature_HasStdExtCOrZcaBit, Feature_HasRVCHintsBit, },
{Feature_HasStdExtCOrZcaBit, Feature_IsRV32Bit, },
{Feature_HasStdExtCOrZcaBit, Feature_IsRV64Bit, },
{Feature_HasStdExtCOrZcdBit, Feature_HasStdExtDBit, },
{Feature_HasStdExtDBit, Feature_IsRV64Bit, },
{Feature_HasStdExtFBit, Feature_IsRV64Bit, },
{Feature_HasStdExtMBit, Feature_IsRV64Bit, },
{Feature_HasStdExtZabhaBit, Feature_HasStdExtZacasBit, },
{Feature_HasStdExtZacasBit, Feature_IsRV32Bit, },
{Feature_HasStdExtZacasBit, Feature_IsRV64Bit, },
{Feature_HasStdExtZalasrBit, Feature_IsRV64Bit, },
{Feature_HasStdExtZbaBit, Feature_IsRV64Bit, },
{Feature_HasStdExtZbbBit, Feature_IsRV32Bit, },
{Feature_HasStdExtZbbBit, Feature_IsRV64Bit, },
{Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV32Bit, },
{Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV64Bit, },
{Feature_HasStdExtZbkbBit, Feature_IsRV32Bit, },
{Feature_HasStdExtZbkbBit, Feature_IsRV64Bit, },
{Feature_HasStdExtZcbBit, Feature_HasStdExtZbbBit, },
{Feature_HasStdExtZcbBit, Feature_HasStdExtZmmulBit, },
{Feature_HasStdExtZdinxBit, Feature_IsRV32Bit, },
{Feature_HasStdExtZdinxBit, Feature_IsRV64Bit, },
{Feature_HasStdExtZfaBit, Feature_HasStdExtDBit, },
{Feature_HasStdExtZfaBit, Feature_HasStdExtZfhBit, },
{Feature_HasStdExtZfaBit, Feature_HasStdExtZfhOrZvfhBit, },
{Feature_HasStdExtZfhBit, Feature_IsRV64Bit, },
{Feature_HasStdExtZfhminBit, Feature_HasStdExtDBit, },
{Feature_HasStdExtZfinxBit, Feature_IsRV64Bit, },
{Feature_HasStdExtZhinxBit, Feature_IsRV64Bit, },
{Feature_HasStdExtZicfissBit, Feature_HasStdExtZcmopBit, },
{Feature_HasStdExtZicfissBit, Feature_IsRV64Bit, },
{Feature_HasStdExtZkndBit, Feature_IsRV32Bit, },
{Feature_HasStdExtZkndBit, Feature_IsRV64Bit, },
{Feature_HasStdExtZkndOrZkneBit, Feature_IsRV64Bit, },
{Feature_HasStdExtZkneBit, Feature_IsRV32Bit, },
{Feature_HasStdExtZkneBit, Feature_IsRV64Bit, },
{Feature_HasStdExtZknhBit, Feature_IsRV32Bit, },
{Feature_HasStdExtZknhBit, Feature_IsRV64Bit, },
{Feature_HasStdExtZmmulBit, Feature_IsRV64Bit, },
{Feature_HasVInstructionsI64Bit, Feature_IsRV64Bit, },
{Feature_HasVendorXCValuBit, Feature_IsRV32Bit, },
{Feature_HasVendorXCVbiBit, Feature_IsRV32Bit, },
{Feature_HasVendorXCVbitmanipBit, Feature_IsRV32Bit, },
{Feature_HasVendorXCVelwBit, Feature_IsRV32Bit, },
{Feature_HasVendorXCVmacBit, Feature_IsRV32Bit, },
{Feature_HasVendorXCVmemBit, Feature_IsRV32Bit, },
{Feature_HasVendorXCVsimdBit, Feature_IsRV32Bit, },
{Feature_HasVendorXTHeadBbBit, Feature_IsRV64Bit, },
{Feature_HasVendorXTHeadFMemIdxBit, Feature_HasStdExtDBit, },
{Feature_HasVendorXTHeadFMemIdxBit, Feature_HasStdExtFBit, },
{Feature_HasVendorXTHeadMacBit, Feature_IsRV64Bit, },
{Feature_HasVendorXTHeadMemIdxBit, Feature_IsRV64Bit, },
{Feature_HasVendorXTHeadMemPairBit, Feature_IsRV64Bit, },
{Feature_IsRV64Bit, Feature_HasStdExtHBit, },
{Feature_IsRV64Bit, Feature_HasVInstructionsI64Bit, },
{Feature_HasStdExtCBit, Feature_HasRVCHintsBit, Feature_HasStdExtZihintntlBit, },
{Feature_HasStdExtCOrZcfOrZceBit, Feature_HasStdExtFBit, Feature_IsRV32Bit, },
{Feature_HasStdExtZbkbBit, Feature_NoStdExtZbbBit, Feature_IsRV32Bit, },
{Feature_HasStdExtZbkbBit, Feature_NoStdExtZbbBit, Feature_IsRV64Bit, },
{Feature_HasStdExtZcbBit, Feature_HasStdExtZbaBit, Feature_IsRV64Bit, },
{Feature_HasStdExtZdinxBit, Feature_IsRV64Bit, Feature_IsRV64Bit, },
{Feature_HasStdExtZfaBit, Feature_HasStdExtDBit, Feature_IsRV32Bit, },
{Feature_HasStdExtZhinxminBit, Feature_HasStdExtZdinxBit, Feature_IsRV32Bit, },
{Feature_HasStdExtZhinxminBit, Feature_HasStdExtZdinxBit, Feature_IsRV64Bit, },
{Feature_HasVendorXTHeadFMemIdxBit, Feature_HasStdExtDBit, Feature_IsRV64Bit, },
{Feature_HasVendorXTHeadFMemIdxBit, Feature_HasStdExtFBit, Feature_IsRV64Bit, },
};
namespace {
struct MatchEntry {
uint16_t Mnemonic;
uint16_t Opcode;
uint16_t ConvertFn;
uint8_t RequiredFeaturesIdx;
uint8_t Classes[7];
StringRef getMnemonic() const {
return StringRef(MnemonicTable + Mnemonic + 1,
MnemonicTable[Mnemonic]);
}
};
struct LessOpcode {
bool operator()(const MatchEntry &LHS, StringRef RHS) {
return LHS.getMnemonic() < RHS;
}
bool operator()(StringRef LHS, const MatchEntry &RHS) {
return LHS < RHS.getMnemonic();
}
bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
return LHS.getMnemonic() < RHS.getMnemonic();
}
};
}
static const MatchEntry MatchTable0[] = {
{ 0 , RISCV::InsnB, Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_3__SImm13Lsb01_4, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_SImm13Lsb0 }, },
{ 8 , RISCV::InsnCA, Convert__AnyRegCOperand1_3__InsnCDirectiveOpcode1_0__UImm61_1__UImm21_2__AnyRegCOperand1_4, AMFBS_HasStdExtCOrZca, { MCK_InsnCDirectiveOpcode, MCK_UImm6, MCK_UImm2, MCK_AnyRegCOperand, MCK_AnyRegCOperand }, },
{ 17 , RISCV::InsnCB, Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__SImm9Lsb01_3, AMFBS_HasStdExtCOrZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK_SImm9Lsb0 }, },
{ 26 , RISCV::InsnCI, Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__SImm61_3, AMFBS_HasStdExtCOrZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_SImm6 }, },
{ 35 , RISCV::InsnCIW, Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__UImm81_3, AMFBS_HasStdExtCOrZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK_UImm8 }, },
{ 45 , RISCV::InsnCJ, Convert__InsnCDirectiveOpcode1_0__UImm31_1__SImm12Lsb01_2, AMFBS_HasStdExtCOrZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_SImm12Lsb0 }, },
{ 54 , RISCV::InsnCL, Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_4__imm_95_0, AMFBS_HasStdExtCOrZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK__40_, MCK_AnyRegCOperand, MCK__41_ }, },
{ 54 , RISCV::InsnCL, Convert__AnyRegCOperand1_2__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_5__UImm51_3, AMFBS_HasStdExtCOrZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK_UImm5, MCK__40_, MCK_AnyRegCOperand, MCK__41_ }, },
{ 63 , RISCV::InsnCR, Convert__AnyRegOperand1_2__InsnCDirectiveOpcode1_0__UImm41_1__AnyRegOperand1_3, AMFBS_HasStdExtCOrZca, { MCK_InsnCDirectiveOpcode, MCK_UImm4, MCK_AnyRegOperand, MCK_AnyRegOperand }, },
{ 72 , RISCV::InsnCS, Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_4__imm_95_0, AMFBS_HasStdExtCOrZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK__40_, MCK_AnyRegCOperand, MCK__41_ }, },
{ 72 , RISCV::InsnCS, Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegCOperand1_2__AnyRegCOperand1_5__UImm51_3, AMFBS_HasStdExtCOrZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegCOperand, MCK_UImm5, MCK__40_, MCK_AnyRegCOperand, MCK__41_ }, },
{ 81 , RISCV::InsnCSS, Convert__InsnCDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__UImm61_3, AMFBS_HasStdExtCOrZca, { MCK_InsnCDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_UImm6 }, },
{ 91 , RISCV::InsnI, Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_3__SImm121_4, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_SImm12 }, },
{ 91 , RISCV::InsnI_Mem, Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_4__imm_95_0, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
{ 91 , RISCV::InsnI_Mem, Convert__AnyRegOperand1_2__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_5__SImm121_3, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_SImm12, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
{ 99 , RISCV::InsnJ, Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__SImm21Lsb0JAL1_2, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_AnyRegOperand, MCK_SImm21Lsb0JAL }, },
{ 107 , RISCV::InsnR, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm71_2__AnyRegOperand1_4__AnyRegOperand1_5, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm7, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand }, },
{ 107 , RISCV::InsnR4, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__AnyRegOperand1_5__AnyRegOperand1_6, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand }, },
{ 115 , RISCV::InsnR4, Convert__AnyRegOperand1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__AnyRegOperand1_4__AnyRegOperand1_5__AnyRegOperand1_6, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_UImm2, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_AnyRegOperand }, },
{ 124 , RISCV::InsnS, Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_4__imm_95_0, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
{ 124 , RISCV::InsnS, Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_5__SImm121_3, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_SImm12, MCK__40_, MCK_AnyRegOperand, MCK__41_ }, },
{ 132 , RISCV::InsnB, Convert__InsnDirectiveOpcode1_0__UImm31_1__AnyRegOperand1_2__AnyRegOperand1_3__SImm13Lsb01_4, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_UImm3, MCK_AnyRegOperand, MCK_AnyRegOperand, MCK_SImm13Lsb0 }, },
{ 141 , RISCV::InsnU, Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__UImm20LUI1_2, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_AnyRegOperand, MCK_UImm20LUI }, },
{ 149 , RISCV::InsnJ, Convert__AnyRegOperand1_1__InsnDirectiveOpcode1_0__SImm21Lsb0JAL1_2, AMFBS_None, { MCK_InsnDirectiveOpcode, MCK_AnyRegOperand, MCK_SImm21Lsb0JAL }, },
{ 158 , RISCV::ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 158 , RISCV::ADDI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
{ 158 , RISCV::PseudoAddTPRel, Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_TPRelAddSymbol }, },
{ 162 , RISCV::ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 169 , RISCV::ADDI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
{ 174 , RISCV::ADDIW, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
{ 180 , RISCV::ADDW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 180 , RISCV::ADDIW, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
{ 185 , RISCV::AES32DSI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZknd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 194 , RISCV::AES32DSMI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZknd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 204 , RISCV::AES32ESI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZkne_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 213 , RISCV::AES32ESMI, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZkne_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 223 , RISCV::AES64DS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknd_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 231 , RISCV::AES64DSM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknd_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 240 , RISCV::AES64ES, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 248 , RISCV::AES64ESM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 257 , RISCV::AES64IM, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknd_IsRV64, { MCK_GPR, MCK_GPR }, },
{ 265 , RISCV::AES64KS1I, Convert__Reg1_0__Reg1_1__RnumArg1_2, AMFBS_HasStdExtZkndOrZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_RnumArg }, },
{ 275 , RISCV::AES64KS2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZkndOrZkne_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 284 , RISCV::AMOADD_B, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 293 , RISCV::AMOADD_B_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 305 , RISCV::AMOADD_B_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 319 , RISCV::AMOADD_B_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 331 , RISCV::AMOADD_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 340 , RISCV::AMOADD_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 352 , RISCV::AMOADD_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 366 , RISCV::AMOADD_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 378 , RISCV::AMOADD_H, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 387 , RISCV::AMOADD_H_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 399 , RISCV::AMOADD_H_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 413 , RISCV::AMOADD_H_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 425 , RISCV::AMOADD_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 434 , RISCV::AMOADD_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 446 , RISCV::AMOADD_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 460 , RISCV::AMOADD_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 472 , RISCV::AMOAND_B, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 481 , RISCV::AMOAND_B_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 493 , RISCV::AMOAND_B_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 507 , RISCV::AMOAND_B_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 519 , RISCV::AMOAND_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 528 , RISCV::AMOAND_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 540 , RISCV::AMOAND_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 554 , RISCV::AMOAND_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 566 , RISCV::AMOAND_H, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 575 , RISCV::AMOAND_H_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 587 , RISCV::AMOAND_H_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 601 , RISCV::AMOAND_H_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 613 , RISCV::AMOAND_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 622 , RISCV::AMOAND_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 634 , RISCV::AMOAND_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 648 , RISCV::AMOAND_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 660 , RISCV::AMOCAS_B, Convert__Reg1_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 669 , RISCV::AMOCAS_B_AQ, Convert__Reg1_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 681 , RISCV::AMOCAS_B_AQ_RL, Convert__Reg1_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 695 , RISCV::AMOCAS_B_RL, Convert__Reg1_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 707 , RISCV::AMOCAS_D_RV64, Convert__Reg1_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 707 , RISCV::AMOCAS_D_RV32, Convert__GPRPairRV321_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__GPRPairRV321_1, AMFBS_HasStdExtZacas_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_ZeroOffsetMemOpOperand }, },
{ 716 , RISCV::AMOCAS_D_RV64_AQ, Convert__Reg1_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 716 , RISCV::AMOCAS_D_RV32_AQ, Convert__GPRPairRV321_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__GPRPairRV321_1, AMFBS_HasStdExtZacas_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_ZeroOffsetMemOpOperand }, },
{ 728 , RISCV::AMOCAS_D_RV64_AQ_RL, Convert__Reg1_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 728 , RISCV::AMOCAS_D_RV32_AQ_RL, Convert__GPRPairRV321_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__GPRPairRV321_1, AMFBS_HasStdExtZacas_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_ZeroOffsetMemOpOperand }, },
{ 742 , RISCV::AMOCAS_D_RV64_RL, Convert__Reg1_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 742 , RISCV::AMOCAS_D_RV32_RL, Convert__GPRPairRV321_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__GPRPairRV321_1, AMFBS_HasStdExtZacas_IsRV32, { MCK_GPRPairRV32, MCK_GPRPairRV32, MCK_ZeroOffsetMemOpOperand }, },
{ 754 , RISCV::AMOCAS_H, Convert__Reg1_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 763 , RISCV::AMOCAS_H_AQ, Convert__Reg1_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 775 , RISCV::AMOCAS_H_AQ_RL, Convert__Reg1_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 789 , RISCV::AMOCAS_H_RL, Convert__Reg1_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 801 , RISCV::AMOCAS_Q, Convert__GPRPairRV641_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__GPRPairRV641_1, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPRPairRV64, MCK_GPRPairRV64, MCK_ZeroOffsetMemOpOperand }, },
{ 810 , RISCV::AMOCAS_Q_AQ, Convert__GPRPairRV641_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__GPRPairRV641_1, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPRPairRV64, MCK_GPRPairRV64, MCK_ZeroOffsetMemOpOperand }, },
{ 822 , RISCV::AMOCAS_Q_AQ_RL, Convert__GPRPairRV641_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__GPRPairRV641_1, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPRPairRV64, MCK_GPRPairRV64, MCK_ZeroOffsetMemOpOperand }, },
{ 836 , RISCV::AMOCAS_Q_RL, Convert__GPRPairRV641_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__GPRPairRV641_1, AMFBS_HasStdExtZacas_IsRV64, { MCK_GPRPairRV64, MCK_GPRPairRV64, MCK_ZeroOffsetMemOpOperand }, },
{ 848 , RISCV::AMOCAS_W, Convert__Reg1_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 857 , RISCV::AMOCAS_W_AQ, Convert__Reg1_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 869 , RISCV::AMOCAS_W_AQ_RL, Convert__Reg1_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 883 , RISCV::AMOCAS_W_RL, Convert__Reg1_0__Tie0_1_1__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZacas, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 895 , RISCV::AMOMAX_B, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 904 , RISCV::AMOMAX_B_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 916 , RISCV::AMOMAX_B_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 930 , RISCV::AMOMAX_B_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 942 , RISCV::AMOMAX_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 951 , RISCV::AMOMAX_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 963 , RISCV::AMOMAX_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 977 , RISCV::AMOMAX_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 989 , RISCV::AMOMAX_H, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 998 , RISCV::AMOMAX_H_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1010 , RISCV::AMOMAX_H_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1024 , RISCV::AMOMAX_H_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1036 , RISCV::AMOMAX_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1045 , RISCV::AMOMAX_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1057 , RISCV::AMOMAX_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1071 , RISCV::AMOMAX_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1083 , RISCV::AMOMAXU_B, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1093 , RISCV::AMOMAXU_B_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1106 , RISCV::AMOMAXU_B_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1121 , RISCV::AMOMAXU_B_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1134 , RISCV::AMOMAXU_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1144 , RISCV::AMOMAXU_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1157 , RISCV::AMOMAXU_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1172 , RISCV::AMOMAXU_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1185 , RISCV::AMOMAXU_H, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1195 , RISCV::AMOMAXU_H_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1208 , RISCV::AMOMAXU_H_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1223 , RISCV::AMOMAXU_H_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1236 , RISCV::AMOMAXU_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1246 , RISCV::AMOMAXU_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1259 , RISCV::AMOMAXU_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1274 , RISCV::AMOMAXU_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1287 , RISCV::AMOMIN_B, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1296 , RISCV::AMOMIN_B_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1308 , RISCV::AMOMIN_B_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1322 , RISCV::AMOMIN_B_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1334 , RISCV::AMOMIN_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1343 , RISCV::AMOMIN_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1355 , RISCV::AMOMIN_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1369 , RISCV::AMOMIN_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1381 , RISCV::AMOMIN_H, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1390 , RISCV::AMOMIN_H_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1402 , RISCV::AMOMIN_H_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1416 , RISCV::AMOMIN_H_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1428 , RISCV::AMOMIN_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1437 , RISCV::AMOMIN_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1449 , RISCV::AMOMIN_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1463 , RISCV::AMOMIN_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1475 , RISCV::AMOMINU_B, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1485 , RISCV::AMOMINU_B_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1498 , RISCV::AMOMINU_B_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1513 , RISCV::AMOMINU_B_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1526 , RISCV::AMOMINU_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1536 , RISCV::AMOMINU_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1549 , RISCV::AMOMINU_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1564 , RISCV::AMOMINU_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1577 , RISCV::AMOMINU_H, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1587 , RISCV::AMOMINU_H_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1600 , RISCV::AMOMINU_H_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1615 , RISCV::AMOMINU_H_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1628 , RISCV::AMOMINU_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1638 , RISCV::AMOMINU_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1651 , RISCV::AMOMINU_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1666 , RISCV::AMOMINU_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1679 , RISCV::AMOOR_B, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1687 , RISCV::AMOOR_B_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1698 , RISCV::AMOOR_B_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1711 , RISCV::AMOOR_B_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1722 , RISCV::AMOOR_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1730 , RISCV::AMOOR_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1741 , RISCV::AMOOR_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1754 , RISCV::AMOOR_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1765 , RISCV::AMOOR_H, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1773 , RISCV::AMOOR_H_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1784 , RISCV::AMOOR_H_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1797 , RISCV::AMOOR_H_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1808 , RISCV::AMOOR_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1816 , RISCV::AMOOR_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1827 , RISCV::AMOOR_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1840 , RISCV::AMOOR_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1851 , RISCV::AMOSWAP_B, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1861 , RISCV::AMOSWAP_B_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1874 , RISCV::AMOSWAP_B_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1889 , RISCV::AMOSWAP_B_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1902 , RISCV::AMOSWAP_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1912 , RISCV::AMOSWAP_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1925 , RISCV::AMOSWAP_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1940 , RISCV::AMOSWAP_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1953 , RISCV::AMOSWAP_H, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1963 , RISCV::AMOSWAP_H_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1976 , RISCV::AMOSWAP_H_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 1991 , RISCV::AMOSWAP_H_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 2004 , RISCV::AMOSWAP_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 2014 , RISCV::AMOSWAP_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 2027 , RISCV::AMOSWAP_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 2042 , RISCV::AMOSWAP_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 2055 , RISCV::AMOXOR_B, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 2064 , RISCV::AMOXOR_B_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 2076 , RISCV::AMOXOR_B_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 2090 , RISCV::AMOXOR_B_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 2102 , RISCV::AMOXOR_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 2111 , RISCV::AMOXOR_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 2123 , RISCV::AMOXOR_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 2137 , RISCV::AMOXOR_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 2149 , RISCV::AMOXOR_H, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 2158 , RISCV::AMOXOR_H_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 2170 , RISCV::AMOXOR_H_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 2184 , RISCV::AMOXOR_H_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZabha, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 2196 , RISCV::AMOXOR_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 2205 , RISCV::AMOXOR_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 2217 , RISCV::AMOXOR_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 2231 , RISCV::AMOXOR_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZaamo, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 2243 , RISCV::AND, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 2243 , RISCV::ANDI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
{ 2247 , RISCV::ANDI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
{ 2252 , RISCV::ANDN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 2257 , RISCV::AUIPC, Convert__Reg1_0__UImm20AUIPC1_1, AMFBS_None, { MCK_GPR, MCK_UImm20AUIPC }, },
{ 2263 , RISCV::BCLR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 2263 , RISCV::BCLRI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
{ 2268 , RISCV::BCLRI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
{ 2274 , RISCV::BEQ, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, },
{ 2278 , RISCV::BEQ, Convert__Reg1_0__regX0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, },
{ 2283 , RISCV::BEXT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 2283 , RISCV::BEXTI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
{ 2288 , RISCV::BEXTI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
{ 2294 , RISCV::BGE, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, },
{ 2298 , RISCV::BGEU, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, },
{ 2303 , RISCV::BGE, Convert__Reg1_0__regX0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, },
{ 2308 , RISCV::BLT, Convert__Reg1_1__Reg1_0__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, },
{ 2312 , RISCV::BLTU, Convert__Reg1_1__Reg1_0__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, },
{ 2317 , RISCV::BLT, Convert__regX0__Reg1_0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, },
{ 2322 , RISCV::BINV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 2322 , RISCV::BINVI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
{ 2327 , RISCV::BINVI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
{ 2333 , RISCV::BGE, Convert__Reg1_1__Reg1_0__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, },
{ 2337 , RISCV::BGEU, Convert__Reg1_1__Reg1_0__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, },
{ 2342 , RISCV::BGE, Convert__regX0__Reg1_0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, },
{ 2347 , RISCV::BLT, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, },
{ 2351 , RISCV::BLTU, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, },
{ 2356 , RISCV::BLT, Convert__Reg1_0__regX0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, },
{ 2361 , RISCV::BNE, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, },
{ 2365 , RISCV::BNE, Convert__Reg1_0__regX0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, },
{ 2370 , RISCV::BREV8, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbkb, { MCK_GPR, MCK_GPR }, },
{ 2376 , RISCV::BSET, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 2376 , RISCV::BSETI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
{ 2381 , RISCV::BSETI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
{ 2387 , RISCV::C_ADD_HINT, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_GPRX0, MCK_GPRNoX0 }, },
{ 2387 , RISCV::C_ADD, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
{ 2393 , RISCV::C_ADDI_NOP, Convert__Reg1_0__Tie0_1_1__ImmZero1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRX0, MCK_ImmZero }, },
{ 2393 , RISCV::C_NOP_HINT, Convert__SImm6NonZero1_1, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_GPRX0, MCK_SImm6NonZero }, },
{ 2393 , RISCV::C_ADDI_HINT_IMM_ZERO, Convert__Reg1_0__Tie0_1_1__ImmZero1_1, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_GPRNoX0, MCK_ImmZero }, },
{ 2393 , RISCV::C_ADDI, Convert__Reg1_0__Tie0_1_1__SImm6NonZero1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRNoX0, MCK_SImm6NonZero }, },
{ 2400 , RISCV::C_ADDI16SP, Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1, AMFBS_HasStdExtCOrZca, { MCK_SP, MCK_SImm10Lsb0000NonZero }, },
{ 2411 , RISCV::C_ADDI4SPN, Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_SP, MCK_UImm10Lsb00NonZero }, },
{ 2422 , RISCV::C_ADDIW, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPRNoX0, MCK_SImm6 }, },
{ 2430 , RISCV::C_ADDW, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPRC, MCK_GPRC }, },
{ 2437 , RISCV::C_AND, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_GPRC }, },
{ 2443 , RISCV::C_ANDI, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_SImm6 }, },
{ 2450 , RISCV::C_BEQZ, Convert__Reg1_0__SImm9Lsb01_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_SImm9Lsb0 }, },
{ 2457 , RISCV::C_BNEZ, Convert__Reg1_0__SImm9Lsb01_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_SImm9Lsb0 }, },
{ 2464 , RISCV::C_EBREAK, Convert_NoOperands, AMFBS_HasStdExtCOrZca, { }, },
{ 2473 , RISCV::C_FLD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64C, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2473 , RISCV::C_FLD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64C, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2479 , RISCV::C_FLDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64, MCK__40_, MCK_SP, MCK__41_ }, },
{ 2479 , RISCV::C_FLDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
{ 2487 , RISCV::C_FLW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcfOrZce_HasStdExtF_IsRV32, { MCK_FPR32C, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2487 , RISCV::C_FLW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtCOrZcfOrZce_HasStdExtF_IsRV32, { MCK_FPR32C, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2493 , RISCV::C_FLWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcfOrZce_HasStdExtF_IsRV32, { MCK_FPR32, MCK__40_, MCK_SP, MCK__41_ }, },
{ 2493 , RISCV::C_FLWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtCOrZcfOrZce_HasStdExtF_IsRV32, { MCK_FPR32, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
{ 2501 , RISCV::C_FSD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64C, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2501 , RISCV::C_FSD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64C, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2507 , RISCV::C_FSDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64, MCK__40_, MCK_SP, MCK__41_ }, },
{ 2507 , RISCV::C_FSDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtCOrZcd_HasStdExtD, { MCK_FPR64, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
{ 2515 , RISCV::C_FSW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcfOrZce_HasStdExtF_IsRV32, { MCK_FPR32C, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2515 , RISCV::C_FSW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtCOrZcfOrZce_HasStdExtF_IsRV32, { MCK_FPR32C, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2521 , RISCV::C_FSWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZcfOrZce_HasStdExtF_IsRV32, { MCK_FPR32, MCK__40_, MCK_SP, MCK__41_ }, },
{ 2521 , RISCV::C_FSWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtCOrZcfOrZce_HasStdExtF_IsRV32, { MCK_FPR32, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
{ 2529 , RISCV::C_J, Convert__SImm12Lsb01_0, AMFBS_HasStdExtCOrZca, { MCK_SImm12Lsb0 }, },
{ 2533 , RISCV::C_JAL, Convert__SImm12Lsb01_0, AMFBS_HasStdExtCOrZca_IsRV32, { MCK_SImm12Lsb0 }, },
{ 2539 , RISCV::C_JALR, Convert__Reg1_0, AMFBS_HasStdExtCOrZca, { MCK_GPRNoX0 }, },
{ 2546 , RISCV::C_JR, Convert__Reg1_0, AMFBS_HasStdExtCOrZca, { MCK_GPRNoX0 }, },
{ 2551 , RISCV::C_LBU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2551 , RISCV::C_LBU, Convert__Reg1_0__Reg1_3__UImm21_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_UImm2, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2557 , RISCV::C_LD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2557 , RISCV::C_LD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPRC, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2562 , RISCV::C_LDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPRNoX0, MCK__40_, MCK_SP, MCK__41_ }, },
{ 2562 , RISCV::C_LDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPRNoX0, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
{ 2569 , RISCV::C_LH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2569 , RISCV::C_LH, Convert__Reg1_0__Reg1_3__UImm2Lsb01_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_UImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2574 , RISCV::C_LHU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2574 , RISCV::C_LHU, Convert__Reg1_0__Reg1_3__UImm2Lsb01_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_UImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2580 , RISCV::C_LI_HINT, Convert__Reg1_0__SImm61_1, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_GPRX0, MCK_SImm6 }, },
{ 2580 , RISCV::C_LI, Convert__Reg1_0__SImm61_1, AMFBS_HasStdExtCOrZca, { MCK_GPRNoX0, MCK_SImm6 }, },
{ 2585 , RISCV::C_LUI_HINT, Convert__Reg1_0__CLUIImm1_1, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_GPRX0, MCK_CLUIImm }, },
{ 2585 , RISCV::C_LUI, Convert__Reg1_0__CLUIImm1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRNoX0X2, MCK_CLUIImm }, },
{ 2591 , RISCV::C_LW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2591 , RISCV::C_LW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2596 , RISCV::C_LWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZca, { MCK_GPRNoX0, MCK__40_, MCK_SP, MCK__41_ }, },
{ 2596 , RISCV::C_LWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtCOrZca, { MCK_GPRNoX0, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
{ 2603 , RISCV::C_MOP1, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
{ 2611 , RISCV::C_MOP11, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
{ 2620 , RISCV::C_MOP13, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
{ 2629 , RISCV::C_MOP15, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
{ 2638 , RISCV::C_MOP3, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
{ 2646 , RISCV::C_MOP5, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
{ 2654 , RISCV::C_MOP7, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
{ 2662 , RISCV::C_MOP9, Convert_NoOperands, AMFBS_HasStdExtZcmop, { }, },
{ 2670 , RISCV::C_MUL, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZcb_HasStdExtZmmul, { MCK_GPRC, MCK_GPRC }, },
{ 2676 , RISCV::C_MV_HINT, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_GPRX0, MCK_GPRNoX0 }, },
{ 2676 , RISCV::C_MV, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
{ 2681 , RISCV::C_NOP, Convert_NoOperands, AMFBS_HasStdExtCOrZca, { }, },
{ 2681 , RISCV::C_NOP_HINT, Convert__SImm6NonZero1_0, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_SImm6NonZero }, },
{ 2687 , RISCV::C_NOT, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb, { MCK_GPRC }, },
{ 2693 , RISCV::C_ADD_HINT, Convert__regX0__Tie0_1_1__regX5, AMFBS_HasStdExtC_HasRVCHints_HasStdExtZihintntl, { }, },
{ 2703 , RISCV::C_ADD_HINT, Convert__regX0__Tie0_1_1__regX2, AMFBS_HasStdExtC_HasRVCHints_HasStdExtZihintntl, { }, },
{ 2712 , RISCV::C_ADD_HINT, Convert__regX0__Tie0_1_1__regX3, AMFBS_HasStdExtC_HasRVCHints_HasStdExtZihintntl, { }, },
{ 2723 , RISCV::C_ADD_HINT, Convert__regX0__Tie0_1_1__regX4, AMFBS_HasStdExtC_HasRVCHints_HasStdExtZihintntl, { }, },
{ 2732 , RISCV::C_OR, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_GPRC }, },
{ 2737 , RISCV::C_SB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2737 , RISCV::C_SB, Convert__Reg1_0__Reg1_3__UImm21_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_UImm2, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2742 , RISCV::C_SD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2742 , RISCV::C_SD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPRC, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2747 , RISCV::C_SDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPRNoX0, MCK__40_, MCK_SP, MCK__41_ }, },
{ 2747 , RISCV::C_SDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPR, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
{ 2754 , RISCV::C_SEXT_B, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb_HasStdExtZbb, { MCK_GPRC }, },
{ 2763 , RISCV::C_SEXT_H, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb_HasStdExtZbb, { MCK_GPRC }, },
{ 2772 , RISCV::C_SH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2772 , RISCV::C_SH, Convert__Reg1_0__Reg1_3__UImm2Lsb01_1, AMFBS_HasStdExtZcb, { MCK_GPRC, MCK_UImm2Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2777 , RISCV::C_SLLI_HINT, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_GPRX0, MCK_UImmLog2XLenNonZero }, },
{ 2777 , RISCV::C_SLLI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRNoX0, MCK_UImmLog2XLenNonZero }, },
{ 2784 , RISCV::C_SLLI64_HINT, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_GPR }, },
{ 2793 , RISCV::C_SRAI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_UImmLog2XLenNonZero }, },
{ 2800 , RISCV::C_SRAI64_HINT, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_GPRC }, },
{ 2809 , RISCV::C_SRLI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_UImmLog2XLenNonZero }, },
{ 2816 , RISCV::C_SRLI64_HINT, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtCOrZca_HasRVCHints, { MCK_GPRC }, },
{ 2825 , RISCV::C_SSPOPCHK, Convert__Reg1_0, AMFBS_HasStdExtZicfiss_HasStdExtZcmop, { MCK_GPRX5 }, },
{ 2836 , RISCV::C_SSPUSH, Convert__Reg1_0, AMFBS_HasStdExtZicfiss_HasStdExtZcmop, { MCK_GPRX1 }, },
{ 2845 , RISCV::C_SUB, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_GPRC }, },
{ 2851 , RISCV::C_SUBW, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtCOrZca_IsRV64, { MCK_GPRC, MCK_GPRC }, },
{ 2858 , RISCV::C_SW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2858 , RISCV::C_SW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 2863 , RISCV::C_SWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtCOrZca, { MCK_GPRNoX0, MCK__40_, MCK_SP, MCK__41_ }, },
{ 2863 , RISCV::C_SWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtCOrZca, { MCK_GPR, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
{ 2870 , RISCV::C_UNIMP, Convert_NoOperands, AMFBS_HasStdExtCOrZca, { }, },
{ 2878 , RISCV::C_XOR, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtCOrZca, { MCK_GPRC, MCK_GPRC }, },
{ 2884 , RISCV::C_ZEXT_B, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb, { MCK_GPRC }, },
{ 2893 , RISCV::C_ZEXT_H, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb_HasStdExtZbb, { MCK_GPRC }, },
{ 2902 , RISCV::C_ZEXT_W, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtZcb_HasStdExtZba_IsRV64, { MCK_GPRC }, },
{ 2911 , RISCV::PseudoCALL, Convert__CallSymbol1_0, AMFBS_None, { MCK_CallSymbol }, },
{ 2911 , RISCV::PseudoCALLReg, Convert__Reg1_0__CallSymbol1_1, AMFBS_None, { MCK_GPR, MCK_CallSymbol }, },
{ 2916 , RISCV::CBO_CLEAN, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicbom, { MCK_ZeroOffsetMemOpOperand }, },
{ 2926 , RISCV::CBO_FLUSH, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicbom, { MCK_ZeroOffsetMemOpOperand }, },
{ 2936 , RISCV::CBO_INVAL, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicbom, { MCK_ZeroOffsetMemOpOperand }, },
{ 2946 , RISCV::CBO_ZERO, Convert__ZeroOffsetMemOpOperand1_0, AMFBS_HasStdExtZicboz, { MCK_ZeroOffsetMemOpOperand }, },
{ 2955 , RISCV::CLMUL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbcOrZbkc, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 2961 , RISCV::CLMULH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbcOrZbkc, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 2968 , RISCV::CLMULR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbc, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 2975 , RISCV::CLZ, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
{ 2979 , RISCV::CLZW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, },
{ 2984 , RISCV::CM_JALT, Convert__UImm8GE321_0, AMFBS_HasStdExtZcmt, { MCK_UImm8GE32 }, },
{ 2992 , RISCV::CM_JT, Convert__UImm51_0, AMFBS_HasStdExtZcmt, { MCK_UImm5 }, },
{ 2998 , RISCV::CM_MVA01S, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZcmp, { MCK_SR07, MCK_SR07 }, },
{ 3008 , RISCV::CM_MVSA01, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZcmp, { MCK_SR07, MCK_SR07 }, },
{ 3018 , RISCV::CM_POP, Convert__Rlist1_0__StackAdj1_1, AMFBS_HasStdExtZcmp, { MCK_Rlist, MCK_StackAdj }, },
{ 3025 , RISCV::CM_POPRET, Convert__Rlist1_0__StackAdj1_1, AMFBS_HasStdExtZcmp, { MCK_Rlist, MCK_StackAdj }, },
{ 3035 , RISCV::CM_POPRETZ, Convert__Rlist1_0__StackAdj1_1, AMFBS_HasStdExtZcmp, { MCK_Rlist, MCK_StackAdj }, },
{ 3046 , RISCV::CM_PUSH, Convert__Rlist1_0__NegStackAdj1_1, AMFBS_HasStdExtZcmp, { MCK_Rlist, MCK_NegStackAdj }, },
{ 3054 , RISCV::CPOP, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
{ 3059 , RISCV::CPOPW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, },
{ 3065 , RISCV::CSRRC, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
{ 3065 , RISCV::CSRRCI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
{ 3070 , RISCV::CSRRCI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
{ 3076 , RISCV::CSRRS, Convert__Reg1_0__CSRSystemRegister1_1__regX0, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister }, },
{ 3081 , RISCV::CSRRC, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
{ 3081 , RISCV::CSRRCI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
{ 3087 , RISCV::CSRRCI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
{ 3094 , RISCV::CSRRS, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
{ 3094 , RISCV::CSRRSI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
{ 3100 , RISCV::CSRRSI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
{ 3107 , RISCV::CSRRW, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
{ 3107 , RISCV::CSRRWI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
{ 3113 , RISCV::CSRRWI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
{ 3120 , RISCV::CSRRS, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
{ 3120 , RISCV::CSRRSI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
{ 3125 , RISCV::CSRRSI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
{ 3131 , RISCV::CSRRW, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
{ 3131 , RISCV::CSRRWI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
{ 3136 , RISCV::CSRRWI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
{ 3142 , RISCV::CTZ, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
{ 3146 , RISCV::CTZW, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, },
{ 3151 , RISCV::CV_ABS, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
{ 3158 , RISCV::CV_ABS_B, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR }, },
{ 3167 , RISCV::CV_ABS_H, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR }, },
{ 3176 , RISCV::CV_ADD_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3185 , RISCV::CV_ADD_DIV2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3197 , RISCV::CV_ADD_DIV4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3209 , RISCV::CV_ADD_DIV8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3221 , RISCV::CV_ADD_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3230 , RISCV::CV_ADD_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3242 , RISCV::CV_ADD_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3254 , RISCV::CV_ADD_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 3267 , RISCV::CV_ADD_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 3280 , RISCV::CV_ADDN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 3288 , RISCV::CV_ADDNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3297 , RISCV::CV_ADDRN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 3306 , RISCV::CV_ADDRNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3316 , RISCV::CV_ADDUN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 3325 , RISCV::CV_ADDUNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3335 , RISCV::CV_ADDURN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 3345 , RISCV::CV_ADDURNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3356 , RISCV::CV_AND_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3365 , RISCV::CV_AND_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3374 , RISCV::CV_AND_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3386 , RISCV::CV_AND_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3398 , RISCV::CV_AND_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 3411 , RISCV::CV_AND_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 3424 , RISCV::CV_AVG_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3433 , RISCV::CV_AVG_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3442 , RISCV::CV_AVG_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3454 , RISCV::CV_AVG_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3466 , RISCV::CV_AVG_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 3479 , RISCV::CV_AVG_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 3492 , RISCV::CV_AVGU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3502 , RISCV::CV_AVGU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3512 , RISCV::CV_AVGU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3525 , RISCV::CV_AVGU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3538 , RISCV::CV_AVGU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 3552 , RISCV::CV_AVGU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 3566 , RISCV::CV_BCLR, Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
{ 3574 , RISCV::CV_BCLRR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3583 , RISCV::CV_BEQIMM, Convert__Reg1_0__SImm51_1__SImm13Lsb01_2, AMFBS_HasVendorXCVbi_IsRV32, { MCK_GPR, MCK_SImm5, MCK_SImm13Lsb0 }, },
{ 3593 , RISCV::CV_BITREV, Convert__Reg1_0__Reg1_1__UImm21_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm2, MCK_UImm5 }, },
{ 3603 , RISCV::CV_BNEIMM, Convert__Reg1_0__SImm51_1__SImm13Lsb01_2, AMFBS_HasVendorXCVbi_IsRV32, { MCK_GPR, MCK_SImm5, MCK_SImm13Lsb0 }, },
{ 3613 , RISCV::CV_BSET, Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
{ 3621 , RISCV::CV_BSETR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3630 , RISCV::CV_CLB, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR }, },
{ 3637 , RISCV::CV_CLIP, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 3645 , RISCV::CV_CLIPR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3654 , RISCV::CV_CLIPU, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 3663 , RISCV::CV_CLIPUR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3673 , RISCV::CV_CMPEQ_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3684 , RISCV::CV_CMPEQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3695 , RISCV::CV_CMPEQ_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3709 , RISCV::CV_CMPEQ_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3723 , RISCV::CV_CMPEQ_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 3738 , RISCV::CV_CMPEQ_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 3753 , RISCV::CV_CMPGE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3764 , RISCV::CV_CMPGE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3775 , RISCV::CV_CMPGE_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3789 , RISCV::CV_CMPGE_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3803 , RISCV::CV_CMPGE_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 3818 , RISCV::CV_CMPGE_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 3833 , RISCV::CV_CMPGEU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3845 , RISCV::CV_CMPGEU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3857 , RISCV::CV_CMPGEU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3872 , RISCV::CV_CMPGEU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3887 , RISCV::CV_CMPGEU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 3903 , RISCV::CV_CMPGEU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 3919 , RISCV::CV_CMPGT_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3930 , RISCV::CV_CMPGT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3941 , RISCV::CV_CMPGT_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3955 , RISCV::CV_CMPGT_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 3969 , RISCV::CV_CMPGT_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 3984 , RISCV::CV_CMPGT_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 3999 , RISCV::CV_CMPGTU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4011 , RISCV::CV_CMPGTU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4023 , RISCV::CV_CMPGTU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4038 , RISCV::CV_CMPGTU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4053 , RISCV::CV_CMPGTU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 4069 , RISCV::CV_CMPGTU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 4085 , RISCV::CV_CMPLE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4096 , RISCV::CV_CMPLE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4107 , RISCV::CV_CMPLE_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4121 , RISCV::CV_CMPLE_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4135 , RISCV::CV_CMPLE_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 4150 , RISCV::CV_CMPLE_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 4165 , RISCV::CV_CMPLEU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4177 , RISCV::CV_CMPLEU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4189 , RISCV::CV_CMPLEU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4204 , RISCV::CV_CMPLEU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4219 , RISCV::CV_CMPLEU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 4235 , RISCV::CV_CMPLEU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 4251 , RISCV::CV_CMPLT_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4262 , RISCV::CV_CMPLT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4273 , RISCV::CV_CMPLT_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4287 , RISCV::CV_CMPLT_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4301 , RISCV::CV_CMPLT_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 4316 , RISCV::CV_CMPLT_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 4331 , RISCV::CV_CMPLTU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4343 , RISCV::CV_CMPLTU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4355 , RISCV::CV_CMPLTU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4370 , RISCV::CV_CMPLTU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4385 , RISCV::CV_CMPLTU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 4401 , RISCV::CV_CMPLTU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 4417 , RISCV::CV_CMPNE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4428 , RISCV::CV_CMPNE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4439 , RISCV::CV_CMPNE_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4453 , RISCV::CV_CMPNE_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4467 , RISCV::CV_CMPNE_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 4482 , RISCV::CV_CMPNE_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 4497 , RISCV::CV_CNT, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR }, },
{ 4504 , RISCV::CV_CPLXCONJ, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR }, },
{ 4516 , RISCV::CV_CPLXMUL_I, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4529 , RISCV::CV_CPLXMUL_I_DIV2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4547 , RISCV::CV_CPLXMUL_I_DIV4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4565 , RISCV::CV_CPLXMUL_I_DIV8, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4583 , RISCV::CV_CPLXMUL_R, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4596 , RISCV::CV_CPLXMUL_R_DIV2, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4614 , RISCV::CV_CPLXMUL_R_DIV4, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4632 , RISCV::CV_CPLXMUL_R_DIV8, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4650 , RISCV::CV_DOTSP_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4661 , RISCV::CV_DOTSP_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4672 , RISCV::CV_DOTSP_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4686 , RISCV::CV_DOTSP_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4700 , RISCV::CV_DOTSP_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 4715 , RISCV::CV_DOTSP_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 4730 , RISCV::CV_DOTUP_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4741 , RISCV::CV_DOTUP_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4752 , RISCV::CV_DOTUP_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4766 , RISCV::CV_DOTUP_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4780 , RISCV::CV_DOTUP_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 4795 , RISCV::CV_DOTUP_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 4810 , RISCV::CV_DOTUSP_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4822 , RISCV::CV_DOTUSP_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4834 , RISCV::CV_DOTUSP_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4849 , RISCV::CV_DOTUSP_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4864 , RISCV::CV_DOTUSP_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 4880 , RISCV::CV_DOTUSP_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 4896 , RISCV::CV_ELW, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasVendorXCVelw_IsRV32, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 4903 , RISCV::CV_EXTBS, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
{ 4912 , RISCV::CV_EXTBZ, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
{ 4921 , RISCV::CV_EXTHS, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
{ 4930 , RISCV::CV_EXTHZ, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR }, },
{ 4939 , RISCV::CV_EXTRACT, Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
{ 4950 , RISCV::CV_EXTRACT_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 4963 , RISCV::CV_EXTRACT_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 4976 , RISCV::CV_EXTRACTR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 4988 , RISCV::CV_EXTRACTU, Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
{ 5000 , RISCV::CV_EXTRACTU_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 5014 , RISCV::CV_EXTRACTU_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 5028 , RISCV::CV_EXTRACTUR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5041 , RISCV::CV_FF1, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR }, },
{ 5048 , RISCV::CV_FL1, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR }, },
{ 5055 , RISCV::CV_INSERT, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__UImm51_3, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
{ 5065 , RISCV::CV_INSERT_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 5077 , RISCV::CV_INSERT_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 5089 , RISCV::CV_INSERTR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5100 , RISCV::CV_LB_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
{ 5100 , RISCV::CV_LB_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
{ 5100 , RISCV::CV_LB_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
{ 5106 , RISCV::CV_LBU_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
{ 5106 , RISCV::CV_LBU_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
{ 5106 , RISCV::CV_LBU_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
{ 5113 , RISCV::CV_LH_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
{ 5113 , RISCV::CV_LH_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
{ 5113 , RISCV::CV_LH_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
{ 5119 , RISCV::CV_LHU_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
{ 5119 , RISCV::CV_LHU_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
{ 5119 , RISCV::CV_LHU_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
{ 5126 , RISCV::CV_LW_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
{ 5126 , RISCV::CV_LW_rr_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
{ 5126 , RISCV::CV_LW_ri_inc, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
{ 5132 , RISCV::CV_MAC, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5139 , RISCV::CV_MACHHSN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 5150 , RISCV::CV_MACHHSRN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 5162 , RISCV::CV_MACHHUN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 5173 , RISCV::CV_MACHHURN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 5185 , RISCV::CV_MACSN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 5194 , RISCV::CV_MACSRN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 5204 , RISCV::CV_MACUN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 5213 , RISCV::CV_MACURN, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 5223 , RISCV::CV_MAX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5230 , RISCV::CV_MAX_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5239 , RISCV::CV_MAX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5248 , RISCV::CV_MAX_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5260 , RISCV::CV_MAX_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5272 , RISCV::CV_MAX_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 5285 , RISCV::CV_MAX_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 5298 , RISCV::CV_MAXU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5306 , RISCV::CV_MAXU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5316 , RISCV::CV_MAXU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5326 , RISCV::CV_MAXU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5339 , RISCV::CV_MAXU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5352 , RISCV::CV_MAXU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 5366 , RISCV::CV_MAXU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 5380 , RISCV::CV_MIN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5387 , RISCV::CV_MIN_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5396 , RISCV::CV_MIN_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5405 , RISCV::CV_MIN_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5417 , RISCV::CV_MIN_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5429 , RISCV::CV_MIN_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 5442 , RISCV::CV_MIN_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 5455 , RISCV::CV_MINU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5463 , RISCV::CV_MINU_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5473 , RISCV::CV_MINU_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5483 , RISCV::CV_MINU_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5496 , RISCV::CV_MINU_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5509 , RISCV::CV_MINU_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 5523 , RISCV::CV_MINU_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 5537 , RISCV::CV_MSU, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5544 , RISCV::CV_MULHHSN, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5554 , RISCV::CV_MULHHSN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 5565 , RISCV::CV_MULHHSRN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 5577 , RISCV::CV_MULHHUN, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5587 , RISCV::CV_MULHHUN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 5598 , RISCV::CV_MULHHURN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 5610 , RISCV::CV_MULSN, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5618 , RISCV::CV_MULSN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 5627 , RISCV::CV_MULSRN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 5637 , RISCV::CV_MULUN, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5645 , RISCV::CV_MULUN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 5654 , RISCV::CV_MULURN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCVmac_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 5664 , RISCV::CV_OR_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5672 , RISCV::CV_OR_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5680 , RISCV::CV_OR_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5691 , RISCV::CV_OR_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5702 , RISCV::CV_OR_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 5714 , RISCV::CV_OR_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 5726 , RISCV::CV_PACK, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5734 , RISCV::CV_PACK_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5744 , RISCV::CV_PACKHI_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5756 , RISCV::CV_PACKLO_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5768 , RISCV::CV_ROR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVbitmanip_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5775 , RISCV::CV_SB_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
{ 5775 , RISCV::CV_SB_rr_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
{ 5775 , RISCV::CV_SB_ri_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
{ 5781 , RISCV::CV_SDOTSP_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5793 , RISCV::CV_SDOTSP_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5805 , RISCV::CV_SDOTSP_SC_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5820 , RISCV::CV_SDOTSP_SC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5835 , RISCV::CV_SDOTSP_SCI_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 5851 , RISCV::CV_SDOTSP_SCI_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 5867 , RISCV::CV_SDOTUP_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5879 , RISCV::CV_SDOTUP_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5891 , RISCV::CV_SDOTUP_SC_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5906 , RISCV::CV_SDOTUP_SC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5921 , RISCV::CV_SDOTUP_SCI_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 5937 , RISCV::CV_SDOTUP_SCI_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 5953 , RISCV::CV_SDOTUSP_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5966 , RISCV::CV_SDOTUSP_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5979 , RISCV::CV_SDOTUSP_SC_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 5995 , RISCV::CV_SDOTUSP_SC_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6011 , RISCV::CV_SDOTUSP_SCI_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 6028 , RISCV::CV_SDOTUSP_SCI_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 6045 , RISCV::CV_SH_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
{ 6045 , RISCV::CV_SH_rr_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
{ 6045 , RISCV::CV_SH_ri_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
{ 6051 , RISCV::CV_SHUFFLE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6064 , RISCV::CV_SHUFFLE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6077 , RISCV::CV_SHUFFLE_SCI_H, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 6094 , RISCV::CV_SHUFFLE2_B, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6108 , RISCV::CV_SHUFFLE2_H, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6122 , RISCV::CV_SHUFFLEI0_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 6141 , RISCV::CV_SHUFFLEI1_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 6160 , RISCV::CV_SHUFFLEI2_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 6179 , RISCV::CV_SHUFFLEI3_SCI_B, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
{ 6198 , RISCV::CV_SLE, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6205 , RISCV::CV_SLEU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6213 , RISCV::CV_SLL_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6222 , RISCV::CV_SLL_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6231 , RISCV::CV_SLL_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6243 , RISCV::CV_SLL_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6255 , RISCV::CV_SLL_SCI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
{ 6268 , RISCV::CV_SLL_SCI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
{ 6281 , RISCV::CV_SRA_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6290 , RISCV::CV_SRA_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6299 , RISCV::CV_SRA_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6311 , RISCV::CV_SRA_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6323 , RISCV::CV_SRA_SCI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
{ 6336 , RISCV::CV_SRA_SCI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
{ 6349 , RISCV::CV_SRL_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6358 , RISCV::CV_SRL_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6367 , RISCV::CV_SRL_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6379 , RISCV::CV_SRL_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6391 , RISCV::CV_SRL_SCI_B, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm3 }, },
{ 6404 , RISCV::CV_SRL_SCI_H, Convert__Reg1_0__Reg1_1__UImm41_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_UImm4 }, },
{ 6417 , RISCV::CV_SUB_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6426 , RISCV::CV_SUB_DIV2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6438 , RISCV::CV_SUB_DIV4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6450 , RISCV::CV_SUB_DIV8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6462 , RISCV::CV_SUB_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6471 , RISCV::CV_SUB_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6483 , RISCV::CV_SUB_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6495 , RISCV::CV_SUB_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 6508 , RISCV::CV_SUB_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 6521 , RISCV::CV_SUBN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 6529 , RISCV::CV_SUBNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6538 , RISCV::CV_SUBRN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 6547 , RISCV::CV_SUBRNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6557 , RISCV::CV_SUBROTMJ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6569 , RISCV::CV_SUBROTMJ_DIV2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6586 , RISCV::CV_SUBROTMJ_DIV4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6603 , RISCV::CV_SUBROTMJ_DIV8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6620 , RISCV::CV_SUBUN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 6629 , RISCV::CV_SUBUNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6639 , RISCV::CV_SUBURN, Convert__Reg1_0__Reg1_1__Reg1_2__UImm51_3, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 6649 , RISCV::CV_SUBURNR, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXCValu_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6660 , RISCV::CV_SW_rr, Convert__Reg1_0__RegReg2_1, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK_RegReg }, },
{ 6660 , RISCV::CV_SW_rr_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__Reg1_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_GPR }, },
{ 6660 , RISCV::CV_SW_ri_inc, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm121_4, AMFBS_HasVendorXCVmem_IsRV32, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm12 }, },
{ 6666 , RISCV::CV_XOR_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6675 , RISCV::CV_XOR_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6684 , RISCV::CV_XOR_SC_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6696 , RISCV::CV_XOR_SC_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6708 , RISCV::CV_XOR_SCI_B, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 6721 , RISCV::CV_XOR_SCI_H, Convert__Reg1_0__Reg1_1__SImm61_2, AMFBS_HasVendorXCVsimd_IsRV32, { MCK_GPR, MCK_GPR, MCK_SImm6 }, },
{ 6734 , RISCV::CZERO_EQZ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZicond, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6744 , RISCV::CZERO_NEZ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZicond, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6754 , RISCV::DIV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6758 , RISCV::DIVU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6763 , RISCV::DIVUW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6769 , RISCV::DIVW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 6774 , RISCV::DRET, Convert_NoOperands, AMFBS_None, { }, },
{ 6779 , RISCV::EBREAK, Convert_NoOperands, AMFBS_None, { }, },
{ 6786 , RISCV::ECALL, Convert_NoOperands, AMFBS_None, { }, },
{ 6792 , RISCV::FSGNJX_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, },
{ 6792 , RISCV::FSGNJX_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
{ 6792 , RISCV::FSGNJX_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
{ 6799 , RISCV::FSGNJX_H, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16 }, },
{ 6799 , RISCV::FSGNJX_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
{ 6806 , RISCV::FSGNJX_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, },
{ 6806 , RISCV::FSGNJX_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
{ 6813 , RISCV::FADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
{ 6813 , RISCV::FADD_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
{ 6813 , RISCV::FADD_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
{ 6820 , RISCV::FADD_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
{ 6820 , RISCV::FADD_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
{ 6827 , RISCV::FADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
{ 6827 , RISCV::FADD_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
{ 6834 , RISCV::FCLASS_D, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64 }, },
{ 6834 , RISCV::FCLASS_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR }, },
{ 6834 , RISCV::FCLASS_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR }, },
{ 6843 , RISCV::FCLASS_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16 }, },
{ 6843 , RISCV::FCLASS_H_INX, Convert__Reg1_0__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16 }, },
{ 6852 , RISCV::FCLASS_S, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, },
{ 6852 , RISCV::FCLASS_S_INX, Convert__Reg1_0__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32 }, },
{ 6861 , RISCV::FCVT_BF16_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfbfmin, { MCK_FPR16, MCK_FPR32, MCK_FRMArg }, },
{ 6873 , RISCV::FCVT_D_H, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZfhmin_HasStdExtD, { MCK_FPR64, MCK_FPR16, MCK_FRMArgLegacy }, },
{ 6873 , RISCV::FCVT_D_H_INX, Convert__GPRF64AsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRAsFPR16, MCK_FRMArgLegacy }, },
{ 6873 , RISCV::FCVT_D_H_IN32X, Convert__GPRPairAsFPR1_0__GPRAsFPR161_1__FRMArgLegacy1_2, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRAsFPR16, MCK_FRMArgLegacy }, },
{ 6882 , RISCV::FCVT_D_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_FRMArg }, },
{ 6882 , RISCV::FCVT_D_L_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArg }, },
{ 6891 , RISCV::FCVT_D_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_FRMArg }, },
{ 6891 , RISCV::FCVT_D_LU_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArg }, },
{ 6901 , RISCV::FCVT_D_S, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR32, MCK_FRMArgLegacy }, },
{ 6901 , RISCV::FCVT_D_S_INX, Convert__GPRF64AsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRAsFPR32, MCK_FRMArgLegacy }, },
{ 6901 , RISCV::FCVT_D_S_IN32X, Convert__GPRPairAsFPR1_0__GPRAsFPR321_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRAsFPR32, MCK_FRMArgLegacy }, },
{ 6910 , RISCV::FCVT_D_W, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_GPR, MCK_FRMArgLegacy }, },
{ 6910 , RISCV::FCVT_D_W_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArgLegacy }, },
{ 6910 , RISCV::FCVT_D_W_IN32X, Convert__GPRPairAsFPR1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPR, MCK_FRMArgLegacy }, },
{ 6919 , RISCV::FCVT_D_WU, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_GPR, MCK_FRMArgLegacy }, },
{ 6919 , RISCV::FCVT_D_WU_INX, Convert__GPRF64AsFPR1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPR, MCK_FRMArgLegacy }, },
{ 6919 , RISCV::FCVT_D_WU_IN32X, Convert__GPRPairAsFPR1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPR, MCK_FRMArgLegacy }, },
{ 6929 , RISCV::FCVT_H_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfhmin_HasStdExtD, { MCK_FPR16, MCK_FPR64, MCK_FRMArg }, },
{ 6929 , RISCV::FCVT_H_D_INX, Convert__GPRAsFPR161_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64, { MCK_GPRAsFPR16, MCK_GPRF64AsFPR, MCK_FRMArg }, },
{ 6929 , RISCV::FCVT_H_D_IN32X, Convert__GPRAsFPR161_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32, { MCK_GPRAsFPR16, MCK_GPRPairAsFPR, MCK_FRMArg }, },
{ 6938 , RISCV::FCVT_H_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, },
{ 6938 , RISCV::FCVT_H_L_INX, Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPRAsFPR16, MCK_GPR, MCK_FRMArg }, },
{ 6947 , RISCV::FCVT_H_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, },
{ 6947 , RISCV::FCVT_H_LU_INX, Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPRAsFPR16, MCK_GPR, MCK_FRMArg }, },
{ 6957 , RISCV::FCVT_H_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfhmin, { MCK_FPR16, MCK_FPR32, MCK_FRMArg }, },
{ 6957 , RISCV::FCVT_H_S_INX, Convert__GPRAsFPR161_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZhinxmin, { MCK_GPRAsFPR16, MCK_GPRAsFPR32, MCK_FRMArg }, },
{ 6966 , RISCV::FCVT_H_W, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, },
{ 6966 , RISCV::FCVT_H_W_INX, Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPR, MCK_FRMArg }, },
{ 6975 , RISCV::FCVT_H_WU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_GPR, MCK_FRMArg }, },
{ 6975 , RISCV::FCVT_H_WU_INX, Convert__GPRAsFPR161_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPR, MCK_FRMArg }, },
{ 6985 , RISCV::FCVT_L_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
{ 6985 , RISCV::FCVT_L_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
{ 6994 , RISCV::FCVT_L_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, },
{ 6994 , RISCV::FCVT_L_H_INX, Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR16, MCK_FRMArg }, },
{ 7003 , RISCV::FCVT_L_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
{ 7003 , RISCV::FCVT_L_S_INX, Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR32, MCK_FRMArg }, },
{ 7012 , RISCV::FCVT_LU_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
{ 7012 , RISCV::FCVT_LU_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
{ 7022 , RISCV::FCVT_LU_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh_IsRV64, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, },
{ 7022 , RISCV::FCVT_LU_H_INX, Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR16, MCK_FRMArg }, },
{ 7032 , RISCV::FCVT_LU_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
{ 7032 , RISCV::FCVT_LU_S_INX, Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPR, MCK_GPRAsFPR32, MCK_FRMArg }, },
{ 7042 , RISCV::FCVT_S_BF16, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZfbfmin, { MCK_FPR32, MCK_FPR16, MCK_FRMArgLegacy }, },
{ 7054 , RISCV::FCVT_S_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_FPR32, MCK_FPR64, MCK_FRMArg }, },
{ 7054 , RISCV::FCVT_S_D_INX, Convert__GPRAsFPR321_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRAsFPR32, MCK_GPRF64AsFPR, MCK_FRMArg }, },
{ 7054 , RISCV::FCVT_S_D_IN32X, Convert__GPRAsFPR321_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRAsFPR32, MCK_GPRPairAsFPR, MCK_FRMArg }, },
{ 7063 , RISCV::FCVT_S_H, Convert__Reg1_0__Reg1_1__FRMArgLegacy1_2, AMFBS_HasStdExtZfhmin, { MCK_FPR32, MCK_FPR16, MCK_FRMArgLegacy }, },
{ 7063 , RISCV::FCVT_S_H_INX, Convert__GPRAsFPR321_0__GPRAsFPR161_1__FRMArgLegacy1_2, AMFBS_HasStdExtZhinxmin, { MCK_GPRAsFPR32, MCK_GPRAsFPR16, MCK_FRMArgLegacy }, },
{ 7072 , RISCV::FCVT_S_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
{ 7072 , RISCV::FCVT_S_L_INX, Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPRAsFPR32, MCK_GPR, MCK_FRMArg }, },
{ 7081 , RISCV::FCVT_S_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
{ 7081 , RISCV::FCVT_S_LU_INX, Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx_IsRV64, { MCK_GPRAsFPR32, MCK_GPR, MCK_FRMArg }, },
{ 7091 , RISCV::FCVT_S_W, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
{ 7091 , RISCV::FCVT_S_W_INX, Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPR, MCK_FRMArg }, },
{ 7100 , RISCV::FCVT_S_WU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
{ 7100 , RISCV::FCVT_S_WU_INX, Convert__GPRAsFPR321_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPR, MCK_FRMArg }, },
{ 7110 , RISCV::FCVT_W_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
{ 7110 , RISCV::FCVT_W_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
{ 7110 , RISCV::FCVT_W_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
{ 7119 , RISCV::FCVT_W_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, },
{ 7119 , RISCV::FCVT_W_H_INX, Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_FRMArg }, },
{ 7128 , RISCV::FCVT_W_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
{ 7128 , RISCV::FCVT_W_S_INX, Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_FRMArg }, },
{ 7137 , RISCV::FCVT_WU_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
{ 7137 , RISCV::FCVT_WU_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
{ 7137 , RISCV::FCVT_WU_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
{ 7147 , RISCV::FCVT_WU_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FRMArg }, },
{ 7147 , RISCV::FCVT_WU_H_INX, Convert__Reg1_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_FRMArg }, },
{ 7157 , RISCV::FCVT_WU_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
{ 7157 , RISCV::FCVT_WU_S_INX, Convert__Reg1_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_FRMArg }, },
{ 7167 , RISCV::FCVTMOD_W_D, Convert__Reg1_0__Reg1_1__RTZArg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_RTZArg }, },
{ 7179 , RISCV::FDIV_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
{ 7179 , RISCV::FDIV_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
{ 7179 , RISCV::FDIV_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
{ 7186 , RISCV::FDIV_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
{ 7186 , RISCV::FDIV_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
{ 7193 , RISCV::FDIV_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
{ 7193 , RISCV::FDIV_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
{ 7200 , RISCV::FENCE, Convert__imm_95_15__imm_95_15, AMFBS_None, { }, },
{ 7200 , RISCV::FENCE, Convert__FenceArg1_0__FenceArg1_1, AMFBS_None, { MCK_FenceArg, MCK_FenceArg }, },
{ 7206 , RISCV::FENCE_I, Convert_NoOperands, AMFBS_None, { }, },
{ 7214 , RISCV::FENCE_TSO, Convert_NoOperands, AMFBS_None, { }, },
{ 7224 , RISCV::FEQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
{ 7224 , RISCV::FEQ_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
{ 7224 , RISCV::FEQ_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
{ 7230 , RISCV::FEQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
{ 7230 , RISCV::FEQ_H_INX, Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
{ 7236 , RISCV::FEQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
{ 7236 , RISCV::FEQ_S_INX, Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
{ 7242 , RISCV::FLE_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
{ 7242 , RISCV::FLE_D_INX, Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
{ 7242 , RISCV::FLE_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_2__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
{ 7248 , RISCV::FLE_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
{ 7248 , RISCV::FLE_H_INX, Convert__Reg1_0__GPRAsFPR161_2__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
{ 7254 , RISCV::FLE_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
{ 7254 , RISCV::FLE_S_INX, Convert__Reg1_0__GPRAsFPR321_2__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
{ 7260 , RISCV::FLEQ_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
{ 7267 , RISCV::FLEQ_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
{ 7274 , RISCV::FLEQ_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
{ 7281 , RISCV::FLT_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
{ 7281 , RISCV::FLT_D_INX, Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
{ 7281 , RISCV::FLT_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_2__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
{ 7287 , RISCV::FLT_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
{ 7287 , RISCV::FLT_H_INX, Convert__Reg1_0__GPRAsFPR161_2__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
{ 7293 , RISCV::FLT_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
{ 7293 , RISCV::FLT_S_INX, Convert__Reg1_0__GPRAsFPR321_2__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
{ 7299 , RISCV::FLTQ_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
{ 7306 , RISCV::FLTQ_H, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
{ 7313 , RISCV::FLTQ_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtZfa, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
{ 7320 , RISCV::PseudoFLD, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_BareSymbol, MCK_GPR }, },
{ 7320 , RISCV::FLD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtD, { MCK_FPR64, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 7320 , RISCV::FLD, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 7324 , RISCV::FLE_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
{ 7324 , RISCV::FLE_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
{ 7324 , RISCV::FLE_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
{ 7330 , RISCV::FLE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
{ 7330 , RISCV::FLE_H_INX, Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
{ 7336 , RISCV::FLE_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
{ 7336 , RISCV::FLE_S_INX, Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
{ 7342 , RISCV::FLEQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
{ 7349 , RISCV::FLEQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
{ 7356 , RISCV::FLEQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
{ 7363 , RISCV::PseudoFLH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtZfhmin, { MCK_FPR16, MCK_BareSymbol, MCK_GPR }, },
{ 7363 , RISCV::FLH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZfhmin, { MCK_FPR16, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 7363 , RISCV::FLH, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 7367 , RISCV::FLI_D, Convert__Reg1_0__LoadFPImm1_1, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_LoadFPImm }, },
{ 7373 , RISCV::FLI_H, Convert__Reg1_0__LoadFPImm1_1, AMFBS_HasStdExtZfa_HasStdExtZfhOrZvfh, { MCK_FPR16, MCK_LoadFPImm }, },
{ 7379 , RISCV::FLI_S, Convert__Reg1_0__LoadFPImm1_1, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_LoadFPImm }, },
{ 7385 , RISCV::FLT_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
{ 7385 , RISCV::FLT_D_INX, Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
{ 7385 , RISCV::FLT_D_IN32X, Convert__Reg1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
{ 7391 , RISCV::FLT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
{ 7391 , RISCV::FLT_H_INX, Convert__Reg1_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPR, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
{ 7397 , RISCV::FLT_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
{ 7397 , RISCV::FLT_S_INX, Convert__Reg1_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPR, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
{ 7403 , RISCV::FLTQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
{ 7410 , RISCV::FLTQ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_GPR, MCK_FPR16, MCK_FPR16 }, },
{ 7417 , RISCV::FLTQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
{ 7424 , RISCV::PseudoFLW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_BareSymbol, MCK_GPR }, },
{ 7424 , RISCV::FLW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtF, { MCK_FPR32, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 7424 , RISCV::FLW, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 7428 , RISCV::FMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
{ 7428 , RISCV::FMADD_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
{ 7428 , RISCV::FMADD_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
{ 7436 , RISCV::FMADD_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
{ 7436 , RISCV::FMADD_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
{ 7444 , RISCV::FMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
{ 7444 , RISCV::FMADD_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
{ 7452 , RISCV::FMAX_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
{ 7452 , RISCV::FMAX_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
{ 7452 , RISCV::FMAX_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
{ 7459 , RISCV::FMAX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
{ 7459 , RISCV::FMAX_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
{ 7466 , RISCV::FMAX_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
{ 7466 , RISCV::FMAX_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
{ 7473 , RISCV::FMAXM_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
{ 7481 , RISCV::FMAXM_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
{ 7489 , RISCV::FMAXM_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
{ 7497 , RISCV::FMIN_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
{ 7497 , RISCV::FMIN_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
{ 7497 , RISCV::FMIN_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
{ 7504 , RISCV::FMIN_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
{ 7504 , RISCV::FMIN_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
{ 7511 , RISCV::FMIN_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
{ 7511 , RISCV::FMIN_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
{ 7518 , RISCV::FMINM_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
{ 7526 , RISCV::FMINM_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
{ 7534 , RISCV::FMINM_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
{ 7542 , RISCV::FMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
{ 7542 , RISCV::FMSUB_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
{ 7542 , RISCV::FMSUB_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
{ 7550 , RISCV::FMSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
{ 7550 , RISCV::FMSUB_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
{ 7558 , RISCV::FMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
{ 7558 , RISCV::FMSUB_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
{ 7566 , RISCV::FMUL_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
{ 7566 , RISCV::FMUL_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
{ 7566 , RISCV::FMUL_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
{ 7573 , RISCV::FMUL_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
{ 7573 , RISCV::FMUL_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
{ 7580 , RISCV::FMUL_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
{ 7580 , RISCV::FMUL_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
{ 7587 , RISCV::FSGNJ_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, },
{ 7587 , RISCV::FSGNJ_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
{ 7587 , RISCV::FSGNJ_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
{ 7593 , RISCV::FMV_D_X, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR }, },
{ 7601 , RISCV::FSGNJ_H, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16 }, },
{ 7601 , RISCV::FSGNJ_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
{ 7607 , RISCV::FMV_H_X, Convert__Reg1_0__Reg1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_GPR }, },
{ 7615 , RISCV::FSGNJ_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, },
{ 7615 , RISCV::FSGNJ_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
{ 7621 , RISCV::FMV_W_X, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR }, },
{ 7629 , RISCV::FMV_X_D, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64 }, },
{ 7637 , RISCV::FMV_X_H, Convert__Reg1_0__Reg1_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_GPR, MCK_FPR16 }, },
{ 7645 , RISCV::FMV_X_W, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, },
{ 7653 , RISCV::FMVH_X_D, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZfa_HasStdExtD_IsRV32, { MCK_GPR, MCK_FPR64 }, },
{ 7662 , RISCV::FMVP_D_X, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfa_HasStdExtD_IsRV32, { MCK_FPR64, MCK_GPR, MCK_GPR }, },
{ 7671 , RISCV::FSGNJN_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, },
{ 7671 , RISCV::FSGNJN_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
{ 7671 , RISCV::FSGNJN_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_1, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
{ 7678 , RISCV::FSGNJN_H, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16 }, },
{ 7678 , RISCV::FSGNJN_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_1, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
{ 7685 , RISCV::FSGNJN_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, },
{ 7685 , RISCV::FSGNJN_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_1, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
{ 7692 , RISCV::FNMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
{ 7692 , RISCV::FNMADD_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
{ 7692 , RISCV::FNMADD_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
{ 7701 , RISCV::FNMADD_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
{ 7701 , RISCV::FNMADD_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
{ 7710 , RISCV::FNMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
{ 7710 , RISCV::FNMADD_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
{ 7719 , RISCV::FNMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
{ 7719 , RISCV::FNMSUB_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
{ 7719 , RISCV::FNMSUB_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__GPRPairAsFPR1_3__FRMArg1_4, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
{ 7728 , RISCV::FNMSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
{ 7728 , RISCV::FNMSUB_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__GPRAsFPR161_3__FRMArg1_4, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
{ 7737 , RISCV::FNMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
{ 7737 , RISCV::FNMSUB_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__GPRAsFPR321_3__FRMArg1_4, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
{ 7746 , RISCV::CSRRS, Convert__Reg1_0__imm_95_3__regX0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
{ 7752 , RISCV::CSRRS, Convert__Reg1_0__imm_95_1__regX0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
{ 7760 , RISCV::FROUND_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
{ 7769 , RISCV::FROUND_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
{ 7778 , RISCV::FROUND_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
{ 7787 , RISCV::FROUNDNX_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
{ 7798 , RISCV::FROUNDNX_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
{ 7809 , RISCV::FROUNDNX_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfa, { MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
{ 7820 , RISCV::CSRRS, Convert__Reg1_0__imm_95_2__regX0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
{ 7825 , RISCV::CSRRS, Convert__Reg1_0__imm_95_3__regX0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
{ 7830 , RISCV::CSRRW, Convert__regX0__imm_95_3__Reg1_0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
{ 7830 , RISCV::CSRRW, Convert__Reg1_0__imm_95_3__Reg1_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_GPR }, },
{ 7836 , RISCV::PseudoFSD, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_BareSymbol, MCK_GPR }, },
{ 7836 , RISCV::FSD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtD, { MCK_FPR64, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 7836 , RISCV::FSD, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 7840 , RISCV::CSRRW, Convert__regX0__imm_95_1__Reg1_0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
{ 7840 , RISCV::CSRRW, Convert__Reg1_0__imm_95_1__Reg1_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_GPR }, },
{ 7848 , RISCV::CSRRWI, Convert__regX0__imm_95_1__UImm51_0, AMFBS_HasStdExtFOrZfinx, { MCK_UImm5 }, },
{ 7848 , RISCV::CSRRWI, Convert__Reg1_0__imm_95_1__UImm51_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_UImm5 }, },
{ 7857 , RISCV::FSGNJ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
{ 7857 , RISCV::FSGNJ_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
{ 7857 , RISCV::FSGNJ_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
{ 7865 , RISCV::FSGNJ_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
{ 7865 , RISCV::FSGNJ_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
{ 7873 , RISCV::FSGNJ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
{ 7873 , RISCV::FSGNJ_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
{ 7881 , RISCV::FSGNJN_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
{ 7881 , RISCV::FSGNJN_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
{ 7881 , RISCV::FSGNJN_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
{ 7890 , RISCV::FSGNJN_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
{ 7890 , RISCV::FSGNJN_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
{ 7899 , RISCV::FSGNJN_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
{ 7899 , RISCV::FSGNJN_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
{ 7908 , RISCV::FSGNJX_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
{ 7908 , RISCV::FSGNJX_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR }, },
{ 7908 , RISCV::FSGNJX_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR }, },
{ 7917 , RISCV::FSGNJX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16 }, },
{ 7917 , RISCV::FSGNJX_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16 }, },
{ 7926 , RISCV::FSGNJX_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
{ 7926 , RISCV::FSGNJX_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32 }, },
{ 7935 , RISCV::PseudoFSH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtZfhmin, { MCK_FPR16, MCK_BareSymbol, MCK_GPR }, },
{ 7935 , RISCV::FSH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtZfhmin, { MCK_FPR16, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 7935 , RISCV::FSH, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasHalfFPLoadStoreMove, { MCK_FPR16, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 7939 , RISCV::FSQRT_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
{ 7939 , RISCV::FSQRT_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
{ 7939 , RISCV::FSQRT_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__FRMArg1_2, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
{ 7947 , RISCV::FSQRT_H, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
{ 7947 , RISCV::FSQRT_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__FRMArg1_2, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
{ 7955 , RISCV::FSQRT_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
{ 7955 , RISCV::FSQRT_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__FRMArg1_2, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
{ 7963 , RISCV::CSRRW, Convert__regX0__imm_95_2__Reg1_0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
{ 7963 , RISCV::CSRRW, Convert__Reg1_0__imm_95_2__Reg1_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_GPR }, },
{ 7968 , RISCV::CSRRWI, Convert__regX0__imm_95_2__UImm51_0, AMFBS_HasStdExtFOrZfinx, { MCK_UImm5 }, },
{ 7968 , RISCV::CSRRWI, Convert__Reg1_0__imm_95_2__UImm51_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_UImm5 }, },
{ 7974 , RISCV::CSRRW, Convert__regX0__imm_95_3__Reg1_0, AMFBS_HasStdExtFOrZfinx, { MCK_GPR }, },
{ 7974 , RISCV::CSRRW, Convert__Reg1_0__imm_95_3__Reg1_1, AMFBS_HasStdExtFOrZfinx, { MCK_GPR, MCK_GPR }, },
{ 7979 , RISCV::FSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
{ 7979 , RISCV::FSUB_D_INX, Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV64, { MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_GPRF64AsFPR, MCK_FRMArg }, },
{ 7979 , RISCV::FSUB_D_IN32X, Convert__GPRPairAsFPR1_0__GPRPairAsFPR1_1__GPRPairAsFPR1_2__FRMArg1_3, AMFBS_HasStdExtZdinx_IsRV32, { MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_GPRPairAsFPR, MCK_FRMArg }, },
{ 7986 , RISCV::FSUB_H, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtZfh, { MCK_FPR16, MCK_FPR16, MCK_FPR16, MCK_FRMArg }, },
{ 7986 , RISCV::FSUB_H_INX, Convert__GPRAsFPR161_0__GPRAsFPR161_1__GPRAsFPR161_2__FRMArg1_3, AMFBS_HasStdExtZhinx, { MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_GPRAsFPR16, MCK_FRMArg }, },
{ 7993 , RISCV::FSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
{ 7993 , RISCV::FSUB_S_INX, Convert__GPRAsFPR321_0__GPRAsFPR321_1__GPRAsFPR321_2__FRMArg1_3, AMFBS_HasStdExtZfinx, { MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_GPRAsFPR32, MCK_FRMArg }, },
{ 8000 , RISCV::PseudoFSW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_BareSymbol, MCK_GPR }, },
{ 8000 , RISCV::FSW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtF, { MCK_FPR32, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8000 , RISCV::FSW, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8004 , RISCV::HFENCE_GVMA, Convert__regX0__regX0, AMFBS_None, { }, },
{ 8004 , RISCV::HFENCE_GVMA, Convert__Reg1_0__regX0, AMFBS_None, { MCK_GPR }, },
{ 8004 , RISCV::HFENCE_GVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_GPR }, },
{ 8016 , RISCV::HFENCE_VVMA, Convert__regX0__regX0, AMFBS_None, { }, },
{ 8016 , RISCV::HFENCE_VVMA, Convert__Reg1_0__regX0, AMFBS_None, { MCK_GPR }, },
{ 8016 , RISCV::HFENCE_VVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_GPR }, },
{ 8028 , RISCV::HINVAL_GVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSvinval, { MCK_GPR, MCK_GPR }, },
{ 8040 , RISCV::HINVAL_VVMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSvinval, { MCK_GPR, MCK_GPR }, },
{ 8052 , RISCV::HLV_B, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8058 , RISCV::HLV_BU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8065 , RISCV::HLV_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_IsRV64_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8071 , RISCV::HLV_H, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8077 , RISCV::HLV_HU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8084 , RISCV::HLV_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8090 , RISCV::HLV_WU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_IsRV64_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8097 , RISCV::HLVX_HU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8105 , RISCV::HLVX_WU, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8113 , RISCV::HSV_B, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8119 , RISCV::HSV_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_IsRV64_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8125 , RISCV::HSV_H, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8131 , RISCV::HSV_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtH, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8137 , RISCV::JAL, Convert__regX0__SImm21Lsb0JAL1_0, AMFBS_None, { MCK_SImm21Lsb0JAL }, },
{ 8139 , RISCV::JAL, Convert__regX1__SImm21Lsb0JAL1_0, AMFBS_None, { MCK_SImm21Lsb0JAL }, },
{ 8139 , RISCV::JAL, Convert__Reg1_0__SImm21Lsb0JAL1_1, AMFBS_None, { MCK_GPR, MCK_SImm21Lsb0JAL }, },
{ 8143 , RISCV::JALR, Convert__regX1__Reg1_0__imm_95_0, AMFBS_None, { MCK_GPR }, },
{ 8143 , RISCV::JALR, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR, MCK_GPR }, },
{ 8143 , RISCV::JALR, Convert__regX1__Reg1_0__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12 }, },
{ 8143 , RISCV::JALR, Convert__regX1__Reg1_1__imm_95_0, AMFBS_None, { MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8143 , RISCV::JALR, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
{ 8143 , RISCV::JALR, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8143 , RISCV::JALR, Convert__regX1__Reg1_2__SImm121_0, AMFBS_None, { MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8143 , RISCV::JALR, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8143 , RISCV::PseudoTLSDESCCall, Convert__Reg1_0__Reg1_3__SImm121_1__TLSDESCCallSymbol1_5, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_, MCK_TLSDESCCallSymbol }, },
{ 8148 , RISCV::JALR, Convert__regX0__Reg1_0__imm_95_0, AMFBS_None, { MCK_GPR }, },
{ 8148 , RISCV::JALR, Convert__regX0__Reg1_0__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12 }, },
{ 8148 , RISCV::JALR, Convert__regX0__Reg1_1__imm_95_0, AMFBS_None, { MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8148 , RISCV::JALR, Convert__regX0__Reg1_2__SImm121_0, AMFBS_None, { MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8151 , RISCV::PseudoJump, Convert__Reg1_1__PseudoJumpSymbol1_0, AMFBS_None, { MCK_PseudoJumpSymbol, MCK_GPR }, },
{ 8156 , RISCV::PseudoLA, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
{ 8156 , RISCV::PseudoLAImm, Convert__Reg1_0__ImmXLenLI_Restricted1_1, AMFBS_None, { MCK_GPR, MCK_ImmXLenLI_Restricted }, },
{ 8159 , RISCV::PseudoLA_TLS_GD, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
{ 8169 , RISCV::PseudoLA_TLS_IE, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
{ 8179 , RISCV::PseudoLA_TLSDESC, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
{ 8190 , RISCV::PseudoLB, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
{ 8190 , RISCV::LB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8190 , RISCV::LB, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8193 , RISCV::LB_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8199 , RISCV::LB_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8207 , RISCV::PseudoLBU, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
{ 8207 , RISCV::LBU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8207 , RISCV::LBU, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8211 , RISCV::PseudoLD, Convert__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol }, },
{ 8211 , RISCV::LD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8211 , RISCV::LD, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8214 , RISCV::LD_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8220 , RISCV::LD_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8228 , RISCV::PseudoLGA, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
{ 8232 , RISCV::PseudoLH, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
{ 8232 , RISCV::LH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8232 , RISCV::LH, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8235 , RISCV::LH_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8241 , RISCV::LH_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8249 , RISCV::PseudoLHU, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
{ 8249 , RISCV::LHU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8249 , RISCV::LHU, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8253 , RISCV::ADDI, Convert__Reg1_0__regX0__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12 }, },
{ 8253 , RISCV::PseudoLI, Convert__Reg1_0__ImmXLenLI1_1, AMFBS_None, { MCK_GPR, MCK_ImmXLenLI }, },
{ 8256 , RISCV::PseudoLLA, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
{ 8256 , RISCV::PseudoLLAImm, Convert__Reg1_0__ImmXLenLI_Restricted1_1, AMFBS_None, { MCK_GPR, MCK_ImmXLenLI_Restricted }, },
{ 8260 , RISCV::AUIPC, Convert__regX0__UImm201_0, AMFBS_HasStdExtZicfilp, { MCK_UImm20 }, },
{ 8265 , RISCV::LR_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtAOrZalrsc_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8270 , RISCV::LR_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtAOrZalrsc_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8278 , RISCV::LR_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtAOrZalrsc_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8288 , RISCV::LR_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtAOrZalrsc_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8296 , RISCV::LR_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtAOrZalrsc, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8301 , RISCV::LR_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtAOrZalrsc, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8309 , RISCV::LR_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtAOrZalrsc, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8319 , RISCV::LR_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtAOrZalrsc, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8327 , RISCV::LUI, Convert__Reg1_0__UImm20LUI1_1, AMFBS_None, { MCK_GPR, MCK_UImm20LUI }, },
{ 8331 , RISCV::PseudoLW, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
{ 8331 , RISCV::LW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8331 , RISCV::LW, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8334 , RISCV::LW_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8340 , RISCV::LW_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 8348 , RISCV::PseudoLWU, Convert__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol }, },
{ 8348 , RISCV::LWU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8348 , RISCV::LWU, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8352 , RISCV::MAX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8356 , RISCV::MAXU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8361 , RISCV::MIN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8365 , RISCV::MINU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8370 , RISCV::MOPR0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8378 , RISCV::MOPR1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8386 , RISCV::MOPR10, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8395 , RISCV::MOPR11, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8404 , RISCV::MOPR12, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8413 , RISCV::MOPR13, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8422 , RISCV::MOPR14, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8431 , RISCV::MOPR15, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8440 , RISCV::MOPR16, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8449 , RISCV::MOPR17, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8458 , RISCV::MOPR18, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8467 , RISCV::MOPR19, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8476 , RISCV::MOPR2, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8484 , RISCV::MOPR20, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8493 , RISCV::MOPR21, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8502 , RISCV::MOPR22, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8511 , RISCV::MOPR23, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8520 , RISCV::MOPR24, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8529 , RISCV::MOPR25, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8538 , RISCV::MOPR26, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8547 , RISCV::MOPR27, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8556 , RISCV::MOPR28, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8565 , RISCV::MOPR29, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8574 , RISCV::MOPR3, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8582 , RISCV::MOPR30, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8591 , RISCV::MOPR31, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8600 , RISCV::MOPR4, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8608 , RISCV::MOPR5, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8616 , RISCV::MOPR6, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8624 , RISCV::MOPR7, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8632 , RISCV::MOPR8, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8640 , RISCV::MOPR9, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR }, },
{ 8648 , RISCV::MOPRR0, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8657 , RISCV::MOPRR1, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8666 , RISCV::MOPRR2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8675 , RISCV::MOPRR3, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8684 , RISCV::MOPRR4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8693 , RISCV::MOPRR5, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8702 , RISCV::MOPRR6, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8711 , RISCV::MOPRR7, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZimop, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8720 , RISCV::MRET, Convert_NoOperands, AMFBS_None, { }, },
{ 8725 , RISCV::MUL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8729 , RISCV::MULH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8734 , RISCV::MULHSU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8741 , RISCV::MULHU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8747 , RISCV::MULW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZmmul_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8752 , RISCV::ADDI, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR, MCK_GPR }, },
{ 8755 , RISCV::SUB, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
{ 8759 , RISCV::SUBW, Convert__Reg1_0__regX0__Reg1_1, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, },
{ 8764 , RISCV::ADDI, Convert__regX0__regX0__imm_95_0, AMFBS_None, { }, },
{ 8768 , RISCV::XORI, Convert__Reg1_0__Reg1_1__imm_95__MINUS_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
{ 8772 , RISCV::ADD, Convert__regX0__regX0__regX5, AMFBS_HasStdExtZihintntl, { }, },
{ 8780 , RISCV::ADD, Convert__regX0__regX0__regX2, AMFBS_HasStdExtZihintntl, { }, },
{ 8787 , RISCV::ADD, Convert__regX0__regX0__regX3, AMFBS_HasStdExtZihintntl, { }, },
{ 8796 , RISCV::ADD, Convert__regX0__regX0__regX4, AMFBS_HasStdExtZihintntl, { }, },
{ 8803 , RISCV::OR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8803 , RISCV::ORI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
{ 8806 , RISCV::ORC_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
{ 8812 , RISCV::ORI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
{ 8816 , RISCV::ORN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8820 , RISCV::PACK, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8825 , RISCV::PACKH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8831 , RISCV::PACKW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 8837 , RISCV::FENCE, Convert__imm_95_1__imm_95_0, AMFBS_HasStdExtZihintpause, { }, },
{ 8843 , RISCV::PREFETCH_I, Convert__Reg1_2__SImm12Lsb000001_0, AMFBS_HasStdExtZicbop, { MCK_SImm12Lsb00000, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8854 , RISCV::PREFETCH_R, Convert__Reg1_2__SImm12Lsb000001_0, AMFBS_HasStdExtZicbop, { MCK_SImm12Lsb00000, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8865 , RISCV::PREFETCH_W, Convert__Reg1_2__SImm12Lsb000001_0, AMFBS_HasStdExtZicbop, { MCK_SImm12Lsb00000, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 8876 , RISCV::QK_C_LBU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 8876 , RISCV::QK_C_LBU, Convert__Reg1_0__Reg1_3__UImm51_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm5, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 8885 , RISCV::QK_C_LBUSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, },
{ 8885 , RISCV::QK_C_LBUSP, Convert__Reg1_0__Reg1_3__UImm41_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm4, MCK__40_, MCK_SP, MCK__41_ }, },
{ 8896 , RISCV::QK_C_LHU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 8896 , RISCV::QK_C_LHU, Convert__Reg1_0__Reg1_3__UImm6Lsb01_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm6Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 8905 , RISCV::QK_C_LHUSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, },
{ 8905 , RISCV::QK_C_LHUSP, Convert__Reg1_0__Reg1_3__UImm5Lsb01_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm5Lsb0, MCK__40_, MCK_SP, MCK__41_ }, },
{ 8916 , RISCV::QK_C_SB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 8916 , RISCV::QK_C_SB, Convert__Reg1_0__Reg1_3__UImm51_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm5, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 8924 , RISCV::QK_C_SBSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, },
{ 8924 , RISCV::QK_C_SBSP, Convert__Reg1_0__Reg1_3__UImm41_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm4, MCK__40_, MCK_SP, MCK__41_ }, },
{ 8934 , RISCV::QK_C_SH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 8934 , RISCV::QK_C_SH, Convert__Reg1_0__Reg1_3__UImm6Lsb01_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm6Lsb0, MCK__40_, MCK_GPRC, MCK__41_ }, },
{ 8942 , RISCV::QK_C_SHSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, },
{ 8942 , RISCV::QK_C_SHSP, Convert__Reg1_0__Reg1_3__UImm5Lsb01_1, AMFBS_HasVendorXwchc, { MCK_GPRC, MCK_UImm5Lsb0, MCK__40_, MCK_SP, MCK__41_ }, },
{ 8952 , RISCV::CSRRS, Convert__Reg1_0__imm_95_3072__regX0, AMFBS_None, { MCK_GPR }, },
{ 8960 , RISCV::CSRRS, Convert__Reg1_0__imm_95_3200__regX0, AMFBS_IsRV32, { MCK_GPR }, },
{ 8969 , RISCV::CSRRS, Convert__Reg1_0__imm_95_3074__regX0, AMFBS_None, { MCK_GPR }, },
{ 8979 , RISCV::CSRRS, Convert__Reg1_0__imm_95_3202__regX0, AMFBS_IsRV32, { MCK_GPR }, },
{ 8990 , RISCV::CSRRS, Convert__Reg1_0__imm_95_3073__regX0, AMFBS_None, { MCK_GPR }, },
{ 8997 , RISCV::CSRRS, Convert__Reg1_0__imm_95_3201__regX0, AMFBS_IsRV32, { MCK_GPR }, },
{ 9005 , RISCV::REM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 9009 , RISCV::REMU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 9014 , RISCV::REMUW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 9020 , RISCV::REMW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 9025 , RISCV::JALR, Convert__regX0__regX1__imm_95_0, AMFBS_None, { }, },
{ 9029 , RISCV::REV8_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbbOrZbkb_IsRV32, { MCK_GPR, MCK_GPR }, },
{ 9029 , RISCV::REV8_RV64, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR }, },
{ 9034 , RISCV::ROL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 9038 , RISCV::ROLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 9043 , RISCV::ROR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 9043 , RISCV::RORI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
{ 9047 , RISCV::RORI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
{ 9052 , RISCV::RORIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 9058 , RISCV::RORW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 9058 , RISCV::RORIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 9063 , RISCV::PseudoSB, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
{ 9063 , RISCV::SB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 9063 , RISCV::SB, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 9066 , RISCV::SB_AQ_RL, Convert__ZeroOffsetMemOpOperand1_1__Reg1_0, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 9074 , RISCV::SB_RL, Convert__ZeroOffsetMemOpOperand1_1__Reg1_0, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 9080 , RISCV::SC_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZalrsc_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 9085 , RISCV::SC_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZalrsc_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 9093 , RISCV::SC_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZalrsc_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 9103 , RISCV::SC_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZalrsc_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 9111 , RISCV::SC_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZalrsc, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 9116 , RISCV::SC_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZalrsc, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 9124 , RISCV::SC_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZalrsc, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 9134 , RISCV::SC_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtAOrZalrsc, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 9142 , RISCV::SCTRCLR, Convert_NoOperands, AMFBS_HasStdExtSmctrOrSsctr, { }, },
{ 9150 , RISCV::PseudoSD, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
{ 9150 , RISCV::SD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 9150 , RISCV::SD, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 9153 , RISCV::SD_AQ_RL, Convert__ZeroOffsetMemOpOperand1_1__Reg1_0, AMFBS_HasStdExtZalasr_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 9161 , RISCV::SD_RL, Convert__ZeroOffsetMemOpOperand1_1__Reg1_0, AMFBS_HasStdExtZalasr_IsRV64, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 9167 , RISCV::SLTIU, Convert__Reg1_0__Reg1_1__imm_95_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
{ 9172 , RISCV::SEXT_B, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
{ 9172 , RISCV::PseudoSEXT_B, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
{ 9179 , RISCV::SEXT_H, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb, { MCK_GPR, MCK_GPR }, },
{ 9179 , RISCV::PseudoSEXT_H, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
{ 9186 , RISCV::ADDIW, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, },
{ 9193 , RISCV::SF_CDISCARD_D_L1, Convert__regX0, AMFBS_HasVendorXSiFivecdiscarddlone, { }, },
{ 9193 , RISCV::SF_CDISCARD_D_L1, Convert__Reg1_0, AMFBS_HasVendorXSiFivecdiscarddlone, { MCK_GPR }, },
{ 9210 , RISCV::SF_CEASE, Convert_NoOperands, AMFBS_HasVendorXSfcease, { }, },
{ 9219 , RISCV::SF_CFLUSH_D_L1, Convert__regX0, AMFBS_HasVendorXSiFivecflushdlone, { }, },
{ 9219 , RISCV::SF_CFLUSH_D_L1, Convert__Reg1_0, AMFBS_HasVendorXSiFivecflushdlone, { MCK_GPR }, },
{ 9234 , RISCV::VC_FV, Convert__UImm11_0__UImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_UImm5, MCK_VM, MCK_FPR32 }, },
{ 9243 , RISCV::VC_FVV, Convert__UImm11_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VM, MCK_VM, MCK_FPR32 }, },
{ 9253 , RISCV::VC_FVW, Convert__UImm11_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VM, MCK_VM, MCK_FPR32 }, },
{ 9263 , RISCV::VC_I, Convert__UImm21_0__UImm51_1__UImm51_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_UImm5, MCK_SImm5 }, },
{ 9271 , RISCV::VC_IV, Convert__UImm21_0__UImm51_1__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VM, MCK_SImm5 }, },
{ 9280 , RISCV::VC_IVV, Convert__UImm21_0__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VM, MCK_VM, MCK_SImm5 }, },
{ 9290 , RISCV::VC_IVW, Convert__UImm21_0__Reg1_1__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VM, MCK_VM, MCK_SImm5 }, },
{ 9300 , RISCV::VC_V_FV, Convert__Reg1_1__UImm11_0__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VM, MCK_VM, MCK_FPR32 }, },
{ 9311 , RISCV::VC_V_FVV, Convert__Reg1_1__UImm11_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VM, MCK_VM, MCK_FPR32 }, },
{ 9323 , RISCV::VC_V_FVW, Convert__Reg1_1__UImm11_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm1, MCK_VM, MCK_VM, MCK_FPR32 }, },
{ 9335 , RISCV::VC_V_I, Convert__Reg1_2__UImm21_0__UImm51_1__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VM, MCK_SImm5 }, },
{ 9345 , RISCV::VC_V_IV, Convert__Reg1_1__UImm21_0__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VM, MCK_VM, MCK_SImm5 }, },
{ 9356 , RISCV::VC_V_IVV, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VM, MCK_VM, MCK_SImm5 }, },
{ 9368 , RISCV::VC_V_IVW, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__SImm51_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VM, MCK_VM, MCK_SImm5 }, },
{ 9380 , RISCV::VC_V_VV, Convert__Reg1_1__UImm21_0__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VM, MCK_VM, MCK_VM }, },
{ 9391 , RISCV::VC_V_VVV, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VM, MCK_VM, MCK_VM }, },
{ 9403 , RISCV::VC_V_VVW, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VM, MCK_VM, MCK_VM }, },
{ 9415 , RISCV::VC_V_X, Convert__Reg1_2__UImm21_0__UImm51_1__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VM, MCK_GPR }, },
{ 9425 , RISCV::VC_V_XV, Convert__Reg1_1__UImm21_0__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VM, MCK_VM, MCK_GPR }, },
{ 9436 , RISCV::VC_V_XVV, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VM, MCK_VM, MCK_GPR }, },
{ 9448 , RISCV::VC_V_XVW, Convert__Reg1_1__UImm21_0__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VM, MCK_VM, MCK_GPR }, },
{ 9460 , RISCV::VC_VV, Convert__UImm21_0__UImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VM, MCK_VM }, },
{ 9469 , RISCV::VC_VVV, Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VM, MCK_VM, MCK_VM }, },
{ 9479 , RISCV::VC_VVW, Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VM, MCK_VM, MCK_VM }, },
{ 9489 , RISCV::VC_X, Convert__UImm21_0__UImm51_1__UImm51_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_UImm5, MCK_GPR }, },
{ 9497 , RISCV::VC_XV, Convert__UImm21_0__UImm51_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_UImm5, MCK_VM, MCK_GPR }, },
{ 9506 , RISCV::VC_XVV, Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VM, MCK_VM, MCK_GPR }, },
{ 9516 , RISCV::VC_XVW, Convert__UImm21_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasVendorXSfvcp, { MCK_UImm2, MCK_VM, MCK_VM, MCK_GPR }, },
{ 9526 , RISCV::VFNRCLIP_X_F_QF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXSfvfnrclipxfqf, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 9545 , RISCV::VFNRCLIP_XU_F_QF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXSfvfnrclipxfqf, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 9565 , RISCV::VFWMACC_4x4x4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvfwmaccqqq, { MCK_VM, MCK_VM, MCK_VM }, },
{ 9582 , RISCV::VQMACC_2x8x2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccdod, { MCK_VM, MCK_VM, MCK_VM }, },
{ 9598 , RISCV::VQMACC_4x8x4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccqoq, { MCK_VM, MCK_VM, MCK_VM }, },
{ 9614 , RISCV::VQMACCSU_2x8x2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccdod, { MCK_VM, MCK_VM, MCK_VM }, },
{ 9632 , RISCV::VQMACCSU_4x8x4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccqoq, { MCK_VM, MCK_VM, MCK_VM }, },
{ 9650 , RISCV::VQMACCU_2x8x2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccdod, { MCK_VM, MCK_VM, MCK_VM }, },
{ 9667 , RISCV::VQMACCU_4x8x4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccqoq, { MCK_VM, MCK_VM, MCK_VM }, },
{ 9684 , RISCV::VQMACCUS_2x8x2, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccdod, { MCK_VM, MCK_VM, MCK_VM }, },
{ 9702 , RISCV::VQMACCUS_4x8x4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXSfvqmaccqoq, { MCK_VM, MCK_VM, MCK_VM }, },
{ 9720 , RISCV::SFENCE_INVAL_IR, Convert_NoOperands, AMFBS_HasStdExtSvinval, { }, },
{ 9736 , RISCV::SFENCE_VMA, Convert__regX0__regX0, AMFBS_None, { }, },
{ 9736 , RISCV::SFENCE_VMA, Convert__Reg1_0__regX0, AMFBS_None, { MCK_GPR }, },
{ 9736 , RISCV::SFENCE_VMA, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
{ 9747 , RISCV::SFENCE_W_INVAL, Convert_NoOperands, AMFBS_HasStdExtSvinval, { }, },
{ 9762 , RISCV::SLT, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 9766 , RISCV::SLTU, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 9771 , RISCV::SLT, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
{ 9776 , RISCV::PseudoSH, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
{ 9776 , RISCV::SH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 9776 , RISCV::SH, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 9779 , RISCV::SH_AQ_RL, Convert__ZeroOffsetMemOpOperand1_1__Reg1_0, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 9787 , RISCV::SH_RL, Convert__ZeroOffsetMemOpOperand1_1__Reg1_0, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 9793 , RISCV::SH1ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 9800 , RISCV::SH1ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 9810 , RISCV::SH2ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 9817 , RISCV::SH2ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 9827 , RISCV::SH3ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 9834 , RISCV::SH3ADD_UW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 9844 , RISCV::SHA256SIG0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, },
{ 9855 , RISCV::SHA256SIG1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, },
{ 9866 , RISCV::SHA256SUM0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, },
{ 9877 , RISCV::SHA256SUM1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh, { MCK_GPR, MCK_GPR }, },
{ 9888 , RISCV::SHA512SIG0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, },
{ 9899 , RISCV::SHA512SIG0H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 9911 , RISCV::SHA512SIG0L, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 9923 , RISCV::SHA512SIG1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, },
{ 9934 , RISCV::SHA512SIG1H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 9946 , RISCV::SHA512SIG1L, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 9958 , RISCV::SHA512SUM0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, },
{ 9969 , RISCV::SHA512SUM0R, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 9981 , RISCV::SHA512SUM1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZknh_IsRV64, { MCK_GPR, MCK_GPR }, },
{ 9992 , RISCV::SHA512SUM1R, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZknh_IsRV32, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 10004 , RISCV::SINVAL_VMA, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtSvinval, { MCK_GPR, MCK_GPR }, },
{ 10015 , RISCV::SLL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 10015 , RISCV::SLLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
{ 10019 , RISCV::SLLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
{ 10024 , RISCV::SLLI_UW, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
{ 10032 , RISCV::SLLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 10038 , RISCV::SLLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 10038 , RISCV::SLLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 10043 , RISCV::SLT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 10043 , RISCV::SLTI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
{ 10047 , RISCV::SLTI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
{ 10052 , RISCV::SLTIU, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
{ 10058 , RISCV::SLTU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 10058 , RISCV::SLTIU, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
{ 10063 , RISCV::SLT, Convert__Reg1_0__Reg1_1__regX0, AMFBS_None, { MCK_GPR, MCK_GPR }, },
{ 10068 , RISCV::SM3P0, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZksh, { MCK_GPR, MCK_GPR }, },
{ 10074 , RISCV::SM3P1, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZksh, { MCK_GPR, MCK_GPR }, },
{ 10080 , RISCV::SM4ED, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZksed, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10086 , RISCV::SM4KS, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasStdExtZksed, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10092 , RISCV::SLTU, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
{ 10097 , RISCV::SRA, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 10097 , RISCV::SRAI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
{ 10101 , RISCV::SRAI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
{ 10106 , RISCV::SRAIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 10112 , RISCV::SRAW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 10112 , RISCV::SRAIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 10117 , RISCV::SRET, Convert_NoOperands, AMFBS_None, { }, },
{ 10122 , RISCV::SRL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 10122 , RISCV::SRLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
{ 10126 , RISCV::SRLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
{ 10131 , RISCV::SRLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 10137 , RISCV::SRLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 10137 , RISCV::SRLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 10142 , RISCV::SSAMOSWAP_D, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZicfiss_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 10154 , RISCV::SSAMOSWAP_D_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZicfiss_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 10169 , RISCV::SSAMOSWAP_D_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZicfiss_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 10186 , RISCV::SSAMOSWAP_D_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZicfiss_IsRV64, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 10201 , RISCV::SSAMOSWAP_W, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZicfiss, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 10213 , RISCV::SSAMOSWAP_W_AQ, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZicfiss, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 10228 , RISCV::SSAMOSWAP_W_AQ_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZicfiss, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 10245 , RISCV::SSAMOSWAP_W_RL, Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtZicfiss, { MCK_GPR, MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 10260 , RISCV::SSPOPCHK, Convert__Reg1_0, AMFBS_HasStdExtZicfiss, { MCK_GPRX1X5 }, },
{ 10269 , RISCV::SSPUSH, Convert__Reg1_0, AMFBS_HasStdExtZicfiss, { MCK_GPRX1X5 }, },
{ 10276 , RISCV::SSRDP, Convert__Reg1_0, AMFBS_HasStdExtZicfiss, { MCK_GPRNoX0 }, },
{ 10282 , RISCV::SUB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 10286 , RISCV::SUBW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 10291 , RISCV::PseudoSW, Convert__Reg1_2__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
{ 10291 , RISCV::SW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 10291 , RISCV::SW, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 10294 , RISCV::SW_AQ_RL, Convert__ZeroOffsetMemOpOperand1_1__Reg1_0, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 10302 , RISCV::SW_RL, Convert__ZeroOffsetMemOpOperand1_1__Reg1_0, AMFBS_HasStdExtZalasr, { MCK_GPR, MCK_ZeroOffsetMemOpOperand }, },
{ 10308 , RISCV::PseudoTAIL, Convert__CallSymbol1_0, AMFBS_None, { MCK_CallSymbol }, },
{ 10313 , RISCV::TH_ADDSL, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadBa, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10322 , RISCV::TH_DCACHE_CALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
{ 10337 , RISCV::TH_DCACHE_CIALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
{ 10353 , RISCV::TH_DCACHE_CIPA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
{ 10368 , RISCV::TH_DCACHE_CISW, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
{ 10383 , RISCV::TH_DCACHE_CIVA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
{ 10398 , RISCV::TH_DCACHE_CPA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
{ 10412 , RISCV::TH_DCACHE_CPAL1, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
{ 10428 , RISCV::TH_DCACHE_CSW, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
{ 10442 , RISCV::TH_DCACHE_CVA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
{ 10456 , RISCV::TH_DCACHE_CVAL1, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
{ 10472 , RISCV::TH_DCACHE_IALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
{ 10487 , RISCV::TH_DCACHE_IPA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
{ 10501 , RISCV::TH_DCACHE_ISW, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
{ 10515 , RISCV::TH_DCACHE_IVA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
{ 10529 , RISCV::TH_EXT, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen, MCK_UImmLog2XLen }, },
{ 10536 , RISCV::TH_EXTU, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2__UImmLog2XLen1_3, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen, MCK_UImmLog2XLen }, },
{ 10544 , RISCV::TH_FF0, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR }, },
{ 10551 , RISCV::TH_FF1, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR }, },
{ 10558 , RISCV::TH_FLRD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD, { MCK_FPR64, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10566 , RISCV::TH_FLRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10574 , RISCV::TH_FLURD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10583 , RISCV::TH_FLURW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10592 , RISCV::TH_FSRD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD, { MCK_FPR64, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10600 , RISCV::TH_FSRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10608 , RISCV::TH_FSURD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10617 , RISCV::TH_FSURW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadFMemIdx_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10626 , RISCV::TH_ICACHE_IALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
{ 10641 , RISCV::TH_ICACHE_IALLS, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
{ 10657 , RISCV::TH_ICACHE_IPA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
{ 10671 , RISCV::TH_ICACHE_IVA, Convert__Reg1_0, AMFBS_HasVendorXTHeadCmo, { MCK_GPR }, },
{ 10685 , RISCV::TH_L2CACHE_CALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
{ 10701 , RISCV::TH_L2CACHE_CIALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
{ 10718 , RISCV::TH_L2CACHE_IALL, Convert_NoOperands, AMFBS_HasVendorXTHeadCmo, { }, },
{ 10734 , RISCV::TH_LBIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 10742 , RISCV::TH_LBIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 10750 , RISCV::TH_LBUIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 10759 , RISCV::TH_LBUIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 10768 , RISCV::TH_LDD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__UImm71_6, AMFBS_HasVendorXTHeadMemPair_IsRV64, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_UImm7 }, },
{ 10775 , RISCV::TH_LDIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 10783 , RISCV::TH_LDIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 10791 , RISCV::TH_LHIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 10799 , RISCV::TH_LHIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 10807 , RISCV::TH_LHUIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 10816 , RISCV::TH_LHUIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 10825 , RISCV::TH_LRB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10832 , RISCV::TH_LRBU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10840 , RISCV::TH_LRD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10847 , RISCV::TH_LRH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10854 , RISCV::TH_LRHU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10862 , RISCV::TH_LRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10869 , RISCV::TH_LRWU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10877 , RISCV::TH_LURB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10885 , RISCV::TH_LURBU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10894 , RISCV::TH_LURD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10902 , RISCV::TH_LURH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10910 , RISCV::TH_LURHU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10919 , RISCV::TH_LURW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10927 , RISCV::TH_LURWU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 10936 , RISCV::TH_LWD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__UImm71_6, AMFBS_HasVendorXTHeadMemPair, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_UImm7 }, },
{ 10943 , RISCV::TH_LWIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 10951 , RISCV::TH_LWIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 10959 , RISCV::TH_LWUD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__UImm71_6, AMFBS_HasVendorXTHeadMemPair, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_UImm7 }, },
{ 10967 , RISCV::TH_LWUIA, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 10976 , RISCV::TH_LWUIB, Convert__Reg1_0__Reg1_2__Tie1_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 10985 , RISCV::TH_MULA, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 10993 , RISCV::TH_MULAH, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 11002 , RISCV::TH_MULAW, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 11011 , RISCV::TH_MULS, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 11019 , RISCV::TH_MULSH, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 11028 , RISCV::TH_MULSW, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadMac_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 11037 , RISCV::TH_MVEQZ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadCondMov, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 11046 , RISCV::TH_MVNEZ, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasVendorXTHeadCondMov, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 11055 , RISCV::TH_REV, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR }, },
{ 11062 , RISCV::TH_REVW, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb_IsRV64, { MCK_GPR, MCK_GPR }, },
{ 11070 , RISCV::TH_SBIA, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 11078 , RISCV::TH_SBIB, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 11086 , RISCV::TH_SDD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__UImm71_6, AMFBS_HasVendorXTHeadMemPair_IsRV64, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_UImm7 }, },
{ 11093 , RISCV::TH_SDIA, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 11101 , RISCV::TH_SDIB, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 11109 , RISCV::TH_SFENCE_VMAS, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadSync, { MCK_GPR, MCK_GPR }, },
{ 11124 , RISCV::TH_SHIA, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 11132 , RISCV::TH_SHIB, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 11140 , RISCV::TH_SRB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 11147 , RISCV::TH_SRD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 11154 , RISCV::TH_SRH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 11161 , RISCV::TH_SRRI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
{ 11169 , RISCV::TH_SRRIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasVendorXTHeadBb_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
{ 11178 , RISCV::TH_SRW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 11185 , RISCV::TH_SURB, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 11193 , RISCV::TH_SURD, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 11201 , RISCV::TH_SURH, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 11209 , RISCV::TH_SURW, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
{ 11217 , RISCV::TH_SWD, Convert__Reg1_0__Reg1_1__Reg1_3__UImm21_5__UImm71_6, AMFBS_HasVendorXTHeadMemPair, { MCK_GPR, MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_UImm2, MCK_UImm7 }, },
{ 11224 , RISCV::TH_SWIA, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 11232 , RISCV::TH_SWIB, Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm51_4__UImm21_5, AMFBS_HasVendorXTHeadMemIdx, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_, MCK_SImm5, MCK_UImm2 }, },
{ 11240 , RISCV::TH_SYNC, Convert_NoOperands, AMFBS_HasVendorXTHeadSync, { }, },
{ 11248 , RISCV::TH_SYNC_I, Convert_NoOperands, AMFBS_HasVendorXTHeadSync, { }, },
{ 11258 , RISCV::TH_SYNC_IS, Convert_NoOperands, AMFBS_HasVendorXTHeadSync, { }, },
{ 11269 , RISCV::TH_SYNC_S, Convert_NoOperands, AMFBS_HasVendorXTHeadSync, { }, },
{ 11279 , RISCV::TH_TST, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_HasVendorXTHeadBs, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
{ 11286 , RISCV::TH_TSTNBZ, Convert__Reg1_0__Reg1_1, AMFBS_HasVendorXTHeadBb, { MCK_GPR, MCK_GPR }, },
{ 11296 , RISCV::THVdotVMAQA_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11308 , RISCV::THVdotVMAQA_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11320 , RISCV::THVdotVMAQASU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11334 , RISCV::THVdotVMAQASU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11348 , RISCV::THVdotVMAQAU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11361 , RISCV::THVdotVMAQAU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11374 , RISCV::THVdotVMAQAUS_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVendorXTHeadVdot, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11388 , RISCV::UNIMP, Convert_NoOperands, AMFBS_None, { }, },
{ 11394 , RISCV::UNZIP_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbkb_IsRV32, { MCK_GPR, MCK_GPR }, },
{ 11400 , RISCV::VAADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11409 , RISCV::VAADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 11418 , RISCV::VAADDU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11428 , RISCV::VAADDU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 11438 , RISCV::VADC_VIM, Convert__Reg1_0__Reg1_1__SImm51_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_VMV0 }, },
{ 11447 , RISCV::VADC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_VMV0 }, },
{ 11456 , RISCV::VADC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_VMV0 }, },
{ 11465 , RISCV::VADD_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
{ 11473 , RISCV::VADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11481 , RISCV::VADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 11489 , RISCV::VAESDF_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VM, MCK_VM }, },
{ 11499 , RISCV::VAESDF_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VM, MCK_VM }, },
{ 11509 , RISCV::VAESDM_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VM, MCK_VM }, },
{ 11519 , RISCV::VAESDM_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VM, MCK_VM }, },
{ 11529 , RISCV::VAESEF_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VM, MCK_VM }, },
{ 11539 , RISCV::VAESEF_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VM, MCK_VM }, },
{ 11549 , RISCV::VAESEM_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VM, MCK_VM }, },
{ 11559 , RISCV::VAESEM_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VM, MCK_VM }, },
{ 11569 , RISCV::VAESKF1_VI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZvkned, { MCK_VM, MCK_VM, MCK_UImm5 }, },
{ 11580 , RISCV::VAESKF2_VI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2, AMFBS_HasStdExtZvkned, { MCK_VM, MCK_VM, MCK_UImm5 }, },
{ 11591 , RISCV::VAESZ_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkned, { MCK_VM, MCK_VM }, },
{ 11600 , RISCV::VAND_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
{ 11608 , RISCV::VAND_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11616 , RISCV::VAND_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 11624 , RISCV::VANDN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11633 , RISCV::VANDN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 11642 , RISCV::VASUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11651 , RISCV::VASUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 11660 , RISCV::VASUBU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11670 , RISCV::VASUBU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 11680 , RISCV::VBREV_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvbb, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11688 , RISCV::VBREV8_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvkb, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11697 , RISCV::VCLMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbcOrZvbc32e, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11707 , RISCV::VCLMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbcOrZvbc32e, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 11717 , RISCV::VCLMULH_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbcOrZvbc32e, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11728 , RISCV::VCLMULH_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbcOrZvbc32e, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 11739 , RISCV::VCLZ_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvbb, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11746 , RISCV::VCOMPRESS_VM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, },
{ 11759 , RISCV::VCPOP_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11767 , RISCV::VCPOP_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvbb, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11775 , RISCV::VCTZ_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvbb, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11782 , RISCV::VDIV_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11790 , RISCV::VDIV_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 11798 , RISCV::VDIVU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11807 , RISCV::VDIVU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 11816 , RISCV::VFSGNJX_VV, Convert__Reg1_0__Reg1_1__Reg1_1__reg0, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM }, },
{ 11816 , RISCV::VFSGNJX_VV, Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11824 , RISCV::VFADD_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 11833 , RISCV::VFADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11842 , RISCV::VFCLASS_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11852 , RISCV::VFCVT_F_X_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11864 , RISCV::VFCVT_F_XU_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11877 , RISCV::VFCVT_RTZ_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11893 , RISCV::VFCVT_RTZ_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11910 , RISCV::VFCVT_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11922 , RISCV::VFCVT_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11935 , RISCV::VFDIV_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 11944 , RISCV::VFDIV_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11953 , RISCV::VFIRST_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11962 , RISCV::VFMACC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11972 , RISCV::VFMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11982 , RISCV::VFMADD_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 11992 , RISCV::VFMADD_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12002 , RISCV::VFMAX_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 12011 , RISCV::VFMAX_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12020 , RISCV::VFMERGE_VFM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_VMV0 }, },
{ 12032 , RISCV::VFMIN_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 12041 , RISCV::VFMIN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12050 , RISCV::VFMSAC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12060 , RISCV::VFMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12070 , RISCV::VFMSUB_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12080 , RISCV::VFMSUB_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12090 , RISCV::VFMUL_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 12099 , RISCV::VFMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12108 , RISCV::VFMV_F_S, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructionsAnyF, { MCK_FPR32, MCK_VM }, },
{ 12117 , RISCV::VFMV_S_F, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32 }, },
{ 12126 , RISCV::VFMV_V_F, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32 }, },
{ 12135 , RISCV::VFNCVT_F_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12148 , RISCV::VFNCVT_F_X_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12161 , RISCV::VFNCVT_F_XU_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12175 , RISCV::VFNCVT_ROD_F_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12192 , RISCV::VFNCVT_RTZ_X_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12209 , RISCV::VFNCVT_RTZ_XU_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12227 , RISCV::VFNCVT_X_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12240 , RISCV::VFNCVT_XU_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12254 , RISCV::VFNCVTBF16_F_F_W, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfbfmin, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12271 , RISCV::VFSGNJN_VV, Convert__Reg1_0__Reg1_1__Reg1_1__reg0, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM }, },
{ 12271 , RISCV::VFSGNJN_VV, Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12279 , RISCV::VFNMACC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12290 , RISCV::VFNMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12301 , RISCV::VFNMADD_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12312 , RISCV::VFNMADD_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12323 , RISCV::VFNMSAC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12334 , RISCV::VFNMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12345 , RISCV::VFNMSUB_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12356 , RISCV::VFNMSUB_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12367 , RISCV::VFRDIV_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 12377 , RISCV::VFREC7_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12386 , RISCV::VFREDMAX_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12398 , RISCV::VFREDMIN_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12410 , RISCV::VFREDOSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12423 , RISCV::VFREDUSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12435 , RISCV::VFREDUSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12448 , RISCV::VFRSQRT7_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12459 , RISCV::VFRSUB_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 12469 , RISCV::VFSGNJ_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 12479 , RISCV::VFSGNJ_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12489 , RISCV::VFSGNJN_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 12500 , RISCV::VFSGNJN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12511 , RISCV::VFSGNJX_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 12522 , RISCV::VFSGNJX_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12533 , RISCV::VFSLIDE1DOWN_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 12549 , RISCV::VFSLIDE1UP_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 12563 , RISCV::VFSQRT_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12572 , RISCV::VFSUB_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 12581 , RISCV::VFSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12590 , RISCV::VFWADD_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 12600 , RISCV::VFWADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12610 , RISCV::VFWADD_WF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 12620 , RISCV::VFWADD_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12630 , RISCV::VFWCVT_F_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12643 , RISCV::VFWCVT_F_X_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12656 , RISCV::VFWCVT_F_XU_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12670 , RISCV::VFWCVT_RTZ_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12687 , RISCV::VFWCVT_RTZ_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12705 , RISCV::VFWCVT_X_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12718 , RISCV::VFWCVT_XU_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12732 , RISCV::VFWCVTBF16_F_F_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvfbfmin, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12749 , RISCV::VFWMACC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12760 , RISCV::VFWMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12771 , RISCV::VFWMACCBF16_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvfbfwma, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12786 , RISCV::VFWMACCBF16_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvfbfwma, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12801 , RISCV::VFWMSAC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12812 , RISCV::VFWMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12823 , RISCV::VFWMUL_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 12833 , RISCV::VFWMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12843 , RISCV::VFWNMACC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12855 , RISCV::VFWNMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12867 , RISCV::VFWNMSAC_VF, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_FPR32, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12879 , RISCV::VFWNMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12891 , RISCV::VFWREDOSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12905 , RISCV::VFWREDUSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12918 , RISCV::VFWREDUSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12932 , RISCV::VFWSUB_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 12942 , RISCV::VFWSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12952 , RISCV::VFWSUB_WF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 12962 , RISCV::VFWSUB_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 12972 , RISCV::VGHSH_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvkgs, { MCK_VM, MCK_VM, MCK_VM }, },
{ 12981 , RISCV::VGHSH_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvkg, { MCK_VM, MCK_VM, MCK_VM }, },
{ 12990 , RISCV::VGMUL_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkgs, { MCK_VM, MCK_VM }, },
{ 12999 , RISCV::VGMUL_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvkg, { MCK_VM, MCK_VM }, },
{ 13008 , RISCV::VID_V, Convert__Reg1_0__RVVMaskRegOpOperand1_1, AMFBS_HasVInstructions, { MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13014 , RISCV::VIOTA_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13022 , RISCV::VL1RE8_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 13029 , RISCV::VL1RE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand }, },
{ 13039 , RISCV::VL1RE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand }, },
{ 13049 , RISCV::VL1RE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand }, },
{ 13059 , RISCV::VL1RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand }, },
{ 13068 , RISCV::VL2RE8_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VRM2, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 13075 , RISCV::VL2RE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
{ 13085 , RISCV::VL2RE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
{ 13095 , RISCV::VL2RE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructionsI64, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
{ 13105 , RISCV::VL2RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
{ 13114 , RISCV::VL4RE8_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VRM4, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 13121 , RISCV::VL4RE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
{ 13131 , RISCV::VL4RE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
{ 13141 , RISCV::VL4RE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructionsI64, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
{ 13151 , RISCV::VL4RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
{ 13160 , RISCV::VL8RE8_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VRM8, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 13167 , RISCV::VL8RE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
{ 13177 , RISCV::VL8RE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
{ 13187 , RISCV::VL8RE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructionsI64, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
{ 13197 , RISCV::VL8RE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
{ 13206 , RISCV::VLM_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 13213 , RISCV::VLE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13221 , RISCV::VLE16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13231 , RISCV::VLE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13239 , RISCV::VLE32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13249 , RISCV::VLE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13257 , RISCV::VLE64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13267 , RISCV::VLE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13274 , RISCV::VLE8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13283 , RISCV::VLM_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand }, },
{ 13289 , RISCV::VLOXEI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13300 , RISCV::VLOXEI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13311 , RISCV::VLOXEI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13322 , RISCV::VLOXEI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13332 , RISCV::VLOXSEG2EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13347 , RISCV::VLOXSEG2EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13362 , RISCV::VLOXSEG2EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13377 , RISCV::VLOXSEG2EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13391 , RISCV::VLOXSEG3EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13406 , RISCV::VLOXSEG3EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13421 , RISCV::VLOXSEG3EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13436 , RISCV::VLOXSEG3EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13450 , RISCV::VLOXSEG4EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13465 , RISCV::VLOXSEG4EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13480 , RISCV::VLOXSEG4EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13495 , RISCV::VLOXSEG4EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13509 , RISCV::VLOXSEG5EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13524 , RISCV::VLOXSEG5EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13539 , RISCV::VLOXSEG5EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13554 , RISCV::VLOXSEG5EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13568 , RISCV::VLOXSEG6EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13583 , RISCV::VLOXSEG6EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13598 , RISCV::VLOXSEG6EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13613 , RISCV::VLOXSEG6EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13627 , RISCV::VLOXSEG7EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13642 , RISCV::VLOXSEG7EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13657 , RISCV::VLOXSEG7EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13672 , RISCV::VLOXSEG7EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13686 , RISCV::VLOXSEG8EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13701 , RISCV::VLOXSEG8EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13716 , RISCV::VLOXSEG8EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13731 , RISCV::VLOXSEG8EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 13745 , RISCV::VLSE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 13754 , RISCV::VLSE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 13763 , RISCV::VLSE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 13772 , RISCV::VLSE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 13780 , RISCV::VLSEG2E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13792 , RISCV::VLSEG2E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13806 , RISCV::VLSEG2E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13818 , RISCV::VLSEG2E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13832 , RISCV::VLSEG2E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13844 , RISCV::VLSEG2E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13858 , RISCV::VLSEG2E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13869 , RISCV::VLSEG2E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13882 , RISCV::VLSEG3E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13894 , RISCV::VLSEG3E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13908 , RISCV::VLSEG3E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13920 , RISCV::VLSEG3E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13934 , RISCV::VLSEG3E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13946 , RISCV::VLSEG3E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13960 , RISCV::VLSEG3E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13971 , RISCV::VLSEG3E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13984 , RISCV::VLSEG4E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 13996 , RISCV::VLSEG4E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14010 , RISCV::VLSEG4E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14022 , RISCV::VLSEG4E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14036 , RISCV::VLSEG4E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14048 , RISCV::VLSEG4E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14062 , RISCV::VLSEG4E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14073 , RISCV::VLSEG4E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14086 , RISCV::VLSEG5E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14098 , RISCV::VLSEG5E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14112 , RISCV::VLSEG5E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14124 , RISCV::VLSEG5E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14138 , RISCV::VLSEG5E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14150 , RISCV::VLSEG5E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14164 , RISCV::VLSEG5E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14175 , RISCV::VLSEG5E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14188 , RISCV::VLSEG6E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14200 , RISCV::VLSEG6E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14214 , RISCV::VLSEG6E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14226 , RISCV::VLSEG6E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14240 , RISCV::VLSEG6E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14252 , RISCV::VLSEG6E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14266 , RISCV::VLSEG6E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14277 , RISCV::VLSEG6E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14290 , RISCV::VLSEG7E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14302 , RISCV::VLSEG7E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14316 , RISCV::VLSEG7E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14328 , RISCV::VLSEG7E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14342 , RISCV::VLSEG7E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14354 , RISCV::VLSEG7E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14368 , RISCV::VLSEG7E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14379 , RISCV::VLSEG7E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14392 , RISCV::VLSEG8E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14404 , RISCV::VLSEG8E16FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14418 , RISCV::VLSEG8E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14430 , RISCV::VLSEG8E32FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14444 , RISCV::VLSEG8E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14456 , RISCV::VLSEG8E64FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14470 , RISCV::VLSEG8E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14481 , RISCV::VLSEG8E8FF_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 14494 , RISCV::VLSSEG2E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14507 , RISCV::VLSSEG2E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14520 , RISCV::VLSSEG2E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14533 , RISCV::VLSSEG2E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14545 , RISCV::VLSSEG3E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14558 , RISCV::VLSSEG3E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14571 , RISCV::VLSSEG3E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14584 , RISCV::VLSSEG3E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14596 , RISCV::VLSSEG4E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14609 , RISCV::VLSSEG4E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14622 , RISCV::VLSSEG4E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14635 , RISCV::VLSSEG4E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14647 , RISCV::VLSSEG5E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14660 , RISCV::VLSSEG5E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14673 , RISCV::VLSSEG5E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14686 , RISCV::VLSSEG5E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14698 , RISCV::VLSSEG6E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14711 , RISCV::VLSSEG6E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14724 , RISCV::VLSSEG6E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14737 , RISCV::VLSSEG6E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14749 , RISCV::VLSSEG7E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14762 , RISCV::VLSSEG7E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14775 , RISCV::VLSSEG7E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14788 , RISCV::VLSSEG7E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14800 , RISCV::VLSSEG8E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14813 , RISCV::VLSSEG8E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14826 , RISCV::VLSSEG8E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14839 , RISCV::VLSSEG8E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 14851 , RISCV::VLUXEI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 14862 , RISCV::VLUXEI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 14873 , RISCV::VLUXEI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 14884 , RISCV::VLUXEI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 14894 , RISCV::VLUXSEG2EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 14909 , RISCV::VLUXSEG2EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 14924 , RISCV::VLUXSEG2EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 14939 , RISCV::VLUXSEG2EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 14953 , RISCV::VLUXSEG3EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 14968 , RISCV::VLUXSEG3EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 14983 , RISCV::VLUXSEG3EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 14998 , RISCV::VLUXSEG3EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15012 , RISCV::VLUXSEG4EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15027 , RISCV::VLUXSEG4EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15042 , RISCV::VLUXSEG4EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15057 , RISCV::VLUXSEG4EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15071 , RISCV::VLUXSEG5EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15086 , RISCV::VLUXSEG5EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15101 , RISCV::VLUXSEG5EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15116 , RISCV::VLUXSEG5EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15130 , RISCV::VLUXSEG6EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15145 , RISCV::VLUXSEG6EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15160 , RISCV::VLUXSEG6EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15175 , RISCV::VLUXSEG6EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15189 , RISCV::VLUXSEG7EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15204 , RISCV::VLUXSEG7EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15219 , RISCV::VLUXSEG7EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15234 , RISCV::VLUXSEG7EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15248 , RISCV::VLUXSEG8EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15263 , RISCV::VLUXSEG8EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15278 , RISCV::VLUXSEG8EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15293 , RISCV::VLUXSEG8EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15307 , RISCV::VMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15316 , RISCV::VMACC_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15325 , RISCV::VMADC_VI, Convert__Reg1_0__Reg1_1__SImm51_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5 }, },
{ 15334 , RISCV::VMADC_VIM, Convert__Reg1_0__Reg1_1__SImm51_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_VMV0 }, },
{ 15344 , RISCV::VMADC_VV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, },
{ 15353 , RISCV::VMADC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_VMV0 }, },
{ 15363 , RISCV::VMADC_VX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR }, },
{ 15372 , RISCV::VMADC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_VMV0 }, },
{ 15382 , RISCV::VMADD_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15391 , RISCV::VMADD_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15400 , RISCV::VMAND_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, },
{ 15409 , RISCV::VMANDN_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, },
{ 15419 , RISCV::VMANDN_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, },
{ 15431 , RISCV::VMAX_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15439 , RISCV::VMAX_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 15447 , RISCV::VMAXU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15456 , RISCV::VMAXU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 15465 , RISCV::VMXOR_MM, Convert__Reg1_0__Reg1_0__Reg1_0, AMFBS_HasVInstructions, { MCK_VM }, },
{ 15473 , RISCV::VMERGE_VIM, Convert__Reg1_0__Reg1_1__SImm51_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_VMV0 }, },
{ 15484 , RISCV::VMERGE_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_VMV0 }, },
{ 15495 , RISCV::VMERGE_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_VMV0 }, },
{ 15506 , RISCV::VMFEQ_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 15515 , RISCV::VMFEQ_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15524 , RISCV::VMFGE_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 15533 , RISCV::VMFLE_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15542 , RISCV::VMFGT_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 15551 , RISCV::VMFLT_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15560 , RISCV::VMFLE_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 15569 , RISCV::VMFLE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15578 , RISCV::VMFLT_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 15587 , RISCV::VMFLT_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15596 , RISCV::VMFNE_VF, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_FPR32, MCK_RVVMaskRegOpOperand }, },
{ 15605 , RISCV::VMFNE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsAnyF, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15614 , RISCV::VMIN_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15622 , RISCV::VMIN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 15630 , RISCV::VMINU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15639 , RISCV::VMINU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 15648 , RISCV::VMAND_MM, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasVInstructions, { MCK_VM, MCK_VM }, },
{ 15655 , RISCV::VMNAND_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, },
{ 15665 , RISCV::VMNOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, },
{ 15674 , RISCV::VMNAND_MM, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasVInstructions, { MCK_VM, MCK_VM }, },
{ 15682 , RISCV::VMOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, },
{ 15690 , RISCV::VMORN_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, },
{ 15699 , RISCV::VMORN_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, },
{ 15710 , RISCV::VMSBC_VV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, },
{ 15719 , RISCV::VMSBC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_VMV0 }, },
{ 15729 , RISCV::VMSBC_VX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR }, },
{ 15738 , RISCV::VMSBC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_VMV0 }, },
{ 15748 , RISCV::VMSBF_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15756 , RISCV::VMSEQ_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
{ 15765 , RISCV::VMSEQ_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15774 , RISCV::VMSEQ_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 15783 , RISCV::VMXNOR_MM, Convert__Reg1_0__Reg1_0__Reg1_0, AMFBS_HasVInstructions, { MCK_VM }, },
{ 15791 , RISCV::PseudoVMSGE_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, },
{ 15800 , RISCV::VMSLE_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15809 , RISCV::PseudoVMSGE_VX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR }, },
{ 15809 , RISCV::PseudoVMSGE_VX_M, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VRNoV0, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 15809 , RISCV::PseudoVMSGE_VX_M_T, Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand, MCK_VRNoV0 }, },
{ 15818 , RISCV::PseudoVMSGEU_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, },
{ 15828 , RISCV::VMSLEU_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15838 , RISCV::PseudoVMSGEU_VX, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR }, },
{ 15838 , RISCV::PseudoVMSGEU_VX_M, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VRNoV0, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 15838 , RISCV::PseudoVMSGEU_VX_M_T, Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand, MCK_VRNoV0 }, },
{ 15848 , RISCV::VMSGT_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
{ 15857 , RISCV::VMSLT_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15866 , RISCV::VMSGT_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 15875 , RISCV::VMSGTU_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
{ 15885 , RISCV::VMSLTU_VV, Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15895 , RISCV::VMSGTU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 15905 , RISCV::VMSIF_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15913 , RISCV::VMSLE_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
{ 15922 , RISCV::VMSLE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15931 , RISCV::VMSLE_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 15940 , RISCV::VMSLEU_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
{ 15950 , RISCV::VMSLEU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15960 , RISCV::VMSLEU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 15970 , RISCV::PseudoVMSLT_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, },
{ 15979 , RISCV::VMSLT_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 15988 , RISCV::VMSLT_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 15997 , RISCV::PseudoVMSLTU_VI, Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5Plus1, MCK_RVVMaskRegOpOperand }, },
{ 16007 , RISCV::VMSLTU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16017 , RISCV::VMSLTU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16027 , RISCV::VMSNE_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
{ 16036 , RISCV::VMSNE_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16045 , RISCV::VMSNE_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16054 , RISCV::VMSOF_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16062 , RISCV::VMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16070 , RISCV::VMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16078 , RISCV::VMULH_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16087 , RISCV::VMULH_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16096 , RISCV::VMULHSU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16107 , RISCV::VMULHSU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16118 , RISCV::VMULHU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16128 , RISCV::VMULHU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16138 , RISCV::VMV_S_X, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasVInstructions, { MCK_VM, MCK_GPR }, },
{ 16146 , RISCV::VMV_V_I, Convert__Reg1_0__SImm51_1, AMFBS_HasVInstructions, { MCK_VM, MCK_SImm5 }, },
{ 16154 , RISCV::VMV_V_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VM, MCK_VM }, },
{ 16162 , RISCV::VMV_V_X, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VM, MCK_GPR }, },
{ 16170 , RISCV::VMV_X_S, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_GPR, MCK_VM }, },
{ 16178 , RISCV::VMV1R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VM, MCK_VM }, },
{ 16186 , RISCV::VMV2R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_VRM2 }, },
{ 16194 , RISCV::VMV4R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_VRM4 }, },
{ 16202 , RISCV::VMV8R_V, Convert__Reg1_0__Reg1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_VRM8 }, },
{ 16210 , RISCV::VMXNOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, },
{ 16220 , RISCV::VMXOR_MM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM }, },
{ 16229 , RISCV::VNCLIP_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
{ 16239 , RISCV::VNCLIP_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16249 , RISCV::VNCLIP_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16259 , RISCV::VNCLIPU_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
{ 16270 , RISCV::VNCLIPU_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16281 , RISCV::VNCLIPU_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16292 , RISCV::VNSRL_WX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM }, },
{ 16292 , RISCV::VNSRL_WX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16304 , RISCV::VRSUB_VX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM }, },
{ 16304 , RISCV::VRSUB_VX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16311 , RISCV::VNMSAC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16321 , RISCV::VNMSAC_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16331 , RISCV::VNMSUB_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16341 , RISCV::VNMSUB_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16351 , RISCV::VXOR_VI, Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__reg0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM }, },
{ 16351 , RISCV::VXOR_VI, Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16358 , RISCV::VNSRA_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
{ 16367 , RISCV::VNSRA_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16376 , RISCV::VNSRA_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16385 , RISCV::VNSRL_WI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
{ 16394 , RISCV::VNSRL_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16403 , RISCV::VNSRL_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16412 , RISCV::VOR_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
{ 16419 , RISCV::VOR_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16426 , RISCV::VOR_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16433 , RISCV::VCPOP_M, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16441 , RISCV::VREDAND_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16452 , RISCV::VREDMAX_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16463 , RISCV::VREDMAXU_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16475 , RISCV::VREDMIN_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16486 , RISCV::VREDMINU_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16498 , RISCV::VREDOR_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16508 , RISCV::VREDSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16519 , RISCV::VREDXOR_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16530 , RISCV::VREM_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16538 , RISCV::VREM_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16546 , RISCV::VREMU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16555 , RISCV::VREMU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16564 , RISCV::VREV8_V, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasStdExtZvkb, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16572 , RISCV::VRGATHER_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
{ 16584 , RISCV::VRGATHER_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16596 , RISCV::VRGATHER_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16608 , RISCV::VRGATHEREI16_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16624 , RISCV::VROL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16632 , RISCV::VROL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16640 , RISCV::VROR_VI, Convert__Reg1_0__Reg1_1__UImm61_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VM, MCK_VM, MCK_UImm6, MCK_RVVMaskRegOpOperand }, },
{ 16648 , RISCV::VROR_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16656 , RISCV::VROR_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvkb, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16664 , RISCV::VRSUB_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
{ 16673 , RISCV::VRSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16682 , RISCV::VS1R_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand }, },
{ 16689 , RISCV::VS2R_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM2, MCK_ZeroOffsetMemOpOperand }, },
{ 16696 , RISCV::VS4R_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM4, MCK_ZeroOffsetMemOpOperand }, },
{ 16703 , RISCV::VS8R_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VRM8, MCK_ZeroOffsetMemOpOperand }, },
{ 16710 , RISCV::VSADD_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
{ 16719 , RISCV::VSADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16728 , RISCV::VSADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16737 , RISCV::VSADDU_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
{ 16747 , RISCV::VSADDU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16757 , RISCV::VSADDU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16767 , RISCV::VSBC_VVM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_VMV0 }, },
{ 16776 , RISCV::VSBC_VXM, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_VMV0 }, },
{ 16785 , RISCV::VSM_V, Convert__Reg1_0__Reg1_2, AMFBS_HasVInstructions, { MCK_VM, MCK__40_, MCK_GPR, MCK__41_ }, },
{ 16792 , RISCV::VSE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 16800 , RISCV::VSE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 16808 , RISCV::VSE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 16816 , RISCV::VSE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 16823 , RISCV::VSETIVLI, Convert__Reg1_0__UImm51_1__VTypeI101_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_UImm5, MCK_VTypeI10 }, },
{ 16832 , RISCV::VSETVL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 16839 , RISCV::VSETVLI, Convert__Reg1_0__Reg1_1__VTypeI111_2, AMFBS_HasVInstructions, { MCK_GPR, MCK_GPR, MCK_VTypeI11 }, },
{ 16847 , RISCV::VSEXT_VF2, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16857 , RISCV::VSEXT_VF4, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16867 , RISCV::VSEXT_VF8, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 16877 , RISCV::VSHA2CH_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvknhaOrZvknhb, { MCK_VM, MCK_VM, MCK_VM }, },
{ 16888 , RISCV::VSHA2CL_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvknhaOrZvknhb, { MCK_VM, MCK_VM, MCK_VM }, },
{ 16899 , RISCV::VSHA2MS_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_HasStdExtZvknhaOrZvknhb, { MCK_VM, MCK_VM, MCK_VM }, },
{ 16910 , RISCV::VSLIDE1DOWN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16925 , RISCV::VSLIDE1UP_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16938 , RISCV::VSLIDEDOWN_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
{ 16952 , RISCV::VSLIDEDOWN_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16966 , RISCV::VSLIDEUP_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
{ 16978 , RISCV::VSLIDEUP_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 16990 , RISCV::VSLL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
{ 16998 , RISCV::VSLL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17006 , RISCV::VSLL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 17014 , RISCV::VSM_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand }, },
{ 17020 , RISCV::VSM3C_VI, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2, AMFBS_HasStdExtZvksh, { MCK_VM, MCK_VM, MCK_UImm5 }, },
{ 17029 , RISCV::VSM3ME_VV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZvksh, { MCK_VM, MCK_VM, MCK_VM }, },
{ 17039 , RISCV::VSM4K_VI, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_HasStdExtZvksed, { MCK_VM, MCK_VM, MCK_UImm5 }, },
{ 17048 , RISCV::VSM4R_VS, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvksed, { MCK_VM, MCK_VM }, },
{ 17057 , RISCV::VSM4R_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtZvksed, { MCK_VM, MCK_VM }, },
{ 17066 , RISCV::VSMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17075 , RISCV::VSMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 17084 , RISCV::VSOXEI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17095 , RISCV::VSOXEI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17106 , RISCV::VSOXEI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17117 , RISCV::VSOXEI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17127 , RISCV::VSOXSEG2EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17142 , RISCV::VSOXSEG2EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17157 , RISCV::VSOXSEG2EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17172 , RISCV::VSOXSEG2EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17186 , RISCV::VSOXSEG3EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17201 , RISCV::VSOXSEG3EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17216 , RISCV::VSOXSEG3EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17231 , RISCV::VSOXSEG3EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17245 , RISCV::VSOXSEG4EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17260 , RISCV::VSOXSEG4EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17275 , RISCV::VSOXSEG4EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17290 , RISCV::VSOXSEG4EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17304 , RISCV::VSOXSEG5EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17319 , RISCV::VSOXSEG5EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17334 , RISCV::VSOXSEG5EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17349 , RISCV::VSOXSEG5EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17363 , RISCV::VSOXSEG6EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17378 , RISCV::VSOXSEG6EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17393 , RISCV::VSOXSEG6EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17408 , RISCV::VSOXSEG6EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17422 , RISCV::VSOXSEG7EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17437 , RISCV::VSOXSEG7EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17452 , RISCV::VSOXSEG7EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17467 , RISCV::VSOXSEG7EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17481 , RISCV::VSOXSEG8EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17496 , RISCV::VSOXSEG8EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17511 , RISCV::VSOXSEG8EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17526 , RISCV::VSOXSEG8EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17540 , RISCV::VSRA_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
{ 17548 , RISCV::VSRA_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17556 , RISCV::VSRA_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 17564 , RISCV::VSRL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
{ 17572 , RISCV::VSRL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17580 , RISCV::VSRL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 17588 , RISCV::VSSE16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 17597 , RISCV::VSSE32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 17606 , RISCV::VSSE64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 17615 , RISCV::VSSE8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 17623 , RISCV::VSSEG2E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17635 , RISCV::VSSEG2E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17647 , RISCV::VSSEG2E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17659 , RISCV::VSSEG2E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17670 , RISCV::VSSEG3E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17682 , RISCV::VSSEG3E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17694 , RISCV::VSSEG3E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17706 , RISCV::VSSEG3E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17717 , RISCV::VSSEG4E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17729 , RISCV::VSSEG4E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17741 , RISCV::VSSEG4E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17753 , RISCV::VSSEG4E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17764 , RISCV::VSSEG5E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17776 , RISCV::VSSEG5E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17788 , RISCV::VSSEG5E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17800 , RISCV::VSSEG5E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17811 , RISCV::VSSEG6E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17823 , RISCV::VSSEG6E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17835 , RISCV::VSSEG6E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17847 , RISCV::VSSEG6E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17858 , RISCV::VSSEG7E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17870 , RISCV::VSSEG7E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17882 , RISCV::VSSEG7E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17894 , RISCV::VSSEG7E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17905 , RISCV::VSSEG8E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17917 , RISCV::VSSEG8E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17929 , RISCV::VSSEG8E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17941 , RISCV::VSSEG8E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_RVVMaskRegOpOperand }, },
{ 17952 , RISCV::VSSRA_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
{ 17961 , RISCV::VSSRA_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17970 , RISCV::VSSRA_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 17979 , RISCV::VSSRL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
{ 17988 , RISCV::VSSRL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 17997 , RISCV::VSSRL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18006 , RISCV::VSSSEG2E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18019 , RISCV::VSSSEG2E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18032 , RISCV::VSSSEG2E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18045 , RISCV::VSSSEG2E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18057 , RISCV::VSSSEG3E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18070 , RISCV::VSSSEG3E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18083 , RISCV::VSSSEG3E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18096 , RISCV::VSSSEG3E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18108 , RISCV::VSSSEG4E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18121 , RISCV::VSSSEG4E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18134 , RISCV::VSSSEG4E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18147 , RISCV::VSSSEG4E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18159 , RISCV::VSSSEG5E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18172 , RISCV::VSSSEG5E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18185 , RISCV::VSSSEG5E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18198 , RISCV::VSSSEG5E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18210 , RISCV::VSSSEG6E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18223 , RISCV::VSSSEG6E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18236 , RISCV::VSSSEG6E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18249 , RISCV::VSSSEG6E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18261 , RISCV::VSSSEG7E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18274 , RISCV::VSSSEG7E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18287 , RISCV::VSSSEG7E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18300 , RISCV::VSSSEG7E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18312 , RISCV::VSSSEG8E16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18325 , RISCV::VSSSEG8E32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18338 , RISCV::VSSSEG8E64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18351 , RISCV::VSSSEG8E8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18363 , RISCV::VSSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18372 , RISCV::VSSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18381 , RISCV::VSSUBU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18391 , RISCV::VSSUBU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18401 , RISCV::VSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18409 , RISCV::VSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18417 , RISCV::VSUXEI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18428 , RISCV::VSUXEI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18439 , RISCV::VSUXEI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_IsRV64_HasVInstructionsI64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18450 , RISCV::VSUXEI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18460 , RISCV::VSUXSEG2EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18475 , RISCV::VSUXSEG2EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18490 , RISCV::VSUXSEG2EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18505 , RISCV::VSUXSEG2EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18519 , RISCV::VSUXSEG3EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18534 , RISCV::VSUXSEG3EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18549 , RISCV::VSUXSEG3EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18564 , RISCV::VSUXSEG3EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18578 , RISCV::VSUXSEG4EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18593 , RISCV::VSUXSEG4EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18608 , RISCV::VSUXSEG4EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18623 , RISCV::VSUXSEG4EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18637 , RISCV::VSUXSEG5EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18652 , RISCV::VSUXSEG5EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18667 , RISCV::VSUXSEG5EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18682 , RISCV::VSUXSEG5EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18696 , RISCV::VSUXSEG6EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18711 , RISCV::VSUXSEG6EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18726 , RISCV::VSUXSEG6EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18741 , RISCV::VSUXSEG6EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18755 , RISCV::VSUXSEG7EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18770 , RISCV::VSUXSEG7EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18785 , RISCV::VSUXSEG7EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18800 , RISCV::VSUXSEG7EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18814 , RISCV::VSUXSEG8EI16_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18829 , RISCV::VSUXSEG8EI32_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18844 , RISCV::VSUXSEG8EI64_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructionsI64_IsRV64, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18859 , RISCV::VSUXSEG8EI8_V, Convert__Reg1_0__ZeroOffsetMemOpOperand1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_ZeroOffsetMemOpOperand, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18873 , RISCV::VT_MASKC, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXVentanaCondOps, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 18882 , RISCV::VT_MASKCN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVendorXVentanaCondOps, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 18892 , RISCV::VWADD_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18901 , RISCV::VWADD_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18910 , RISCV::VWADD_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18919 , RISCV::VWADD_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18928 , RISCV::VWADDU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18938 , RISCV::VWADDU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18948 , RISCV::VWADDU_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18958 , RISCV::VWADDU_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 18968 , RISCV::VWADD_VX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM }, },
{ 18968 , RISCV::VWADD_VX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18980 , RISCV::VWADDU_VX, Convert__Reg1_0__Reg1_1__regX0__reg0, AMFBS_HasVInstructions, { MCK_VM, MCK_VM }, },
{ 18980 , RISCV::VWADDU_VX, Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 18993 , RISCV::VWMACC_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 19003 , RISCV::VWMACC_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 19013 , RISCV::VWMACCSU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 19025 , RISCV::VWMACCSU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 19037 , RISCV::VWMACCU_VV, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 19048 , RISCV::VWMACCU_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 19059 , RISCV::VWMACCUS_VX, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_GPR, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 19071 , RISCV::VWMUL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 19080 , RISCV::VWMUL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 19089 , RISCV::VWMULSU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 19100 , RISCV::VWMULSU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 19111 , RISCV::VWMULU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 19121 , RISCV::VWMULU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 19131 , RISCV::VWREDSUM_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 19143 , RISCV::VWREDSUMU_VS, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 19156 , RISCV::VWSLL_VI, Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbb, { MCK_VM, MCK_VM, MCK_UImm5, MCK_RVVMaskRegOpOperand }, },
{ 19165 , RISCV::VWSLL_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbb, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 19174 , RISCV::VWSLL_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasStdExtZvbb, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 19183 , RISCV::VWSUB_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 19192 , RISCV::VWSUB_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 19201 , RISCV::VWSUB_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 19210 , RISCV::VWSUB_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 19219 , RISCV::VWSUBU_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 19229 , RISCV::VWSUBU_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 19239 , RISCV::VWSUBU_WV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 19249 , RISCV::VWSUBU_WX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 19259 , RISCV::VXOR_VI, Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_SImm5, MCK_RVVMaskRegOpOperand }, },
{ 19267 , RISCV::VXOR_VV, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 19275 , RISCV::VXOR_VX, Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_GPR, MCK_RVVMaskRegOpOperand }, },
{ 19283 , RISCV::VZEXT_VF2, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 19293 , RISCV::VZEXT_VF4, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 19303 , RISCV::VZEXT_VF8, Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2, AMFBS_HasVInstructions, { MCK_VM, MCK_VM, MCK_RVVMaskRegOpOperand }, },
{ 19313 , RISCV::WFI, Convert_NoOperands, AMFBS_None, { }, },
{ 19317 , RISCV::WRS_NTO, Convert_NoOperands, AMFBS_HasStdExtZawrs, { }, },
{ 19325 , RISCV::WRS_STO, Convert_NoOperands, AMFBS_HasStdExtZawrs, { }, },
{ 19333 , RISCV::XNOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbbOrZbkb, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 19338 , RISCV::XOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 19338 , RISCV::XORI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
{ 19342 , RISCV::XORI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
{ 19347 , RISCV::XPERM4, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkx, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 19354 , RISCV::XPERM8, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtZbkx, { MCK_GPR, MCK_GPR, MCK_GPR }, },
{ 19361 , RISCV::ANDI, Convert__Reg1_0__Reg1_1__imm_95_255, AMFBS_None, { MCK_GPR, MCK_GPR }, },
{ 19368 , RISCV::PACK, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtZbkb_NoStdExtZbb_IsRV32, { MCK_GPR, MCK_GPR }, },
{ 19368 , RISCV::PACKW, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtZbkb_NoStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, },
{ 19368 , RISCV::ZEXT_H_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV32, { MCK_GPR, MCK_GPR }, },
{ 19368 , RISCV::ZEXT_H_RV64, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbb_IsRV64, { MCK_GPR, MCK_GPR }, },
{ 19368 , RISCV::PseudoZEXT_H, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
{ 19375 , RISCV::ADD_UW, Convert__Reg1_0__Reg1_1__regX0, AMFBS_HasStdExtZba_IsRV64, { MCK_GPR, MCK_GPR }, },
{ 19375 , RISCV::PseudoZEXT_W, Convert__Reg1_0__Reg1_1, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, },
{ 19382 , RISCV::ZIP_RV32, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtZbkb_IsRV32, { MCK_GPR, MCK_GPR }, },
};
#include "llvm/Support/Debug.h"
#include "llvm/Support/Format.h"
unsigned RISCVAsmParser::
MatchInstructionImpl(const OperandVector &Operands,
MCInst &Inst,
uint64_t &ErrorInfo,
FeatureBitset &MissingFeatures,
bool matchingInlineAsm, unsigned VariantID) {
if (Operands.size() > 8) {
ErrorInfo = 8;
return Match_InvalidOperand;
}
const FeatureBitset &AvailableFeatures = getAvailableFeatures();
StringRef Mnemonic = ((RISCVOperand &)*Operands[0]).getToken();
applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
bool HadMatchOtherThanFeatures = false;
bool HadMatchOtherThanPredicate = false;
unsigned RetCode = Match_InvalidOperand;
MissingFeatures.set();
ErrorInfo = ~0ULL;
SmallBitVector OptionalOperandsMask(7);
const MatchEntry *Start, *End;
switch (VariantID) {
default: llvm_unreachable("invalid variant!");
case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
}
auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
std::distance(MnemonicRange.first, MnemonicRange.second) <<
" encodings with mnemonic '" << Mnemonic << "'\n");
if (MnemonicRange.first == MnemonicRange.second)
return Match_MnemonicFail;
for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
it != ie; ++it) {
const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
bool HasRequiredFeatures =
(AvailableFeatures & RequiredFeatures) == RequiredFeatures;
DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
<< MII.getName(it->Opcode) << "\n");
assert(Mnemonic == it->getMnemonic());
bool OperandsValid = true;
OptionalOperandsMask.reset(0, 7);
for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 7; ++FormalIdx) {
auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
DEBUG_WITH_TYPE("asm-matcher",
dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
<< " against actual operand at index " << ActualIdx);
if (ActualIdx < Operands.size())
DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
Operands[ActualIdx]->print(dbgs()); dbgs() << "): ");
else
DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
if (ActualIdx >= Operands.size()) {
DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n");
if (Formal == InvalidMatchClass) {
OptionalOperandsMask.set(FormalIdx, 7);
break;
}
if (isSubclass(Formal, OptionalMatchClass)) {
OptionalOperandsMask.set(FormalIdx);
continue;
}
OperandsValid = false;
ErrorInfo = ActualIdx;
break;
}
MCParsedAsmOperand &Actual = *Operands[ActualIdx];
unsigned Diag = validateOperandClass(Actual, Formal);
if (Diag == Match_Success) {
DEBUG_WITH_TYPE("asm-matcher",
dbgs() << "match success using generic matcher\n");
++ActualIdx;
continue;
}
if (Diag != Match_Success) {
unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
if (TargetDiag == Match_Success) {
DEBUG_WITH_TYPE("asm-matcher",
dbgs() << "match success using target matcher\n");
++ActualIdx;
continue;
}
if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
Diag = TargetDiag;
}
if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
OptionalOperandsMask.set(FormalIdx);
DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
continue;
}
if (!HadMatchOtherThanPredicate &&
(it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand))
RetCode = Diag;
ErrorInfo = ActualIdx;
}
OperandsValid = false;
break;
}
if (!OperandsValid) {
DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
"operand mismatches, ignoring "
"this opcode\n");
continue;
}
if (!HasRequiredFeatures) {
HadMatchOtherThanFeatures = true;
FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures;
DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:";
for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)
if (NewMissingFeatures[I])
dbgs() << ' ' << I;
dbgs() << "\n");
if (NewMissingFeatures.count() <=
MissingFeatures.count())
MissingFeatures = NewMissingFeatures;
continue;
}
Inst.clear();
Inst.setOpcode(it->Opcode);
unsigned MatchResult;
if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
Inst.clear();
DEBUG_WITH_TYPE(
"asm-matcher",
dbgs() << "Early target match predicate failed with diag code "
<< MatchResult << "\n");
RetCode = MatchResult;
HadMatchOtherThanPredicate = true;
continue;
}
unsigned DefaultsOffset[8] = { 0 };
assert(OptionalOperandsMask.size() == 7);
for (unsigned i = 0, NumDefaults = 0; i < 7; ++i) {
DefaultsOffset[i + 1] = NumDefaults;
NumDefaults += (OptionalOperandsMask[i] ? 1 : 0);
}
if (matchingInlineAsm) {
convertToMapAndConstraints(it->ConvertFn, Operands);
if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
DefaultsOffset, ErrorInfo))
return Match_InvalidTiedOperand;
return Match_Success;
}
convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands,
OptionalOperandsMask, DefaultsOffset);
if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
DEBUG_WITH_TYPE("asm-matcher",
dbgs() << "Target match predicate failed with diag code "
<< MatchResult << "\n");
Inst.clear();
RetCode = MatchResult;
HadMatchOtherThanPredicate = true;
continue;
}
if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
DefaultsOffset, ErrorInfo))
return Match_InvalidTiedOperand;
DEBUG_WITH_TYPE(
"asm-matcher",
dbgs() << "Opcode result: complete match, selecting this opcode\n");
return Match_Success;
}
if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
return RetCode;
ErrorInfo = 0;
return Match_MissingFeature;
}
namespace {
struct OperandMatchEntry {
uint16_t Mnemonic;
uint8_t OperandMask;
uint8_t Class;
uint8_t RequiredFeaturesIdx;
StringRef getMnemonic() const {
return StringRef(MnemonicTable + Mnemonic + 1,
MnemonicTable[Mnemonic]);
}
};
struct LessOpcodeOperand {
bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
return LHS.getMnemonic() < RHS;
}
bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
return LHS < RHS.getMnemonic();
}
bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
return LHS.getMnemonic() < RHS.getMnemonic();
}
};
}
static const OperandMatchEntry OperandMatchTable[1541] = {
{ 0 , 1 , MCK_InsnDirectiveOpcode, AMFBS_None },
{ 8 , 1 , MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtCOrZca },
{ 17 , 1 , MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtCOrZca },
{ 26 , 1 , MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtCOrZca },
{ 35 , 1 , MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtCOrZca },
{ 45 , 1 , MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtCOrZca },
{ 54 , 1 , MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtCOrZca },
{ 54 , 1 , MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtCOrZca },
{ 63 , 1 , MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtCOrZca },
{ 72 , 1 , MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtCOrZca },
{ 72 , 1 , MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtCOrZca },
{ 81 , 1 , MCK_InsnCDirectiveOpcode, AMFBS_HasStdExtCOrZca },
{ 91 , 1 , MCK_InsnDirectiveOpcode, AMFBS_None },
{ 91 , 1 , MCK_InsnDirectiveOpcode, AMFBS_None },
{ 91 , 1 , MCK_InsnDirectiveOpcode, AMFBS_None },
{ 99 , 1 , MCK_InsnDirectiveOpcode, AMFBS_None },
{ 99 , 4 , MCK_SImm21Lsb0JAL, AMFBS_None },
{ 107 , 1 , MCK_InsnDirectiveOpcode, AMFBS_None },
{ 107 , 1 , MCK_InsnDirectiveOpcode, AMFBS_None },
{ 115 , 1 , MCK_InsnDirectiveOpcode, AMFBS_None },
{ 124 , 1 , MCK_InsnDirectiveOpcode, AMFBS_None },
{ 124 , 1 , MCK_InsnDirectiveOpcode, AMFBS_None },
{ 132 , 1 , MCK_InsnDirectiveOpcode, AMFBS_None },
{ 141 , 1 , MCK_InsnDirectiveOpcode, AMFBS_None },
{ 149 , 1 , MCK_InsnDirectiveOpcode, AMFBS_None },
{ 149 , 4 , MCK_SImm21Lsb0JAL, AMFBS_None },
{ 158 , 8 , MCK_TPRelAddSymbol, AMFBS_None },
{ 284 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 293 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 305 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 319 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 331 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 340 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 352 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 366 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 378 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 387 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 399 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 413 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 425 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 434 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 446 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 460 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 472 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 481 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 493 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 507 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 519 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 528 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 540 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 554 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 566 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 575 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 587 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 601 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 613 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 622 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 634 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 648 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 660 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
{ 669 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
{ 681 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
{ 695 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
{ 707 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
{ 707 , 3 , MCK_GPRPairRV32, AMFBS_HasStdExtZacas_IsRV32 },
{ 707 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV32 },
{ 716 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
{ 716 , 3 , MCK_GPRPairRV32, AMFBS_HasStdExtZacas_IsRV32 },
{ 716 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV32 },
{ 728 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
{ 728 , 3 , MCK_GPRPairRV32, AMFBS_HasStdExtZacas_IsRV32 },
{ 728 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV32 },
{ 742 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
{ 742 , 3 , MCK_GPRPairRV32, AMFBS_HasStdExtZacas_IsRV32 },
{ 742 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV32 },
{ 754 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
{ 763 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
{ 775 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
{ 789 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha_HasStdExtZacas },
{ 801 , 3 , MCK_GPRPairRV64, AMFBS_HasStdExtZacas_IsRV64 },
{ 801 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
{ 810 , 3 , MCK_GPRPairRV64, AMFBS_HasStdExtZacas_IsRV64 },
{ 810 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
{ 822 , 3 , MCK_GPRPairRV64, AMFBS_HasStdExtZacas_IsRV64 },
{ 822 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
{ 836 , 3 , MCK_GPRPairRV64, AMFBS_HasStdExtZacas_IsRV64 },
{ 836 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas_IsRV64 },
{ 848 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas },
{ 857 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas },
{ 869 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas },
{ 883 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZacas },
{ 895 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 904 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 916 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 930 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 942 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 951 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 963 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 977 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 989 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 998 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1010 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1024 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1036 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 1045 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 1057 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 1071 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 1083 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1093 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1106 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1121 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1134 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 1144 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 1157 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 1172 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 1185 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1195 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1208 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1223 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1236 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 1246 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 1259 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 1274 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 1287 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1296 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1308 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1322 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1334 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 1343 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 1355 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 1369 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 1381 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1390 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1402 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1416 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1428 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 1437 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 1449 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 1463 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 1475 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1485 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1498 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1513 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1526 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 1536 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 1549 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 1564 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 1577 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1587 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1600 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1615 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1628 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 1638 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 1651 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 1666 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 1679 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1687 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1698 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1711 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1722 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 1730 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 1741 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 1754 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 1765 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1773 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1784 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1797 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1808 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 1816 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 1827 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 1840 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 1851 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1861 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1874 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1889 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1902 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 1912 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 1925 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 1940 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 1953 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1963 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1976 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 1991 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 2004 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 2014 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 2027 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 2042 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 2055 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 2064 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 2076 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 2090 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 2102 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 2111 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 2123 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 2137 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo_IsRV64 },
{ 2149 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 2158 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 2170 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 2184 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZabha },
{ 2196 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 2205 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 2217 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 2231 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZaamo },
{ 2911 , 1 , MCK_CallSymbol, AMFBS_None },
{ 2911 , 2 , MCK_CallSymbol, AMFBS_None },
{ 2916 , 1 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicbom },
{ 2926 , 1 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicbom },
{ 2936 , 1 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicbom },
{ 2946 , 1 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicboz },
{ 3018 , 1 , MCK_Rlist, AMFBS_HasStdExtZcmp },
{ 3018 , 2 , MCK_StackAdj, AMFBS_HasStdExtZcmp },
{ 3025 , 1 , MCK_Rlist, AMFBS_HasStdExtZcmp },
{ 3025 , 2 , MCK_StackAdj, AMFBS_HasStdExtZcmp },
{ 3035 , 1 , MCK_Rlist, AMFBS_HasStdExtZcmp },
{ 3035 , 2 , MCK_StackAdj, AMFBS_HasStdExtZcmp },
{ 3046 , 2 , MCK_NegStackAdj, AMFBS_HasStdExtZcmp },
{ 3046 , 1 , MCK_Rlist, AMFBS_HasStdExtZcmp },
{ 3065 , 1 , MCK_CSRSystemRegister, AMFBS_None },
{ 3065 , 1 , MCK_CSRSystemRegister, AMFBS_None },
{ 3070 , 1 , MCK_CSRSystemRegister, AMFBS_None },
{ 3076 , 2 , MCK_CSRSystemRegister, AMFBS_None },
{ 3081 , 2 , MCK_CSRSystemRegister, AMFBS_None },
{ 3081 , 2 , MCK_CSRSystemRegister, AMFBS_None },
{ 3087 , 2 , MCK_CSRSystemRegister, AMFBS_None },
{ 3094 , 2 , MCK_CSRSystemRegister, AMFBS_None },
{ 3094 , 2 , MCK_CSRSystemRegister, AMFBS_None },
{ 3100 , 2 , MCK_CSRSystemRegister, AMFBS_None },
{ 3107 , 2 , MCK_CSRSystemRegister, AMFBS_None },
{ 3107 , 2 , MCK_CSRSystemRegister, AMFBS_None },
{ 3113 , 2 , MCK_CSRSystemRegister, AMFBS_None },
{ 3120 , 1 , MCK_CSRSystemRegister, AMFBS_None },
{ 3120 , 1 , MCK_CSRSystemRegister, AMFBS_None },
{ 3125 , 1 , MCK_CSRSystemRegister, AMFBS_None },
{ 3131 , 1 , MCK_CSRSystemRegister, AMFBS_None },
{ 3131 , 1 , MCK_CSRSystemRegister, AMFBS_None },
{ 3136 , 1 , MCK_CSRSystemRegister, AMFBS_None },
{ 5100 , 2 , MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
{ 5106 , 2 , MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
{ 5113 , 2 , MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
{ 5119 , 2 , MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
{ 5126 , 2 , MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
{ 5775 , 2 , MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
{ 6045 , 2 , MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
{ 6660 , 2 , MCK_RegReg, AMFBS_HasVendorXCVmem_IsRV32 },
{ 6792 , 3 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 6792 , 3 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 6799 , 3 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 6806 , 3 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 6813 , 8 , MCK_FRMArg, AMFBS_HasStdExtD },
{ 6813 , 8 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
{ 6813 , 7 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 6813 , 8 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
{ 6813 , 7 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 6820 , 8 , MCK_FRMArg, AMFBS_HasStdExtZfh },
{ 6820 , 8 , MCK_FRMArg, AMFBS_HasStdExtZhinx },
{ 6820 , 7 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 6827 , 8 , MCK_FRMArg, AMFBS_HasStdExtF },
{ 6827 , 8 , MCK_FRMArg, AMFBS_HasStdExtZfinx },
{ 6827 , 7 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 6834 , 2 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 6834 , 2 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 6843 , 2 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 6852 , 2 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 6861 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfbfmin },
{ 6873 , 4 , MCK_FRMArgLegacy, AMFBS_HasStdExtZfhmin_HasStdExtD },
{ 6873 , 4 , MCK_FRMArgLegacy, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
{ 6873 , 2 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
{ 6873 , 1 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
{ 6873 , 4 , MCK_FRMArgLegacy, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
{ 6873 , 2 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
{ 6873 , 1 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
{ 6882 , 4 , MCK_FRMArg, AMFBS_HasStdExtD_IsRV64 },
{ 6882 , 4 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
{ 6882 , 1 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
{ 6891 , 4 , MCK_FRMArg, AMFBS_HasStdExtD_IsRV64 },
{ 6891 , 4 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
{ 6891 , 1 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
{ 6901 , 4 , MCK_FRMArgLegacy, AMFBS_HasStdExtD },
{ 6901 , 4 , MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV64 },
{ 6901 , 2 , MCK_GPRAsFPR32, AMFBS_HasStdExtZdinx_IsRV64 },
{ 6901 , 1 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 6901 , 4 , MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV32 },
{ 6901 , 2 , MCK_GPRAsFPR32, AMFBS_HasStdExtZdinx_IsRV32 },
{ 6901 , 1 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 6910 , 4 , MCK_FRMArgLegacy, AMFBS_HasStdExtD },
{ 6910 , 4 , MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV64 },
{ 6910 , 1 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 6910 , 4 , MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV32 },
{ 6910 , 1 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 6919 , 4 , MCK_FRMArgLegacy, AMFBS_HasStdExtD },
{ 6919 , 4 , MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV64 },
{ 6919 , 1 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 6919 , 4 , MCK_FRMArgLegacy, AMFBS_HasStdExtZdinx_IsRV32 },
{ 6919 , 1 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 6929 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfhmin_HasStdExtD },
{ 6929 , 4 , MCK_FRMArg, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
{ 6929 , 1 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
{ 6929 , 2 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV64 },
{ 6929 , 4 , MCK_FRMArg, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
{ 6929 , 1 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
{ 6929 , 2 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZhinxmin_HasStdExtZdinx_IsRV32 },
{ 6938 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfh_IsRV64 },
{ 6938 , 4 , MCK_FRMArg, AMFBS_HasStdExtZhinx_IsRV64 },
{ 6938 , 1 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx_IsRV64 },
{ 6947 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfh_IsRV64 },
{ 6947 , 4 , MCK_FRMArg, AMFBS_HasStdExtZhinx_IsRV64 },
{ 6947 , 1 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx_IsRV64 },
{ 6957 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfhmin },
{ 6957 , 4 , MCK_FRMArg, AMFBS_HasStdExtZhinxmin },
{ 6957 , 1 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin },
{ 6957 , 2 , MCK_GPRAsFPR32, AMFBS_HasStdExtZhinxmin },
{ 6966 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfh },
{ 6966 , 4 , MCK_FRMArg, AMFBS_HasStdExtZhinx },
{ 6966 , 1 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 6975 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfh },
{ 6975 , 4 , MCK_FRMArg, AMFBS_HasStdExtZhinx },
{ 6975 , 1 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 6985 , 4 , MCK_FRMArg, AMFBS_HasStdExtD_IsRV64 },
{ 6985 , 4 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
{ 6985 , 2 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
{ 6994 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfh_IsRV64 },
{ 6994 , 4 , MCK_FRMArg, AMFBS_HasStdExtZhinx_IsRV64 },
{ 6994 , 2 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx_IsRV64 },
{ 7003 , 4 , MCK_FRMArg, AMFBS_HasStdExtF_IsRV64 },
{ 7003 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfinx_IsRV64 },
{ 7003 , 2 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx_IsRV64 },
{ 7012 , 4 , MCK_FRMArg, AMFBS_HasStdExtD_IsRV64 },
{ 7012 , 4 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
{ 7012 , 2 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64_IsRV64 },
{ 7022 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfh_IsRV64 },
{ 7022 , 4 , MCK_FRMArg, AMFBS_HasStdExtZhinx_IsRV64 },
{ 7022 , 2 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx_IsRV64 },
{ 7032 , 4 , MCK_FRMArg, AMFBS_HasStdExtF_IsRV64 },
{ 7032 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfinx_IsRV64 },
{ 7032 , 2 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx_IsRV64 },
{ 7042 , 4 , MCK_FRMArgLegacy, AMFBS_HasStdExtZfbfmin },
{ 7054 , 4 , MCK_FRMArg, AMFBS_HasStdExtD },
{ 7054 , 4 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7054 , 1 , MCK_GPRAsFPR32, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7054 , 2 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7054 , 4 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7054 , 1 , MCK_GPRAsFPR32, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7054 , 2 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7063 , 4 , MCK_FRMArgLegacy, AMFBS_HasStdExtZfhmin },
{ 7063 , 4 , MCK_FRMArgLegacy, AMFBS_HasStdExtZhinxmin },
{ 7063 , 2 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinxmin },
{ 7063 , 1 , MCK_GPRAsFPR32, AMFBS_HasStdExtZhinxmin },
{ 7072 , 4 , MCK_FRMArg, AMFBS_HasStdExtF_IsRV64 },
{ 7072 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfinx_IsRV64 },
{ 7072 , 1 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx_IsRV64 },
{ 7081 , 4 , MCK_FRMArg, AMFBS_HasStdExtF_IsRV64 },
{ 7081 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfinx_IsRV64 },
{ 7081 , 1 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx_IsRV64 },
{ 7091 , 4 , MCK_FRMArg, AMFBS_HasStdExtF },
{ 7091 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfinx },
{ 7091 , 1 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7100 , 4 , MCK_FRMArg, AMFBS_HasStdExtF },
{ 7100 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfinx },
{ 7100 , 1 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7110 , 4 , MCK_FRMArg, AMFBS_HasStdExtD },
{ 7110 , 4 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7110 , 2 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7110 , 4 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7110 , 2 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7119 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfh },
{ 7119 , 4 , MCK_FRMArg, AMFBS_HasStdExtZhinx },
{ 7119 , 2 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7128 , 4 , MCK_FRMArg, AMFBS_HasStdExtF },
{ 7128 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfinx },
{ 7128 , 2 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7137 , 4 , MCK_FRMArg, AMFBS_HasStdExtD },
{ 7137 , 4 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7137 , 2 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7137 , 4 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7137 , 2 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7147 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfh },
{ 7147 , 4 , MCK_FRMArg, AMFBS_HasStdExtZhinx },
{ 7147 , 2 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7157 , 4 , MCK_FRMArg, AMFBS_HasStdExtF },
{ 7157 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfinx },
{ 7157 , 2 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7167 , 4 , MCK_RTZArg, AMFBS_HasStdExtZfa_HasStdExtD },
{ 7179 , 8 , MCK_FRMArg, AMFBS_HasStdExtD },
{ 7179 , 8 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7179 , 7 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7179 , 8 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7179 , 7 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7186 , 8 , MCK_FRMArg, AMFBS_HasStdExtZfh },
{ 7186 , 8 , MCK_FRMArg, AMFBS_HasStdExtZhinx },
{ 7186 , 7 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7193 , 8 , MCK_FRMArg, AMFBS_HasStdExtF },
{ 7193 , 8 , MCK_FRMArg, AMFBS_HasStdExtZfinx },
{ 7193 , 7 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7200 , 3 , MCK_FenceArg, AMFBS_None },
{ 7224 , 6 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7224 , 6 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7230 , 6 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7236 , 6 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7242 , 6 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7242 , 6 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7248 , 6 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7254 , 6 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7281 , 6 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7281 , 6 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7287 , 6 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7293 , 6 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7320 , 2 , MCK_BareSymbol, AMFBS_HasStdExtD },
{ 7324 , 6 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7324 , 6 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7330 , 6 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7336 , 6 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7363 , 2 , MCK_BareSymbol, AMFBS_HasStdExtZfhmin },
{ 7367 , 2 , MCK_LoadFPImm, AMFBS_HasStdExtZfa_HasStdExtD },
{ 7373 , 2 , MCK_LoadFPImm, AMFBS_HasStdExtZfa_HasStdExtZfhOrZvfh },
{ 7379 , 2 , MCK_LoadFPImm, AMFBS_HasStdExtZfa },
{ 7385 , 6 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7385 , 6 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7391 , 6 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7397 , 6 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7424 , 2 , MCK_BareSymbol, AMFBS_HasStdExtF },
{ 7428 , 16 , MCK_FRMArg, AMFBS_HasStdExtD },
{ 7428 , 16 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7428 , 15 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7428 , 16 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7428 , 15 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7436 , 16 , MCK_FRMArg, AMFBS_HasStdExtZfh },
{ 7436 , 16 , MCK_FRMArg, AMFBS_HasStdExtZhinx },
{ 7436 , 15 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7444 , 16 , MCK_FRMArg, AMFBS_HasStdExtF },
{ 7444 , 16 , MCK_FRMArg, AMFBS_HasStdExtZfinx },
{ 7444 , 15 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7452 , 7 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7452 , 7 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7459 , 7 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7466 , 7 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7497 , 7 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7497 , 7 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7504 , 7 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7511 , 7 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7542 , 16 , MCK_FRMArg, AMFBS_HasStdExtD },
{ 7542 , 16 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7542 , 15 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7542 , 16 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7542 , 15 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7550 , 16 , MCK_FRMArg, AMFBS_HasStdExtZfh },
{ 7550 , 16 , MCK_FRMArg, AMFBS_HasStdExtZhinx },
{ 7550 , 15 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7558 , 16 , MCK_FRMArg, AMFBS_HasStdExtF },
{ 7558 , 16 , MCK_FRMArg, AMFBS_HasStdExtZfinx },
{ 7558 , 15 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7566 , 8 , MCK_FRMArg, AMFBS_HasStdExtD },
{ 7566 , 8 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7566 , 7 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7566 , 8 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7566 , 7 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7573 , 8 , MCK_FRMArg, AMFBS_HasStdExtZfh },
{ 7573 , 8 , MCK_FRMArg, AMFBS_HasStdExtZhinx },
{ 7573 , 7 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7580 , 8 , MCK_FRMArg, AMFBS_HasStdExtF },
{ 7580 , 8 , MCK_FRMArg, AMFBS_HasStdExtZfinx },
{ 7580 , 7 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7587 , 3 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7587 , 3 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7601 , 3 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7615 , 3 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7671 , 3 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7671 , 3 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7678 , 3 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7685 , 3 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7692 , 16 , MCK_FRMArg, AMFBS_HasStdExtD },
{ 7692 , 16 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7692 , 15 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7692 , 16 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7692 , 15 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7701 , 16 , MCK_FRMArg, AMFBS_HasStdExtZfh },
{ 7701 , 16 , MCK_FRMArg, AMFBS_HasStdExtZhinx },
{ 7701 , 15 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7710 , 16 , MCK_FRMArg, AMFBS_HasStdExtF },
{ 7710 , 16 , MCK_FRMArg, AMFBS_HasStdExtZfinx },
{ 7710 , 15 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7719 , 16 , MCK_FRMArg, AMFBS_HasStdExtD },
{ 7719 , 16 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7719 , 15 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7719 , 16 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7719 , 15 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7728 , 16 , MCK_FRMArg, AMFBS_HasStdExtZfh },
{ 7728 , 16 , MCK_FRMArg, AMFBS_HasStdExtZhinx },
{ 7728 , 15 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7737 , 16 , MCK_FRMArg, AMFBS_HasStdExtF },
{ 7737 , 16 , MCK_FRMArg, AMFBS_HasStdExtZfinx },
{ 7737 , 15 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7760 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtD },
{ 7769 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtZfh },
{ 7778 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfa },
{ 7787 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtD },
{ 7798 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfa_HasStdExtZfh },
{ 7809 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfa },
{ 7836 , 2 , MCK_BareSymbol, AMFBS_HasStdExtD },
{ 7857 , 7 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7857 , 7 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7865 , 7 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7873 , 7 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7881 , 7 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7881 , 7 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7890 , 7 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7899 , 7 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7908 , 7 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7908 , 7 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7917 , 7 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7926 , 7 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7935 , 2 , MCK_BareSymbol, AMFBS_HasStdExtZfhmin },
{ 7939 , 4 , MCK_FRMArg, AMFBS_HasStdExtD },
{ 7939 , 4 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7939 , 3 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7939 , 4 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7939 , 3 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7947 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfh },
{ 7947 , 4 , MCK_FRMArg, AMFBS_HasStdExtZhinx },
{ 7947 , 3 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7955 , 4 , MCK_FRMArg, AMFBS_HasStdExtF },
{ 7955 , 4 , MCK_FRMArg, AMFBS_HasStdExtZfinx },
{ 7955 , 3 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 7979 , 8 , MCK_FRMArg, AMFBS_HasStdExtD },
{ 7979 , 8 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7979 , 7 , MCK_GPRF64AsFPR, AMFBS_HasStdExtZdinx_IsRV64 },
{ 7979 , 8 , MCK_FRMArg, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7979 , 7 , MCK_GPRPairAsFPR, AMFBS_HasStdExtZdinx_IsRV32 },
{ 7986 , 8 , MCK_FRMArg, AMFBS_HasStdExtZfh },
{ 7986 , 8 , MCK_FRMArg, AMFBS_HasStdExtZhinx },
{ 7986 , 7 , MCK_GPRAsFPR16, AMFBS_HasStdExtZhinx },
{ 7993 , 8 , MCK_FRMArg, AMFBS_HasStdExtF },
{ 7993 , 8 , MCK_FRMArg, AMFBS_HasStdExtZfinx },
{ 7993 , 7 , MCK_GPRAsFPR32, AMFBS_HasStdExtZfinx },
{ 8000 , 2 , MCK_BareSymbol, AMFBS_HasStdExtF },
{ 8052 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
{ 8058 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
{ 8065 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasStdExtH },
{ 8071 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
{ 8077 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
{ 8084 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
{ 8090 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasStdExtH },
{ 8097 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
{ 8105 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
{ 8113 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
{ 8119 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasStdExtH },
{ 8125 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
{ 8131 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtH },
{ 8137 , 1 , MCK_SImm21Lsb0JAL, AMFBS_None },
{ 8139 , 1 , MCK_SImm21Lsb0JAL, AMFBS_None },
{ 8139 , 2 , MCK_SImm21Lsb0JAL, AMFBS_None },
{ 8143 , 32 , MCK_TLSDESCCallSymbol, AMFBS_None },
{ 8151 , 1 , MCK_PseudoJumpSymbol, AMFBS_None },
{ 8156 , 2 , MCK_BareSymbol, AMFBS_None },
{ 8159 , 2 , MCK_BareSymbol, AMFBS_None },
{ 8169 , 2 , MCK_BareSymbol, AMFBS_None },
{ 8179 , 2 , MCK_BareSymbol, AMFBS_None },
{ 8190 , 2 , MCK_BareSymbol, AMFBS_None },
{ 8193 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
{ 8199 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
{ 8207 , 2 , MCK_BareSymbol, AMFBS_None },
{ 8211 , 2 , MCK_BareSymbol, AMFBS_IsRV64 },
{ 8214 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr_IsRV64 },
{ 8220 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr_IsRV64 },
{ 8228 , 2 , MCK_BareSymbol, AMFBS_None },
{ 8232 , 2 , MCK_BareSymbol, AMFBS_None },
{ 8235 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
{ 8241 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
{ 8249 , 2 , MCK_BareSymbol, AMFBS_None },
{ 8256 , 2 , MCK_BareSymbol, AMFBS_None },
{ 8265 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZalrsc_IsRV64 },
{ 8270 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZalrsc_IsRV64 },
{ 8278 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZalrsc_IsRV64 },
{ 8288 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZalrsc_IsRV64 },
{ 8296 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZalrsc },
{ 8301 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZalrsc },
{ 8309 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZalrsc },
{ 8319 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZalrsc },
{ 8331 , 2 , MCK_BareSymbol, AMFBS_None },
{ 8334 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
{ 8340 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
{ 8348 , 2 , MCK_BareSymbol, AMFBS_IsRV64 },
{ 9063 , 2 , MCK_BareSymbol, AMFBS_None },
{ 9066 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
{ 9074 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
{ 9080 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZalrsc_IsRV64 },
{ 9085 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZalrsc_IsRV64 },
{ 9093 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZalrsc_IsRV64 },
{ 9103 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZalrsc_IsRV64 },
{ 9111 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZalrsc },
{ 9116 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZalrsc },
{ 9124 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZalrsc },
{ 9134 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtAOrZalrsc },
{ 9150 , 2 , MCK_BareSymbol, AMFBS_IsRV64 },
{ 9153 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr_IsRV64 },
{ 9161 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr_IsRV64 },
{ 9526 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXSfvfnrclipxfqf },
{ 9545 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXSfvfnrclipxfqf },
{ 9776 , 2 , MCK_BareSymbol, AMFBS_None },
{ 9779 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
{ 9787 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
{ 10142 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss_IsRV64 },
{ 10154 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss_IsRV64 },
{ 10169 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss_IsRV64 },
{ 10186 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss_IsRV64 },
{ 10201 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss },
{ 10213 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss },
{ 10228 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss },
{ 10245 , 4 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZicfiss },
{ 10291 , 2 , MCK_BareSymbol, AMFBS_None },
{ 10294 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
{ 10302 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasStdExtZalasr },
{ 10308 , 1 , MCK_CallSymbol, AMFBS_None },
{ 11296 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
{ 11308 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
{ 11320 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
{ 11334 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
{ 11348 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
{ 11361 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
{ 11374 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVendorXTHeadVdot },
{ 11400 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 11409 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 11418 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 11428 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 11465 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 11473 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 11481 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 11600 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 11608 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 11616 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 11624 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
{ 11633 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
{ 11642 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 11651 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 11660 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 11670 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 11680 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
{ 11688 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvkb },
{ 11697 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbcOrZvbc32e },
{ 11707 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbcOrZvbc32e },
{ 11717 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbcOrZvbc32e },
{ 11728 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbcOrZvbc32e },
{ 11739 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
{ 11759 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 11767 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
{ 11775 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
{ 11782 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 11790 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 11798 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 11807 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 11816 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 11824 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 11833 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 11842 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 11852 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 11864 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 11877 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 11893 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 11910 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 11922 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 11935 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 11944 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 11953 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 11962 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 11972 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 11982 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 11992 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12002 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12011 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12032 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12041 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12050 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12060 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12070 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12080 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12090 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12099 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12135 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12148 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12161 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12175 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12192 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12209 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12227 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12240 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12254 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbfmin },
{ 12271 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12279 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12290 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12301 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12312 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12323 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12334 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12345 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12356 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12367 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12377 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12386 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12398 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12410 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12423 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12435 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12448 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12459 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12469 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12479 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12489 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12500 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12511 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12522 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12533 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12549 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12563 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12572 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12581 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12590 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12600 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12610 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12620 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12630 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12643 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12656 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12670 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12687 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12705 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12718 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12732 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbfmin },
{ 12749 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12760 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12771 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbfwma },
{ 12786 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvfbfwma },
{ 12801 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12812 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12823 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12833 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12843 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12855 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12867 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12879 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12891 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12905 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12918 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12932 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12942 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12952 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 12962 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsAnyF },
{ 13008 , 2 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13014 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13029 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13039 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13049 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
{ 13059 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13075 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13085 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13095 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
{ 13105 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13121 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13131 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13141 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
{ 13151 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13167 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13177 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13187 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
{ 13197 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13213 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13213 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13221 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13221 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13231 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13231 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13239 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13239 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13249 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
{ 13249 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
{ 13257 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
{ 13257 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
{ 13267 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13267 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13274 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13274 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13283 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13289 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13289 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13300 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13300 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13311 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
{ 13311 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
{ 13322 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13322 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13332 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13332 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13347 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13347 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13362 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 13362 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 13377 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13377 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13391 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13391 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13406 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13406 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13421 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 13421 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 13436 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13436 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13450 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13450 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13465 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13465 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13480 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 13480 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 13495 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13495 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13509 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13509 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13524 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13524 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13539 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 13539 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 13554 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13554 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13568 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13568 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13583 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13583 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13598 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 13598 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 13613 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13613 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13627 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13627 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13642 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13642 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13657 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 13657 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 13672 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13672 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13686 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13686 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13701 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13701 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13716 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 13716 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 13731 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13731 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13745 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13745 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13754 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13754 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13763 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64 },
{ 13763 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64 },
{ 13772 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13772 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13780 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13780 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13792 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13792 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13806 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 13806 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 13818 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
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{ 18391 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18401 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18409 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18417 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18417 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18428 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18428 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18439 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
{ 18439 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_IsRV64_HasVInstructionsI64 },
{ 18450 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18450 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18460 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18460 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18475 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18475 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18490 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 18490 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 18505 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18505 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18519 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18519 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18534 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18534 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18549 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 18549 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 18564 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18564 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18578 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18578 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18593 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18593 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18608 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 18608 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 18623 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18623 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18637 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18637 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18652 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18652 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18667 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 18667 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 18682 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18682 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18696 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18696 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18711 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18711 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18726 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 18726 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 18741 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18741 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18755 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18755 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18770 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18770 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18785 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 18785 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 18800 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18800 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18814 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18814 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18829 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18829 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18844 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 18844 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructionsI64_IsRV64 },
{ 18859 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18859 , 2 , MCK_ZeroOffsetMemOpOperand, AMFBS_HasVInstructions },
{ 18892 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18901 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18910 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18919 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18928 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18938 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18948 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18958 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18968 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18980 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 18993 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19003 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19013 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19025 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19037 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19048 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19059 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19071 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19080 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19089 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19100 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19111 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19121 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19131 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19143 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19156 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
{ 19165 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
{ 19174 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasStdExtZvbb },
{ 19183 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19192 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19201 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19210 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19219 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19229 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19239 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19249 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19259 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19267 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19275 , 8 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19283 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19293 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
{ 19303 , 4 , MCK_RVVMaskRegOpOperand, AMFBS_HasVInstructions },
};
ParseStatus RISCVAsmParser::
tryCustomParseOperand(OperandVector &Operands,
unsigned MCK) {
switch(MCK) {
case MCK_BareSymbol:
return parseBareSymbol(Operands);
case MCK_CSRSystemRegister:
return parseCSRSystemRegister(Operands);
case MCK_RegReg:
return parseRegReg(Operands);
case MCK_CallSymbol:
return parseCallSymbol(Operands);
case MCK_FRMArg:
return parseFRMArg(Operands);
case MCK_FRMArgLegacy:
return parseFRMArg(Operands);
case MCK_FenceArg:
return parseFenceArg(Operands);
case MCK_GPRAsFPR16:
return parseGPRAsFPR(Operands);
case MCK_GPRAsFPR32:
return parseGPRAsFPR(Operands);
case MCK_GPRF64AsFPR:
return parseGPRAsFPR64(Operands);
case MCK_GPRPairAsFPR:
return parseGPRPairAsFPR64(Operands);
case MCK_GPRPairRV32:
return parseGPRPair<false>(Operands);
case MCK_GPRPairRV64:
return parseGPRPair<true>(Operands);
case MCK_InsnCDirectiveOpcode:
return parseInsnCDirectiveOpcode(Operands);
case MCK_InsnDirectiveOpcode:
return parseInsnDirectiveOpcode(Operands);
case MCK_LoadFPImm:
return parseFPImm(Operands);
case MCK_NegStackAdj:
return parseZcmpNegStackAdj(Operands);
case MCK_PseudoJumpSymbol:
return parsePseudoJumpSymbol(Operands);
case MCK_RTZArg:
return parseFRMArg(Operands);
case MCK_Rlist:
return parseReglist(Operands);
case MCK_SImm21Lsb0JAL:
return parseJALOffset(Operands);
case MCK_StackAdj:
return parseZcmpStackAdj(Operands);
case MCK_TLSDESCCallSymbol:
return parseOperandWithModifier(Operands);
case MCK_TPRelAddSymbol:
return parseOperandWithModifier(Operands);
case MCK_RVVMaskRegOpOperand:
return parseMaskReg(Operands);
case MCK_ZeroOffsetMemOpOperand:
return parseZeroOffsetMemOp(Operands);
case MCK_VTypeI10:
return parseVTypeI(Operands);
case MCK_VTypeI11:
return parseVTypeI(Operands);
default:
return ParseStatus::NoMatch;
}
return ParseStatus::NoMatch;
}
ParseStatus RISCVAsmParser::
MatchOperandParserImpl(OperandVector &Operands,
StringRef Mnemonic,
bool ParseForAllFeatures) {
const FeatureBitset &AvailableFeatures = getAvailableFeatures();
unsigned NextOpNum = Operands.size() - 1;
auto MnemonicRange =
std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
Mnemonic, LessOpcodeOperand());
if (MnemonicRange.first == MnemonicRange.second)
return ParseStatus::NoMatch;
for (const OperandMatchEntry *it = MnemonicRange.first,
*ie = MnemonicRange.second; it != ie; ++it) {
assert(Mnemonic == it->getMnemonic());
const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures)
continue;
if (!(it->OperandMask & (1 << NextOpNum)))
continue;
ParseStatus Result = tryCustomParseOperand(Operands, it->Class);
if (!Result.isNoMatch())
return Result;
}
return ParseStatus::NoMatch;
}
#endif
#ifdef GET_MNEMONIC_SPELL_CHECKER
#undef GET_MNEMONIC_SPELL_CHECKER
static std::string RISCVMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) {
const unsigned MaxEditDist = 2;
std::vector<StringRef> Candidates;
StringRef Prev = "";
const MatchEntry *Start, *End;
switch (VariantID) {
default: llvm_unreachable("invalid variant!");
case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
}
for (auto I = Start; I < End; I++) {
const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx];
if ((FBS & RequiredFeatures) != RequiredFeatures)
continue;
StringRef T = I->getMnemonic();
if (T == Prev)
continue;
Prev = T;
unsigned Dist = S.edit_distance(T, false, MaxEditDist);
if (Dist <= MaxEditDist)
Candidates.push_back(T);
}
if (Candidates.empty())
return "";
std::string Res = ", did you mean: ";
unsigned i = 0;
for (; i < Candidates.size() - 1; i++)
Res += Candidates[i].str() + ", ";
return Res + Candidates[i].str() + "?";
}
#endif
#ifdef GET_MNEMONIC_CHECKER
#undef GET_MNEMONIC_CHECKER
static bool RISCVCheckMnemonic(StringRef Mnemonic,
const FeatureBitset &AvailableFeatures,
unsigned VariantID) {
applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
const MatchEntry *Start, *End;
switch (VariantID) {
default: llvm_unreachable("invalid variant!");
case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
}
auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
if (MnemonicRange.first == MnemonicRange.second)
return false;
for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
it != ie; ++it) {
const FeatureBitset &RequiredFeatures =
FeatureBitsets[it->RequiredFeaturesIdx];
if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures)
return true;
}
return false;
}
#endif