/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM namespace llvm { namespace WebAssembly { enum { … }; } // end namespace WebAssembly } // end namespace llvm #endif // GET_INSTRINFO_ENUM #ifdef GET_INSTRINFO_SCHED_ENUM #undef GET_INSTRINFO_SCHED_ENUM namespace llvm { namespace WebAssembly { namespace Sched { enum { NoInstrModel = 0, SCHED_LIST_END = 1 }; } // end namespace Sched } // end namespace WebAssembly } // end namespace llvm #endif // GET_INSTRINFO_SCHED_ENUM #if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) namespace llvm { struct WebAssemblyInstrTable { MCInstrDesc Insts[1918]; static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo"); MCOperandInfo OperandInfo[810]; static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps"); MCPhysReg ImplicitOps[10]; }; } // end namespace llvm #endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) #ifdef GET_INSTRINFO_MC_DESC #undef GET_INSTRINFO_MC_DESC namespace llvm { static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0); static constexpr unsigned WebAssemblyImpOpBase = sizeof WebAssemblyInstrTable::OperandInfo / (sizeof(MCPhysReg)); extern const WebAssemblyInstrTable WebAssemblyDescs = { { { 1917, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1917 = uint_to_fp_F32x4_S { 1916, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1916 = uint_to_fp_F32x4 { 1915, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1915 = uint_to_fp_F16x8_S { 1914, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1914 = uint_to_fp_F16x8 { 1913, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1913 = trunc_sat_zero_u_I32x4_S { 1912, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1912 = trunc_sat_zero_u_I32x4 { 1911, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1911 = trunc_sat_zero_s_I32x4_S { 1910, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1910 = trunc_sat_zero_s_I32x4 { 1909, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1909 = sint_to_fp_F32x4_S { 1908, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1908 = sint_to_fp_F32x4 { 1907, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1907 = sint_to_fp_F16x8_S { 1906, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1906 = sint_to_fp_F16x8 { 1905, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1905 = promote_low_F64x2_S { 1904, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1904 = promote_low_F64x2 { 1903, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1903 = int_wasm_relaxed_trunc_unsigned_zero_I32x4_S { 1902, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1902 = int_wasm_relaxed_trunc_unsigned_zero_I32x4 { 1901, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1901 = int_wasm_relaxed_trunc_unsigned_I32x4_S { 1900, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1900 = int_wasm_relaxed_trunc_unsigned_I32x4 { 1899, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1899 = int_wasm_relaxed_trunc_signed_zero_I32x4_S { 1898, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1898 = int_wasm_relaxed_trunc_signed_zero_I32x4 { 1897, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1897 = int_wasm_relaxed_trunc_signed_I32x4_S { 1896, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1896 = int_wasm_relaxed_trunc_signed_I32x4 { 1895, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1895 = int_wasm_extadd_pairwise_unsigned_I32x4_S { 1894, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1894 = int_wasm_extadd_pairwise_unsigned_I32x4 { 1893, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1893 = int_wasm_extadd_pairwise_unsigned_I16x8_S { 1892, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1892 = int_wasm_extadd_pairwise_unsigned_I16x8 { 1891, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1891 = int_wasm_extadd_pairwise_signed_I32x4_S { 1890, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1890 = int_wasm_extadd_pairwise_signed_I32x4 { 1889, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1889 = int_wasm_extadd_pairwise_signed_I16x8_S { 1888, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1888 = int_wasm_extadd_pairwise_signed_I16x8 { 1887, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1887 = fp_to_uint_I32x4_S { 1886, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1886 = fp_to_uint_I32x4 { 1885, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1885 = fp_to_uint_I16x8_S { 1884, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1884 = fp_to_uint_I16x8 { 1883, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1883 = fp_to_sint_I32x4_S { 1882, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1882 = fp_to_sint_I32x4 { 1881, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1881 = fp_to_sint_I16x8_S { 1880, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1880 = fp_to_sint_I16x8 { 1879, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1879 = extend_low_u_I64x2_S { 1878, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1878 = extend_low_u_I64x2 { 1877, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1877 = extend_low_u_I32x4_S { 1876, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1876 = extend_low_u_I32x4 { 1875, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1875 = extend_low_u_I16x8_S { 1874, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1874 = extend_low_u_I16x8 { 1873, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1873 = extend_low_s_I64x2_S { 1872, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1872 = extend_low_s_I64x2 { 1871, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1871 = extend_low_s_I32x4_S { 1870, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1870 = extend_low_s_I32x4 { 1869, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1869 = extend_low_s_I16x8_S { 1868, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1868 = extend_low_s_I16x8 { 1867, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1867 = extend_high_u_I64x2_S { 1866, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1866 = extend_high_u_I64x2 { 1865, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1865 = extend_high_u_I32x4_S { 1864, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1864 = extend_high_u_I32x4 { 1863, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1863 = extend_high_u_I16x8_S { 1862, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1862 = extend_high_u_I16x8 { 1861, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1861 = extend_high_s_I64x2_S { 1860, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1860 = extend_high_s_I64x2 { 1859, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1859 = extend_high_s_I32x4_S { 1858, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1858 = extend_high_s_I32x4 { 1857, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1857 = extend_high_s_I16x8_S { 1856, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1856 = extend_high_s_I16x8 { 1855, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1855 = demote_zero_F32x4_S { 1854, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1854 = demote_zero_F32x4 { 1853, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1853 = convert_low_u_F64x2_S { 1852, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1852 = convert_low_u_F64x2 { 1851, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1851 = convert_low_s_F64x2_S { 1850, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1850 = convert_low_s_F64x2 { 1849, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 790, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1849 = anonymous_8999MEMORY_INIT_A64_S { 1848, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 805, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1848 = anonymous_8999MEMORY_INIT_A64 { 1847, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 301, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1847 = anonymous_8999MEMORY_FILL_A64_S { 1846, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 801, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1846 = anonymous_8999MEMORY_FILL_A64 { 1845, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 790, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1845 = anonymous_8999MEMORY_COPY_A64_S { 1844, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 796, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1844 = anonymous_8999MEMORY_COPY_A64 { 1843, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 301, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1843 = anonymous_8999DATA_DROP_S { 1842, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 301, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1842 = anonymous_8999DATA_DROP { 1841, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 790, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1841 = anonymous_8998MEMORY_INIT_A32_S { 1840, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 785, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1840 = anonymous_8998MEMORY_INIT_A32 { 1839, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 301, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1839 = anonymous_8998MEMORY_FILL_A32_S { 1838, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 792, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1838 = anonymous_8998MEMORY_FILL_A32 { 1837, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 790, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1837 = anonymous_8998MEMORY_COPY_A32_S { 1836, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 785, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1836 = anonymous_8998MEMORY_COPY_A32 { 1835, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 301, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1835 = anonymous_8998DATA_DROP_S { 1834, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 301, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1834 = anonymous_8998DATA_DROP { 1833, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1833 = anonymous_8278MEMORY_SIZE_A64_S { 1832, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 190, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1832 = anonymous_8278MEMORY_SIZE_A64 { 1831, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1831 = anonymous_8278MEMORY_GROW_A64_S { 1830, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 782, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1830 = anonymous_8278MEMORY_GROW_A64 { 1829, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1829 = anonymous_8277MEMORY_SIZE_A32_S { 1828, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1828 = anonymous_8277MEMORY_SIZE_A32 { 1827, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1827 = anonymous_8277MEMORY_GROW_A32_S { 1826, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 779, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1826 = anonymous_8277MEMORY_GROW_A32 { 1825, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1825 = XOR_S { 1824, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1824 = XOR_I64_S { 1823, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1823 = XOR_I64 { 1822, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1822 = XOR_I32_S { 1821, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1821 = XOR_I32 { 1820, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1820 = XOR { 1819, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1819 = UNREACHABLE_S { 1818, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1818 = UNREACHABLE { 1817, 2, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 777, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1817 = TRY_TABLE_S { 1816, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1816 = TRY_TABLE { 1815, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1815 = TRY_S { 1814, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1814 = TRY { 1813, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1813 = TRUNC_F64x2_S { 1812, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1812 = TRUNC_F64x2 { 1811, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1811 = TRUNC_F64_S { 1810, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1810 = TRUNC_F64 { 1809, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1809 = TRUNC_F32x4_S { 1808, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1808 = TRUNC_F32x4 { 1807, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1807 = TRUNC_F32_S { 1806, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1806 = TRUNC_F32 { 1805, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1805 = TRUNC_F16x8_S { 1804, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1804 = TRUNC_F16x8 { 1803, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1803 = THROW_S { 1802, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1802 = THROW_REF_S { 1801, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1801 = THROW_REF { 1800, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1800 = THROW { 1799, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1799 = TEE_V128_S { 1798, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1798 = TEE_V128 { 1797, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1797 = TEE_I64_S { 1796, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1796 = TEE_I64 { 1795, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1795 = TEE_I32_S { 1794, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1794 = TEE_I32 { 1793, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1793 = TEE_FUNCREF_S { 1792, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 774, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1792 = TEE_FUNCREF { 1791, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1791 = TEE_F64_S { 1790, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1790 = TEE_F64 { 1789, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1789 = TEE_F32_S { 1788, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1788 = TEE_F32 { 1787, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1787 = TEE_EXTERNREF_S { 1786, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 771, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1786 = TEE_EXTERNREF { 1785, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1785 = TEE_EXNREF_S { 1784, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 768, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1784 = TEE_EXNREF { 1783, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1783 = TABLE_SIZE_S { 1782, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 766, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1782 = TABLE_SIZE { 1781, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1781 = TABLE_SET_FUNCREF_S { 1780, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 763, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1780 = TABLE_SET_FUNCREF { 1779, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1779 = TABLE_SET_EXTERNREF_S { 1778, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 760, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1778 = TABLE_SET_EXTERNREF { 1777, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1777 = TABLE_SET_EXNREF_S { 1776, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 757, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1776 = TABLE_SET_EXNREF { 1775, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1775 = TABLE_GROW_FUNCREF_S { 1774, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 753, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1774 = TABLE_GROW_FUNCREF { 1773, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1773 = TABLE_GROW_EXTERNREF_S { 1772, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 749, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1772 = TABLE_GROW_EXTERNREF { 1771, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1771 = TABLE_GROW_EXNREF_S { 1770, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 745, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1770 = TABLE_GROW_EXNREF { 1769, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1769 = TABLE_GET_FUNCREF_S { 1768, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 742, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1768 = TABLE_GET_FUNCREF { 1767, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1767 = TABLE_GET_EXTERNREF_S { 1766, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 739, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1766 = TABLE_GET_EXTERNREF { 1765, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1765 = TABLE_GET_EXNREF_S { 1764, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 736, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1764 = TABLE_GET_EXNREF { 1763, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1763 = TABLE_FILL_FUNCREF_S { 1762, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 732, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1762 = TABLE_FILL_FUNCREF { 1761, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1761 = TABLE_FILL_EXTERNREF_S { 1760, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 728, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1760 = TABLE_FILL_EXTERNREF { 1759, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1759 = TABLE_FILL_EXNREF_S { 1758, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 723, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1758 = TABLE_FILL_EXNREF { 1757, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 721, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1757 = TABLE_COPY_S { 1756, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 716, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1756 = TABLE_COPY { 1755, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1755 = SWIZZLE_S { 1754, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1754 = SWIZZLE { 1753, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1753 = SUB_SAT_U_I8x16_S { 1752, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1752 = SUB_SAT_U_I8x16 { 1751, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1751 = SUB_SAT_U_I16x8_S { 1750, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1750 = SUB_SAT_U_I16x8 { 1749, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1749 = SUB_SAT_S_I8x16_S { 1748, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1748 = SUB_SAT_S_I8x16 { 1747, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1747 = SUB_SAT_S_I16x8_S { 1746, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1746 = SUB_SAT_S_I16x8 { 1745, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1745 = SUB_I8x16_S { 1744, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1744 = SUB_I8x16 { 1743, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1743 = SUB_I64x2_S { 1742, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1742 = SUB_I64x2 { 1741, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1741 = SUB_I64_S { 1740, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1740 = SUB_I64 { 1739, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1739 = SUB_I32x4_S { 1738, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1738 = SUB_I32x4 { 1737, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1737 = SUB_I32_S { 1736, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1736 = SUB_I32 { 1735, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1735 = SUB_I16x8_S { 1734, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1734 = SUB_I16x8 { 1733, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1733 = SUB_F64x2_S { 1732, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1732 = SUB_F64x2 { 1731, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1731 = SUB_F64_S { 1730, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1730 = SUB_F64 { 1729, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1729 = SUB_F32x4_S { 1728, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1728 = SUB_F32x4 { 1727, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1727 = SUB_F32_S { 1726, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1726 = SUB_F32 { 1725, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1725 = SUB_F16x8_S { 1724, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1724 = SUB_F16x8 { 1723, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1723 = STORE_V128_A64_S { 1722, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 712, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1722 = STORE_V128_A64 { 1721, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1721 = STORE_V128_A32_S { 1720, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 708, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1720 = STORE_V128_A32 { 1719, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1719 = STORE_LANE_I8x16_A64_S { 1718, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 703, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1718 = STORE_LANE_I8x16_A64 { 1717, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1717 = STORE_LANE_I8x16_A32_S { 1716, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 698, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1716 = STORE_LANE_I8x16_A32 { 1715, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1715 = STORE_LANE_I64x2_A64_S { 1714, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 703, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1714 = STORE_LANE_I64x2_A64 { 1713, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1713 = STORE_LANE_I64x2_A32_S { 1712, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 698, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1712 = STORE_LANE_I64x2_A32 { 1711, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1711 = STORE_LANE_I32x4_A64_S { 1710, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 703, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1710 = STORE_LANE_I32x4_A64 { 1709, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1709 = STORE_LANE_I32x4_A32_S { 1708, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 698, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1708 = STORE_LANE_I32x4_A32 { 1707, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1707 = STORE_LANE_I16x8_A64_S { 1706, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 703, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1706 = STORE_LANE_I16x8_A64 { 1705, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1705 = STORE_LANE_I16x8_A32_S { 1704, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 698, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1704 = STORE_LANE_I16x8_A32 { 1703, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1703 = STORE_I64_A64_S { 1702, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1702 = STORE_I64_A64 { 1701, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1701 = STORE_I64_A32_S { 1700, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1700 = STORE_I64_A32 { 1699, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1699 = STORE_I32_A64_S { 1698, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1698 = STORE_I32_A64 { 1697, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1697 = STORE_I32_A32_S { 1696, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1696 = STORE_I32_A32 { 1695, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1695 = STORE_F64_A64_S { 1694, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 694, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1694 = STORE_F64_A64 { 1693, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1693 = STORE_F64_A32_S { 1692, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 690, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1692 = STORE_F64_A32 { 1691, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1691 = STORE_F32_A64_S { 1690, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 686, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1690 = STORE_F32_A64 { 1689, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1689 = STORE_F32_A32_S { 1688, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 682, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1688 = STORE_F32_A32 { 1687, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1687 = STORE_F16_F32_A64_S { 1686, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 686, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1686 = STORE_F16_F32_A64 { 1685, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1685 = STORE_F16_F32_A32_S { 1684, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 682, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1684 = STORE_F16_F32_A32 { 1683, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1683 = STORE8_I64_A64_S { 1682, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1682 = STORE8_I64_A64 { 1681, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1681 = STORE8_I64_A32_S { 1680, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1680 = STORE8_I64_A32 { 1679, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1679 = STORE8_I32_A64_S { 1678, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1678 = STORE8_I32_A64 { 1677, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1677 = STORE8_I32_A32_S { 1676, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1676 = STORE8_I32_A32 { 1675, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1675 = STORE32_I64_A64_S { 1674, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1674 = STORE32_I64_A64 { 1673, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1673 = STORE32_I64_A32_S { 1672, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1672 = STORE32_I64_A32 { 1671, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1671 = STORE16_I64_A64_S { 1670, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1670 = STORE16_I64_A64 { 1669, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1669 = STORE16_I64_A32_S { 1668, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1668 = STORE16_I64_A32 { 1667, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1667 = STORE16_I32_A64_S { 1666, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1666 = STORE16_I32_A64 { 1665, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1665 = STORE16_I32_A32_S { 1664, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1664 = STORE16_I32_A32 { 1663, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1663 = SQRT_F64x2_S { 1662, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1662 = SQRT_F64x2 { 1661, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1661 = SQRT_F64_S { 1660, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1660 = SQRT_F64 { 1659, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1659 = SQRT_F32x4_S { 1658, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1658 = SQRT_F32x4 { 1657, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1657 = SQRT_F32_S { 1656, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1656 = SQRT_F32 { 1655, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1655 = SQRT_F16x8_S { 1654, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1654 = SQRT_F16x8 { 1653, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1653 = SPLAT_I8x16_S { 1652, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 678, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1652 = SPLAT_I8x16 { 1651, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1651 = SPLAT_I64x2_S { 1650, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 680, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1650 = SPLAT_I64x2 { 1649, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1649 = SPLAT_I32x4_S { 1648, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 678, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1648 = SPLAT_I32x4 { 1647, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1647 = SPLAT_I16x8_S { 1646, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 678, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1646 = SPLAT_I16x8 { 1645, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1645 = SPLAT_F64x2_S { 1644, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 676, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1644 = SPLAT_F64x2 { 1643, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1643 = SPLAT_F32x4_S { 1642, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 674, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1642 = SPLAT_F32x4 { 1641, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1641 = SPLAT_F16x8_S { 1640, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 674, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1640 = SPLAT_F16x8 { 1639, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1639 = SIMD_RELAXED_FMIN_F64x2_S { 1638, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1638 = SIMD_RELAXED_FMIN_F64x2 { 1637, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1637 = SIMD_RELAXED_FMIN_F32x4_S { 1636, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1636 = SIMD_RELAXED_FMIN_F32x4 { 1635, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1635 = SIMD_RELAXED_FMAX_F64x2_S { 1634, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1634 = SIMD_RELAXED_FMAX_F64x2 { 1633, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1633 = SIMD_RELAXED_FMAX_F32x4_S { 1632, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1632 = SIMD_RELAXED_FMAX_F32x4 { 1631, 16, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 367, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1631 = SHUFFLE_S { 1630, 19, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 655, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1630 = SHUFFLE { 1629, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1629 = SHR_U_I8x16_S { 1628, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1628 = SHR_U_I8x16 { 1627, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1627 = SHR_U_I64x2_S { 1626, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1626 = SHR_U_I64x2 { 1625, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1625 = SHR_U_I64_S { 1624, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1624 = SHR_U_I64 { 1623, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1623 = SHR_U_I32x4_S { 1622, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1622 = SHR_U_I32x4 { 1621, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1621 = SHR_U_I32_S { 1620, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1620 = SHR_U_I32 { 1619, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1619 = SHR_U_I16x8_S { 1618, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1618 = SHR_U_I16x8 { 1617, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1617 = SHR_S_I8x16_S { 1616, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1616 = SHR_S_I8x16 { 1615, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1615 = SHR_S_I64x2_S { 1614, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1614 = SHR_S_I64x2 { 1613, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1613 = SHR_S_I64_S { 1612, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1612 = SHR_S_I64 { 1611, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1611 = SHR_S_I32x4_S { 1610, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1610 = SHR_S_I32x4 { 1609, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1609 = SHR_S_I32_S { 1608, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1608 = SHR_S_I32 { 1607, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1607 = SHR_S_I16x8_S { 1606, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1606 = SHR_S_I16x8 { 1605, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1605 = SHL_I8x16_S { 1604, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1604 = SHL_I8x16 { 1603, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1603 = SHL_I64x2_S { 1602, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1602 = SHL_I64x2 { 1601, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1601 = SHL_I64_S { 1600, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1600 = SHL_I64 { 1599, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1599 = SHL_I32x4_S { 1598, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1598 = SHL_I32x4 { 1597, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1597 = SHL_I32_S { 1596, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1596 = SHL_I32 { 1595, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1595 = SHL_I16x8_S { 1594, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1594 = SHL_I16x8 { 1593, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1593 = SELECT_V128_S { 1592, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 648, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1592 = SELECT_V128 { 1591, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1591 = SELECT_I64_S { 1590, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 644, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1590 = SELECT_I64 { 1589, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1589 = SELECT_I32_S { 1588, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 640, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1588 = SELECT_I32 { 1587, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1587 = SELECT_FUNCREF_S { 1586, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 636, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1586 = SELECT_FUNCREF { 1585, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1585 = SELECT_F64_S { 1584, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 632, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1584 = SELECT_F64 { 1583, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1583 = SELECT_F32_S { 1582, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 628, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1582 = SELECT_F32 { 1581, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1581 = SELECT_EXTERNREF_S { 1580, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 624, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1580 = SELECT_EXTERNREF { 1579, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1579 = SELECT_EXNREF_S { 1578, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 620, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1578 = SELECT_EXNREF { 1577, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1577 = ROTR_I64_S { 1576, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1576 = ROTR_I64 { 1575, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1575 = ROTR_I32_S { 1574, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1574 = ROTR_I32 { 1573, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1573 = ROTL_I64_S { 1572, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1572 = ROTL_I64 { 1571, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1571 = ROTL_I32_S { 1570, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1570 = ROTL_I32 { 1569, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1569 = RET_CALL_S { 1568, 2, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 285, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1568 = RET_CALL_INDIRECT_S { 1567, 2, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 285, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1567 = RET_CALL_INDIRECT { 1566, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1566 = RET_CALL { 1565, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1565 = RETURN_S { 1564, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1564 = RETURN { 1563, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1563 = RETHROW_S { 1562, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1562 = RETHROW { 1561, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1561 = REPLACE_LANE_I8x16_S { 1560, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 612, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1560 = REPLACE_LANE_I8x16 { 1559, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1559 = REPLACE_LANE_I64x2_S { 1558, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 616, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1558 = REPLACE_LANE_I64x2 { 1557, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1557 = REPLACE_LANE_I32x4_S { 1556, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 612, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1556 = REPLACE_LANE_I32x4 { 1555, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1555 = REPLACE_LANE_I16x8_S { 1554, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 612, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1554 = REPLACE_LANE_I16x8 { 1553, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1553 = REPLACE_LANE_F64x2_S { 1552, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 608, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1552 = REPLACE_LANE_F64x2 { 1551, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1551 = REPLACE_LANE_F32x4_S { 1550, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 604, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1550 = REPLACE_LANE_F32x4 { 1549, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1549 = REPLACE_LANE_F16x8_S { 1548, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 604, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1548 = REPLACE_LANE_F16x8 { 1547, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1547 = REM_U_I64_S { 1546, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1546 = REM_U_I64 { 1545, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1545 = REM_U_I32_S { 1544, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1544 = REM_U_I32 { 1543, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1543 = REM_S_I64_S { 1542, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1542 = REM_S_I64 { 1541, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1541 = REM_S_I32_S { 1540, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1540 = REM_S_I32 { 1539, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1539 = RELAXED_SWIZZLE_S { 1538, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1538 = RELAXED_SWIZZLE { 1537, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1537 = RELAXED_Q15MULR_S_I16x8_S { 1536, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1536 = RELAXED_Q15MULR_S_I16x8 { 1535, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1535 = RELAXED_DOT_S { 1534, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1534 = RELAXED_DOT_BFLOAT_S { 1533, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1533 = RELAXED_DOT_BFLOAT { 1532, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1532 = RELAXED_DOT_ADD_S { 1531, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1531 = RELAXED_DOT_ADD { 1530, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1530 = RELAXED_DOT { 1529, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1529 = REF_NULL_FUNCREF_S { 1528, 1, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 392, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1528 = REF_NULL_FUNCREF { 1527, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1527 = REF_NULL_EXTERNREF_S { 1526, 1, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 389, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1526 = REF_NULL_EXTERNREF { 1525, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1525 = REF_NULL_EXNREF_S { 1524, 1, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1524 = REF_NULL_EXNREF { 1523, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1523 = REF_IS_NULL_FUNCREF_S { 1522, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 602, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1522 = REF_IS_NULL_FUNCREF { 1521, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1521 = REF_IS_NULL_EXTERNREF_S { 1520, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 600, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1520 = REF_IS_NULL_EXTERNREF { 1519, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1519 = REF_IS_NULL_EXNREF_S { 1518, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 598, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1518 = REF_IS_NULL_EXNREF { 1517, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1517 = Q15MULR_SAT_S_I16x8_S { 1516, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1516 = Q15MULR_SAT_S_I16x8 { 1515, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1515 = POPCNT_I8x16_S { 1514, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1514 = POPCNT_I8x16 { 1513, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1513 = POPCNT_I64_S { 1512, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 291, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1512 = POPCNT_I64 { 1511, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1511 = POPCNT_I32_S { 1510, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 289, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1510 = POPCNT_I32 { 1509, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1509 = PMIN_F64x2_S { 1508, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1508 = PMIN_F64x2 { 1507, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1507 = PMIN_F32x4_S { 1506, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1506 = PMIN_F32x4 { 1505, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1505 = PMIN_F16x8_S { 1504, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1504 = PMIN_F16x8 { 1503, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1503 = PMAX_F64x2_S { 1502, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1502 = PMAX_F64x2 { 1501, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1501 = PMAX_F32x4_S { 1500, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1500 = PMAX_F32x4 { 1499, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1499 = PMAX_F16x8_S { 1498, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1498 = PMAX_F16x8 { 1497, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1497 = OR_S { 1496, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1496 = OR_I64_S { 1495, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1495 = OR_I64 { 1494, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1494 = OR_I32_S { 1493, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1493 = OR_I32 { 1492, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1492 = OR { 1491, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1491 = NOT_S { 1490, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1490 = NOT { 1489, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1489 = NOP_S { 1488, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1488 = NOP { 1487, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1487 = NMADD_F64x2_S { 1486, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1486 = NMADD_F64x2 { 1485, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1485 = NMADD_F32x4_S { 1484, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1484 = NMADD_F32x4 { 1483, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1483 = NMADD_F16x8_S { 1482, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1482 = NMADD_F16x8 { 1481, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1481 = NE_I8x16_S { 1480, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1480 = NE_I8x16 { 1479, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1479 = NE_I64x2_S { 1478, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1478 = NE_I64x2 { 1477, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1477 = NE_I64_S { 1476, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1476 = NE_I64 { 1475, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1475 = NE_I32x4_S { 1474, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1474 = NE_I32x4 { 1473, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1473 = NE_I32_S { 1472, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1472 = NE_I32 { 1471, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1471 = NE_I16x8_S { 1470, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1470 = NE_I16x8 { 1469, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1469 = NE_F64x2_S { 1468, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1468 = NE_F64x2 { 1467, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1467 = NE_F64_S { 1466, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1466 = NE_F64 { 1465, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1465 = NE_F32x4_S { 1464, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1464 = NE_F32x4 { 1463, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1463 = NE_F32_S { 1462, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1462 = NE_F32 { 1461, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1461 = NE_F16x8_S { 1460, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1460 = NE_F16x8 { 1459, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1459 = NEG_I8x16_S { 1458, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1458 = NEG_I8x16 { 1457, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1457 = NEG_I64x2_S { 1456, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1456 = NEG_I64x2 { 1455, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1455 = NEG_I32x4_S { 1454, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1454 = NEG_I32x4 { 1453, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1453 = NEG_I16x8_S { 1452, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1452 = NEG_I16x8 { 1451, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1451 = NEG_F64x2_S { 1450, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1450 = NEG_F64x2 { 1449, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1449 = NEG_F64_S { 1448, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1448 = NEG_F64 { 1447, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1447 = NEG_F32x4_S { 1446, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1446 = NEG_F32x4 { 1445, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1445 = NEG_F32_S { 1444, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1444 = NEG_F32 { 1443, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1443 = NEG_F16x8_S { 1442, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1442 = NEG_F16x8 { 1441, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1441 = NEAREST_F64x2_S { 1440, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1440 = NEAREST_F64x2 { 1439, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1439 = NEAREST_F64_S { 1438, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1438 = NEAREST_F64 { 1437, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1437 = NEAREST_F32x4_S { 1436, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1436 = NEAREST_F32x4 { 1435, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1435 = NEAREST_F32_S { 1434, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1434 = NEAREST_F32 { 1433, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1433 = NEAREST_F16x8_S { 1432, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1432 = NEAREST_F16x8 { 1431, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1431 = NARROW_U_I8x16_S { 1430, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1430 = NARROW_U_I8x16 { 1429, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1429 = NARROW_U_I16x8_S { 1428, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1428 = NARROW_U_I16x8 { 1427, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1427 = NARROW_S_I8x16_S { 1426, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1426 = NARROW_S_I8x16 { 1425, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1425 = NARROW_S_I16x8_S { 1424, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1424 = NARROW_S_I16x8 { 1423, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1423 = MUL_I64x2_S { 1422, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1422 = MUL_I64x2 { 1421, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1421 = MUL_I64_S { 1420, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1420 = MUL_I64 { 1419, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1419 = MUL_I32x4_S { 1418, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1418 = MUL_I32x4 { 1417, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1417 = MUL_I32_S { 1416, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1416 = MUL_I32 { 1415, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1415 = MUL_I16x8_S { 1414, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1414 = MUL_I16x8 { 1413, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1413 = MUL_F64x2_S { 1412, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1412 = MUL_F64x2 { 1411, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1411 = MUL_F64_S { 1410, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1410 = MUL_F64 { 1409, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1409 = MUL_F32x4_S { 1408, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1408 = MUL_F32x4 { 1407, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1407 = MUL_F32_S { 1406, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1406 = MUL_F32 { 1405, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1405 = MUL_F16x8_S { 1404, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1404 = MUL_F16x8 { 1403, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1403 = MIN_U_I8x16_S { 1402, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1402 = MIN_U_I8x16 { 1401, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1401 = MIN_U_I32x4_S { 1400, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1400 = MIN_U_I32x4 { 1399, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1399 = MIN_U_I16x8_S { 1398, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1398 = MIN_U_I16x8 { 1397, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1397 = MIN_S_I8x16_S { 1396, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1396 = MIN_S_I8x16 { 1395, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1395 = MIN_S_I32x4_S { 1394, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1394 = MIN_S_I32x4 { 1393, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1393 = MIN_S_I16x8_S { 1392, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1392 = MIN_S_I16x8 { 1391, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1391 = MIN_F64x2_S { 1390, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1390 = MIN_F64x2 { 1389, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1389 = MIN_F64_S { 1388, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1388 = MIN_F64 { 1387, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1387 = MIN_F32x4_S { 1386, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1386 = MIN_F32x4 { 1385, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1385 = MIN_F32_S { 1384, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1384 = MIN_F32 { 1383, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1383 = MIN_F16x8_S { 1382, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1382 = MIN_F16x8 { 1381, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1381 = MEMORY_ATOMIC_WAIT64_A64_S { 1380, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 592, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1380 = MEMORY_ATOMIC_WAIT64_A64 { 1379, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1379 = MEMORY_ATOMIC_WAIT64_A32_S { 1378, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1378 = MEMORY_ATOMIC_WAIT64_A32 { 1377, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1377 = MEMORY_ATOMIC_WAIT32_A64_S { 1376, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 580, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1376 = MEMORY_ATOMIC_WAIT32_A64 { 1375, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1375 = MEMORY_ATOMIC_WAIT32_A32_S { 1374, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 574, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1374 = MEMORY_ATOMIC_WAIT32_A32 { 1373, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1373 = MEMORY_ATOMIC_NOTIFY_A64_S { 1372, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1372 = MEMORY_ATOMIC_NOTIFY_A64 { 1371, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1371 = MEMORY_ATOMIC_NOTIFY_A32_S { 1370, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1370 = MEMORY_ATOMIC_NOTIFY_A32 { 1369, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1369 = MAX_U_I8x16_S { 1368, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1368 = MAX_U_I8x16 { 1367, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1367 = MAX_U_I32x4_S { 1366, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1366 = MAX_U_I32x4 { 1365, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1365 = MAX_U_I16x8_S { 1364, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1364 = MAX_U_I16x8 { 1363, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1363 = MAX_S_I8x16_S { 1362, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1362 = MAX_S_I8x16 { 1361, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1361 = MAX_S_I32x4_S { 1360, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1360 = MAX_S_I32x4 { 1359, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1359 = MAX_S_I16x8_S { 1358, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1358 = MAX_S_I16x8 { 1357, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1357 = MAX_F64x2_S { 1356, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1356 = MAX_F64x2 { 1355, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1355 = MAX_F64_S { 1354, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1354 = MAX_F64 { 1353, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1353 = MAX_F32x4_S { 1352, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1352 = MAX_F32x4 { 1351, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1351 = MAX_F32_S { 1350, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1350 = MAX_F32 { 1349, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1349 = MAX_F16x8_S { 1348, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1348 = MAX_F16x8 { 1347, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1347 = MADD_F64x2_S { 1346, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1346 = MADD_F64x2 { 1345, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1345 = MADD_F32x4_S { 1344, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1344 = MADD_F32x4 { 1343, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1343 = MADD_F16x8_S { 1342, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1342 = MADD_F16x8 { 1341, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1341 = LT_U_I8x16_S { 1340, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1340 = LT_U_I8x16 { 1339, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1339 = LT_U_I64_S { 1338, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1338 = LT_U_I64 { 1337, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1337 = LT_U_I32x4_S { 1336, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1336 = LT_U_I32x4 { 1335, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1335 = LT_U_I32_S { 1334, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1334 = LT_U_I32 { 1333, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1333 = LT_U_I16x8_S { 1332, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1332 = LT_U_I16x8 { 1331, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1331 = LT_S_I8x16_S { 1330, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1330 = LT_S_I8x16 { 1329, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1329 = LT_S_I64x2_S { 1328, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1328 = LT_S_I64x2 { 1327, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1327 = LT_S_I64_S { 1326, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1326 = LT_S_I64 { 1325, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1325 = LT_S_I32x4_S { 1324, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1324 = LT_S_I32x4 { 1323, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1323 = LT_S_I32_S { 1322, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1322 = LT_S_I32 { 1321, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1321 = LT_S_I16x8_S { 1320, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1320 = LT_S_I16x8 { 1319, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1319 = LT_F64x2_S { 1318, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1318 = LT_F64x2 { 1317, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1317 = LT_F64_S { 1316, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1316 = LT_F64 { 1315, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1315 = LT_F32x4_S { 1314, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1314 = LT_F32x4 { 1313, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1313 = LT_F32_S { 1312, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1312 = LT_F32 { 1311, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1311 = LT_F16x8_S { 1310, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1310 = LT_F16x8 { 1309, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1309 = LOOP_S { 1308, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1308 = LOOP { 1307, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1307 = LOCAL_TEE_V128_S { 1306, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 571, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1306 = LOCAL_TEE_V128 { 1305, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1305 = LOCAL_TEE_I64_S { 1304, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 568, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1304 = LOCAL_TEE_I64 { 1303, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1303 = LOCAL_TEE_I32_S { 1302, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 565, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1302 = LOCAL_TEE_I32 { 1301, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1301 = LOCAL_TEE_FUNCREF_S { 1300, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 562, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1300 = LOCAL_TEE_FUNCREF { 1299, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1299 = LOCAL_TEE_F64_S { 1298, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 559, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1298 = LOCAL_TEE_F64 { 1297, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1297 = LOCAL_TEE_F32_S { 1296, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 556, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1296 = LOCAL_TEE_F32 { 1295, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1295 = LOCAL_TEE_EXTERNREF_S { 1294, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 553, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1294 = LOCAL_TEE_EXTERNREF { 1293, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1293 = LOCAL_TEE_EXNREF_S { 1292, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 550, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1292 = LOCAL_TEE_EXNREF { 1291, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1291 = LOCAL_SET_V128_S { 1290, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 548, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1290 = LOCAL_SET_V128 { 1289, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1289 = LOCAL_SET_I64_S { 1288, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 546, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1288 = LOCAL_SET_I64 { 1287, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1287 = LOCAL_SET_I32_S { 1286, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 544, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1286 = LOCAL_SET_I32 { 1285, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1285 = LOCAL_SET_FUNCREF_S { 1284, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 542, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1284 = LOCAL_SET_FUNCREF { 1283, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1283 = LOCAL_SET_F64_S { 1282, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 540, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1282 = LOCAL_SET_F64 { 1281, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1281 = LOCAL_SET_F32_S { 1280, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 538, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1280 = LOCAL_SET_F32 { 1279, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1279 = LOCAL_SET_EXTERNREF_S { 1278, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 536, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1278 = LOCAL_SET_EXTERNREF { 1277, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1277 = LOCAL_SET_EXNREF_S { 1276, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 534, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1276 = LOCAL_SET_EXNREF { 1275, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1275 = LOCAL_GET_V128_S { 1274, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 532, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1274 = LOCAL_GET_V128 { 1273, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1273 = LOCAL_GET_I64_S { 1272, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 530, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1272 = LOCAL_GET_I64 { 1271, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1271 = LOCAL_GET_I32_S { 1270, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 528, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1270 = LOCAL_GET_I32 { 1269, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1269 = LOCAL_GET_FUNCREF_S { 1268, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 526, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1268 = LOCAL_GET_FUNCREF { 1267, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1267 = LOCAL_GET_F64_S { 1266, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 524, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1266 = LOCAL_GET_F64 { 1265, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1265 = LOCAL_GET_F32_S { 1264, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 522, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1264 = LOCAL_GET_F32 { 1263, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1263 = LOCAL_GET_EXTERNREF_S { 1262, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 520, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1262 = LOCAL_GET_EXTERNREF { 1261, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1261 = LOCAL_GET_EXNREF_S { 1260, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 517, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1260 = LOCAL_GET_EXNREF { 1259, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1259 = LOAD_ZERO_64_A64_S { 1258, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1258 = LOAD_ZERO_64_A64 { 1257, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1257 = LOAD_ZERO_64_A32_S { 1256, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1256 = LOAD_ZERO_64_A32 { 1255, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1255 = LOAD_ZERO_32_A64_S { 1254, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1254 = LOAD_ZERO_32_A64 { 1253, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1253 = LOAD_ZERO_32_A32_S { 1252, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1252 = LOAD_ZERO_32_A32 { 1251, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1251 = LOAD_V128_A64_S { 1250, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1250 = LOAD_V128_A64 { 1249, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1249 = LOAD_V128_A32_S { 1248, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1248 = LOAD_V128_A32 { 1247, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1247 = LOAD_LANE_8_A64_S { 1246, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 508, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1246 = LOAD_LANE_8_A64 { 1245, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1245 = LOAD_LANE_8_A32_S { 1244, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 499, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1244 = LOAD_LANE_8_A32 { 1243, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1243 = LOAD_LANE_64_A64_S { 1242, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 508, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1242 = LOAD_LANE_64_A64 { 1241, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1241 = LOAD_LANE_64_A32_S { 1240, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 499, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1240 = LOAD_LANE_64_A32 { 1239, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1239 = LOAD_LANE_32_A64_S { 1238, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 508, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1238 = LOAD_LANE_32_A64 { 1237, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1237 = LOAD_LANE_32_A32_S { 1236, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 499, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1236 = LOAD_LANE_32_A32 { 1235, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1235 = LOAD_LANE_16_A64_S { 1234, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 508, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1234 = LOAD_LANE_16_A64 { 1233, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1233 = LOAD_LANE_16_A32_S { 1232, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 499, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1232 = LOAD_LANE_16_A32 { 1231, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1231 = LOAD_I64_A64_S { 1230, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1230 = LOAD_I64_A64 { 1229, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1229 = LOAD_I64_A32_S { 1228, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1228 = LOAD_I64_A32 { 1227, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1227 = LOAD_I32_A64_S { 1226, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1226 = LOAD_I32_A64 { 1225, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1225 = LOAD_I32_A32_S { 1224, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1224 = LOAD_I32_A32 { 1223, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1223 = LOAD_F64_A64_S { 1222, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 495, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1222 = LOAD_F64_A64 { 1221, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1221 = LOAD_F64_A32_S { 1220, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 491, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1220 = LOAD_F64_A32 { 1219, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1219 = LOAD_F32_A64_S { 1218, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 487, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1218 = LOAD_F32_A64 { 1217, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1217 = LOAD_F32_A32_S { 1216, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 483, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1216 = LOAD_F32_A32 { 1215, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1215 = LOAD_F16_F32_A64_S { 1214, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 487, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1214 = LOAD_F16_F32_A64 { 1213, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1213 = LOAD_F16_F32_A32_S { 1212, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 483, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1212 = LOAD_F16_F32_A32 { 1211, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1211 = LOAD_EXTEND_U_I64x2_A64_S { 1210, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1210 = LOAD_EXTEND_U_I64x2_A64 { 1209, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1209 = LOAD_EXTEND_U_I64x2_A32_S { 1208, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1208 = LOAD_EXTEND_U_I64x2_A32 { 1207, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1207 = LOAD_EXTEND_U_I32x4_A64_S { 1206, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1206 = LOAD_EXTEND_U_I32x4_A64 { 1205, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1205 = LOAD_EXTEND_U_I32x4_A32_S { 1204, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1204 = LOAD_EXTEND_U_I32x4_A32 { 1203, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1203 = LOAD_EXTEND_U_I16x8_A64_S { 1202, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1202 = LOAD_EXTEND_U_I16x8_A64 { 1201, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1201 = LOAD_EXTEND_U_I16x8_A32_S { 1200, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1200 = LOAD_EXTEND_U_I16x8_A32 { 1199, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1199 = LOAD_EXTEND_S_I64x2_A64_S { 1198, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1198 = LOAD_EXTEND_S_I64x2_A64 { 1197, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1197 = LOAD_EXTEND_S_I64x2_A32_S { 1196, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1196 = LOAD_EXTEND_S_I64x2_A32 { 1195, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1195 = LOAD_EXTEND_S_I32x4_A64_S { 1194, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1194 = LOAD_EXTEND_S_I32x4_A64 { 1193, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1193 = LOAD_EXTEND_S_I32x4_A32_S { 1192, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1192 = LOAD_EXTEND_S_I32x4_A32 { 1191, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1191 = LOAD_EXTEND_S_I16x8_A64_S { 1190, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1190 = LOAD_EXTEND_S_I16x8_A64 { 1189, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1189 = LOAD_EXTEND_S_I16x8_A32_S { 1188, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1188 = LOAD_EXTEND_S_I16x8_A32 { 1187, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1187 = LOAD8_U_I64_A64_S { 1186, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1186 = LOAD8_U_I64_A64 { 1185, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1185 = LOAD8_U_I64_A32_S { 1184, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1184 = LOAD8_U_I64_A32 { 1183, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1183 = LOAD8_U_I32_A64_S { 1182, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1182 = LOAD8_U_I32_A64 { 1181, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1181 = LOAD8_U_I32_A32_S { 1180, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1180 = LOAD8_U_I32_A32 { 1179, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1179 = LOAD8_S_I64_A64_S { 1178, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1178 = LOAD8_S_I64_A64 { 1177, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1177 = LOAD8_S_I64_A32_S { 1176, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1176 = LOAD8_S_I64_A32 { 1175, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1175 = LOAD8_S_I32_A64_S { 1174, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1174 = LOAD8_S_I32_A64 { 1173, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1173 = LOAD8_S_I32_A32_S { 1172, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1172 = LOAD8_S_I32_A32 { 1171, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1171 = LOAD8_SPLAT_A64_S { 1170, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1170 = LOAD8_SPLAT_A64 { 1169, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1169 = LOAD8_SPLAT_A32_S { 1168, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1168 = LOAD8_SPLAT_A32 { 1167, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1167 = LOAD64_SPLAT_A64_S { 1166, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1166 = LOAD64_SPLAT_A64 { 1165, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1165 = LOAD64_SPLAT_A32_S { 1164, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1164 = LOAD64_SPLAT_A32 { 1163, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1163 = LOAD32_U_I64_A64_S { 1162, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1162 = LOAD32_U_I64_A64 { 1161, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1161 = LOAD32_U_I64_A32_S { 1160, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1160 = LOAD32_U_I64_A32 { 1159, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1159 = LOAD32_S_I64_A64_S { 1158, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1158 = LOAD32_S_I64_A64 { 1157, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1157 = LOAD32_S_I64_A32_S { 1156, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1156 = LOAD32_S_I64_A32 { 1155, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1155 = LOAD32_SPLAT_A64_S { 1154, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1154 = LOAD32_SPLAT_A64 { 1153, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1153 = LOAD32_SPLAT_A32_S { 1152, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1152 = LOAD32_SPLAT_A32 { 1151, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1151 = LOAD16_U_I64_A64_S { 1150, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1150 = LOAD16_U_I64_A64 { 1149, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1149 = LOAD16_U_I64_A32_S { 1148, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1148 = LOAD16_U_I64_A32 { 1147, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1147 = LOAD16_U_I32_A64_S { 1146, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1146 = LOAD16_U_I32_A64 { 1145, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1145 = LOAD16_U_I32_A32_S { 1144, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1144 = LOAD16_U_I32_A32 { 1143, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1143 = LOAD16_S_I64_A64_S { 1142, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1142 = LOAD16_S_I64_A64 { 1141, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1141 = LOAD16_S_I64_A32_S { 1140, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1140 = LOAD16_S_I64_A32 { 1139, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1139 = LOAD16_S_I32_A64_S { 1138, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1138 = LOAD16_S_I32_A64 { 1137, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1137 = LOAD16_S_I32_A32_S { 1136, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1136 = LOAD16_S_I32_A32 { 1135, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1135 = LOAD16_SPLAT_A64_S { 1134, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1134 = LOAD16_SPLAT_A64 { 1133, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1133 = LOAD16_SPLAT_A32_S { 1132, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1132 = LOAD16_SPLAT_A32 { 1131, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1131 = LE_U_I8x16_S { 1130, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1130 = LE_U_I8x16 { 1129, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1129 = LE_U_I64_S { 1128, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1128 = LE_U_I64 { 1127, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1127 = LE_U_I32x4_S { 1126, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1126 = LE_U_I32x4 { 1125, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1125 = LE_U_I32_S { 1124, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1124 = LE_U_I32 { 1123, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1123 = LE_U_I16x8_S { 1122, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1122 = LE_U_I16x8 { 1121, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1121 = LE_S_I8x16_S { 1120, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1120 = LE_S_I8x16 { 1119, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1119 = LE_S_I64x2_S { 1118, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1118 = LE_S_I64x2 { 1117, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1117 = LE_S_I64_S { 1116, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1116 = LE_S_I64 { 1115, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1115 = LE_S_I32x4_S { 1114, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1114 = LE_S_I32x4 { 1113, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1113 = LE_S_I32_S { 1112, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1112 = LE_S_I32 { 1111, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1111 = LE_S_I16x8_S { 1110, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1110 = LE_S_I16x8 { 1109, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1109 = LE_F64x2_S { 1108, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1108 = LE_F64x2 { 1107, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1107 = LE_F64_S { 1106, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1106 = LE_F64 { 1105, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1105 = LE_F32x4_S { 1104, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1104 = LE_F32x4 { 1103, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1103 = LE_F32_S { 1102, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1102 = LE_F32 { 1101, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1101 = LE_F16x8_S { 1100, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1100 = LE_F16x8 { 1099, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1099 = LANESELECT_I8x16_S { 1098, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1098 = LANESELECT_I8x16 { 1097, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1097 = LANESELECT_I64x2_S { 1096, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1096 = LANESELECT_I64x2 { 1095, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1095 = LANESELECT_I32x4_S { 1094, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1094 = LANESELECT_I32x4 { 1093, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1093 = LANESELECT_I16x8_S { 1092, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1092 = LANESELECT_I16x8 { 1091, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1091 = IF_S { 1090, 2, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 473, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1090 = IF { 1089, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1089 = I64_TRUNC_U_SAT_F64_S { 1088, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1088 = I64_TRUNC_U_SAT_F64 { 1087, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1087 = I64_TRUNC_U_SAT_F32_S { 1086, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1086 = I64_TRUNC_U_SAT_F32 { 1085, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1085 = I64_TRUNC_U_F64_S { 1084, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1084 = I64_TRUNC_U_F64 { 1083, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1083 = I64_TRUNC_U_F32_S { 1082, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1082 = I64_TRUNC_U_F32 { 1081, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1081 = I64_TRUNC_S_SAT_F64_S { 1080, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1080 = I64_TRUNC_S_SAT_F64 { 1079, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1079 = I64_TRUNC_S_SAT_F32_S { 1078, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1078 = I64_TRUNC_S_SAT_F32 { 1077, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1077 = I64_TRUNC_S_F64_S { 1076, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1076 = I64_TRUNC_S_F64 { 1075, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1075 = I64_TRUNC_S_F32_S { 1074, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1074 = I64_TRUNC_S_F32 { 1073, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1073 = I64_REINTERPRET_F64_S { 1072, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1072 = I64_REINTERPRET_F64 { 1071, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1071 = I64_EXTEND_U_I32_S { 1070, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 471, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1070 = I64_EXTEND_U_I32 { 1069, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1069 = I64_EXTEND_S_I32_S { 1068, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 471, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1068 = I64_EXTEND_S_I32 { 1067, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1067 = I64_EXTEND8_S_I64_S { 1066, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 291, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1066 = I64_EXTEND8_S_I64 { 1065, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1065 = I64_EXTEND32_S_I64_S { 1064, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 291, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1064 = I64_EXTEND32_S_I64 { 1063, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1063 = I64_EXTEND16_S_I64_S { 1062, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 291, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1062 = I64_EXTEND16_S_I64 { 1061, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1061 = I32_WRAP_I64_S { 1060, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 394, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1060 = I32_WRAP_I64 { 1059, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1059 = I32_TRUNC_U_SAT_F64_S { 1058, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1058 = I32_TRUNC_U_SAT_F64 { 1057, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1057 = I32_TRUNC_U_SAT_F32_S { 1056, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1056 = I32_TRUNC_U_SAT_F32 { 1055, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1055 = I32_TRUNC_U_F64_S { 1054, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1054 = I32_TRUNC_U_F64 { 1053, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1053 = I32_TRUNC_U_F32_S { 1052, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1052 = I32_TRUNC_U_F32 { 1051, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1051 = I32_TRUNC_S_SAT_F64_S { 1050, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1050 = I32_TRUNC_S_SAT_F64 { 1049, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1049 = I32_TRUNC_S_SAT_F32_S { 1048, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1048 = I32_TRUNC_S_SAT_F32 { 1047, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1047 = I32_TRUNC_S_F64_S { 1046, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1046 = I32_TRUNC_S_F64 { 1045, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1045 = I32_TRUNC_S_F32_S { 1044, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1044 = I32_TRUNC_S_F32 { 1043, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1043 = I32_REINTERPRET_F32_S { 1042, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1042 = I32_REINTERPRET_F32 { 1041, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1041 = I32_EXTEND8_S_I32_S { 1040, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 289, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1040 = I32_EXTEND8_S_I32 { 1039, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1039 = I32_EXTEND16_S_I32_S { 1038, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 289, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1038 = I32_EXTEND16_S_I32 { 1037, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1037 = GT_U_I8x16_S { 1036, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1036 = GT_U_I8x16 { 1035, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1035 = GT_U_I64_S { 1034, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1034 = GT_U_I64 { 1033, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1033 = GT_U_I32x4_S { 1032, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1032 = GT_U_I32x4 { 1031, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1031 = GT_U_I32_S { 1030, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1030 = GT_U_I32 { 1029, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1029 = GT_U_I16x8_S { 1028, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1028 = GT_U_I16x8 { 1027, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1027 = GT_S_I8x16_S { 1026, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1026 = GT_S_I8x16 { 1025, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1025 = GT_S_I64x2_S { 1024, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1024 = GT_S_I64x2 { 1023, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1023 = GT_S_I64_S { 1022, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1022 = GT_S_I64 { 1021, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1021 = GT_S_I32x4_S { 1020, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1020 = GT_S_I32x4 { 1019, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1019 = GT_S_I32_S { 1018, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1018 = GT_S_I32 { 1017, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1017 = GT_S_I16x8_S { 1016, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1016 = GT_S_I16x8 { 1015, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1015 = GT_F64x2_S { 1014, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1014 = GT_F64x2 { 1013, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1013 = GT_F64_S { 1012, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1012 = GT_F64 { 1011, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1011 = GT_F32x4_S { 1010, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1010 = GT_F32x4 { 1009, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1009 = GT_F32_S { 1008, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1008 = GT_F32 { 1007, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1007 = GT_F16x8_S { 1006, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1006 = GT_F16x8 { 1005, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1005 = GLOBAL_SET_V128_S { 1004, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 469, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1004 = GLOBAL_SET_V128 { 1003, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1003 = GLOBAL_SET_I64_S { 1002, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 467, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1002 = GLOBAL_SET_I64 { 1001, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1001 = GLOBAL_SET_I32_S { 1000, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 465, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1000 = GLOBAL_SET_I32 { 999, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #999 = GLOBAL_SET_FUNCREF_S { 998, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 463, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #998 = GLOBAL_SET_FUNCREF { 997, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #997 = GLOBAL_SET_F64_S { 996, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 461, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #996 = GLOBAL_SET_F64 { 995, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #995 = GLOBAL_SET_F32_S { 994, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 459, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #994 = GLOBAL_SET_F32 { 993, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #993 = GLOBAL_SET_EXTERNREF_S { 992, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 457, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #992 = GLOBAL_SET_EXTERNREF { 991, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #991 = GLOBAL_SET_EXNREF_S { 990, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 455, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #990 = GLOBAL_SET_EXNREF { 989, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #989 = GLOBAL_GET_V128_S { 988, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 453, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #988 = GLOBAL_GET_V128 { 987, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #987 = GLOBAL_GET_I64_S { 986, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 451, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #986 = GLOBAL_GET_I64 { 985, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #985 = GLOBAL_GET_I32_S { 984, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 449, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #984 = GLOBAL_GET_I32 { 983, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #983 = GLOBAL_GET_FUNCREF_S { 982, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 447, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #982 = GLOBAL_GET_FUNCREF { 981, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #981 = GLOBAL_GET_F64_S { 980, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 445, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #980 = GLOBAL_GET_F64 { 979, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #979 = GLOBAL_GET_F32_S { 978, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 443, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #978 = GLOBAL_GET_F32 { 977, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #977 = GLOBAL_GET_EXTERNREF_S { 976, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 441, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #976 = GLOBAL_GET_EXTERNREF { 975, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #975 = GLOBAL_GET_EXNREF_S { 974, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 438, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #974 = GLOBAL_GET_EXNREF { 973, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #973 = GE_U_I8x16_S { 972, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #972 = GE_U_I8x16 { 971, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #971 = GE_U_I64_S { 970, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #970 = GE_U_I64 { 969, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #969 = GE_U_I32x4_S { 968, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #968 = GE_U_I32x4 { 967, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #967 = GE_U_I32_S { 966, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #966 = GE_U_I32 { 965, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #965 = GE_U_I16x8_S { 964, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #964 = GE_U_I16x8 { 963, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #963 = GE_S_I8x16_S { 962, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #962 = GE_S_I8x16 { 961, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #961 = GE_S_I64x2_S { 960, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #960 = GE_S_I64x2 { 959, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #959 = GE_S_I64_S { 958, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #958 = GE_S_I64 { 957, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #957 = GE_S_I32x4_S { 956, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #956 = GE_S_I32x4 { 955, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #955 = GE_S_I32_S { 954, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #954 = GE_S_I32 { 953, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #953 = GE_S_I16x8_S { 952, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #952 = GE_S_I16x8 { 951, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #951 = GE_F64x2_S { 950, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #950 = GE_F64x2 { 949, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #949 = GE_F64_S { 948, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #948 = GE_F64 { 947, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #947 = GE_F32x4_S { 946, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #946 = GE_F32x4 { 945, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #945 = GE_F32_S { 944, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #944 = GE_F32 { 943, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #943 = GE_F16x8_S { 942, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #942 = GE_F16x8 { 941, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #941 = FP_TO_UINT_I64_F64_S { 940, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #940 = FP_TO_UINT_I64_F64 { 939, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #939 = FP_TO_UINT_I64_F32_S { 938, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #938 = FP_TO_UINT_I64_F32 { 937, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #937 = FP_TO_UINT_I32_F64_S { 936, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #936 = FP_TO_UINT_I32_F64 { 935, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #935 = FP_TO_UINT_I32_F32_S { 934, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #934 = FP_TO_UINT_I32_F32 { 933, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #933 = FP_TO_SINT_I64_F64_S { 932, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #932 = FP_TO_SINT_I64_F64 { 931, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #931 = FP_TO_SINT_I64_F32_S { 930, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #930 = FP_TO_SINT_I64_F32 { 929, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #929 = FP_TO_SINT_I32_F64_S { 928, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #928 = FP_TO_SINT_I32_F64 { 927, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #927 = FP_TO_SINT_I32_F32_S { 926, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #926 = FP_TO_SINT_I32_F32 { 925, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #925 = FLOOR_F64x2_S { 924, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #924 = FLOOR_F64x2 { 923, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #923 = FLOOR_F64_S { 922, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #922 = FLOOR_F64 { 921, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #921 = FLOOR_F32x4_S { 920, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #920 = FLOOR_F32x4 { 919, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #919 = FLOOR_F32_S { 918, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #918 = FLOOR_F32 { 917, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #917 = FLOOR_F16x8_S { 916, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #916 = FLOOR_F16x8 { 915, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #915 = FALLTHROUGH_RETURN_S { 914, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #914 = FALLTHROUGH_RETURN { 913, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #913 = F64_REINTERPRET_I64_S { 912, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 426, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #912 = F64_REINTERPRET_I64 { 911, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #911 = F64_PROMOTE_F32_S { 910, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 428, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #910 = F64_PROMOTE_F32 { 909, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #909 = F64_CONVERT_U_I64_S { 908, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 426, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #908 = F64_CONVERT_U_I64 { 907, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #907 = F64_CONVERT_U_I32_S { 906, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 424, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #906 = F64_CONVERT_U_I32 { 905, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #905 = F64_CONVERT_S_I64_S { 904, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 426, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #904 = F64_CONVERT_S_I64 { 903, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #903 = F64_CONVERT_S_I32_S { 902, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 424, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #902 = F64_CONVERT_S_I32 { 901, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #901 = F32_REINTERPRET_I32_S { 900, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 418, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #900 = F32_REINTERPRET_I32 { 899, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #899 = F32_DEMOTE_F64_S { 898, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 422, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #898 = F32_DEMOTE_F64 { 897, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #897 = F32_CONVERT_U_I64_S { 896, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 420, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #896 = F32_CONVERT_U_I64 { 895, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #895 = F32_CONVERT_U_I32_S { 894, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 418, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #894 = F32_CONVERT_U_I32 { 893, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #893 = F32_CONVERT_S_I64_S { 892, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 420, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #892 = F32_CONVERT_S_I64 { 891, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #891 = F32_CONVERT_S_I32_S { 890, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 418, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #890 = F32_CONVERT_S_I32 { 889, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #889 = EXTRACT_LANE_I8x16_u_S { 888, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 412, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #888 = EXTRACT_LANE_I8x16_u { 887, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #887 = EXTRACT_LANE_I8x16_s_S { 886, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 412, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #886 = EXTRACT_LANE_I8x16_s { 885, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #885 = EXTRACT_LANE_I64x2_S { 884, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 415, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #884 = EXTRACT_LANE_I64x2 { 883, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #883 = EXTRACT_LANE_I32x4_S { 882, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 412, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #882 = EXTRACT_LANE_I32x4 { 881, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #881 = EXTRACT_LANE_I16x8_u_S { 880, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 412, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #880 = EXTRACT_LANE_I16x8_u { 879, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #879 = EXTRACT_LANE_I16x8_s_S { 878, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 412, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #878 = EXTRACT_LANE_I16x8_s { 877, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #877 = EXTRACT_LANE_F64x2_S { 876, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 409, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #876 = EXTRACT_LANE_F64x2 { 875, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #875 = EXTRACT_LANE_F32x4_S { 874, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 405, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #874 = EXTRACT_LANE_F32x4 { 873, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #873 = EXTRACT_LANE_F16x8_S { 872, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 405, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #872 = EXTRACT_LANE_F16x8 { 871, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #871 = EXTMUL_LOW_U_I64x2_S { 870, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #870 = EXTMUL_LOW_U_I64x2 { 869, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #869 = EXTMUL_LOW_U_I32x4_S { 868, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #868 = EXTMUL_LOW_U_I32x4 { 867, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #867 = EXTMUL_LOW_U_I16x8_S { 866, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #866 = EXTMUL_LOW_U_I16x8 { 865, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #865 = EXTMUL_LOW_S_I64x2_S { 864, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #864 = EXTMUL_LOW_S_I64x2 { 863, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #863 = EXTMUL_LOW_S_I32x4_S { 862, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #862 = EXTMUL_LOW_S_I32x4 { 861, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #861 = EXTMUL_LOW_S_I16x8_S { 860, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #860 = EXTMUL_LOW_S_I16x8 { 859, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #859 = EXTMUL_HIGH_U_I64x2_S { 858, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #858 = EXTMUL_HIGH_U_I64x2 { 857, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #857 = EXTMUL_HIGH_U_I32x4_S { 856, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #856 = EXTMUL_HIGH_U_I32x4 { 855, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #855 = EXTMUL_HIGH_U_I16x8_S { 854, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #854 = EXTMUL_HIGH_U_I16x8 { 853, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #853 = EXTMUL_HIGH_S_I64x2_S { 852, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #852 = EXTMUL_HIGH_S_I64x2 { 851, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #851 = EXTMUL_HIGH_S_I32x4_S { 850, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #850 = EXTMUL_HIGH_S_I32x4 { 849, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #849 = EXTMUL_HIGH_S_I16x8_S { 848, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #848 = EXTMUL_HIGH_S_I16x8 { 847, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #847 = EQ_I8x16_S { 846, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #846 = EQ_I8x16 { 845, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #845 = EQ_I64x2_S { 844, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #844 = EQ_I64x2 { 843, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #843 = EQ_I64_S { 842, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #842 = EQ_I64 { 841, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #841 = EQ_I32x4_S { 840, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #840 = EQ_I32x4 { 839, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #839 = EQ_I32_S { 838, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #838 = EQ_I32 { 837, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #837 = EQ_I16x8_S { 836, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #836 = EQ_I16x8 { 835, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #835 = EQ_F64x2_S { 834, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #834 = EQ_F64x2 { 833, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #833 = EQ_F64_S { 832, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #832 = EQ_F64 { 831, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #831 = EQ_F32x4_S { 830, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #830 = EQ_F32x4 { 829, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #829 = EQ_F32_S { 828, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #828 = EQ_F32 { 827, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #827 = EQ_F16x8_S { 826, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #826 = EQ_F16x8 { 825, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #825 = EQZ_I64_S { 824, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 394, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #824 = EQZ_I64 { 823, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #823 = EQZ_I32_S { 822, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 289, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #822 = EQZ_I32 { 821, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #821 = END_TRY_TABLE_S { 820, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #820 = END_TRY_TABLE { 819, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #819 = END_TRY_S { 818, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #818 = END_TRY { 817, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #817 = END_S { 816, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #816 = END_LOOP_S { 815, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #815 = END_LOOP { 814, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #814 = END_IF_S { 813, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #813 = END_IF { 812, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #812 = END_FUNCTION_S { 811, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #811 = END_FUNCTION { 810, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #810 = END_BLOCK_S { 809, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #809 = END_BLOCK { 808, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #808 = END { 807, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #807 = ELSE_S { 806, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #806 = ELSE { 805, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #805 = DROP_V128_S { 804, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 393, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #804 = DROP_V128 { 803, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #803 = DROP_I64_S { 802, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 284, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #802 = DROP_I64 { 801, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #801 = DROP_I32_S { 800, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 282, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #800 = DROP_I32 { 799, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #799 = DROP_FUNCREF_S { 798, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 392, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #798 = DROP_FUNCREF { 797, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #797 = DROP_F64_S { 796, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 391, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #796 = DROP_F64 { 795, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #795 = DROP_F32_S { 794, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 390, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #794 = DROP_F32 { 793, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #793 = DROP_EXTERNREF_S { 792, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 389, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #792 = DROP_EXTERNREF { 791, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #791 = DROP_EXNREF_S { 790, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #790 = DROP_EXNREF { 789, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #789 = DOT_S { 788, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #788 = DOT { 787, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #787 = DIV_U_I64_S { 786, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #786 = DIV_U_I64 { 785, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #785 = DIV_U_I32_S { 784, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #784 = DIV_U_I32 { 783, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #783 = DIV_S_I64_S { 782, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #782 = DIV_S_I64 { 781, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #781 = DIV_S_I32_S { 780, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #780 = DIV_S_I32 { 779, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #779 = DIV_F64x2_S { 778, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #778 = DIV_F64x2 { 777, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #777 = DIV_F64_S { 776, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #776 = DIV_F64 { 775, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #775 = DIV_F32x4_S { 774, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #774 = DIV_F32x4 { 773, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #773 = DIV_F32_S { 772, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #772 = DIV_F32 { 771, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #771 = DIV_F16x8_S { 770, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #770 = DIV_F16x8 { 769, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #769 = DELEGATE_S { 768, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #768 = DELEGATE { 767, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #767 = DEBUG_UNREACHABLE_S { 766, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #766 = DEBUG_UNREACHABLE { 765, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #765 = CTZ_I64_S { 764, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 291, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #764 = CTZ_I64 { 763, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #763 = CTZ_I32_S { 762, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 289, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #762 = CTZ_I32 { 761, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #761 = COPY_V128_S { 760, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #760 = COPY_V128 { 759, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #759 = COPY_I64_S { 758, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 291, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #758 = COPY_I64 { 757, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #757 = COPY_I32_S { 756, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 289, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #756 = COPY_I32 { 755, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #755 = COPY_FUNCREF_S { 754, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 387, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #754 = COPY_FUNCREF { 753, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #753 = COPY_F64_S { 752, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #752 = COPY_F64 { 751, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #751 = COPY_F32_S { 750, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #750 = COPY_F32 { 749, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #749 = COPY_EXTERNREF_S { 748, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 385, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #748 = COPY_EXTERNREF { 747, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #747 = COPY_EXNREF_S { 746, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 383, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #746 = COPY_EXNREF { 745, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #745 = COPYSIGN_F64_S { 744, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #744 = COPYSIGN_F64 { 743, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #743 = COPYSIGN_F32_S { 742, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #742 = COPYSIGN_F32 { 741, 16, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 367, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #741 = CONST_V128_I8x16_S { 740, 17, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 350, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #740 = CONST_V128_I8x16 { 739, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 348, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #739 = CONST_V128_I64x2_S { 738, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 345, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #738 = CONST_V128_I64x2 { 737, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 341, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #737 = CONST_V128_I32x4_S { 736, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 336, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #736 = CONST_V128_I32x4 { 735, 8, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 328, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #735 = CONST_V128_I16x8_S { 734, 9, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 319, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #734 = CONST_V128_I16x8 { 733, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 317, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #733 = CONST_V128_F64x2_S { 732, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 314, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #732 = CONST_V128_F64x2 { 731, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 310, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #731 = CONST_V128_F32x4_S { 730, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 305, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #730 = CONST_V128_F32x4 { 729, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 304, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #729 = CONST_I64_S { 728, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 302, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #728 = CONST_I64 { 727, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 301, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #727 = CONST_I32_S { 726, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 299, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #726 = CONST_I32 { 725, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 298, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #725 = CONST_F64_S { 724, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 296, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #724 = CONST_F64 { 723, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 295, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #723 = CONST_F32_S { 722, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 293, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #722 = CONST_F32 { 721, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #721 = CLZ_I64_S { 720, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 291, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #720 = CLZ_I64 { 719, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #719 = CLZ_I32_S { 718, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 289, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #718 = CLZ_I32 { 717, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #717 = CEIL_F64x2_S { 716, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #716 = CEIL_F64x2 { 715, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #715 = CEIL_F64_S { 714, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #714 = CEIL_F64 { 713, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #713 = CEIL_F32x4_S { 712, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #712 = CEIL_F32x4 { 711, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #711 = CEIL_F32_S { 710, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #710 = CEIL_F32 { 709, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #709 = CEIL_F16x8_S { 708, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #708 = CEIL_F16x8 { 707, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #707 = CATCH_S { 706, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #706 = CATCH_REF_S { 705, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #705 = CATCH_REF { 704, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #704 = CATCH_LEGACY_S { 703, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #703 = CATCH_LEGACY { 702, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #702 = CATCH_ALL_S { 701, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #701 = CATCH_ALL_REF_S { 700, 1, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #700 = CATCH_ALL_REF { 699, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #699 = CATCH_ALL_LEGACY_S { 698, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #698 = CATCH_ALL_LEGACY { 697, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #697 = CATCH_ALL { 696, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #696 = CATCH { 695, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #695 = CALL_S { 694, 2, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 285, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #694 = CALL_INDIRECT_S { 693, 2, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 285, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #693 = CALL_INDIRECT { 692, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #692 = CALL { 691, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #691 = BR_UNLESS_S { 690, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 280, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #690 = BR_UNLESS { 689, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 283, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #689 = BR_TABLE_I64_S { 688, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 284, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #688 = BR_TABLE_I64 { 687, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 283, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #687 = BR_TABLE_I32_S { 686, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 282, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #686 = BR_TABLE_I32 { 685, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #685 = BR_S { 684, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #684 = BR_IF_S { 683, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 280, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #683 = BR_IF { 682, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #682 = BR { 681, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #681 = BLOCK_S { 680, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #680 = BLOCK { 679, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #679 = BITSELECT_S { 678, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #678 = BITSELECT { 677, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #677 = BITMASK_I8x16_S { 676, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #676 = BITMASK_I8x16 { 675, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #675 = BITMASK_I64x2_S { 674, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #674 = BITMASK_I64x2 { 673, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #673 = BITMASK_I32x4_S { 672, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #672 = BITMASK_I32x4 { 671, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #671 = BITMASK_I16x8_S { 670, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #670 = BITMASK_I16x8 { 669, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #669 = AVGR_U_I8x16_S { 668, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #668 = AVGR_U_I8x16 { 667, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #667 = AVGR_U_I16x8_S { 666, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #666 = AVGR_U_I16x8 { 665, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #665 = ATOMIC_STORE_I64_A64_S { 664, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #664 = ATOMIC_STORE_I64_A64 { 663, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #663 = ATOMIC_STORE_I64_A32_S { 662, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #662 = ATOMIC_STORE_I64_A32 { 661, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #661 = ATOMIC_STORE_I32_A64_S { 660, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #660 = ATOMIC_STORE_I32_A64 { 659, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #659 = ATOMIC_STORE_I32_A32_S { 658, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #658 = ATOMIC_STORE_I32_A32 { 657, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #657 = ATOMIC_STORE8_I64_A64_S { 656, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #656 = ATOMIC_STORE8_I64_A64 { 655, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #655 = ATOMIC_STORE8_I64_A32_S { 654, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #654 = ATOMIC_STORE8_I64_A32 { 653, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #653 = ATOMIC_STORE8_I32_A64_S { 652, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #652 = ATOMIC_STORE8_I32_A64 { 651, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #651 = ATOMIC_STORE8_I32_A32_S { 650, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #650 = ATOMIC_STORE8_I32_A32 { 649, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #649 = ATOMIC_STORE32_I64_A64_S { 648, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #648 = ATOMIC_STORE32_I64_A64 { 647, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #647 = ATOMIC_STORE32_I64_A32_S { 646, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #646 = ATOMIC_STORE32_I64_A32 { 645, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #645 = ATOMIC_STORE16_I64_A64_S { 644, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #644 = ATOMIC_STORE16_I64_A64 { 643, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #643 = ATOMIC_STORE16_I64_A32_S { 642, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #642 = ATOMIC_STORE16_I64_A32 { 641, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #641 = ATOMIC_STORE16_I32_A64_S { 640, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #640 = ATOMIC_STORE16_I32_A64 { 639, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #639 = ATOMIC_STORE16_I32_A32_S { 638, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #638 = ATOMIC_STORE16_I32_A32 { 637, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #637 = ATOMIC_RMW_XOR_I64_A64_S { 636, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #636 = ATOMIC_RMW_XOR_I64_A64 { 635, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #635 = ATOMIC_RMW_XOR_I64_A32_S { 634, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #634 = ATOMIC_RMW_XOR_I64_A32 { 633, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #633 = ATOMIC_RMW_XOR_I32_A64_S { 632, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #632 = ATOMIC_RMW_XOR_I32_A64 { 631, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #631 = ATOMIC_RMW_XOR_I32_A32_S { 630, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #630 = ATOMIC_RMW_XOR_I32_A32 { 629, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #629 = ATOMIC_RMW_XCHG_I64_A64_S { 628, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #628 = ATOMIC_RMW_XCHG_I64_A64 { 627, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #627 = ATOMIC_RMW_XCHG_I64_A32_S { 626, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #626 = ATOMIC_RMW_XCHG_I64_A32 { 625, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #625 = ATOMIC_RMW_XCHG_I32_A64_S { 624, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #624 = ATOMIC_RMW_XCHG_I32_A64 { 623, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #623 = ATOMIC_RMW_XCHG_I32_A32_S { 622, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #622 = ATOMIC_RMW_XCHG_I32_A32 { 621, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #621 = ATOMIC_RMW_SUB_I64_A64_S { 620, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #620 = ATOMIC_RMW_SUB_I64_A64 { 619, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #619 = ATOMIC_RMW_SUB_I64_A32_S { 618, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #618 = ATOMIC_RMW_SUB_I64_A32 { 617, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #617 = ATOMIC_RMW_SUB_I32_A64_S { 616, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #616 = ATOMIC_RMW_SUB_I32_A64 { 615, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #615 = ATOMIC_RMW_SUB_I32_A32_S { 614, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #614 = ATOMIC_RMW_SUB_I32_A32 { 613, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #613 = ATOMIC_RMW_OR_I64_A64_S { 612, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #612 = ATOMIC_RMW_OR_I64_A64 { 611, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #611 = ATOMIC_RMW_OR_I64_A32_S { 610, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #610 = ATOMIC_RMW_OR_I64_A32 { 609, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #609 = ATOMIC_RMW_OR_I32_A64_S { 608, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #608 = ATOMIC_RMW_OR_I32_A64 { 607, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #607 = ATOMIC_RMW_OR_I32_A32_S { 606, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #606 = ATOMIC_RMW_OR_I32_A32 { 605, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #605 = ATOMIC_RMW_CMPXCHG_I64_A64_S { 604, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 252, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #604 = ATOMIC_RMW_CMPXCHG_I64_A64 { 603, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #603 = ATOMIC_RMW_CMPXCHG_I64_A32_S { 602, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 246, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #602 = ATOMIC_RMW_CMPXCHG_I64_A32 { 601, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #601 = ATOMIC_RMW_CMPXCHG_I32_A64_S { 600, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 240, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #600 = ATOMIC_RMW_CMPXCHG_I32_A64 { 599, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #599 = ATOMIC_RMW_CMPXCHG_I32_A32_S { 598, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #598 = ATOMIC_RMW_CMPXCHG_I32_A32 { 597, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #597 = ATOMIC_RMW_AND_I64_A64_S { 596, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #596 = ATOMIC_RMW_AND_I64_A64 { 595, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #595 = ATOMIC_RMW_AND_I64_A32_S { 594, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #594 = ATOMIC_RMW_AND_I64_A32 { 593, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #593 = ATOMIC_RMW_AND_I32_A64_S { 592, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #592 = ATOMIC_RMW_AND_I32_A64 { 591, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #591 = ATOMIC_RMW_AND_I32_A32_S { 590, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #590 = ATOMIC_RMW_AND_I32_A32 { 589, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #589 = ATOMIC_RMW_ADD_I64_A64_S { 588, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #588 = ATOMIC_RMW_ADD_I64_A64 { 587, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #587 = ATOMIC_RMW_ADD_I64_A32_S { 586, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #586 = ATOMIC_RMW_ADD_I64_A32 { 585, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #585 = ATOMIC_RMW_ADD_I32_A64_S { 584, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #584 = ATOMIC_RMW_ADD_I32_A64 { 583, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #583 = ATOMIC_RMW_ADD_I32_A32_S { 582, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #582 = ATOMIC_RMW_ADD_I32_A32 { 581, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #581 = ATOMIC_RMW8_U_XOR_I64_A64_S { 580, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #580 = ATOMIC_RMW8_U_XOR_I64_A64 { 579, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #579 = ATOMIC_RMW8_U_XOR_I64_A32_S { 578, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #578 = ATOMIC_RMW8_U_XOR_I64_A32 { 577, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #577 = ATOMIC_RMW8_U_XOR_I32_A64_S { 576, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #576 = ATOMIC_RMW8_U_XOR_I32_A64 { 575, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #575 = ATOMIC_RMW8_U_XOR_I32_A32_S { 574, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #574 = ATOMIC_RMW8_U_XOR_I32_A32 { 573, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #573 = ATOMIC_RMW8_U_XCHG_I64_A64_S { 572, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #572 = ATOMIC_RMW8_U_XCHG_I64_A64 { 571, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #571 = ATOMIC_RMW8_U_XCHG_I64_A32_S { 570, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #570 = ATOMIC_RMW8_U_XCHG_I64_A32 { 569, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #569 = ATOMIC_RMW8_U_XCHG_I32_A64_S { 568, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #568 = ATOMIC_RMW8_U_XCHG_I32_A64 { 567, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #567 = ATOMIC_RMW8_U_XCHG_I32_A32_S { 566, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #566 = ATOMIC_RMW8_U_XCHG_I32_A32 { 565, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #565 = ATOMIC_RMW8_U_SUB_I64_A64_S { 564, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #564 = ATOMIC_RMW8_U_SUB_I64_A64 { 563, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #563 = ATOMIC_RMW8_U_SUB_I64_A32_S { 562, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #562 = ATOMIC_RMW8_U_SUB_I64_A32 { 561, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #561 = ATOMIC_RMW8_U_SUB_I32_A64_S { 560, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #560 = ATOMIC_RMW8_U_SUB_I32_A64 { 559, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #559 = ATOMIC_RMW8_U_SUB_I32_A32_S { 558, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #558 = ATOMIC_RMW8_U_SUB_I32_A32 { 557, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #557 = ATOMIC_RMW8_U_OR_I64_A64_S { 556, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #556 = ATOMIC_RMW8_U_OR_I64_A64 { 555, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #555 = ATOMIC_RMW8_U_OR_I64_A32_S { 554, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #554 = ATOMIC_RMW8_U_OR_I64_A32 { 553, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #553 = ATOMIC_RMW8_U_OR_I32_A64_S { 552, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #552 = ATOMIC_RMW8_U_OR_I32_A64 { 551, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #551 = ATOMIC_RMW8_U_OR_I32_A32_S { 550, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #550 = ATOMIC_RMW8_U_OR_I32_A32 { 549, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #549 = ATOMIC_RMW8_U_CMPXCHG_I64_A64_S { 548, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 252, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #548 = ATOMIC_RMW8_U_CMPXCHG_I64_A64 { 547, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #547 = ATOMIC_RMW8_U_CMPXCHG_I64_A32_S { 546, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 246, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #546 = ATOMIC_RMW8_U_CMPXCHG_I64_A32 { 545, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #545 = ATOMIC_RMW8_U_CMPXCHG_I32_A64_S { 544, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 240, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #544 = ATOMIC_RMW8_U_CMPXCHG_I32_A64 { 543, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #543 = ATOMIC_RMW8_U_CMPXCHG_I32_A32_S { 542, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #542 = ATOMIC_RMW8_U_CMPXCHG_I32_A32 { 541, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #541 = ATOMIC_RMW8_U_AND_I64_A64_S { 540, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #540 = ATOMIC_RMW8_U_AND_I64_A64 { 539, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #539 = ATOMIC_RMW8_U_AND_I64_A32_S { 538, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #538 = ATOMIC_RMW8_U_AND_I64_A32 { 537, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #537 = ATOMIC_RMW8_U_AND_I32_A64_S { 536, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #536 = ATOMIC_RMW8_U_AND_I32_A64 { 535, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #535 = ATOMIC_RMW8_U_AND_I32_A32_S { 534, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #534 = ATOMIC_RMW8_U_AND_I32_A32 { 533, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #533 = ATOMIC_RMW8_U_ADD_I64_A64_S { 532, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #532 = ATOMIC_RMW8_U_ADD_I64_A64 { 531, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #531 = ATOMIC_RMW8_U_ADD_I64_A32_S { 530, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #530 = ATOMIC_RMW8_U_ADD_I64_A32 { 529, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #529 = ATOMIC_RMW8_U_ADD_I32_A64_S { 528, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #528 = ATOMIC_RMW8_U_ADD_I32_A64 { 527, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #527 = ATOMIC_RMW8_U_ADD_I32_A32_S { 526, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #526 = ATOMIC_RMW8_U_ADD_I32_A32 { 525, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #525 = ATOMIC_RMW32_U_XOR_I64_A64_S { 524, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #524 = ATOMIC_RMW32_U_XOR_I64_A64 { 523, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #523 = ATOMIC_RMW32_U_XOR_I64_A32_S { 522, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #522 = ATOMIC_RMW32_U_XOR_I64_A32 { 521, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #521 = ATOMIC_RMW32_U_XCHG_I64_A64_S { 520, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #520 = ATOMIC_RMW32_U_XCHG_I64_A64 { 519, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #519 = ATOMIC_RMW32_U_XCHG_I64_A32_S { 518, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #518 = ATOMIC_RMW32_U_XCHG_I64_A32 { 517, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #517 = ATOMIC_RMW32_U_SUB_I64_A64_S { 516, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #516 = ATOMIC_RMW32_U_SUB_I64_A64 { 515, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #515 = ATOMIC_RMW32_U_SUB_I64_A32_S { 514, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #514 = ATOMIC_RMW32_U_SUB_I64_A32 { 513, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #513 = ATOMIC_RMW32_U_OR_I64_A64_S { 512, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #512 = ATOMIC_RMW32_U_OR_I64_A64 { 511, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #511 = ATOMIC_RMW32_U_OR_I64_A32_S { 510, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #510 = ATOMIC_RMW32_U_OR_I64_A32 { 509, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #509 = ATOMIC_RMW32_U_CMPXCHG_I64_A64_S { 508, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 252, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #508 = ATOMIC_RMW32_U_CMPXCHG_I64_A64 { 507, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #507 = ATOMIC_RMW32_U_CMPXCHG_I64_A32_S { 506, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 246, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #506 = ATOMIC_RMW32_U_CMPXCHG_I64_A32 { 505, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #505 = ATOMIC_RMW32_U_AND_I64_A64_S { 504, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #504 = ATOMIC_RMW32_U_AND_I64_A64 { 503, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #503 = ATOMIC_RMW32_U_AND_I64_A32_S { 502, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #502 = ATOMIC_RMW32_U_AND_I64_A32 { 501, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #501 = ATOMIC_RMW32_U_ADD_I64_A64_S { 500, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #500 = ATOMIC_RMW32_U_ADD_I64_A64 { 499, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #499 = ATOMIC_RMW32_U_ADD_I64_A32_S { 498, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #498 = ATOMIC_RMW32_U_ADD_I64_A32 { 497, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #497 = ATOMIC_RMW16_U_XOR_I64_A64_S { 496, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #496 = ATOMIC_RMW16_U_XOR_I64_A64 { 495, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #495 = ATOMIC_RMW16_U_XOR_I64_A32_S { 494, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #494 = ATOMIC_RMW16_U_XOR_I64_A32 { 493, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #493 = ATOMIC_RMW16_U_XOR_I32_A64_S { 492, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #492 = ATOMIC_RMW16_U_XOR_I32_A64 { 491, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #491 = ATOMIC_RMW16_U_XOR_I32_A32_S { 490, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #490 = ATOMIC_RMW16_U_XOR_I32_A32 { 489, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #489 = ATOMIC_RMW16_U_XCHG_I64_A64_S { 488, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #488 = ATOMIC_RMW16_U_XCHG_I64_A64 { 487, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #487 = ATOMIC_RMW16_U_XCHG_I64_A32_S { 486, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #486 = ATOMIC_RMW16_U_XCHG_I64_A32 { 485, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #485 = ATOMIC_RMW16_U_XCHG_I32_A64_S { 484, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #484 = ATOMIC_RMW16_U_XCHG_I32_A64 { 483, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #483 = ATOMIC_RMW16_U_XCHG_I32_A32_S { 482, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #482 = ATOMIC_RMW16_U_XCHG_I32_A32 { 481, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #481 = ATOMIC_RMW16_U_SUB_I64_A64_S { 480, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #480 = ATOMIC_RMW16_U_SUB_I64_A64 { 479, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #479 = ATOMIC_RMW16_U_SUB_I64_A32_S { 478, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #478 = ATOMIC_RMW16_U_SUB_I64_A32 { 477, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #477 = ATOMIC_RMW16_U_SUB_I32_A64_S { 476, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #476 = ATOMIC_RMW16_U_SUB_I32_A64 { 475, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #475 = ATOMIC_RMW16_U_SUB_I32_A32_S { 474, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #474 = ATOMIC_RMW16_U_SUB_I32_A32 { 473, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #473 = ATOMIC_RMW16_U_OR_I64_A64_S { 472, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #472 = ATOMIC_RMW16_U_OR_I64_A64 { 471, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #471 = ATOMIC_RMW16_U_OR_I64_A32_S { 470, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #470 = ATOMIC_RMW16_U_OR_I64_A32 { 469, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #469 = ATOMIC_RMW16_U_OR_I32_A64_S { 468, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #468 = ATOMIC_RMW16_U_OR_I32_A64 { 467, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #467 = ATOMIC_RMW16_U_OR_I32_A32_S { 466, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #466 = ATOMIC_RMW16_U_OR_I32_A32 { 465, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #465 = ATOMIC_RMW16_U_CMPXCHG_I64_A64_S { 464, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 252, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #464 = ATOMIC_RMW16_U_CMPXCHG_I64_A64 { 463, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #463 = ATOMIC_RMW16_U_CMPXCHG_I64_A32_S { 462, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 246, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #462 = ATOMIC_RMW16_U_CMPXCHG_I64_A32 { 461, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #461 = ATOMIC_RMW16_U_CMPXCHG_I32_A64_S { 460, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 240, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #460 = ATOMIC_RMW16_U_CMPXCHG_I32_A64 { 459, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #459 = ATOMIC_RMW16_U_CMPXCHG_I32_A32_S { 458, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #458 = ATOMIC_RMW16_U_CMPXCHG_I32_A32 { 457, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #457 = ATOMIC_RMW16_U_AND_I64_A64_S { 456, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #456 = ATOMIC_RMW16_U_AND_I64_A64 { 455, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #455 = ATOMIC_RMW16_U_AND_I64_A32_S { 454, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #454 = ATOMIC_RMW16_U_AND_I64_A32 { 453, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #453 = ATOMIC_RMW16_U_AND_I32_A64_S { 452, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #452 = ATOMIC_RMW16_U_AND_I32_A64 { 451, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #451 = ATOMIC_RMW16_U_AND_I32_A32_S { 450, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #450 = ATOMIC_RMW16_U_AND_I32_A32 { 449, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #449 = ATOMIC_RMW16_U_ADD_I64_A64_S { 448, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #448 = ATOMIC_RMW16_U_ADD_I64_A64 { 447, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #447 = ATOMIC_RMW16_U_ADD_I64_A32_S { 446, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #446 = ATOMIC_RMW16_U_ADD_I64_A32 { 445, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #445 = ATOMIC_RMW16_U_ADD_I32_A64_S { 444, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #444 = ATOMIC_RMW16_U_ADD_I32_A64 { 443, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #443 = ATOMIC_RMW16_U_ADD_I32_A32_S { 442, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #442 = ATOMIC_RMW16_U_ADD_I32_A32 { 441, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #441 = ATOMIC_LOAD_I64_A64_S { 440, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #440 = ATOMIC_LOAD_I64_A64 { 439, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #439 = ATOMIC_LOAD_I64_A32_S { 438, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #438 = ATOMIC_LOAD_I64_A32 { 437, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #437 = ATOMIC_LOAD_I32_A64_S { 436, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #436 = ATOMIC_LOAD_I32_A64 { 435, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #435 = ATOMIC_LOAD_I32_A32_S { 434, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #434 = ATOMIC_LOAD_I32_A32 { 433, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #433 = ATOMIC_LOAD8_U_I64_A64_S { 432, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #432 = ATOMIC_LOAD8_U_I64_A64 { 431, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #431 = ATOMIC_LOAD8_U_I64_A32_S { 430, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #430 = ATOMIC_LOAD8_U_I64_A32 { 429, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #429 = ATOMIC_LOAD8_U_I32_A64_S { 428, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #428 = ATOMIC_LOAD8_U_I32_A64 { 427, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #427 = ATOMIC_LOAD8_U_I32_A32_S { 426, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #426 = ATOMIC_LOAD8_U_I32_A32 { 425, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #425 = ATOMIC_LOAD32_U_I64_A64_S { 424, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #424 = ATOMIC_LOAD32_U_I64_A64 { 423, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #423 = ATOMIC_LOAD32_U_I64_A32_S { 422, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #422 = ATOMIC_LOAD32_U_I64_A32 { 421, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #421 = ATOMIC_LOAD16_U_I64_A64_S { 420, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #420 = ATOMIC_LOAD16_U_I64_A64 { 419, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #419 = ATOMIC_LOAD16_U_I64_A32_S { 418, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #418 = ATOMIC_LOAD16_U_I64_A32 { 417, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #417 = ATOMIC_LOAD16_U_I32_A64_S { 416, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #416 = ATOMIC_LOAD16_U_I32_A64 { 415, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #415 = ATOMIC_LOAD16_U_I32_A32_S { 414, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #414 = ATOMIC_LOAD16_U_I32_A32 { 413, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #413 = ATOMIC_FENCE_S { 412, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #412 = ATOMIC_FENCE { 411, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #411 = ARGUMENT_v8i16_S { 410, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #410 = ARGUMENT_v8i16 { 409, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #409 = ARGUMENT_v8f16_S { 408, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #408 = ARGUMENT_v8f16 { 407, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #407 = ARGUMENT_v4i32_S { 406, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #406 = ARGUMENT_v4i32 { 405, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #405 = ARGUMENT_v4f32_S { 404, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #404 = ARGUMENT_v4f32 { 403, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #403 = ARGUMENT_v2i64_S { 402, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #402 = ARGUMENT_v2i64 { 401, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #401 = ARGUMENT_v2f64_S { 400, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #400 = ARGUMENT_v2f64 { 399, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #399 = ARGUMENT_v16i8_S { 398, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #398 = ARGUMENT_v16i8 { 397, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #397 = ARGUMENT_i64_S { 396, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 190, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #396 = ARGUMENT_i64 { 395, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #395 = ARGUMENT_i32_S { 394, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 188, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #394 = ARGUMENT_i32 { 393, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #393 = ARGUMENT_funcref_S { 392, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 186, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #392 = ARGUMENT_funcref { 391, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #391 = ARGUMENT_f64_S { 390, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 184, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #390 = ARGUMENT_f64 { 389, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #389 = ARGUMENT_f32_S { 388, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 182, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #388 = ARGUMENT_f32 { 387, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #387 = ARGUMENT_externref_S { 386, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 180, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #386 = ARGUMENT_externref { 385, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #385 = ARGUMENT_exnref_S { 384, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 178, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #384 = ARGUMENT_exnref { 383, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #383 = ANYTRUE_S { 382, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #382 = ANYTRUE { 381, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #381 = AND_S { 380, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #380 = AND_I64_S { 379, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #379 = AND_I64 { 378, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #378 = AND_I32_S { 377, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #377 = AND_I32 { 376, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #376 = ANDNOT_S { 375, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #375 = ANDNOT { 374, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #374 = AND { 373, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #373 = ALLTRUE_I8x16_S { 372, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #372 = ALLTRUE_I8x16 { 371, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #371 = ALLTRUE_I64x2_S { 370, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #370 = ALLTRUE_I64x2 { 369, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #369 = ALLTRUE_I32x4_S { 368, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #368 = ALLTRUE_I32x4 { 367, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #367 = ALLTRUE_I16x8_S { 366, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #366 = ALLTRUE_I16x8 { 365, 2, 0, 0, 0, 2, 2, WebAssemblyImpOpBase + 4, 21, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #365 = ADJCALLSTACKUP_S { 364, 2, 0, 0, 0, 2, 2, WebAssemblyImpOpBase + 4, 21, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #364 = ADJCALLSTACKUP { 363, 2, 0, 0, 0, 2, 2, WebAssemblyImpOpBase + 4, 21, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #363 = ADJCALLSTACKDOWN_S { 362, 2, 0, 0, 0, 2, 2, WebAssemblyImpOpBase + 4, 21, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #362 = ADJCALLSTACKDOWN { 361, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #361 = ADD_SAT_U_I8x16_S { 360, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #360 = ADD_SAT_U_I8x16 { 359, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #359 = ADD_SAT_U_I16x8_S { 358, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #358 = ADD_SAT_U_I16x8 { 357, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #357 = ADD_SAT_S_I8x16_S { 356, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #356 = ADD_SAT_S_I8x16 { 355, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #355 = ADD_SAT_S_I16x8_S { 354, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #354 = ADD_SAT_S_I16x8 { 353, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #353 = ADD_I8x16_S { 352, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #352 = ADD_I8x16 { 351, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #351 = ADD_I64x2_S { 350, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #350 = ADD_I64x2 { 349, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #349 = ADD_I64_S { 348, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #348 = ADD_I64 { 347, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #347 = ADD_I32x4_S { 346, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #346 = ADD_I32x4 { 345, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #345 = ADD_I32_S { 344, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #344 = ADD_I32 { 343, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #343 = ADD_I16x8_S { 342, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #342 = ADD_I16x8 { 341, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #341 = ADD_F64x2_S { 340, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #340 = ADD_F64x2 { 339, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #339 = ADD_F64_S { 338, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #338 = ADD_F64 { 337, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #337 = ADD_F32x4_S { 336, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #336 = ADD_F32x4 { 335, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #335 = ADD_F32_S { 334, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #334 = ADD_F32 { 333, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #333 = ADD_F16x8_S { 332, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #332 = ADD_F16x8 { 331, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #331 = ABS_I8x16_S { 330, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #330 = ABS_I8x16 { 329, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #329 = ABS_I64x2_S { 328, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #328 = ABS_I64x2 { 327, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #327 = ABS_I32x4_S { 326, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #326 = ABS_I32x4 { 325, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #325 = ABS_I16x8_S { 324, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #324 = ABS_I16x8 { 323, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #323 = ABS_F64x2_S { 322, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #322 = ABS_F64x2 { 321, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #321 = ABS_F64_S { 320, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #320 = ABS_F64 { 319, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #319 = ABS_F32x4_S { 318, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #318 = ABS_F32x4 { 317, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #317 = ABS_F32_S { 316, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #316 = ABS_F32 { 315, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #315 = ABS_F16x8_S { 314, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #314 = ABS_F16x8 { 313, 0, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #313 = RET_CALL_RESULTS_S { 312, 0, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #312 = RET_CALL_RESULTS { 311, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #311 = COMPILER_FENCE_S { 310, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #310 = COMPILER_FENCE { 309, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #309 = CLEANUPRET_S { 308, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #308 = CLEANUPRET { 307, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 153, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #307 = CATCHRET_S { 306, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 153, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #306 = CATCHRET { 305, 0, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #305 = CALL_RESULTS_S { 304, 0, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #304 = CALL_RESULTS { 303, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #303 = CALL_PARAMS_S { 302, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #302 = CALL_PARAMS { 301, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #301 = G_UBFX { 300, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #300 = G_SBFX { 299, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #299 = G_VECREDUCE_UMIN { 298, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #298 = G_VECREDUCE_UMAX { 297, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #297 = G_VECREDUCE_SMIN { 296, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #296 = G_VECREDUCE_SMAX { 295, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #295 = G_VECREDUCE_XOR { 294, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #294 = G_VECREDUCE_OR { 293, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #293 = G_VECREDUCE_AND { 292, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #292 = G_VECREDUCE_MUL { 291, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #291 = G_VECREDUCE_ADD { 290, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #290 = G_VECREDUCE_FMINIMUM { 289, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #289 = G_VECREDUCE_FMAXIMUM { 288, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #288 = G_VECREDUCE_FMIN { 287, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #287 = G_VECREDUCE_FMAX { 286, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #286 = G_VECREDUCE_FMUL { 285, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #285 = G_VECREDUCE_FADD { 284, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #284 = G_VECREDUCE_SEQ_FMUL { 283, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #283 = G_VECREDUCE_SEQ_FADD { 282, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #282 = G_UBSANTRAP { 281, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #281 = G_DEBUGTRAP { 280, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #280 = G_TRAP { 279, 3, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #279 = G_BZERO { 278, 4, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #278 = G_MEMSET { 277, 4, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #277 = G_MEMMOVE { 276, 3, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #276 = G_MEMCPY_INLINE { 275, 4, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #275 = G_MEMCPY { 274, 2, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #274 = G_WRITE_REGISTER { 273, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #273 = G_READ_REGISTER { 272, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #272 = G_STRICT_FLDEXP { 271, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #271 = G_STRICT_FSQRT { 270, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #270 = G_STRICT_FMA { 269, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #269 = G_STRICT_FREM { 268, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #268 = G_STRICT_FDIV { 267, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #267 = G_STRICT_FMUL { 266, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #266 = G_STRICT_FSUB { 265, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #265 = G_STRICT_FADD { 264, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #264 = G_STACKRESTORE { 263, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #263 = G_STACKSAVE { 262, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #262 = G_DYN_STACKALLOC { 261, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #261 = G_JUMP_TABLE { 260, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #260 = G_BLOCK_ADDR { 259, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #259 = G_ADDRSPACE_CAST { 258, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #258 = G_FNEARBYINT { 257, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #257 = G_FRINT { 256, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #256 = G_FFLOOR { 255, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #255 = G_FSQRT { 254, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #254 = G_FTANH { 253, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #253 = G_FSINH { 252, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #252 = G_FCOSH { 251, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #251 = G_FATAN2 { 250, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #250 = G_FATAN { 249, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #249 = G_FASIN { 248, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #248 = G_FACOS { 247, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #247 = G_FTAN { 246, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #246 = G_FSIN { 245, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #245 = G_FCOS { 244, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #244 = G_FCEIL { 243, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #243 = G_BITREVERSE { 242, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #242 = G_BSWAP { 241, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #241 = G_CTPOP { 240, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #240 = G_CTLZ_ZERO_UNDEF { 239, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #239 = G_CTLZ { 238, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #238 = G_CTTZ_ZERO_UNDEF { 237, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #237 = G_CTTZ { 236, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #236 = G_VECTOR_COMPRESS { 235, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #235 = G_SPLAT_VECTOR { 234, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #234 = G_SHUFFLE_VECTOR { 233, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #233 = G_EXTRACT_VECTOR_ELT { 232, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #232 = G_INSERT_VECTOR_ELT { 231, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #231 = G_EXTRACT_SUBVECTOR { 230, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #230 = G_INSERT_SUBVECTOR { 229, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #229 = G_VSCALE { 228, 3, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #228 = G_BRJT { 227, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #227 = G_BR { 226, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #226 = G_LLROUND { 225, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #225 = G_LROUND { 224, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #224 = G_ABS { 223, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #223 = G_UMAX { 222, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #222 = G_UMIN { 221, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #221 = G_SMAX { 220, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #220 = G_SMIN { 219, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #219 = G_PTRMASK { 218, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #218 = G_PTR_ADD { 217, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #217 = G_RESET_FPMODE { 216, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #216 = G_SET_FPMODE { 215, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #215 = G_GET_FPMODE { 214, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #214 = G_RESET_FPENV { 213, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #213 = G_SET_FPENV { 212, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #212 = G_GET_FPENV { 211, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #211 = G_FMAXIMUM { 210, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #210 = G_FMINIMUM { 209, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #209 = G_FMAXNUM_IEEE { 208, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #208 = G_FMINNUM_IEEE { 207, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #207 = G_FMAXNUM { 206, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #206 = G_FMINNUM { 205, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #205 = G_FCANONICALIZE { 204, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #204 = G_IS_FPCLASS { 203, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #203 = G_FCOPYSIGN { 202, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #202 = G_FABS { 201, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #201 = G_FPTOUI_SAT { 200, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #200 = G_FPTOSI_SAT { 199, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #199 = G_UITOFP { 198, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #198 = G_SITOFP { 197, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #197 = G_FPTOUI { 196, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #196 = G_FPTOSI { 195, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #195 = G_FPTRUNC { 194, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #194 = G_FPEXT { 193, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #193 = G_FNEG { 192, 3, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #192 = G_FFREXP { 191, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #191 = G_FLDEXP { 190, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #190 = G_FLOG10 { 189, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #189 = G_FLOG2 { 188, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #188 = G_FLOG { 187, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #187 = G_FEXP10 { 186, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #186 = G_FEXP2 { 185, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #185 = G_FEXP { 184, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #184 = G_FPOWI { 183, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #183 = G_FPOW { 182, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #182 = G_FREM { 181, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #181 = G_FDIV { 180, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #180 = G_FMAD { 179, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::<TRUNCATED>#ifdef __GNUC__#pragma GCC diagnostic push#pragma GCC diagnostic ignored "-Woverlength-strings"#endif#ifdef __GNUC__#pragma GCC diagnostic pop#endif#endif // GET_INSTRINFO_MC_DESC#ifdef GET_INSTRINFO_HEADER#undef GET_INSTRINFO_HEADER#endif // GET_INSTRINFO_HEADER#ifdef GET_INSTRINFO_HELPER_DECLS#undef GET_INSTRINFO_HELPER_DECLS#endif // GET_INSTRINFO_HELPER_DECLS#ifdef GET_INSTRINFO_HELPERS#undef GET_INSTRINFO_HELPERS#endif // GET_INSTRINFO_HELPERS#ifdef GET_INSTRINFO_CTOR_DTOR#undef GET_INSTRINFO_CTOR_DTOR#endif // GET_INSTRINFO_CTOR_DTOR#ifdef GET_INSTRINFO_OPERAND_ENUM#undef GET_INSTRINFO_OPERAND_ENUM#endif //GET_INSTRINFO_OPERAND_ENUM#ifdef GET_INSTRINFO_NAMED_OPS#undef GET_INSTRINFO_NAMED_OPS#endif //GET_INSTRINFO_NAMED_OPS#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM#undef GET_INSTRINFO_OPERAND_TYPES_ENUM#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM#ifdef GET_INSTRINFO_OPERAND_TYPE#undef GET_INSTRINFO_OPERAND_TYPE#endif // GET_INSTRINFO_OPERAND_TYPE#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE#undef GET_INSTRINFO_MEM_OPERAND_SIZE#endif // GET_INSTRINFO_MEM_OPERAND_SIZE#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP#ifdef GET_INSTRINFO_MC_HELPER_DECLS#undef GET_INSTRINFO_MC_HELPER_DECLSclass MCInstclass FeatureBitsetvoid verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features)#endif // GET_INSTRINFO_MC_HELPER_DECLS#ifdef GET_INSTRINFO_MC_HELPERS#undef GET_INSTRINFO_MC_HELPERS#endif // GET_GENISTRINFO_MC_HELPERS#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\ defined(GET_AVAILABLE_OPCODE_CHECKER)#define GET_COMPUTE_FEATURES#endif#ifdef GET_COMPUTE_FEATURES#undef GET_COMPUTE_FEATURES#endif // GET_COMPUTE_FEATURES#ifdef GET_AVAILABLE_OPCODE_CHECKER#undef GET_AVAILABLE_OPCODE_CHECKER#endif // GET_AVAILABLE_OPCODE_CHECKER#ifdef ENABLE_INSTR_PREDICATE_VERIFIER#undef ENABLE_INSTR_PREDICATE_VERIFIER#include <sstream>#ifndef NDEBUG#endif // NDEBUG#ifndef NDEBUG#endif // NDEBUG#endif // ENABLE_INSTR_PREDICATE_VERIFIER#ifdef GET_INSTRMAP_INFO#undef GET_INSTRMAP_INFO#endif // GET_INSTRMAP_INFO
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