//=== X86CallingConv.cpp - X86 Custom Calling Convention Impl -*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file contains the implementation of custom routines for the X86 // Calling Convention that aren't done by tablegen. // //===----------------------------------------------------------------------===// #include "X86CallingConv.h" #include "X86Subtarget.h" #include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/IR/CallingConv.h" #include "llvm/IR/Module.h" usingnamespacellvm; /// When regcall calling convention compiled to 32 bit arch, special treatment /// is required for 64 bit masks. /// The value should be assigned to two GPRs. /// \return true if registers were allocated and false otherwise. static bool CC_X86_32_RegCall_Assign2Regs(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { … } static ArrayRef<MCPhysReg> CC_X86_VectorCallGetSSEs(const MVT &ValVT) { … } static ArrayRef<MCPhysReg> CC_X86_64_VectorCallGetGPRs() { … } static bool CC_X86_VectorCallAssignRegister(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { … } /// Vectorcall calling convention has special handling for vector types or /// HVA for 64 bit arch. /// For HVAs shadow registers might be allocated on the first pass /// and actual XMM registers are allocated on the second pass. /// For vector types, actual XMM registers are allocated on the first pass. /// \return true if registers were allocated and false otherwise. static bool CC_X86_64_VectorCall(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { … } /// Vectorcall calling convention has special handling for vector types or /// HVA for 32 bit arch. /// For HVAs actual XMM registers are allocated on the second pass. /// For vector types, actual XMM registers are allocated on the first pass. /// \return true if registers were allocated and false otherwise. static bool CC_X86_32_VectorCall(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { … } static bool CC_X86_AnyReg_Error(unsigned &, MVT &, MVT &, CCValAssign::LocInfo &, ISD::ArgFlagsTy &, CCState &) { … } static bool CC_X86_32_MCUInReg(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { … } /// X86 interrupt handlers can only take one or two stack arguments, but if /// there are two arguments, they are in the opposite order from the standard /// convention. Therefore, we have to look at the argument count up front before /// allocating stack for each argument. static bool CC_X86_Intr(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { … } static bool CC_X86_64_Pointer(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { … } // Provides entry points of CC_X86 and RetCC_X86. #include "X86GenCallingConv.inc"