//===-- X86DisassemblerDecoderInternal.h - Disassembler decoder -*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file is part of the X86 Disassembler. // It contains the public interface of the instruction decoder. // Documentation for the disassembler can be found in X86Disassembler.h. // //===----------------------------------------------------------------------===// #ifndef LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H #define LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H #include "llvm/ADT/ArrayRef.h" #include "llvm/Support/X86DisassemblerDecoderCommon.h" namespace llvm { namespace X86Disassembler { // Helper macros #define bitFromOffset0(val) … #define bitFromOffset1(val) … #define bitFromOffset2(val) … #define bitFromOffset3(val) … #define bitFromOffset4(val) … #define bitFromOffset5(val) … #define bitFromOffset6(val) … #define bitFromOffset7(val) … #define twoBitsFromOffset0(val) … #define twoBitsFromOffset6(val) … #define threeBitsFromOffset0(val) … #define threeBitsFromOffset3(val) … #define fourBitsFromOffset0(val) … #define fourBitsFromOffset3(val) … #define fiveBitsFromOffset0(val) … #define invertedBitFromOffset2(val) … #define invertedBitFromOffset3(val) … #define invertedBitFromOffset4(val) … #define invertedBitFromOffset5(val) … #define invertedBitFromOffset6(val) … #define invertedBitFromOffset7(val) … #define invertedFourBitsFromOffset3(val) … // MOD/RM #define modFromModRM(modRM) … #define regFromModRM(modRM) … #define rmFromModRM(modRM) … // SIB #define scaleFromSIB(sib) … #define indexFromSIB(sib) … #define baseFromSIB(sib) … // REX #define wFromREX(rex) … #define rFromREX(rex) … #define xFromREX(rex) … #define bFromREX(rex) … // REX2 #define mFromREX2(rex2) … #define r2FromREX2(rex2) … #define x2FromREX2(rex2) … #define b2FromREX2(rex2) … #define wFromREX2(rex2) … #define rFromREX2(rex2) … #define xFromREX2(rex2) … #define bFromREX2(rex2) … // XOP #define rFromXOP2of3(xop) … #define xFromXOP2of3(xop) … #define bFromXOP2of3(xop) … #define mmmmmFromXOP2of3(xop) … #define wFromXOP3of3(xop) … #define vvvvFromXOP3of3(xop) … #define lFromXOP3of3(xop) … #define ppFromXOP3of3(xop) … // VEX2 #define rFromVEX2of2(vex) … #define vvvvFromVEX2of2(vex) … #define lFromVEX2of2(vex) … #define ppFromVEX2of2(vex) … // VEX3 #define rFromVEX2of3(vex) … #define xFromVEX2of3(vex) … #define bFromVEX2of3(vex) … #define mmmmmFromVEX2of3(vex) … #define wFromVEX3of3(vex) … #define vvvvFromVEX3of3(vex) … #define lFromVEX3of3(vex) … #define ppFromVEX3of3(vex) … // EVEX #define rFromEVEX2of4(evex) … #define xFromEVEX2of4(evex) … #define bFromEVEX2of4(evex) … #define r2FromEVEX2of4(evex) … #define b2FromEVEX2of4(evex) … #define mmmFromEVEX2of4(evex) … #define wFromEVEX3of4(evex) … #define vvvvFromEVEX3of4(evex) … #define uFromEVEX3of4(evex) … #define ppFromEVEX3of4(evex) … #define oszcFromEVEX3of4(evex) … #define zFromEVEX4of4(evex) … #define l2FromEVEX4of4(evex) … #define lFromEVEX4of4(evex) … #define bFromEVEX4of4(evex) … #define v2FromEVEX4of4(evex) … #define aaaFromEVEX4of4(evex) … #define nfFromEVEX4of4(evex) … #define scFromEVEX4of4(evex) … // These enums represent Intel registers for use by the decoder. #define REGS_8BIT … #define EA_BASES_16BIT … #define REGS_16BIT … #define EA_BASES_32BIT … #define REGS_32BIT … #define EA_BASES_64BIT … #define REGS_64BIT … #define REGS_MMX … #define REGS_XMM … #define REGS_YMM … #define REGS_ZMM … #define REGS_MASKS … #define REGS_MASK_PAIRS … #define REGS_SEGMENT … #define REGS_DEBUG … #define REGS_CONTROL … #undef REGS_TMM #define REGS_TMM … #define ALL_EA_BASES … #define ALL_SIB_BASES … #define ALL_REGS … /// All possible values of the base field for effective-address /// computations, a.k.a. the Mod and R/M fields of the ModR/M byte. /// We distinguish between bases (EA_BASE_*) and registers that just happen /// to be referred to when Mod == 0b11 (EA_REG_*). enum EABase { … }; /// All possible values of the SIB index field. /// borrows entries from ALL_EA_BASES with the special case that /// sib is synonymous with NONE. /// Vector SIB: index can be XMM or YMM. enum SIBIndex { … }; /// All possible values of the SIB base field. enum SIBBase { … }; /// Possible displacement types for effective-address computations. enum EADisplacement { … }; /// All possible values of the reg field in the ModR/M byte. // clang-format off enum Reg { … }; // clang-format on /// All possible segment overrides. enum SegmentOverride { … }; /// Possible values for the VEX.m-mmmm field enum VEXLeadingOpcodeByte { … }; enum XOPMapSelect { … }; /// Possible values for the VEX.pp/EVEX.pp field enum VEXPrefixCode { … }; enum VectorExtensionType { … }; /// The specification for how to extract and interpret a full instruction and /// its operands. struct InstructionSpecifier { … }; /// The x86 internal instruction, which is produced by the decoder. struct InternalInstruction { … }; } // namespace X86Disassembler } // namespace llvm #endif
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