#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
namespace llvm {
namespace XCore {
enum {
PHI = 0,
INLINEASM = 1,
INLINEASM_BR = 2,
CFI_INSTRUCTION = 3,
EH_LABEL = 4,
GC_LABEL = 5,
ANNOTATION_LABEL = 6,
KILL = 7,
EXTRACT_SUBREG = 8,
INSERT_SUBREG = 9,
IMPLICIT_DEF = 10,
INIT_UNDEF = 11,
SUBREG_TO_REG = 12,
COPY_TO_REGCLASS = 13,
DBG_VALUE = 14,
DBG_VALUE_LIST = 15,
DBG_INSTR_REF = 16,
DBG_PHI = 17,
DBG_LABEL = 18,
REG_SEQUENCE = 19,
COPY = 20,
BUNDLE = 21,
LIFETIME_START = 22,
LIFETIME_END = 23,
PSEUDO_PROBE = 24,
ARITH_FENCE = 25,
STACKMAP = 26,
FENTRY_CALL = 27,
PATCHPOINT = 28,
LOAD_STACK_GUARD = 29,
PREALLOCATED_SETUP = 30,
PREALLOCATED_ARG = 31,
STATEPOINT = 32,
LOCAL_ESCAPE = 33,
FAULTING_OP = 34,
PATCHABLE_OP = 35,
PATCHABLE_FUNCTION_ENTER = 36,
PATCHABLE_RET = 37,
PATCHABLE_FUNCTION_EXIT = 38,
PATCHABLE_TAIL_CALL = 39,
PATCHABLE_EVENT_CALL = 40,
PATCHABLE_TYPED_EVENT_CALL = 41,
ICALL_BRANCH_FUNNEL = 42,
FAKE_USE = 43,
MEMBARRIER = 44,
JUMP_TABLE_DEBUG_INFO = 45,
CONVERGENCECTRL_ENTRY = 46,
CONVERGENCECTRL_ANCHOR = 47,
CONVERGENCECTRL_LOOP = 48,
CONVERGENCECTRL_GLUE = 49,
G_ASSERT_SEXT = 50,
G_ASSERT_ZEXT = 51,
G_ASSERT_ALIGN = 52,
G_ADD = 53,
G_SUB = 54,
G_MUL = 55,
G_SDIV = 56,
G_UDIV = 57,
G_SREM = 58,
G_UREM = 59,
G_SDIVREM = 60,
G_UDIVREM = 61,
G_AND = 62,
G_OR = 63,
G_XOR = 64,
G_IMPLICIT_DEF = 65,
G_PHI = 66,
G_FRAME_INDEX = 67,
G_GLOBAL_VALUE = 68,
G_PTRAUTH_GLOBAL_VALUE = 69,
G_CONSTANT_POOL = 70,
G_EXTRACT = 71,
G_UNMERGE_VALUES = 72,
G_INSERT = 73,
G_MERGE_VALUES = 74,
G_BUILD_VECTOR = 75,
G_BUILD_VECTOR_TRUNC = 76,
G_CONCAT_VECTORS = 77,
G_PTRTOINT = 78,
G_INTTOPTR = 79,
G_BITCAST = 80,
G_FREEZE = 81,
G_CONSTANT_FOLD_BARRIER = 82,
G_INTRINSIC_FPTRUNC_ROUND = 83,
G_INTRINSIC_TRUNC = 84,
G_INTRINSIC_ROUND = 85,
G_INTRINSIC_LRINT = 86,
G_INTRINSIC_LLRINT = 87,
G_INTRINSIC_ROUNDEVEN = 88,
G_READCYCLECOUNTER = 89,
G_READSTEADYCOUNTER = 90,
G_LOAD = 91,
G_SEXTLOAD = 92,
G_ZEXTLOAD = 93,
G_INDEXED_LOAD = 94,
G_INDEXED_SEXTLOAD = 95,
G_INDEXED_ZEXTLOAD = 96,
G_STORE = 97,
G_INDEXED_STORE = 98,
G_ATOMIC_CMPXCHG_WITH_SUCCESS = 99,
G_ATOMIC_CMPXCHG = 100,
G_ATOMICRMW_XCHG = 101,
G_ATOMICRMW_ADD = 102,
G_ATOMICRMW_SUB = 103,
G_ATOMICRMW_AND = 104,
G_ATOMICRMW_NAND = 105,
G_ATOMICRMW_OR = 106,
G_ATOMICRMW_XOR = 107,
G_ATOMICRMW_MAX = 108,
G_ATOMICRMW_MIN = 109,
G_ATOMICRMW_UMAX = 110,
G_ATOMICRMW_UMIN = 111,
G_ATOMICRMW_FADD = 112,
G_ATOMICRMW_FSUB = 113,
G_ATOMICRMW_FMAX = 114,
G_ATOMICRMW_FMIN = 115,
G_ATOMICRMW_UINC_WRAP = 116,
G_ATOMICRMW_UDEC_WRAP = 117,
G_ATOMICRMW_USUB_COND = 118,
G_ATOMICRMW_USUB_SAT = 119,
G_FENCE = 120,
G_PREFETCH = 121,
G_BRCOND = 122,
G_BRINDIRECT = 123,
G_INVOKE_REGION_START = 124,
G_INTRINSIC = 125,
G_INTRINSIC_W_SIDE_EFFECTS = 126,
G_INTRINSIC_CONVERGENT = 127,
G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 128,
G_ANYEXT = 129,
G_TRUNC = 130,
G_CONSTANT = 131,
G_FCONSTANT = 132,
G_VASTART = 133,
G_VAARG = 134,
G_SEXT = 135,
G_SEXT_INREG = 136,
G_ZEXT = 137,
G_SHL = 138,
G_LSHR = 139,
G_ASHR = 140,
G_FSHL = 141,
G_FSHR = 142,
G_ROTR = 143,
G_ROTL = 144,
G_ICMP = 145,
G_FCMP = 146,
G_SCMP = 147,
G_UCMP = 148,
G_SELECT = 149,
G_UADDO = 150,
G_UADDE = 151,
G_USUBO = 152,
G_USUBE = 153,
G_SADDO = 154,
G_SADDE = 155,
G_SSUBO = 156,
G_SSUBE = 157,
G_UMULO = 158,
G_SMULO = 159,
G_UMULH = 160,
G_SMULH = 161,
G_UADDSAT = 162,
G_SADDSAT = 163,
G_USUBSAT = 164,
G_SSUBSAT = 165,
G_USHLSAT = 166,
G_SSHLSAT = 167,
G_SMULFIX = 168,
G_UMULFIX = 169,
G_SMULFIXSAT = 170,
G_UMULFIXSAT = 171,
G_SDIVFIX = 172,
G_UDIVFIX = 173,
G_SDIVFIXSAT = 174,
G_UDIVFIXSAT = 175,
G_FADD = 176,
G_FSUB = 177,
G_FMUL = 178,
G_FMA = 179,
G_FMAD = 180,
G_FDIV = 181,
G_FREM = 182,
G_FPOW = 183,
G_FPOWI = 184,
G_FEXP = 185,
G_FEXP2 = 186,
G_FEXP10 = 187,
G_FLOG = 188,
G_FLOG2 = 189,
G_FLOG10 = 190,
G_FLDEXP = 191,
G_FFREXP = 192,
G_FNEG = 193,
G_FPEXT = 194,
G_FPTRUNC = 195,
G_FPTOSI = 196,
G_FPTOUI = 197,
G_SITOFP = 198,
G_UITOFP = 199,
G_FPTOSI_SAT = 200,
G_FPTOUI_SAT = 201,
G_FABS = 202,
G_FCOPYSIGN = 203,
G_IS_FPCLASS = 204,
G_FCANONICALIZE = 205,
G_FMINNUM = 206,
G_FMAXNUM = 207,
G_FMINNUM_IEEE = 208,
G_FMAXNUM_IEEE = 209,
G_FMINIMUM = 210,
G_FMAXIMUM = 211,
G_GET_FPENV = 212,
G_SET_FPENV = 213,
G_RESET_FPENV = 214,
G_GET_FPMODE = 215,
G_SET_FPMODE = 216,
G_RESET_FPMODE = 217,
G_PTR_ADD = 218,
G_PTRMASK = 219,
G_SMIN = 220,
G_SMAX = 221,
G_UMIN = 222,
G_UMAX = 223,
G_ABS = 224,
G_LROUND = 225,
G_LLROUND = 226,
G_BR = 227,
G_BRJT = 228,
G_VSCALE = 229,
G_INSERT_SUBVECTOR = 230,
G_EXTRACT_SUBVECTOR = 231,
G_INSERT_VECTOR_ELT = 232,
G_EXTRACT_VECTOR_ELT = 233,
G_SHUFFLE_VECTOR = 234,
G_SPLAT_VECTOR = 235,
G_VECTOR_COMPRESS = 236,
G_CTTZ = 237,
G_CTTZ_ZERO_UNDEF = 238,
G_CTLZ = 239,
G_CTLZ_ZERO_UNDEF = 240,
G_CTPOP = 241,
G_BSWAP = 242,
G_BITREVERSE = 243,
G_FCEIL = 244,
G_FCOS = 245,
G_FSIN = 246,
G_FTAN = 247,
G_FACOS = 248,
G_FASIN = 249,
G_FATAN = 250,
G_FATAN2 = 251,
G_FCOSH = 252,
G_FSINH = 253,
G_FTANH = 254,
G_FSQRT = 255,
G_FFLOOR = 256,
G_FRINT = 257,
G_FNEARBYINT = 258,
G_ADDRSPACE_CAST = 259,
G_BLOCK_ADDR = 260,
G_JUMP_TABLE = 261,
G_DYN_STACKALLOC = 262,
G_STACKSAVE = 263,
G_STACKRESTORE = 264,
G_STRICT_FADD = 265,
G_STRICT_FSUB = 266,
G_STRICT_FMUL = 267,
G_STRICT_FDIV = 268,
G_STRICT_FREM = 269,
G_STRICT_FMA = 270,
G_STRICT_FSQRT = 271,
G_STRICT_FLDEXP = 272,
G_READ_REGISTER = 273,
G_WRITE_REGISTER = 274,
G_MEMCPY = 275,
G_MEMCPY_INLINE = 276,
G_MEMMOVE = 277,
G_MEMSET = 278,
G_BZERO = 279,
G_TRAP = 280,
G_DEBUGTRAP = 281,
G_UBSANTRAP = 282,
G_VECREDUCE_SEQ_FADD = 283,
G_VECREDUCE_SEQ_FMUL = 284,
G_VECREDUCE_FADD = 285,
G_VECREDUCE_FMUL = 286,
G_VECREDUCE_FMAX = 287,
G_VECREDUCE_FMIN = 288,
G_VECREDUCE_FMAXIMUM = 289,
G_VECREDUCE_FMINIMUM = 290,
G_VECREDUCE_ADD = 291,
G_VECREDUCE_MUL = 292,
G_VECREDUCE_AND = 293,
G_VECREDUCE_OR = 294,
G_VECREDUCE_XOR = 295,
G_VECREDUCE_SMAX = 296,
G_VECREDUCE_SMIN = 297,
G_VECREDUCE_UMAX = 298,
G_VECREDUCE_UMIN = 299,
G_SBFX = 300,
G_UBFX = 301,
ADJCALLSTACKDOWN = 302,
ADJCALLSTACKUP = 303,
BR_JT = 304,
BR_JT32 = 305,
EH_RETURN = 306,
FRAME_TO_ARGS_OFFSET = 307,
LDAWFI = 308,
LDWFI = 309,
SELECT_CC = 310,
STWFI = 311,
ADD_2rus = 312,
ADD_3r = 313,
ANDNOT_2r = 314,
AND_3r = 315,
ASHR_l2rus = 316,
ASHR_l3r = 317,
BAU_1r = 318,
BITREV_l2r = 319,
BLACP_lu10 = 320,
BLACP_u10 = 321,
BLAT_lu6 = 322,
BLAT_u6 = 323,
BLA_1r = 324,
BLRB_lu10 = 325,
BLRB_u10 = 326,
BLRF_lu10 = 327,
BLRF_u10 = 328,
BRBF_lru6 = 329,
BRBF_ru6 = 330,
BRBT_lru6 = 331,
BRBT_ru6 = 332,
BRBU_lu6 = 333,
BRBU_u6 = 334,
BRFF_lru6 = 335,
BRFF_ru6 = 336,
BRFT_lru6 = 337,
BRFT_ru6 = 338,
BRFU_lu6 = 339,
BRFU_u6 = 340,
BRU_1r = 341,
BYTEREV_l2r = 342,
CHKCT_2r = 343,
CHKCT_rus = 344,
CLRE_0R = 345,
CLRPT_1R = 346,
CLRSR_branch_lu6 = 347,
CLRSR_branch_u6 = 348,
CLRSR_lu6 = 349,
CLRSR_u6 = 350,
CLZ_l2r = 351,
CRC8_l4r = 352,
CRC_l3r = 353,
DCALL_0R = 354,
DENTSP_0R = 355,
DGETREG_1r = 356,
DIVS_l3r = 357,
DIVU_l3r = 358,
DRESTSP_0R = 359,
DRET_0R = 360,
ECALLF_1r = 361,
ECALLT_1r = 362,
EDU_1r = 363,
EEF_2r = 364,
EET_2r = 365,
EEU_1r = 366,
ENDIN_2r = 367,
ENTSP_lu6 = 368,
ENTSP_u6 = 369,
EQ_2rus = 370,
EQ_3r = 371,
EXTDP_lu6 = 372,
EXTDP_u6 = 373,
EXTSP_lu6 = 374,
EXTSP_u6 = 375,
FREER_1r = 376,
FREET_0R = 377,
GETD_l2r = 378,
GETED_0R = 379,
GETET_0R = 380,
GETID_0R = 381,
GETKEP_0R = 382,
GETKSP_0R = 383,
GETN_l2r = 384,
GETPS_l2r = 385,
GETR_rus = 386,
GETSR_lu6 = 387,
GETSR_u6 = 388,
GETST_2r = 389,
GETTS_2r = 390,
INCT_2r = 391,
INITCP_2r = 392,
INITDP_2r = 393,
INITLR_l2r = 394,
INITPC_2r = 395,
INITSP_2r = 396,
INPW_l2rus = 397,
INSHR_2r = 398,
INT_2r = 399,
IN_2r = 400,
KCALL_1r = 401,
KCALL_lu6 = 402,
KCALL_u6 = 403,
KENTSP_lu6 = 404,
KENTSP_u6 = 405,
KRESTSP_lu6 = 406,
KRESTSP_u6 = 407,
KRET_0R = 408,
LADD_l5r = 409,
LD16S_3r = 410,
LD8U_3r = 411,
LDA16B_l3r = 412,
LDA16F_l3r = 413,
LDAPB_lu10 = 414,
LDAPB_u10 = 415,
LDAPF_lu10 = 416,
LDAPF_lu10_ba = 417,
LDAPF_u10 = 418,
LDAWB_l2rus = 419,
LDAWB_l3r = 420,
LDAWCP_lu6 = 421,
LDAWCP_u6 = 422,
LDAWDP_lru6 = 423,
LDAWDP_ru6 = 424,
LDAWF_l2rus = 425,
LDAWF_l3r = 426,
LDAWSP_lru6 = 427,
LDAWSP_ru6 = 428,
LDC_lru6 = 429,
LDC_ru6 = 430,
LDET_0R = 431,
LDIVU_l5r = 432,
LDSED_0R = 433,
LDSPC_0R = 434,
LDSSR_0R = 435,
LDWCP_lru6 = 436,
LDWCP_lu10 = 437,
LDWCP_ru6 = 438,
LDWCP_u10 = 439,
LDWDP_lru6 = 440,
LDWDP_ru6 = 441,
LDWSP_lru6 = 442,
LDWSP_ru6 = 443,
LDW_2rus = 444,
LDW_3r = 445,
LMUL_l6r = 446,
LSS_3r = 447,
LSUB_l5r = 448,
LSU_3r = 449,
MACCS_l4r = 450,
MACCU_l4r = 451,
MJOIN_1r = 452,
MKMSK_2r = 453,
MKMSK_rus = 454,
MSYNC_1r = 455,
MUL_l3r = 456,
NEG = 457,
NOT = 458,
OR_3r = 459,
OUTCT_2r = 460,
OUTCT_rus = 461,
OUTPW_l2rus = 462,
OUTSHR_2r = 463,
OUTT_2r = 464,
OUT_2r = 465,
PEEK_2r = 466,
REMS_l3r = 467,
REMU_l3r = 468,
RETSP_lu6 = 469,
RETSP_u6 = 470,
SETCLK_l2r = 471,
SETCP_1r = 472,
SETC_l2r = 473,
SETC_lru6 = 474,
SETC_ru6 = 475,
SETDP_1r = 476,
SETD_2r = 477,
SETEV_1r = 478,
SETKEP_0R = 479,
SETN_l2r = 480,
SETPSC_2r = 481,
SETPS_l2r = 482,
SETPT_2r = 483,
SETRDY_l2r = 484,
SETSP_1r = 485,
SETSR_branch_lu6 = 486,
SETSR_branch_u6 = 487,
SETSR_lu6 = 488,
SETSR_u6 = 489,
SETTW_l2r = 490,
SETV_1r = 491,
SEXT_2r = 492,
SEXT_rus = 493,
SHL_2rus = 494,
SHL_3r = 495,
SHR_2rus = 496,
SHR_3r = 497,
SSYNC_0r = 498,
ST16_l3r = 499,
ST8_l3r = 500,
STET_0R = 501,
STSED_0R = 502,
STSPC_0R = 503,
STSSR_0R = 504,
STWDP_lru6 = 505,
STWDP_ru6 = 506,
STWSP_lru6 = 507,
STWSP_ru6 = 508,
STW_2rus = 509,
STW_l3r = 510,
SUB_2rus = 511,
SUB_3r = 512,
SYNCR_1r = 513,
TESTCT_2r = 514,
TESTLCL_l2r = 515,
TESTWCT_2r = 516,
TSETMR_2r = 517,
TSETR_3r = 518,
TSTART_1R = 519,
WAITEF_1R = 520,
WAITET_1R = 521,
WAITEU_0R = 522,
XOR_l3r = 523,
ZEXT_2r = 524,
ZEXT_rus = 525,
INSTRUCTION_LIST_END = 526
};
}
}
#endif
#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM
namespace llvm {
namespace XCore {
namespace Sched {
enum {
NoInstrModel = 0,
SCHED_LIST_END = 1
};
}
}
}
#endif
#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
namespace llvm {
struct XCoreInstrTable {
MCInstrDesc Insts[526];
static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
MCOperandInfo OperandInfo[213];
static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
MCPhysReg ImplicitOps[11];
};
}
#endif
#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC
namespace llvm {
static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
static constexpr unsigned XCoreImpOpBase = sizeof XCoreInstrTable::OperandInfo / (sizeof(MCPhysReg));
extern const XCoreInstrTable XCoreDescs = {
{
{ 525, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 205, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 524, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 523, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 522, 0, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 521, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 520, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 519, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 518, 3, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 210, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 517, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 208, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 516, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 515, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 514, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 513, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 512, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 511, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 510, 3, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 509, 3, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 508, 2, 0, 2, 0, 1, 0, XCoreImpOpBase + 10, 191, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 507, 2, 0, 4, 0, 1, 0, XCoreImpOpBase + 10, 191, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 506, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 191, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 505, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 191, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 504, 0, 0, 2, 0, 1, 0, XCoreImpOpBase + 10, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 503, 0, 0, 2, 0, 1, 0, XCoreImpOpBase + 10, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 502, 0, 0, 2, 0, 1, 0, XCoreImpOpBase + 10, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 501, 0, 0, 2, 0, 1, 0, XCoreImpOpBase + 10, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 500, 3, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 499, 3, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 498, 0, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 497, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 496, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 495, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 494, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 493, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 205, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 492, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 491, 1, 0, 2, 0, 1, 0, XCoreImpOpBase + 9, 156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 490, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 489, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 488, 1, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 487, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 486, 1, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 485, 1, 0, 2, 0, 0, 1, XCoreImpOpBase + 10, 156, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 484, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 483, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 482, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 481, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 480, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 479, 0, 0, 2, 0, 1, 0, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 478, 1, 0, 2, 0, 1, 0, XCoreImpOpBase + 9, 156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 477, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 476, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 475, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 474, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 473, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 472, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 471, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 470, 1, 0, 2, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 469, 1, 0, 4, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 468, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 467, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 466, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 465, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 464, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 463, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 170, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 462, 3, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 461, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 460, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 459, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 458, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 457, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 456, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 455, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 454, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 175, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 453, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 452, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 451, 6, 2, 4, 0, 0, 0, XCoreImpOpBase + 0, 199, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 450, 6, 2, 4, 0, 0, 0, XCoreImpOpBase + 0, 199, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 449, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 448, 5, 2, 4, 0, 0, 0, XCoreImpOpBase + 0, 186, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 447, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 446, 6, 2, 4, 0, 0, 0, XCoreImpOpBase + 0, 193, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 445, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 444, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 443, 2, 1, 2, 0, 1, 0, XCoreImpOpBase + 10, 191, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 442, 2, 1, 4, 0, 1, 0, XCoreImpOpBase + 10, 191, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 441, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 191, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 440, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 191, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 439, 1, 0, 2, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 438, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 191, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 437, 1, 0, 4, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 436, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 191, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 435, 0, 0, 2, 0, 1, 0, XCoreImpOpBase + 10, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 434, 0, 0, 2, 0, 1, 0, XCoreImpOpBase + 10, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 433, 0, 0, 2, 0, 1, 0, XCoreImpOpBase + 10, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 432, 5, 2, 4, 0, 0, 0, XCoreImpOpBase + 0, 186, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 431, 0, 0, 2, 0, 1, 0, XCoreImpOpBase + 10, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 430, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 191, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 429, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 191, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 428, 2, 1, 2, 0, 1, 0, XCoreImpOpBase + 10, 191, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 427, 2, 1, 4, 0, 1, 0, XCoreImpOpBase + 10, 191, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 426, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 425, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 424, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 191, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 423, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 191, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 422, 1, 0, 2, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 421, 1, 0, 4, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 420, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 419, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 418, 1, 0, 2, 0, 0, 1, XCoreImpOpBase + 9, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 417, 1, 0, 4, 0, 0, 1, XCoreImpOpBase + 9, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 416, 1, 0, 4, 0, 0, 1, XCoreImpOpBase + 9, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 415, 1, 0, 2, 0, 0, 1, XCoreImpOpBase + 9, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 414, 1, 0, 4, 0, 0, 1, XCoreImpOpBase + 9, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 413, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 412, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 411, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 410, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 409, 5, 2, 4, 0, 0, 0, XCoreImpOpBase + 0, 186, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 408, 0, 0, 2, 0, 0, 1, XCoreImpOpBase + 10, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 407, 1, 0, 2, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 406, 1, 0, 4, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 405, 1, 0, 2, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 404, 1, 0, 4, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 403, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 402, 1, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 401, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 400, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 399, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 398, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 170, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 397, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 396, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 395, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 394, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 393, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 392, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 391, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 390, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 389, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 388, 1, 0, 2, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 387, 1, 0, 4, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 386, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 385, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 384, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 383, 0, 0, 2, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 382, 0, 0, 2, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 381, 0, 0, 2, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 380, 0, 0, 2, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 379, 0, 0, 2, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 378, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 377, 0, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 376, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 375, 1, 0, 2, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 374, 1, 0, 4, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 373, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 372, 1, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 371, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 370, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 369, 1, 0, 2, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 368, 1, 0, 4, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 367, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 366, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 365, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 364, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 363, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 362, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 361, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 360, 0, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 359, 0, 0, 2, 0, 0, 1, XCoreImpOpBase + 10, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 358, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 357, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 356, 1, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 355, 0, 0, 2, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 354, 0, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 353, 4, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 182, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 352, 5, 2, 4, 0, 0, 0, XCoreImpOpBase + 0, 177, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 351, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 350, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 349, 1, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 348, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 347, 1, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 346, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 345, 0, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 344, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 343, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 342, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 341, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 340, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 339, 1, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 338, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 173, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 337, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 173, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 336, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 173, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 335, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 173, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 334, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 333, 1, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 332, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 173, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 331, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 173, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 330, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 173, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 329, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 173, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 328, 1, 0, 2, 0, 1, 6, XCoreImpOpBase + 2, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 327, 1, 0, 4, 0, 1, 6, XCoreImpOpBase + 2, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 326, 1, 0, 2, 0, 1, 6, XCoreImpOpBase + 2, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 325, 1, 0, 4, 0, 1, 6, XCoreImpOpBase + 2, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 324, 1, 0, 2, 0, 1, 6, XCoreImpOpBase + 2, 156, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 323, 1, 0, 2, 0, 1, 0, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 322, 1, 0, 4, 0, 1, 0, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 321, 1, 0, 2, 0, 1, 6, XCoreImpOpBase + 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 320, 1, 0, 4, 0, 1, 6, XCoreImpOpBase + 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 319, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 318, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 317, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 316, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 315, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 314, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 313, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 312, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 311, 3, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 310, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 160, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 309, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 308, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 307, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 306, 2, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 305, 2, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 304, 2, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 303, 2, 0, 0, 0, 1, 1, XCoreImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 302, 2, 0, 0, 0, 1, 1, XCoreImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 301, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 300, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 299, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 298, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 297, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 296, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 295, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 294, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 293, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 292, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 291, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 290, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 289, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 288, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 287, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 286, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 285, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 284, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 283, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 282, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 281, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 280, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 279, 3, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 278, 4, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 277, 4, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 276, 3, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 275, 4, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 274, 2, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 273, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 272, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 271, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 270, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 269, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 268, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 267, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 266, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 265, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 264, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 263, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 262, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 261, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 260, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 259, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 258, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 257, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 256, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 255, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 254, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 253, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 252, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 251, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 250, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 249, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 248, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 247, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 246, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 245, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 244, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 243, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 242, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 241, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 240, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 239, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 238, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 237, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 236, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 235, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 234, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 233, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 232, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 231, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 230, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 229, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 228, 3, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 227, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 226, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 225, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 224, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 223, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 222, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 221, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 220, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 219, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 218, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 217, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 216, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 215, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 214, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 213, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 212, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 211, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 210, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 209, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 208, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 207, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 206, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 205, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 204, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 203, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 202, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 201, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 200, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 199, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 198, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 197, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 196, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 195, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 194, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 193, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 192, 3, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 191, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 190, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 189, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 188, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 187, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 186, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 185, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 184, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 183, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 182, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 181, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 180, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 179, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 178, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 177, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 176, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 175, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 174, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 173, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 172, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 171, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 170, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 169, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 168, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 167, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 166, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 165, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 164, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 163, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 162, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 161, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 160, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 159, 4, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 158, 4, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 157, 5, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 156, 4, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 155, 5, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 154, 4, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 153, 5, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 152, 4, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 151, 5, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 150, 4, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 149, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 148, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 147, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 146, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 145, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 144, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 143, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 142, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 141, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 140, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 139, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 138, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 137, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 136, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 135, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 134, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 133, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 132, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 131, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 130, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 129, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 128, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 127, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 126, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 125, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 124, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 123, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 122, 2, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 121, 4, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 94, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 120, 2, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 119, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 118, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 117, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 116, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 115, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 114, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 113, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 112, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 111, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 110, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 109, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 108, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 107, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 106, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 105, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 104, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 103, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 102, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 101, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 100, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 99, 5, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 98, 5, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 97, 2, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 96, 5, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 95, 5, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 94, 5, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 93, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 92, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 91, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 90, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 89, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 88, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 87, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 86, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 85, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 84, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 83, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 82, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 81, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 80, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 79, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 78, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 77, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 76, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 75, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 74, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 73, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 72, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 71, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 70, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 69, 5, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 68, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 67, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 66, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 65, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 64, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 63, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 62, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 61, 4, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 60, 4, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 59, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 58, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 57, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 56, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 55, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 54, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 53, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 52, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 51, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 50, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 49, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 48, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 47, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 46, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },
{ 45, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 44, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 43, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 42, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 41, 3, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 40, 2, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 39, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 38, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 37, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 36, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 35, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 34, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 33, 2, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 32, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 31, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 30, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 29, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 28, 6, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 27, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 26, 2, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 25, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 24, 4, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 23, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 22, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 21, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 20, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 19, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 18, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 17, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 16, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 15, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 14, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 13, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 12, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 11, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 10, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 9, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 8, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 7, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 6, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 5, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 4, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 3, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 2, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 1, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
{ 0, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },
}, {
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
{ -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
{ -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
{ -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
{ XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ XCore::RRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
{ -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
{ -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
}, {
XCore::SP, XCore::SP,
XCore::SP, XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R11, XCore::LR,
XCore::R11,
XCore::SP,
}
};
#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char XCoreInstrNameData[] = {
"G_FLOG10\0"
"G_FEXP10\0"
"LDAPB_u10\0"
"BLRB_u10\0"
"LDAPF_u10\0"
"BLRF_u10\0"
"BLACP_u10\0"
"LDWCP_u10\0"
"LDAPB_lu10\0"
"BLRB_lu10\0"
"LDAPF_lu10\0"
"BLRF_lu10\0"
"BLACP_lu10\0"
"LDWCP_lu10\0"
"BR_JT32\0"
"G_FLOG2\0"
"G_FATAN2\0"
"G_FEXP2\0"
"KCALL_u6\0"
"LDAWCP_u6\0"
"EXTDP_u6\0"
"RETSP_u6\0"
"KENTSP_u6\0"
"KRESTSP_u6\0"
"EXTSP_u6\0"
"CLRSR_u6\0"
"GETSR_u6\0"
"SETSR_u6\0"
"BLAT_u6\0"
"BRBU_u6\0"
"BRFU_u6\0"
"CLRSR_branch_u6\0"
"SETSR_branch_u6\0"
"KCALL_lu6\0"
"LDAWCP_lu6\0"
"EXTDP_lu6\0"
"RETSP_lu6\0"
"KENTSP_lu6\0"
"KRESTSP_lu6\0"
"EXTSP_lu6\0"
"CLRSR_lu6\0"
"GETSR_lu6\0"
"SETSR_lu6\0"
"BLAT_lu6\0"
"BRBU_lu6\0"
"BRFU_lu6\0"
"CLRSR_branch_lu6\0"
"SETSR_branch_lu6\0"
"LDC_ru6\0"
"SETC_ru6\0"
"BRBF_ru6\0"
"BRFF_ru6\0"
"LDWCP_ru6\0"
"LDAWDP_ru6\0"
"LDWDP_ru6\0"
"STWDP_ru6\0"
"LDAWSP_ru6\0"
"LDWSP_ru6\0"
"STWSP_ru6\0"
"BRBT_ru6\0"
"BRFT_ru6\0"
"LDC_lru6\0"
"SETC_lru6\0"
"BRBF_lru6\0"
"BRFF_lru6\0"
"LDWCP_lru6\0"
"LDAWDP_lru6\0"
"LDWDP_lru6\0"
"STWDP_lru6\0"
"LDAWSP_lru6\0"
"LDWSP_lru6\0"
"STWSP_lru6\0"
"BRBT_lru6\0"
"BRFT_lru6\0"
"G_FMA\0"
"G_STRICT_FMA\0"
"G_FSUB\0"
"G_STRICT_FSUB\0"
"G_ATOMICRMW_FSUB\0"
"G_SUB\0"
"G_ATOMICRMW_SUB\0"
"SELECT_CC\0"
"G_INTRINSIC\0"
"G_FPTRUNC\0"
"G_INTRINSIC_TRUNC\0"
"G_TRUNC\0"
"G_BUILD_VECTOR_TRUNC\0"
"G_DYN_STACKALLOC\0"
"G_FMAD\0"
"G_INDEXED_SEXTLOAD\0"
"G_SEXTLOAD\0"
"G_INDEXED_ZEXTLOAD\0"
"G_ZEXTLOAD\0"
"G_INDEXED_LOAD\0"
"G_LOAD\0"
"G_VECREDUCE_FADD\0"
"G_FADD\0"
"G_VECREDUCE_SEQ_FADD\0"
"G_STRICT_FADD\0"
"G_ATOMICRMW_FADD\0"
"G_VECREDUCE_ADD\0"
"G_ADD\0"
"G_PTR_ADD\0"
"G_ATOMICRMW_ADD\0"
"G_ATOMICRMW_NAND\0"
"G_VECREDUCE_AND\0"
"G_AND\0"
"G_ATOMICRMW_AND\0"
"LIFETIME_END\0"
"G_BRCOND\0"
"G_ATOMICRMW_USUB_COND\0"
"G_LLROUND\0"
"G_LROUND\0"
"G_INTRINSIC_ROUND\0"
"G_INTRINSIC_FPTRUNC_ROUND\0"
"LOAD_STACK_GUARD\0"
"PSEUDO_PROBE\0"
"G_SSUBE\0"
"G_USUBE\0"
"G_FENCE\0"
"ARITH_FENCE\0"
"REG_SEQUENCE\0"
"G_SADDE\0"
"G_UADDE\0"
"G_GET_FPMODE\0"
"G_RESET_FPMODE\0"
"G_SET_FPMODE\0"
"G_FMINNUM_IEEE\0"
"G_FMAXNUM_IEEE\0"
"G_VSCALE\0"
"G_JUMP_TABLE\0"
"BUNDLE\0"
"G_MEMCPY_INLINE\0"
"LOCAL_ESCAPE\0"
"G_STACKRESTORE\0"
"G_INDEXED_STORE\0"
"G_STORE\0"
"G_BITREVERSE\0"
"FAKE_USE\0"
"DBG_VALUE\0"
"G_GLOBAL_VALUE\0"
"G_PTRAUTH_GLOBAL_VALUE\0"
"CONVERGENCECTRL_GLUE\0"
"G_STACKSAVE\0"
"G_MEMMOVE\0"
"G_FREEZE\0"
"G_FCANONICALIZE\0"
"G_CTLZ_ZERO_UNDEF\0"
"G_CTTZ_ZERO_UNDEF\0"
"INIT_UNDEF\0"
"G_IMPLICIT_DEF\0"
"DBG_INSTR_REF\0"
"G_FNEG\0"
"EXTRACT_SUBREG\0"
"INSERT_SUBREG\0"
"G_SEXT_INREG\0"
"SUBREG_TO_REG\0"
"G_ATOMIC_CMPXCHG\0"
"G_ATOMICRMW_XCHG\0"
"G_FLOG\0"
"G_VAARG\0"
"PREALLOCATED_ARG\0"
"G_PREFETCH\0"
"G_SMULH\0"
"G_UMULH\0"
"G_FTANH\0"
"G_FSINH\0"
"G_FCOSH\0"
"LDAWFI\0"
"LDWFI\0"
"STWFI\0"
"DBG_PHI\0"
"G_FPTOSI\0"
"G_FPTOUI\0"
"G_FPOWI\0"
"G_PTRMASK\0"
"GC_LABEL\0"
"DBG_LABEL\0"
"EH_LABEL\0"
"ANNOTATION_LABEL\0"
"ICALL_BRANCH_FUNNEL\0"
"G_FSHL\0"
"G_SHL\0"
"G_FCEIL\0"
"PATCHABLE_TAIL_CALL\0"
"PATCHABLE_TYPED_EVENT_CALL\0"
"PATCHABLE_EVENT_CALL\0"
"FENTRY_CALL\0"
"KILL\0"
"G_CONSTANT_POOL\0"
"G_ROTL\0"
"G_VECREDUCE_FMUL\0"
"G_FMUL\0"
"G_VECREDUCE_SEQ_FMUL\0"
"G_STRICT_FMUL\0"
"G_VECREDUCE_MUL\0"
"G_MUL\0"
"G_FREM\0"
"G_STRICT_FREM\0"
"G_SREM\0"
"G_UREM\0"
"G_SDIVREM\0"
"G_UDIVREM\0"
"INLINEASM\0"
"G_VECREDUCE_FMINIMUM\0"
"G_FMINIMUM\0"
"G_VECREDUCE_FMAXIMUM\0"
"G_FMAXIMUM\0"
"G_FMINNUM\0"
"G_FMAXNUM\0"
"G_FATAN\0"
"G_FTAN\0"
"G_INTRINSIC_ROUNDEVEN\0"
"G_ASSERT_ALIGN\0"
"G_FCOPYSIGN\0"
"G_VECREDUCE_FMIN\0"
"G_ATOMICRMW_FMIN\0"
"G_VECREDUCE_SMIN\0"
"G_SMIN\0"
"G_VECREDUCE_UMIN\0"
"G_UMIN\0"
"G_ATOMICRMW_UMIN\0"
"G_ATOMICRMW_MIN\0"
"G_FASIN\0"
"G_FSIN\0"
"CFI_INSTRUCTION\0"
"EH_RETURN\0"
"ADJCALLSTACKDOWN\0"
"G_SSUBO\0"
"G_USUBO\0"
"G_SADDO\0"
"G_UADDO\0"
"JUMP_TABLE_DEBUG_INFO\0"
"G_SMULO\0"
"G_UMULO\0"
"G_BZERO\0"
"STACKMAP\0"
"G_DEBUGTRAP\0"
"G_UBSANTRAP\0"
"G_TRAP\0"
"G_ATOMICRMW_UDEC_WRAP\0"
"G_ATOMICRMW_UINC_WRAP\0"
"G_BSWAP\0"
"G_SITOFP\0"
"G_UITOFP\0"
"G_FCMP\0"
"G_ICMP\0"
"G_SCMP\0"
"G_UCMP\0"
"CONVERGENCECTRL_LOOP\0"
"G_CTPOP\0"
"PATCHABLE_OP\0"
"FAULTING_OP\0"
"ADJCALLSTACKUP\0"
"PREALLOCATED_SETUP\0"
"G_FLDEXP\0"
"G_STRICT_FLDEXP\0"
"G_FEXP\0"
"G_FFREXP\0"
"LDSPC_0R\0"
"STSPC_0R\0"
"LDSED_0R\0"
"STSED_0R\0"
"GETED_0R\0"
"GETID_0R\0"
"CLRE_0R\0"
"DCALL_0R\0"
"GETKEP_0R\0"
"SETKEP_0R\0"
"GETKSP_0R\0"
"DENTSP_0R\0"
"DRESTSP_0R\0"
"LDSSR_0R\0"
"STSSR_0R\0"
"LDET_0R\0"
"FREET_0R\0"
"DRET_0R\0"
"KRET_0R\0"
"GETET_0R\0"
"STET_0R\0"
"WAITEU_0R\0"
"WAITEF_1R\0"
"WAITET_1R\0"
"CLRPT_1R\0"
"TSTART_1R\0"
"G_BR\0"
"INLINEASM_BR\0"
"G_BLOCK_ADDR\0"
"MEMBARRIER\0"
"G_CONSTANT_FOLD_BARRIER\0"
"PATCHABLE_FUNCTION_ENTER\0"
"G_READCYCLECOUNTER\0"
"G_READSTEADYCOUNTER\0"
"G_READ_REGISTER\0"
"G_WRITE_REGISTER\0"
"G_ASHR\0"
"G_FSHR\0"
"G_LSHR\0"
"CONVERGENCECTRL_ANCHOR\0"
"G_FFLOOR\0"
"G_EXTRACT_SUBVECTOR\0"
"G_INSERT_SUBVECTOR\0"
"G_BUILD_VECTOR\0"
"G_SHUFFLE_VECTOR\0"
"G_SPLAT_VECTOR\0"
"G_VECREDUCE_XOR\0"
"G_XOR\0"
"G_ATOMICRMW_XOR\0"
"G_VECREDUCE_OR\0"
"G_OR\0"
"G_ATOMICRMW_OR\0"
"G_ROTR\0"
"G_INTTOPTR\0"
"G_FABS\0"
"G_ABS\0"
"G_UNMERGE_VALUES\0"
"G_MERGE_VALUES\0"
"G_FACOS\0"
"G_FCOS\0"
"G_CONCAT_VECTORS\0"
"COPY_TO_REGCLASS\0"
"G_IS_FPCLASS\0"
"G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
"G_VECTOR_COMPRESS\0"
"G_INTRINSIC_W_SIDE_EFFECTS\0"
"G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
"G_SSUBSAT\0"
"G_USUBSAT\0"
"G_SADDSAT\0"
"G_UADDSAT\0"
"G_SSHLSAT\0"
"G_USHLSAT\0"
"G_SMULFIXSAT\0"
"G_UMULFIXSAT\0"
"G_SDIVFIXSAT\0"
"G_UDIVFIXSAT\0"
"G_ATOMICRMW_USUB_SAT\0"
"G_FPTOSI_SAT\0"
"G_FPTOUI_SAT\0"
"G_EXTRACT\0"
"G_SELECT\0"
"G_BRINDIRECT\0"
"PATCHABLE_RET\0"
"FRAME_TO_ARGS_OFFSET\0"
"G_MEMSET\0"
"PATCHABLE_FUNCTION_EXIT\0"
"G_BRJT\0"
"BR_JT\0"
"G_EXTRACT_VECTOR_ELT\0"
"G_INSERT_VECTOR_ELT\0"
"G_FCONSTANT\0"
"G_CONSTANT\0"
"G_INTRINSIC_CONVERGENT\0"
"STATEPOINT\0"
"PATCHPOINT\0"
"G_PTRTOINT\0"
"G_FRINT\0"
"G_INTRINSIC_LLRINT\0"
"G_INTRINSIC_LRINT\0"
"G_FNEARBYINT\0"
"NOT\0"
"G_VASTART\0"
"LIFETIME_START\0"
"G_INVOKE_REGION_START\0"
"G_INSERT\0"
"G_FSQRT\0"
"G_STRICT_FSQRT\0"
"G_BITCAST\0"
"G_ADDRSPACE_CAST\0"
"DBG_VALUE_LIST\0"
"G_FPEXT\0"
"G_SEXT\0"
"G_ASSERT_SEXT\0"
"G_ANYEXT\0"
"G_ZEXT\0"
"G_ASSERT_ZEXT\0"
"G_FDIV\0"
"G_STRICT_FDIV\0"
"G_SDIV\0"
"G_UDIV\0"
"G_GET_FPENV\0"
"G_RESET_FPENV\0"
"G_SET_FPENV\0"
"G_FPOW\0"
"G_VECREDUCE_FMAX\0"
"G_ATOMICRMW_FMAX\0"
"G_VECREDUCE_SMAX\0"
"G_SMAX\0"
"G_VECREDUCE_UMAX\0"
"G_UMAX\0"
"G_ATOMICRMW_UMAX\0"
"G_ATOMICRMW_MAX\0"
"G_FRAME_INDEX\0"
"G_SBFX\0"
"G_UBFX\0"
"G_SMULFIX\0"
"G_UMULFIX\0"
"G_SDIVFIX\0"
"G_UDIVFIX\0"
"G_MEMCPY\0"
"COPY\0"
"CONVERGENCECTRL_ENTRY\0"
"G_CTLZ\0"
"G_CTTZ\0"
"LDAPF_lu10_ba\0"
"SSYNC_0r\0"
"BLA_1r\0"
"MSYNC_1r\0"
"ECALLF_1r\0"
"DGETREG_1r\0"
"KCALL_1r\0"
"MJOIN_1r\0"
"SETCP_1r\0"
"SETDP_1r\0"
"SETSP_1r\0"
"SYNCR_1r\0"
"FREER_1r\0"
"ECALLT_1r\0"
"BAU_1r\0"
"EDU_1r\0"
"EEU_1r\0"
"BRU_1r\0"
"SETEV_1r\0"
"SETV_1r\0"
"INITPC_2r\0"
"SETPSC_2r\0"
"SETD_2r\0"
"EEF_2r\0"
"PEEK_2r\0"
"MKMSK_2r\0"
"ENDIN_2r\0"
"INITCP_2r\0"
"INITDP_2r\0"
"INITSP_2r\0"
"INSHR_2r\0"
"OUTSHR_2r\0"
"TSETMR_2r\0"
"GETTS_2r\0"
"CHKCT_2r\0"
"INCT_2r\0"
"TESTCT_2r\0"
"OUTCT_2r\0"
"TESTWCT_2r\0"
"EET_2r\0"
"INT_2r\0"
"ANDNOT_2r\0"
"SETPT_2r\0"
"GETST_2r\0"
"OUTT_2r\0"
"OUT_2r\0"
"SEXT_2r\0"
"ZEXT_2r\0"
"SETC_l2r\0"
"GETD_l2r\0"
"SETCLK_l2r\0"
"TESTLCL_l2r\0"
"GETN_l2r\0"
"SETN_l2r\0"
"INITLR_l2r\0"
"GETPS_l2r\0"
"SETPS_l2r\0"
"BYTEREV_l2r\0"
"BITREV_l2r\0"
"SETTW_l2r\0"
"SETRDY_l2r\0"
"CLZ_l2r\0"
"SUB_3r\0"
"ADD_3r\0"
"AND_3r\0"
"SHL_3r\0"
"EQ_3r\0"
"SHR_3r\0"
"OR_3r\0"
"TSETR_3r\0"
"LD16S_3r\0"
"LSS_3r\0"
"LD8U_3r\0"
"LSU_3r\0"
"LDW_3r\0"
"ST16_l3r\0"
"ST8_l3r\0"
"LDA16B_l3r\0"
"LDAWB_l3r\0"
"CRC_l3r\0"
"LDA16F_l3r\0"
"LDAWF_l3r\0"
"MUL_l3r\0"
"ASHR_l3r\0"
"XOR_l3r\0"
"REMS_l3r\0"
"DIVS_l3r\0"
"REMU_l3r\0"
"DIVU_l3r\0"
"STW_l3r\0"
"CRC8_l4r\0"
"MACCS_l4r\0"
"MACCU_l4r\0"
"LSUB_l5r\0"
"LADD_l5r\0"
"LDIVU_l5r\0"
"LMUL_l6r\0"
"SUB_2rus\0"
"ADD_2rus\0"
"SHL_2rus\0"
"EQ_2rus\0"
"SHR_2rus\0"
"LDW_2rus\0"
"STW_2rus\0"
"LDAWB_l2rus\0"
"LDAWF_l2rus\0"
"ASHR_l2rus\0"
"INPW_l2rus\0"
"OUTPW_l2rus\0"
"MKMSK_rus\0"
"GETR_rus\0"
"CHKCT_rus\0"
"OUTCT_rus\0"
"SEXT_rus\0"
"ZEXT_rus\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif
extern const unsigned XCoreInstrNameIndices[] = {
1981U, 2351U, 3271U, 2639U, 2040U, 2021U, 2049U, 2187U,
1785U, 1800U, 1751U, 1738U, 1827U, 3736U, 1586U, 4439U,
1764U, 1977U, 2030U, 1367U, 4785U, 1489U, 4343U, 1194U,
1318U, 1355U, 2760U, 2175U, 4249U, 1301U, 2967U, 1890U,
4238U, 1512U, 2940U, 2927U, 3332U, 4070U, 4114U, 2107U,
2154U, 2127U, 2066U, 1577U, 3297U, 2714U, 4790U, 3450U,
2898U, 1634U, 4469U, 4499U, 2482U, 1107U, 808U, 2290U,
4534U, 4541U, 2317U, 2324U, 2331U, 2341U, 1172U, 3621U,
3584U, 1749U, 1979U, 4708U, 1596U, 1611U, 2192U, 4038U,
3672U, 4380U, 3689U, 3521U, 888U, 3719U, 4260U, 3648U,
4412U, 1677U, 3308U, 1275U, 862U, 1257U, 4298U, 4279U,
2460U, 3357U, 3376U, 1008U, 952U, 982U, 993U, 933U,
963U, 1556U, 1540U, 3766U, 1841U, 1858U, 1123U, 814U,
1178U, 1139U, 3626U, 3590U, 4692U, 2608U, 4675U, 2591U,
1074U, 791U, 4610U, 2526U, 2822U, 2800U, 1216U, 3991U,
1347U, 1907U, 1207U, 4057U, 4358U, 840U, 3814U, 4215U,
3841U, 4483U, 880U, 4204U, 4192U, 4333U, 1882U, 4462U,
1814U, 4492U, 2093U, 3443U, 3429U, 2086U, 3436U, 3641U,
2208U, 2877U, 2870U, 2884U, 2891U, 4048U, 2706U, 1388U,
2690U, 1339U, 2698U, 1380U, 2682U, 1331U, 2744U, 2736U,
1926U, 1918U, 3909U, 3899U, 3889U, 3879U, 3929U, 3919U,
4736U, 4746U, 3939U, 3952U, 4756U, 4766U, 3965U, 3978U,
1032U, 770U, 2232U, 751U, 926U, 4513U, 2296U, 4586U,
2003U, 3011U, 165U, 9U, 1875U, 148U, 0U, 2986U,
3018U, 1778U, 4454U, 852U, 1985U, 1994U, 2852U, 2861U,
4012U, 4025U, 3659U, 2497U, 3753U, 1686U, 2425U, 2435U,
1437U, 1452U, 2382U, 2414U, 4548U, 4574U, 4560U, 1396U,
1424U, 1409U, 1113U, 2011U, 2560U, 4644U, 2584U, 4668U,
3666U, 1248U, 1238U, 3266U, 4138U, 1467U, 3502U, 3482U,
4172U, 4151U, 3536U, 3553U, 3796U, 4819U, 1720U, 4812U,
1702U, 2919U, 2844U, 1564U, 2099U, 3712U, 2632U, 2453U,
3704U, 2624U, 2445U, 156U, 1950U, 1942U, 1934U, 4389U,
3473U, 4271U, 4316U, 4422U, 3284U, 1476U, 909U, 1655U,
1525U, 1060U, 777U, 2260U, 4520U, 2303U, 757U, 4397U,
2995U, 3396U, 3412U, 4776U, 1496U, 1667U, 4105U, 2752U,
2793U, 2769U, 2781U, 1039U, 2239U, 1015U, 2215U, 4593U,
2509U, 2393U, 2361U, 1091U, 2274U, 1156U, 3606U, 3568U,
4627U, 2543U, 4651U, 2567U, 4722U, 4729U, 2665U, 2952U,
4145U, 140U, 2655U, 4084U, 1958U, 1965U, 830U, 1971U,
5700U, 5402U, 5194U, 5409U, 5777U, 5564U, 4959U, 5355U,
118U, 56U, 427U, 267U, 4849U, 87U, 28U, 108U,
47U, 632U, 505U, 731U, 595U, 436U, 275U, 642U,
514U, 741U, 604U, 445U, 283U, 4980U, 5343U, 5133U,
5830U, 3081U, 3247U, 454U, 291U, 397U, 240U, 5387U,
5625U, 5527U, 3089U, 3128U, 4875U, 5590U, 5608U, 3138U,
3184U, 4865U, 4949U, 4966U, 5032U, 5180U, 4973U, 5056U,
365U, 211U, 5718U, 5423U, 344U, 192U, 387U, 231U,
4940U, 3175U, 5262U, 3063U, 3200U, 3072U, 3098U, 3118U,
5294U, 5323U, 5821U, 407U, 249U, 5213U, 5124U, 5142U,
5065U, 5075U, 5312U, 5004U, 5085U, 5788U, 5095U, 5187U,
5059U, 4886U, 323U, 173U, 364U, 210U, 375U, 220U,
3192U, 5663U, 5451U, 5467U, 5506U, 5535U, 76U, 18U,
97U, 4826U, 37U, 5753U, 5517U, 333U, 182U, 663U,
533U, 5765U, 5546U, 697U, 564U, 613U, 488U, 3167U,
5672U, 3045U, 3027U, 3149U, 652U, 129U, 523U, 66U,
675U, 544U, 709U, 575U, 5735U, 5482U, 5682U, 5460U,
5654U, 5475U, 5634U, 5644U, 4895U, 5047U, 5811U, 4856U,
5556U, 1781U, 4329U, 5436U, 5160U, 5840U, 5799U, 5104U,
5222U, 5230U, 5039U, 5581U, 5599U, 354U, 201U, 5271U,
4904U, 5253U, 622U, 496U, 4913U, 5024U, 4987U, 3108U,
5303U, 5014U, 5333U, 5204U, 5376U, 4922U, 471U, 307U,
417U, 258U, 5366U, 4996U, 5237U, 5850U, 5709U, 5416U,
5726U, 5429U, 4840U, 5489U, 5498U, 3209U, 3054U, 3036U,
3158U, 686U, 554U, 720U, 585U, 5744U, 5617U, 5691U,
5395U, 4931U, 5150U, 5282U, 5169U, 5114U, 5442U, 3256U,
3227U, 3237U, 3217U, 5573U, 5245U, 5859U,
};
static inline void InitXCoreMCInstrInfo(MCInstrInfo *II) {
II->InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, 526);
}
}
#endif
#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER
namespace llvm {
struct XCoreGenInstrInfo : public TargetInstrInfo { … };
}
#endif
#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS
#endif
#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS
#endif
#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR
namespace llvm {
extern const XCoreInstrTable XCoreDescs;
extern const unsigned XCoreInstrNameIndices[];
extern const char XCoreInstrNameData[];
XCoreGenInstrInfo::XCoreGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
: TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, 526);
}
}
#endif
#ifdef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_OPERAND_ENUM
namespace llvm {
namespace XCore {
namespace OpName {
enum {
OPERAND_LAST
};
}
}
}
#endif
#ifdef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_NAMED_OPS
namespace llvm {
namespace XCore {
LLVM_READONLY
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
return -1;
}
}
}
#endif
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
namespace llvm {
namespace XCore {
namespace OpTypes {
enum OperandType {
InlineJT = 0,
InlineJT32 = 1,
MEMii = 2,
brtarget = 3,
brtarget_neg = 4,
f32imm = 5,
f64imm = 6,
i1imm = 7,
i8imm = 8,
i16imm = 9,
i32imm = 10,
i64imm = 11,
pcrel_imm = 12,
pcrel_imm_neg = 13,
ptype0 = 14,
ptype1 = 15,
ptype2 = 16,
ptype3 = 17,
ptype4 = 18,
ptype5 = 19,
type0 = 20,
type1 = 21,
type2 = 22,
type3 = 23,
type4 = 24,
type5 = 25,
untyped_imm_0 = 26,
GRRegs = 27,
RRegs = 28,
OPERAND_TYPE_LIST_END
};
}
}
}
#endif
#ifdef GET_INSTRINFO_OPERAND_TYPE
#undef GET_INSTRINFO_OPERAND_TYPE
namespace llvm {
namespace XCore {
LLVM_READONLY
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
static const uint16_t Offsets[] = {
0,
1,
1,
1,
2,
3,
4,
5,
5,
8,
12,
13,
14,
18,
21,
21,
21,
21,
21,
22,
24,
26,
26,
27,
28,
32,
34,
36,
36,
42,
43,
44,
47,
47,
49,
50,
50,
50,
50,
50,
50,
52,
55,
55,
55,
55,
56,
57,
58,
60,
61,
64,
67,
70,
73,
76,
79,
82,
85,
88,
91,
95,
99,
102,
105,
108,
109,
110,
112,
114,
119,
121,
124,
126,
130,
132,
134,
136,
138,
140,
142,
144,
146,
148,
151,
153,
155,
157,
159,
161,
162,
163,
165,
167,
169,
174,
179,
184,
186,
191,
196,
200,
203,
206,
209,
212,
215,
218,
221,
224,
227,
230,
233,
236,
239,
242,
245,
248,
251,
254,
257,
259,
263,
265,
266,
266,
267,
268,
269,
270,
272,
274,
276,
278,
279,
282,
284,
287,
289,
292,
295,
298,
302,
306,
309,
312,
316,
320,
323,
326,
330,
334,
339,
343,
348,
352,
357,
361,
366,
370,
374,
377,
380,
383,
386,
389,
392,
395,
398,
402,
406,
410,
414,
418,
422,
426,
430,
433,
436,
439,
443,
447,
450,
453,
456,
459,
461,
463,
465,
467,
469,
471,
474,
477,
479,
481,
483,
485,
487,
489,
491,
493,
495,
497,
500,
503,
505,
508,
511,
514,
517,
520,
523,
524,
525,
525,
526,
527,
527,
530,
533,
536,
539,
542,
545,
547,
549,
551,
552,
555,
557,
561,
564,
568,
571,
575,
577,
581,
583,
585,
587,
589,
591,
593,
595,
597,
599,
601,
603,
605,
607,
609,
612,
614,
616,
618,
620,
622,
624,
626,
628,
630,
632,
635,
636,
637,
640,
643,
646,
649,
652,
656,
658,
661,
663,
665,
669,
672,
676,
680,
683,
683,
683,
684,
687,
690,
692,
694,
696,
698,
700,
702,
704,
706,
708,
710,
712,
714,
716,
718,
720,
724,
728,
730,
732,
734,
736,
738,
739,
742,
745,
749,
752,
755,
758,
761,
764,
767,
770,
771,
773,
774,
775,
776,
777,
778,
779,
780,
781,
782,
784,
786,
788,
790,
791,
792,
794,
796,
798,
800,
801,
802,
803,
805,
807,
809,
809,
810,
811,
812,
813,
814,
816,
821,
825,
825,
825,
826,
829,
832,
832,
832,
833,
834,
835,
837,
839,
840,
842,
843,
844,
847,
850,
851,
852,
853,
854,
855,
855,
857,
857,
857,
857,
857,
857,
859,
861,
863,
864,
865,
867,
869,
871,
873,
875,
877,
879,
881,
884,
887,
889,
891,
892,
893,
894,
895,
896,
897,
898,
898,
903,
906,
909,
912,
915,
916,
917,
918,
919,
920,
923,
926,
927,
928,
930,
932,
935,
938,
940,
942,
944,
946,
946,
951,
951,
951,
951,
953,
954,
956,
957,
959,
961,
963,
965,
968,
971,
977,
980,
985,
988,
994,
1000,
1001,
1003,
1005,
1006,
1009,
1011,
1013,
1016,
1018,
1020,
1023,
1026,
1028,
1030,
1032,
1035,
1038,
1039,
1040,
1042,
1043,
1045,
1047,
1049,
1050,
1052,
1053,
1053,
1055,
1057,
1059,
1061,
1063,
1064,
1065,
1066,
1067,
1068,
1070,
1071,
1074,
1077,
1080,
1083,
1086,
1089,
1089,
1092,
1095,
1095,
1095,
1095,
1095,
1097,
1099,
1101,
1103,
1106,
1109,
1112,
1115,
1116,
1118,
1120,
1122,
1124,
1127,
1128,
1129,
1130,
1130,
1133,
1136,
};
using namespace OpTypes;
static const int8_t OpcodeOperandTypes[] = {
-1,
i32imm,
i32imm,
i32imm,
i32imm,
-1, -1, i32imm,
-1, -1, -1, i32imm,
-1,
-1,
-1, -1, -1, i32imm,
-1, -1, i32imm,
-1,
-1, -1,
-1, -1,
i32imm,
i32imm,
i64imm, i64imm, i8imm, i32imm,
-1, -1,
i64imm, i32imm,
-1, i64imm, i32imm, -1, i32imm, i32imm,
-1,
i32imm,
-1, i32imm, i32imm,
-1, i32imm,
-1,
-1, -1,
-1, -1, -1,
i64imm,
-1,
-1,
-1, -1,
-1,
type0, type0, untyped_imm_0,
type0, type0, untyped_imm_0,
type0, type0, untyped_imm_0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0, type0,
type0, type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0,
type0,
type0, -1,
type0, -1,
type0, -1, i32imm, type1, i64imm,
type0, -1,
type0, type1, untyped_imm_0,
type0, type1,
type0, type0, type1, untyped_imm_0,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type0,
type0, type0,
type0, type1, i32imm,
type0, type0,
type0, type0,
type0, type1,
type0, type1,
type0, type0,
type0,
type0,
type0, ptype1,
type0, ptype1,
type0, ptype1,
type0, ptype1, ptype1, type2, -1,
type0, ptype1, ptype1, type2, -1,
type0, ptype1, ptype1, type2, -1,
type0, ptype1,
ptype0, type1, ptype0, ptype2, -1,
type0, type1, type2, type0, type0,
type0, ptype1, type0, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
type0, ptype1, type0,
i32imm, i32imm,
ptype0, i32imm, i32imm, i32imm,
type0, -1,
type0,
-1,
-1,
-1,
-1,
type0, type1,
type0, type1,
type0, -1,
type0, -1,
type0,
type0, type1, -1,
type0, type1,
type0, type0, untyped_imm_0,
type0, type1,
type0, type0, type1,
type0, type0, type1,
type0, type0, type1,
type0, type0, type0, type1,
type0, type0, type0, type1,
type0, type0, type1,
type0, type0, type1,
type0, -1, type1, type1,
type0, -1, type1, type1,
type0, type1, type1,
type0, type1, type1,
type0, type1, type0, type0,
type0, type1, type0, type0,
type0, type1, type0, type0, type1,
type0, type1, type0, type0,
type0, type1, type0, type0, type1,
type0, type1, type0, type0,
type0, type1, type0, type0, type1,
type0, type1, type0, type0,
type0, type1, type0, type0, type1,
type0, type1, type0, type0,
type0, type1, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type1,
type0, type0, type1,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0, untyped_imm_0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0, type0,
type0, type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type1,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0, type1,
type0, type1, type0,
type0, type0,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type0,
type0, type0, type1,
type0, type1, -1,
type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0,
type0,
type0,
type0,
ptype0, ptype0, type1,
ptype0, ptype0, type1,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0,
type0, type1,
type0, type1,
-1,
ptype0, -1, type1,
type0, -1,
type0, type0, type1, untyped_imm_0,
type0, type1, untyped_imm_0,
type0, type0, type1, type2,
type0, type1, type2,
type0, type1, type1, -1,
type0, type1,
type0, type0, type1, type0,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type0,
type0, type1,
type0, -1,
type0, -1,
ptype0, type1, i32imm,
ptype0,
ptype0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0,
type0, type0, type0, type0,
type0, type0,
type0, type0, type1,
type0, -1,
-1, type0,
ptype0, ptype1, type2, untyped_imm_0,
ptype0, ptype1, type2,
ptype0, ptype1, type2, untyped_imm_0,
ptype0, type1, type2, untyped_imm_0,
ptype0, type1, untyped_imm_0,
i8imm,
type0, type1, type2,
type0, type1, type2,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type1,
type0, type0, type1, type1,
type0, type0, type1, type1,
i32imm, i32imm,
i32imm, i32imm,
InlineJT, GRRegs,
InlineJT32, GRRegs,
GRRegs, GRRegs,
GRRegs,
GRRegs, i32imm, i32imm,
GRRegs, i32imm, i32imm,
GRRegs, GRRegs, GRRegs, GRRegs,
GRRegs, i32imm, i32imm,
GRRegs, GRRegs, i32imm,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, i32imm,
GRRegs, GRRegs, GRRegs,
GRRegs,
GRRegs, GRRegs,
i32imm,
i32imm,
i32imm,
i32imm,
GRRegs,
pcrel_imm_neg,
pcrel_imm_neg,
pcrel_imm,
pcrel_imm,
GRRegs, brtarget_neg,
GRRegs, brtarget_neg,
GRRegs, brtarget_neg,
GRRegs, brtarget_neg,
brtarget_neg,
brtarget_neg,
GRRegs, brtarget,
GRRegs, brtarget,
GRRegs, brtarget,
GRRegs, brtarget,
brtarget,
brtarget,
GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs, i32imm,
GRRegs,
i32imm,
i32imm,
i32imm,
i32imm,
GRRegs, GRRegs,
GRRegs, GRRegs, GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, GRRegs, GRRegs,
GRRegs,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, GRRegs,
GRRegs,
GRRegs,
GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs,
GRRegs, GRRegs,
i32imm,
i32imm,
GRRegs, GRRegs, i32imm,
GRRegs, GRRegs, GRRegs,
i32imm,
i32imm,
i32imm,
i32imm,
GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs, i32imm,
i32imm,
i32imm,
GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs, i32imm,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs,
i32imm,
i32imm,
i32imm,
i32imm,
i32imm,
i32imm,
GRRegs, GRRegs, GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, GRRegs,
pcrel_imm_neg,
pcrel_imm_neg,
pcrel_imm,
pcrel_imm,
pcrel_imm,
GRRegs, GRRegs, i32imm,
GRRegs, GRRegs, GRRegs,
i32imm,
i32imm,
RRegs, i32imm,
RRegs, i32imm,
GRRegs, GRRegs, i32imm,
GRRegs, GRRegs, GRRegs,
RRegs, i32imm,
RRegs, i32imm,
RRegs, i32imm,
RRegs, i32imm,
GRRegs, GRRegs, GRRegs, GRRegs, GRRegs,
RRegs, i32imm,
i32imm,
RRegs, i32imm,
i32imm,
RRegs, i32imm,
RRegs, i32imm,
RRegs, i32imm,
RRegs, i32imm,
GRRegs, GRRegs, i32imm,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, GRRegs,
GRRegs,
GRRegs, GRRegs,
GRRegs, i32imm,
GRRegs,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs, i32imm,
GRRegs, GRRegs, i32imm,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, GRRegs,
i32imm,
i32imm,
GRRegs, GRRegs,
GRRegs,
GRRegs, GRRegs,
GRRegs, i32imm,
GRRegs, i32imm,
GRRegs,
GRRegs, GRRegs,
GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs,
i32imm,
i32imm,
i32imm,
i32imm,
GRRegs, GRRegs,
GRRegs,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, i32imm,
GRRegs, GRRegs, i32imm,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, i32imm,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, GRRegs,
RRegs, i32imm,
RRegs, i32imm,
RRegs, i32imm,
RRegs, i32imm,
GRRegs, GRRegs, i32imm,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, i32imm,
GRRegs, GRRegs, GRRegs,
GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs,
GRRegs, GRRegs,
i32imm, GRRegs,
i32imm, GRRegs, GRRegs,
GRRegs,
GRRegs,
GRRegs,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, GRRegs,
GRRegs, GRRegs, i32imm,
};
return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
}
}
}
#endif
#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
namespace llvm {
namespace XCore {
LLVM_READONLY
static int getMemOperandSize(int OpType) {
switch (OpType) {
default: return 0;
}
}
}
}
#endif
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
namespace llvm {
namespace XCore {
LLVM_READONLY static unsigned
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
return LogicalOpIdx;
}
LLVM_READONLY static inline unsigned
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
auto S = 0U;
for (auto i = 0U; i < LogicalOpIdx; ++i)
S += getLogicalOperandSize(Opcode, i);
return S;
}
}
}
#endif
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
namespace llvm {
namespace XCore {
LLVM_READONLY static int
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
return -1;
}
}
}
#endif
#ifdef GET_INSTRINFO_MC_HELPER_DECLS
#undef GET_INSTRINFO_MC_HELPER_DECLS
namespace llvm {
class MCInst;
class FeatureBitset;
namespace XCore_MC {
void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
}
}
#endif
#ifdef GET_INSTRINFO_MC_HELPERS
#undef GET_INSTRINFO_MC_HELPERS
namespace llvm {
namespace XCore_MC {
}
}
#endif
#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
defined(GET_AVAILABLE_OPCODE_CHECKER)
#define GET_COMPUTE_FEATURES
#endif
#ifdef GET_COMPUTE_FEATURES
#undef GET_COMPUTE_FEATURES
namespace llvm {
namespace XCore_MC {
enum SubtargetFeatureBits : uint8_t {
};
inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
FeatureBitset Features;
return Features;
}
inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
enum : uint8_t {
CEFBS_None,
};
static constexpr FeatureBitset FeatureBitsets[] = {
{},
};
static constexpr uint8_t RequiredFeaturesRefs[] = {
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
CEFBS_None,
};
assert(Opcode < 526);
return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
}
}
}
#endif
#ifdef GET_AVAILABLE_OPCODE_CHECKER
#undef GET_AVAILABLE_OPCODE_CHECKER
namespace llvm {
namespace XCore_MC {
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
FeatureBitset MissingFeatures =
(AvailableFeatures & RequiredFeatures) ^
RequiredFeatures;
return !MissingFeatures.any();
}
}
}
#endif
#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
#undef ENABLE_INSTR_PREDICATE_VERIFIER
#include <sstream>
namespace llvm {
namespace XCore_MC {
#ifndef NDEBUG
static const char *SubtargetFeatureNames[] = {
nullptr
};
#endif
void verifyInstructionPredicates(
unsigned Opcode, const FeatureBitset &Features) {
#ifndef NDEBUG
FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
FeatureBitset MissingFeatures =
(AvailableFeatures & RequiredFeatures) ^
RequiredFeatures;
if (MissingFeatures.any()) {
std::ostringstream Msg;
Msg << "Attempting to emit " << &XCoreInstrNameData[XCoreInstrNameIndices[Opcode]]
<< " instruction but the ";
for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
if (MissingFeatures.test(i))
Msg << SubtargetFeatureNames[i] << " ";
Msg << "predicate(s) are not met";
report_fatal_error(Msg.str().c_str());
}
#endif
}
}
}
#endif