llvm/llvm/test/Transforms/PhaseOrdering/icmp-ashr-breaking-select-idiom.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
; RUN: opt -O1 -S < %s  | FileCheck %s

define i32 @testa(i32 %mul) {
; CHECK-LABEL: define range(i32 -65536, 32768) i32 @testa(
; CHECK-SAME: i32 [[MUL:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:    [[SHR:%.*]] = ashr i32 [[MUL]], 15
; CHECK-NEXT:    [[SPEC_SELECT_I:%.*]] = tail call i32 @llvm.smin.i32(i32 [[SHR]], i32 32767)
; CHECK-NEXT:    ret i32 [[SPEC_SELECT_I]]
;
  %shr = ashr i32 %mul, 15
  %cmp4.i = icmp sgt i32 %shr, 32767
  %switch.i = icmp ult i1 %cmp4.i, true
  %spec.select.i = select i1 %switch.i, i32 %shr, i32 32767
  ret i32 %spec.select.i
}

define i32 @testb(i32 %mul) {
; CHECK-LABEL: define range(i32 -128, 128) i32 @testb(
; CHECK-SAME: i32 [[MUL:%.*]]) local_unnamed_addr #[[ATTR0]] {
; CHECK-NEXT:    [[SHR102:%.*]] = ashr i32 [[MUL]], 7
; CHECK-NEXT:    [[TMP1:%.*]] = tail call i32 @llvm.smax.i32(i32 [[SHR102]], i32 -128)
; CHECK-NEXT:    [[SPEC_SELECT_I:%.*]] = tail call i32 @llvm.smin.i32(i32 [[TMP1]], i32 127)
; CHECK-NEXT:    ret i32 [[SPEC_SELECT_I]]
;
  %shr102 = ashr i32 %mul, 7
  %cmp4.i = icmp sgt i32 %shr102, 127
  %cmp6.i = icmp slt i32 %shr102, -128
  %retval.0.i = select i1 %cmp4.i, i32 127, i32 -128
  %cleanup.dest.slot.0.i = select i1 %cmp4.i, i1 true, i1 %cmp6.i
  %switch.i = icmp ult i1 %cleanup.dest.slot.0.i, true
  %spec.select.i = select i1 %switch.i, i32 %shr102, i32 %retval.0.i
  ret i32 %spec.select.i
}