modulo.ll | Explore in Territory

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -S -passes=instcombine | FileCheck %s

; PR21929
define i32 @modulo2(i32 %x) {
; CHECK-LABEL: @modulo2(
; CHECK-NEXT:    [[RET_I:%.*]] = and i32 [[X:%.*]], 1
; CHECK-NEXT:    ret i32 [[RET_I]]
;
  %rem.i = srem i32 %x, 2
  %cmp.i = icmp slt i32 %rem.i, 0
  %add.i = select i1 %cmp.i, i32 2, i32 0
  %ret.i = add nsw i32 %add.i, %rem.i
  ret i32 %ret.i
}

define <2 x i32> @modulo2_vec(<2 x i32> %x) {
; CHECK-LABEL: @modulo2_vec(
; CHECK-NEXT:    [[RET_I:%.*]] = and <2 x i32> [[X:%.*]], <i32 1, i32 1>
; CHECK-NEXT:    ret <2 x i32> [[RET_I]]
;
  %rem.i = srem <2 x i32> %x, <i32 2, i32 2>
  %cmp.i = icmp slt <2 x i32> %rem.i, zeroinitializer
  %add.i = select <2 x i1> %cmp.i, <2 x i32> <i32 2, i32 2>, <2 x i32> zeroinitializer
  %ret.i = add nsw <2 x i32> %add.i, %rem.i
  ret <2 x i32> %ret.i
}

define i32 @modulo3(i32 %x) {
; CHECK-LABEL: @modulo3(
; CHECK-NEXT:    [[REM_I:%.*]] = srem i32 [[X:%.*]], 3
; CHECK-NEXT:    [[CMP_I:%.*]] = icmp slt i32 [[REM_I]], 0
; CHECK-NEXT:    [[ADD_I:%.*]] = select i1 [[CMP_I]], i32 3, i32 0
; CHECK-NEXT:    [[RET_I:%.*]] = add nsw i32 [[ADD_I]], [[REM_I]]
; CHECK-NEXT:    ret i32 [[RET_I]]
;
  %rem.i = srem i32 %x, 3
  %cmp.i = icmp slt i32 %rem.i, 0
  %add.i = select i1 %cmp.i, i32 3, i32 0
  %ret.i = add nsw i32 %add.i, %rem.i
  ret i32 %ret.i
}

define <2 x i32> @modulo3_vec(<2 x i32> %x) {
; CHECK-LABEL: @modulo3_vec(
; CHECK-NEXT:    [[REM_I:%.*]] = srem <2 x i32> [[X:%.*]], <i32 3, i32 3>
; CHECK-NEXT:    [[CMP_I:%.*]] = icmp slt <2 x i32> [[REM_I]], zeroinitializer
; CHECK-NEXT:    [[ADD_I:%.*]] = select <2 x i1> [[CMP_I]], <2 x i32> <i32 3, i32 3>, <2 x i32> zeroinitializer
; CHECK-NEXT:    [[RET_I:%.*]] = add nsw <2 x i32> [[ADD_I]], [[REM_I]]
; CHECK-NEXT:    ret <2 x i32> [[RET_I]]
;
  %rem.i = srem <2 x i32> %x, <i32 3, i32 3>
  %cmp.i = icmp slt <2 x i32> %rem.i, zeroinitializer
  %add.i = select <2 x i1> %cmp.i, <2 x i32> <i32 3, i32 3>, <2 x i32> zeroinitializer
  %ret.i = add nsw <2 x i32> %add.i, %rem.i
  ret <2 x i32> %ret.i
}

define i32 @modulo4(i32 %x) {
; CHECK-LABEL: @modulo4(
; CHECK-NEXT:    [[RET_I:%.*]] = and i32 [[X:%.*]], 3
; CHECK-NEXT:    ret i32 [[RET_I]]
;
  %rem.i = srem i32 %x, 4
  %cmp.i = icmp slt i32 %rem.i, 0
  %add.i = select i1 %cmp.i, i32 4, i32 0
  %ret.i = add nsw i32 %add.i, %rem.i
  ret i32 %ret.i
}

define <2 x i32> @modulo4_vec(<2 x i32> %x) {
; CHECK-LABEL: @modulo4_vec(
; CHECK-NEXT:    [[RET_I:%.*]] = and <2 x i32> [[X:%.*]], <i32 3, i32 3>
; CHECK-NEXT:    ret <2 x i32> [[RET_I]]
;
  %rem.i = srem <2 x i32> %x, <i32 4, i32 4>
  %cmp.i = icmp slt <2 x i32> %rem.i, zeroinitializer
  %add.i = select <2 x i1> %cmp.i, <2 x i32> <i32 4, i32 4>, <2 x i32> zeroinitializer
  %ret.i = add nsw <2 x i32> %add.i, %rem.i
  ret <2 x i32> %ret.i
}

define i32 @modulo7(i32 %x) {
; CHECK-LABEL: @modulo7(
; CHECK-NEXT:    [[REM_I:%.*]] = srem i32 [[X:%.*]], 7
; CHECK-NEXT:    [[CMP_I:%.*]] = icmp slt i32 [[REM_I]], 0
; CHECK-NEXT:    [[ADD_I:%.*]] = select i1 [[CMP_I]], i32 7, i32 0
; CHECK-NEXT:    [[RET_I:%.*]] = add nsw i32 [[ADD_I]], [[REM_I]]
; CHECK-NEXT:    ret i32 [[RET_I]]
;
  %rem.i = srem i32 %x, 7
  %cmp.i = icmp slt i32 %rem.i, 0
  %add.i = select i1 %cmp.i, i32 7, i32 0
  %ret.i = add nsw i32 %add.i, %rem.i
  ret i32 %ret.i
}

define <2 x i32> @modulo7_vec(<2 x i32> %x) {
; CHECK-LABEL: @modulo7_vec(
; CHECK-NEXT:    [[REM_I:%.*]] = srem <2 x i32> [[X:%.*]], <i32 7, i32 7>
; CHECK-NEXT:    [[CMP_I:%.*]] = icmp slt <2 x i32> [[REM_I]], zeroinitializer
; CHECK-NEXT:    [[ADD_I:%.*]] = select <2 x i1> [[CMP_I]], <2 x i32> <i32 7, i32 7>, <2 x i32> zeroinitializer
; CHECK-NEXT:    [[RET_I:%.*]] = add nsw <2 x i32> [[ADD_I]], [[REM_I]]
; CHECK-NEXT:    ret <2 x i32> [[RET_I]]
;
  %rem.i = srem <2 x i32> %x, <i32 7, i32 7>
  %cmp.i = icmp slt <2 x i32> %rem.i, zeroinitializer
  %add.i = select <2 x i1> %cmp.i, <2 x i32> <i32 7, i32 7>, <2 x i32> zeroinitializer
  %ret.i = add nsw <2 x i32> %add.i, %rem.i
  ret <2 x i32> %ret.i
}

define i32 @modulo32(i32 %x) {
; CHECK-LABEL: @modulo32(
; CHECK-NEXT:    [[RET_I:%.*]] = and i32 [[X:%.*]], 31
; CHECK-NEXT:    ret i32 [[RET_I]]
;
  %rem.i = srem i32 %x, 32
  %cmp.i = icmp slt i32 %rem.i, 0
  %add.i = select i1 %cmp.i, i32 32, i32 0
  %ret.i = add nsw i32 %add.i, %rem.i
  ret i32 %ret.i
}

define <2 x i32> @modulo32_vec(<2 x i32> %x) {
; CHECK-LABEL: @modulo32_vec(
; CHECK-NEXT:    [[RET_I:%.*]] = and <2 x i32> [[X:%.*]], <i32 31, i32 31>
; CHECK-NEXT:    ret <2 x i32> [[RET_I]]
;
  %rem.i = srem <2 x i32> %x, <i32 32, i32 32>
  %cmp.i = icmp slt <2 x i32> %rem.i, zeroinitializer
  %add.i = select <2 x i1> %cmp.i, <2 x i32> <i32 32, i32 32>, <2 x i32> zeroinitializer
  %ret.i = add nsw <2 x i32> %add.i, %rem.i
  ret <2 x i32> %ret.i
}

define <2 x i32> @modulo16_32_vec(<2 x i32> %x) {
; CHECK-LABEL: @modulo16_32_vec(
; CHECK-NEXT:    [[REM_I:%.*]] = srem <2 x i32> [[X:%.*]], <i32 16, i32 32>
; CHECK-NEXT:    [[CMP_I:%.*]] = icmp slt <2 x i32> [[REM_I]], zeroinitializer
; CHECK-NEXT:    [[ADD_I:%.*]] = select <2 x i1> [[CMP_I]], <2 x i32> <i32 16, i32 32>, <2 x i32> zeroinitializer
; CHECK-NEXT:    [[RET_I:%.*]] = add nsw <2 x i32> [[ADD_I]], [[REM_I]]
; CHECK-NEXT:    ret <2 x i32> [[RET_I]]
;
  %rem.i = srem <2 x i32> %x, <i32 16, i32 32>
  %cmp.i = icmp slt <2 x i32> %rem.i, zeroinitializer
  %add.i = select <2 x i1> %cmp.i, <2 x i32> <i32 16, i32 32>, <2 x i32> zeroinitializer
  %ret.i = add nsw <2 x i32> %add.i, %rem.i
  ret <2 x i32> %ret.i
}
llvm/llvm/test/Transforms/InstCombine/modulo.ll
