llvm/llvm/test/Transforms/InstCombine/pr72433.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
; RUN: opt -passes=instcombine -S < %s | FileCheck %s

define i32 @widget(i32 %arg, i32 %arg1) {
; CHECK-LABEL: define i32 @widget(
; CHECK-SAME: i32 [[ARG:%.*]], i32 [[ARG1:%.*]]) {
; CHECK-NEXT:  bb:
; CHECK-NEXT:    [[ICMP:%.*]] = icmp ne i32 [[ARG]], 0
; CHECK-NEXT:    [[TMP0:%.*]] = zext i1 [[ICMP]] to i32
; CHECK-NEXT:    [[MUL:%.*]] = shl nuw nsw i32 20, [[TMP0]]
; CHECK-NEXT:    [[XOR:%.*]] = zext i1 [[ICMP]] to i32
; CHECK-NEXT:    [[ADD9:%.*]] = or disjoint i32 [[MUL]], [[XOR]]
; CHECK-NEXT:    [[TMP1:%.*]] = zext i1 [[ICMP]] to i32
; CHECK-NEXT:    [[MUL2:%.*]] = shl nuw nsw i32 [[ADD9]], [[TMP1]]
; CHECK-NEXT:    ret i32 [[MUL2]]
;
bb:
  %icmp = icmp eq i32 %arg, 0
  %zext = zext i1 %icmp to i32
  %sub = sub i32 2, %zext
  %mul = mul i32 20, %sub
  %zext8 = zext i1 %icmp to i32
  %xor = xor i32 %zext8, 1
  %add9 = add i32 %mul, %xor
  %mul2 = mul i32 %add9, %sub
  ret i32 %mul2
}