; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=hexagon < %s | FileCheck %s
define <128 x i8> @test0000(<128 x i8> %a0, i8 %a1) #0 {
; CHECK-LABEL: test0000:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v1:0.uh = vzxt(v0.ub)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: v0.h = vasl(v0.h,r0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: v1.h = vasl(v1.h,r0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
%b0 = insertelement <128 x i8> zeroinitializer, i8 %a1, i32 0
%b1 = shufflevector <128 x i8> %b0, <128 x i8> undef, <128 x i32> zeroinitializer
%v0 = shl <128 x i8> %a0, %b1
ret <128 x i8> %v0
}
define <128 x i8> @test0001(<128 x i8> %a0, i8 %a1) #0 {
; CHECK-LABEL: test0001:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v1:0.h = vsxt(v0.b)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: v0.h = vasr(v0.h,r0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: v1.h = vasr(v1.h,r0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
%b0 = insertelement <128 x i8> zeroinitializer, i8 %a1, i32 0
%b1 = shufflevector <128 x i8> %b0, <128 x i8> undef, <128 x i32> zeroinitializer
%v0 = ashr <128 x i8> %a0, %b1
ret <128 x i8> %v0
}
define <128 x i8> @test0002(<128 x i8> %a0, i8 %a1) #0 {
; CHECK-LABEL: test0002:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v1:0.uh = vzxt(v0.ub)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: v0.uh = vlsr(v0.uh,r0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: v1.uh = vlsr(v1.uh,r0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
%b0 = insertelement <128 x i8> zeroinitializer, i8 %a1, i32 0
%b1 = shufflevector <128 x i8> %b0, <128 x i8> undef, <128 x i32> zeroinitializer
%v0 = lshr <128 x i8> %a0, %b1
ret <128 x i8> %v0
}
define <64 x i16> @test0010(<64 x i16> %a0, i16 %a1) #0 {
; CHECK-LABEL: test0010:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v0.h = vasl(v0.h,r0)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
%b0 = insertelement <64 x i16> zeroinitializer, i16 %a1, i32 0
%b1 = shufflevector <64 x i16> %b0, <64 x i16> undef, <64 x i32> zeroinitializer
%v0 = shl <64 x i16> %a0, %b1
ret <64 x i16> %v0
}
define <64 x i16> @test0011(<64 x i16> %a0, i16 %a1) #0 {
; CHECK-LABEL: test0011:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v0.h = vasr(v0.h,r0)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
%b0 = insertelement <64 x i16> zeroinitializer, i16 %a1, i32 0
%b1 = shufflevector <64 x i16> %b0, <64 x i16> undef, <64 x i32> zeroinitializer
%v0 = ashr <64 x i16> %a0, %b1
ret <64 x i16> %v0
}
define <64 x i16> @test0012(<64 x i16> %a0, i16 %a1) #0 {
; CHECK-LABEL: test0012:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v0.uh = vlsr(v0.uh,r0)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
%b0 = insertelement <64 x i16> zeroinitializer, i16 %a1, i32 0
%b1 = shufflevector <64 x i16> %b0, <64 x i16> undef, <64 x i32> zeroinitializer
%v0 = lshr <64 x i16> %a0, %b1
ret <64 x i16> %v0
}
define <32 x i32> @test0020(<32 x i32> %a0, i32 %a1) #0 {
; CHECK-LABEL: test0020:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v0.w = vasl(v0.w,r0)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
%b0 = insertelement <32 x i32> zeroinitializer, i32 %a1, i32 0
%b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer
%v0 = shl <32 x i32> %a0, %b1
ret <32 x i32> %v0
}
define <32 x i32> @test0021(<32 x i32> %a0, i32 %a1) #0 {
; CHECK-LABEL: test0021:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v0.w = vasr(v0.w,r0)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
%b0 = insertelement <32 x i32> zeroinitializer, i32 %a1, i32 0
%b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer
%v0 = ashr <32 x i32> %a0, %b1
ret <32 x i32> %v0
}
define <32 x i32> @test0022(<32 x i32> %a0, i32 %a1) #0 {
; CHECK-LABEL: test0022:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v0.uw = vlsr(v0.uw,r0)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
%b0 = insertelement <32 x i32> zeroinitializer, i32 %a1, i32 0
%b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer
%v0 = lshr <32 x i32> %a0, %b1
ret <32 x i32> %v0
}
define <32 x i32> @test0023(<32 x i32> %a0, <32 x i32> %a1, i32 %a2) #0 {
; CHECK-LABEL: test0023:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v0.w += vasl(v1.w,r0)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
%b0 = insertelement <32 x i32> zeroinitializer, i32 %a2, i32 0
%b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer
%v0 = shl <32 x i32> %a1, %b1
%v1 = add <32 x i32> %a0, %v0
ret <32 x i32> %v1
}
define <32 x i32> @test0024(<32 x i32> %a0, <32 x i32> %a1, i32 %a2) #0 {
; CHECK-LABEL: test0024:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v0.w += vasr(v1.w,r0)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
%b0 = insertelement <32 x i32> zeroinitializer, i32 %a2, i32 0
%b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer
%v0 = ashr <32 x i32> %a1, %b1
%v1 = add <32 x i32> %a0, %v0
ret <32 x i32> %v1
}
define <128 x i8> @test0030(<128 x i8> %a0, <128 x i8> %a1) #0 {
; CHECK-LABEL: test0030:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v3:2.uh = vzxt(v0.ub)
; CHECK-NEXT: v31:30.uh = vzxt(v1.ub)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: v0.h = vasl(v2.h,v30.h)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: v1.h = vasl(v3.h,v31.h)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
%v0 = shl <128 x i8> %a0, %a1
ret <128 x i8> %v0
}
define <128 x i8> @test0031(<128 x i8> %a0, <128 x i8> %a1) #0 {
; CHECK-LABEL: test0031:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v3:2.h = vsxt(v0.b)
; CHECK-NEXT: v31:30.uh = vzxt(v1.ub)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: v0.h = vasr(v2.h,v30.h)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: v1.h = vasr(v3.h,v31.h)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
%v0 = ashr <128 x i8> %a0, %a1
ret <128 x i8> %v0
}
define <128 x i8> @test0032(<128 x i8> %a0, <128 x i8> %a1) #0 {
; CHECK-LABEL: test0032:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v3:2.uh = vzxt(v0.ub)
; CHECK-NEXT: v31:30.uh = vzxt(v1.ub)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: v0.h = vlsr(v2.h,v30.h)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: v1.h = vlsr(v3.h,v31.h)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
%v0 = lshr <128 x i8> %a0, %a1
ret <128 x i8> %v0
}
define <64 x i16> @test0040(<64 x i16> %a0, <64 x i16> %a1) #0 {
; CHECK-LABEL: test0040:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v0.h = vasl(v0.h,v1.h)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
%v0 = shl <64 x i16> %a0, %a1
ret <64 x i16> %v0
}
define <64 x i16> @test0041(<64 x i16> %a0, <64 x i16> %a1) #0 {
; CHECK-LABEL: test0041:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v0.h = vasr(v0.h,v1.h)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
%v0 = ashr <64 x i16> %a0, %a1
ret <64 x i16> %v0
}
define <64 x i16> @test0042(<64 x i16> %a0, <64 x i16> %a1) #0 {
; CHECK-LABEL: test0042:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v0.h = vlsr(v0.h,v1.h)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
%v0 = lshr <64 x i16> %a0, %a1
ret <64 x i16> %v0
}
define <32 x i32> @test0050(<32 x i32> %a0, <32 x i32> %a1) #0 {
; CHECK-LABEL: test0050:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v0.w = vasl(v0.w,v1.w)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
%v0 = shl <32 x i32> %a0, %a1
ret <32 x i32> %v0
}
define <32 x i32> @test0051(<32 x i32> %a0, <32 x i32> %a1) #0 {
; CHECK-LABEL: test0051:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v0.w = vasr(v0.w,v1.w)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
%v0 = ashr <32 x i32> %a0, %a1
ret <32 x i32> %v0
}
define <32 x i32> @test0052(<32 x i32> %a0, <32 x i32> %a1) #0 {
; CHECK-LABEL: test0052:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v0.w = vlsr(v0.w,v1.w)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
%v0 = lshr <32 x i32> %a0, %a1
ret <32 x i32> %v0
}
attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
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