llvm/llvm/test/CodeGen/Hexagon/autohvx/qmul-add-over-32-bit.ll

; RUN: llc -march=hexagon < %s | FileCheck %s

; Make sure the add isn't dropped.
; CHECK: vadd{{.*}}:carry

target triple = "hexagon"

define <32 x i32> @f0(<32 x i32> %a0) #0 {
b0:
  %v0 = sext <32 x i32> %a0 to <32 x i64>
  %v1 = mul nsw <32 x i64> %v0, <i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240, i64 1288490240>
  %v2 = add nsw <32 x i64> %v1, <i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296, i64 4294967296>
  %v3 = ashr <32 x i64> %v2, <i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33>
  %v4 = trunc <32 x i64> %v3 to <32 x i32>
  ret <32 x i32> %v4
}

attributes #0 = { noinline "target-cpu"="hexagonv68" "target-features"="+hvxv68,+hvx-length128b,+hvx-qfloat,-hvx-ieee-fp,-packets" }