llvm/llvm/test/CodeGen/AMDGPU/load-range-metadata-assert.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s

define <2 x i32> @range_metata_sext_range_0_i24_i64_bitcast(ptr addrspace(1) %ptr) {
; GCN-LABEL: range_metata_sext_range_0_i24_i64_bitcast:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT:    global_load_dwordx2 v[0:1], v[0:1], off glc
; GCN-NEXT:    s_waitcnt vmcnt(0)
; GCN-NEXT:    s_setpc_b64 s[30:31]
  %val = load volatile i64, ptr addrspace(1) %ptr, align 4, !range !0, !noundef !{}
  %shl = shl i64 %val, 22
  %ashr = ashr i64 %shl, 22
  %cast = bitcast i64 %ashr to <2 x i32>
  ret <2 x i32> %cast
}

define <2 x i32> @no_range_sext_range_0_i24_i64_bitcast(ptr addrspace(1) %ptr) {
; GCN-LABEL: no_range_sext_range_0_i24_i64_bitcast:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT:    global_load_dwordx2 v[0:1], v[0:1], off glc
; GCN-NEXT:    s_waitcnt vmcnt(0)
; GCN-NEXT:    v_lshlrev_b64 v[0:1], 22, v[0:1]
; GCN-NEXT:    v_ashrrev_i64 v[0:1], 22, v[0:1]
; GCN-NEXT:    s_setpc_b64 s[30:31]
  %val = load volatile i64, ptr addrspace(1) %ptr, align 4
  %shl = shl i64 %val, 22
  %ashr = ashr i64 %shl, 22
  %cast = bitcast i64 %ashr to <2 x i32>
  ret <2 x i32> %cast
}

!0 = !{i64 0, i64 16777216}