llvm/llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx906 -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs -o - %s | FileCheck %s

# Make sure the modified CSR VGPRs are added as live-in to the entry
# block.

---
name: def_csr_sgpr
tracksRegLiveness: true
machineFunctionInfo:
  scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
  stackPtrOffsetReg: $sgpr32
body: |
  ; CHECK-LABEL: name: def_csr_sgpr
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   liveins: $sgpr42, $sgpr43, $sgpr46, $sgpr47
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $sgpr4_sgpr5 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5)
  ; CHECK-NEXT:   $exec = S_MOV_B64 killed $sgpr4_sgpr5
  ; CHECK-NEXT:   $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr42, 0, $vgpr0
  ; CHECK-NEXT:   $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr43, 1, $vgpr0
  ; CHECK-NEXT:   $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr46, 2, $vgpr0
  ; CHECK-NEXT:   $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr47, 3, $vgpr0
  ; CHECK-NEXT:   S_NOP 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   $sgpr42 = S_MOV_B32 0
  ; CHECK-NEXT:   $sgpr43 = S_MOV_B32 1
  ; CHECK-NEXT:   $sgpr46_sgpr47 = S_MOV_B64 2
  bb.0:
    S_NOP 0

  bb.1:
    $sgpr42 = S_MOV_B32 0
    $sgpr43 = S_MOV_B32 1
    $sgpr46_sgpr47 = S_MOV_B64 2
...