# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-n1 2>&1 | FileCheck %s
# test pipeliner code genearation by MVE algorithm
# exit loop when condition holds
...
---
name: func
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: func
; CHECK: bb.0.entry:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[FMOVDi:%[0-9]+]]:fpr64 = FMOVDi 1
; CHECK-NEXT: B %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.7(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY1]], [[COPY1]]
; CHECK-NEXT: dead $xzr = SUBSXrr [[COPY]], [[ADDXrr]], implicit-def $nzcv
; CHECK-NEXT: [[CSINCXr:%[0-9]+]]:gpr64common = CSINCXr $xzr, $xzr, 1, implicit $nzcv
; CHECK-NEXT: [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr [[ADDXrr]], [[COPY1]]
; CHECK-NEXT: dead $xzr = SUBSXrr [[COPY]], [[ADDXrr1]], implicit-def $nzcv
; CHECK-NEXT: [[CSINCXr1:%[0-9]+]]:gpr64common = CSINCXr [[CSINCXr]], [[CSINCXr]], 1, implicit $nzcv
; CHECK-NEXT: [[ADDXrr2:%[0-9]+]]:gpr64 = ADDXrr [[ADDXrr1]], [[COPY1]]
; CHECK-NEXT: dead $xzr = SUBSXrr [[COPY]], [[ADDXrr2]], implicit-def $nzcv
; CHECK-NEXT: [[CSINCXr2:%[0-9]+]]:gpr64common = CSINCXr [[CSINCXr1]], [[CSINCXr1]], 1, implicit $nzcv
; CHECK-NEXT: [[ADDXrr3:%[0-9]+]]:gpr64 = ADDXrr [[ADDXrr2]], [[COPY1]]
; CHECK-NEXT: dead $xzr = SUBSXrr [[COPY]], [[ADDXrr3]], implicit-def $nzcv
; CHECK-NEXT: [[CSINCXr3:%[0-9]+]]:gpr64common = CSINCXr [[CSINCXr2]], [[CSINCXr2]], 1, implicit $nzcv
; CHECK-NEXT: dead $xzr = SUBSXri [[CSINCXr3]], 0, 0, implicit-def $nzcv
; CHECK-NEXT: Bcc 0, %bb.4, implicit $nzcv
; CHECK-NEXT: B %bb.7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4:
; CHECK-NEXT: successors: %bb.5(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[FADDDrr:%[0-9]+]]:fpr64 = FADDDrr [[FMOVDi]], [[FMOVDi]], implicit $fpcr
; CHECK-NEXT: [[ADDXrr4:%[0-9]+]]:gpr64 = ADDXrr [[COPY1]], [[COPY1]]
; CHECK-NEXT: dead $xzr = SUBSXrr [[COPY]], [[ADDXrr4]], implicit-def $nzcv
; CHECK-NEXT: [[FADDDrr1:%[0-9]+]]:fpr64 = FADDDrr [[FADDDrr]], [[FMOVDi]], implicit $fpcr
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5:
; CHECK-NEXT: successors: %bb.5(0x40000000), %bb.6(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:fpr64 = PHI [[FADDDrr5:%[0-9]+]], %bb.5, [[FMOVDi]], %bb.4
; CHECK-NEXT: [[PHI1:%[0-9]+]]:gpr64 = PHI [[ADDXrr6:%[0-9]+]], %bb.5, [[COPY1]], %bb.4
; CHECK-NEXT: [[PHI2:%[0-9]+]]:fpr64 = PHI [[FADDDrr8:%[0-9]+]], %bb.5, [[FADDDrr]], %bb.4
; CHECK-NEXT: [[PHI3:%[0-9]+]]:gpr64 = PHI [[ADDXrr7:%[0-9]+]], %bb.5, [[ADDXrr4]], %bb.4
; CHECK-NEXT: [[PHI4:%[0-9]+]]:fpr64 = PHI [[FADDDrr10:%[0-9]+]], %bb.5, [[FADDDrr1]], %bb.4
; CHECK-NEXT: [[FADDDrr2:%[0-9]+]]:fpr64 = FADDDrr [[FMOVDi]], [[PHI2]], implicit $fpcr
; CHECK-NEXT: [[ADDXrr5:%[0-9]+]]:gpr64 = ADDXrr [[PHI3]], [[COPY1]]
; CHECK-NEXT: [[FADDDrr3:%[0-9]+]]:fpr64 = FADDDrr [[PHI4]], [[PHI]], implicit $fpcr
; CHECK-NEXT: dead $xzr = SUBSXrr [[COPY]], [[ADDXrr5]], implicit-def $nzcv
; CHECK-NEXT: [[FADDDrr4:%[0-9]+]]:fpr64 = FADDDrr [[FADDDrr2]], [[PHI2]], implicit $fpcr
; CHECK-NEXT: [[FADDDrr5]]:fpr64 = FADDDrr [[FMOVDi]], [[FADDDrr2]], implicit $fpcr
; CHECK-NEXT: [[ADDXrr6]]:gpr64 = ADDXrr [[ADDXrr5]], [[COPY1]]
; CHECK-NEXT: [[FADDDrr6:%[0-9]+]]:fpr64 = FADDDrr [[FADDDrr4]], [[PHI2]], implicit $fpcr
; CHECK-NEXT: dead $xzr = SUBSXrr [[COPY]], [[ADDXrr6]], implicit-def $nzcv
; CHECK-NEXT: [[FADDDrr7:%[0-9]+]]:fpr64 = FADDDrr [[FADDDrr5]], [[FADDDrr2]], implicit $fpcr
; CHECK-NEXT: [[FADDDrr8]]:fpr64 = FADDDrr [[FMOVDi]], [[FADDDrr5]], implicit $fpcr
; CHECK-NEXT: [[ADDXrr7]]:gpr64 = ADDXrr [[ADDXrr6]], [[COPY1]]
; CHECK-NEXT: [[FADDDrr9:%[0-9]+]]:fpr64 = FADDDrr [[FADDDrr7]], [[FADDDrr2]], implicit $fpcr
; CHECK-NEXT: dead $xzr = SUBSXrr [[COPY]], [[ADDXrr7]], implicit-def $nzcv
; CHECK-NEXT: [[FADDDrr10]]:fpr64 = FADDDrr [[FADDDrr8]], [[FADDDrr5]], implicit $fpcr
; CHECK-NEXT: [[CSINCXr4:%[0-9]+]]:gpr64common = CSINCXr $xzr, $xzr, 1, implicit $nzcv
; CHECK-NEXT: [[ADDXrr8:%[0-9]+]]:gpr64 = ADDXrr [[ADDXrr7]], [[COPY1]]
; CHECK-NEXT: dead $xzr = SUBSXrr [[COPY]], [[ADDXrr8]], implicit-def $nzcv
; CHECK-NEXT: [[CSINCXr5:%[0-9]+]]:gpr64common = CSINCXr [[CSINCXr4]], [[CSINCXr4]], 1, implicit $nzcv
; CHECK-NEXT: [[ADDXrr9:%[0-9]+]]:gpr64 = ADDXrr [[ADDXrr8]], [[COPY1]]
; CHECK-NEXT: dead $xzr = SUBSXrr [[COPY]], [[ADDXrr9]], implicit-def $nzcv
; CHECK-NEXT: [[CSINCXr6:%[0-9]+]]:gpr64common = CSINCXr [[CSINCXr5]], [[CSINCXr5]], 1, implicit $nzcv
; CHECK-NEXT: dead $xzr = SUBSXri [[CSINCXr6]], 0, 0, implicit-def $nzcv
; CHECK-NEXT: Bcc 0, %bb.5, implicit $nzcv
; CHECK-NEXT: B %bb.6
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6:
; CHECK-NEXT: successors: %bb.7(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[FADDDrr11:%[0-9]+]]:fpr64 = FADDDrr [[FADDDrr10]], [[FADDDrr5]], implicit $fpcr
; CHECK-NEXT: dead $xzr = SUBSXrr [[COPY]], [[ADDXrr7]], implicit-def $nzcv
; CHECK-NEXT: [[CSINCXr7:%[0-9]+]]:gpr64common = CSINCXr $xzr, $xzr, 1, implicit $nzcv
; CHECK-NEXT: dead $xzr = SUBSXri [[CSINCXr7]], 0, 0, implicit-def $nzcv
; CHECK-NEXT: Bcc 0, %bb.7, implicit $nzcv
; CHECK-NEXT: B %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.7:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI5:%[0-9]+]]:fpr64 = PHI [[FMOVDi]], %bb.3, [[FADDDrr8]], %bb.6
; CHECK-NEXT: [[PHI6:%[0-9]+]]:gpr64 = PHI [[COPY1]], %bb.3, [[ADDXrr7]], %bb.6
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI7:%[0-9]+]]:gpr64 = PHI [[PHI6]], %bb.7, [[ADDXrr10:%[0-9]+]], %bb.1
; CHECK-NEXT: [[PHI8:%[0-9]+]]:fpr64 = PHI [[PHI5]], %bb.7, [[FADDDrr12:%[0-9]+]], %bb.1
; CHECK-NEXT: [[ADDXrr10]]:gpr64 = ADDXrr [[PHI7]], [[COPY1]]
; CHECK-NEXT: dead $xzr = SUBSXrr [[COPY]], [[ADDXrr10]], implicit-def $nzcv
; CHECK-NEXT: [[FADDDrr12]]:fpr64 = FADDDrr [[FMOVDi]], [[PHI8]], implicit $fpcr
; CHECK-NEXT: [[FADDDrr13:%[0-9]+]]:fpr64 = FADDDrr [[FADDDrr12]], [[PHI8]], implicit $fpcr
; CHECK-NEXT: [[FADDDrr14:%[0-9]+]]:fpr64 = FADDDrr [[FADDDrr13]], [[PHI8]], implicit $fpcr
; CHECK-NEXT: Bcc 0, %bb.2, implicit $nzcv
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: [[PHI9:%[0-9]+]]:fpr64 = PHI [[FADDDrr12]], %bb.1, [[FADDDrr8]], %bb.6
; CHECK-NEXT: [[PHI10:%[0-9]+]]:fpr64 = PHI [[FADDDrr14]], %bb.1, [[FADDDrr11]], %bb.6
; CHECK-NEXT: [[FMULDrr:%[0-9]+]]:fpr64 = FMULDrr [[PHI9]], [[PHI10]], implicit $fpcr
; CHECK-NEXT: $d0 = COPY [[FMULDrr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
bb.0.entry:
liveins: $x0, $x1
%10:gpr64 = COPY $x0
%11:gpr64 = COPY $x1
%20:fpr64 = FMOVDi 1
bb.1:
%12:gpr64 = PHI %11, %bb.0, %13, %bb.1
%24:fpr64 = PHI %20, %bb.0, %21, %bb.1
%13:gpr64 = ADDXrr %12, %11
dead $xzr = SUBSXrr %10, %13, implicit-def $nzcv
%21:fpr64 = FADDDrr %20, %24, implicit $fpcr
%22:fpr64 = FADDDrr %21, %24, implicit $fpcr
%23:fpr64 = FADDDrr %22, %24, implicit $fpcr
Bcc 0, %bb.2, implicit $nzcv
B %bb.1
bb.2:
%25:fpr64 = FMULDrr %21, %23, implicit $fpcr
$d0 = COPY %25
RET_ReallyLR implicit $d0
...
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