llvm/llvm/test/CodeGen/AArch64/a57-csel.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -mcpu=cortex-a57 -aarch64-enable-early-ifcvt=false | FileCheck %s

; Check that the select isn't expanded into a branch sequence
; when the icmp's first operand %x0 is from load.
define i64 @f(i64 %a, i64 %b, ptr %c, i64 %d, i64 %e) {
; CHECK-LABEL: f:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr x8, [x2]
; CHECK-NEXT:    cmp x8, #0
; CHECK-NEXT:    csel x8, x0, x1, eq
; CHECK-NEXT:    add x0, x8, x3
; CHECK-NEXT:    ret
  %x0 = load i64, ptr %c
  %x1 = icmp eq i64 %x0, 0
  %x2 = select i1 %x1, i64 %a, i64 %b
  %x3 = add i64 %x2, %d
  ret i64 %x3
}